TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 features D PACKAGE (TOP VIEW) (cid:0) Dual 8-Bit Voltage Output DAC (cid:0) Programmable Internal Reference DIN 1 8 VDD (cid:0) Programmable Settling Time: SCLK 2 7 OUTB 0.8 m s in Fast Mode , CS 3 6 REF 2.8 m s in Slow Mode OUTA 4 5 AGND (cid:0) Compatible With TMS320 and SPI Serial Ports (cid:0) Differential Nonlinearity <0.1 LSB Typ (cid:0) Monotonic Over Temperature applications (cid:0) Digital Servo Control Loops (cid:0) Digital Offset and Gain Adjustment (cid:0) Industrial Process Control (cid:0) Machine and Motion Control Devices (cid:0) Mass Storage Devices description The TLV5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 2 control and 8 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a ClassAB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5626 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC (D) 0°C to 70°C TLV5626CD –40°C to 85°C TLV5626ID Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 functional block diagram REF AGND VDD PGA With Output Enable Voltage Bandgap Power Power-On and Speed Reset Control 2 2 2-Bit Control Latch x2 OUTA DIN 8 8-Bit 8 DAC A Latch SCLK Serial Interface 8 and Buffer CS Control 8 8 8-Bit DAC B Latch x2 OUTB Terminal Functions TERMINAL II//OO//PP DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUTA 4 I DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (V to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V + 0.3 V DD Operating free-air temperature range, T :TLV5626C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A TLV5626I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT VDD = 5 V 4.5 5 5.5 V SSuuppppllyy vvoollttaaggee, VVDDDD VDD = 3 V 2.7 3 3.3 V Power on threshold voltage, POR 0.55 2 V High-level digital input voltage, VIH VDD = 2.7 V to 5.5 V 2 V Low-level digital input voltage, VIL VDD = 2.7 V to 5.5 V 0.8 V Reference voltage, Vref to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V Reference voltage, Vref to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V Load resistance, RL 2 kW Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz TLV5626C 0 70 OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTAA °°CC TLV5626I –40 85 NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD – 0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDDD = 5 V, Fast 4.2 7 mA Int. ref. Slow 2 3.6 mA VDDDD = 3 V, Fast 3.7 6.3 mA No load, Int. ref. Slow 1.7 3.0 mA IIDDDD PPoowweerr ssuuppppllyy ccuurrrreenntt AAllll iinnppuuttss == AAGGNNDD oorr VVDDDD, DAC latch = 0x800 VDDDD = 5 V, Fast 3.8 6.3 mA Ext. ref. Slow 1.7 3.0 mA VDDDD = 3 V, Fast 3.4 5.7 mA Ext. ref. Slow 1.4 2.6 mA Power-down supply current 1 m A Zero scale, See Note 2 –65 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo ddBB Full scale, See Note 3 –65 NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 8 bits INL Integral nonlinearity, end point adjusted See Note 4 ±0.4 ±1 LSB DNL Differential nonlinearity See Note 5 ±0.1 ±0.5 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 ±24 mV EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C % full EG Gain error See Note 8 ±0.6 scale V EG TC Gain error temperature coefficient See Note 9 10 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) – EZS(Tmin)]/Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage RL = 10 kW 0 VDD–0.4 V % full Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kW vs 10 k ±0.25 scale V 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) reference pin configured as output (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vref(OUTL) Low reference voltage 1.003 1.024 1.045 V Vref(OUTH) High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V Iref(source) Output source current 1 mA Iref(sink) Output sink current –1 mA Load capacitance 100 pF PSRR Power supply rejection ratio –65 dB reference pin configured as input (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 0 VDD–1.5 V RI Input resistance 10 MW CI Input capacitance 5 pF Fast 1.3 MHz RReeffeerreennccee iinnppuutt bbaannddwwiiddtthh RREEFF == 00.22 VVpp ++ 11.002244 VV ddcc Slow 525 kHz Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB NOTE 10:Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 m A IIL Low-level digital input current VI = 0 V –1 m A Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tts((FFSS)) OOuuttppuutt sseettttlliinngg ttiimmee, ffuullll ssccaallee RLL = 10 kW ,, CLL = 100 pF,, Fast 0.8 2.4 mm ss See Note 11 Slow 2.8 5.5 tts((CCCC)) OOuuttppuutt sseettttlliinngg ttiimmee, ccooddee ttoo ccooddee RLL = 10 kW ,, CLL = 100 pF,, Fast 0.4 1.2 mm ss See Note 12 Slow 0.8 1.6 SSRR SSlleeww rraattee RLL = 10 kW ,, CLL = 100 pF,, Fast 12 VV//mm ss See Note 13 Slow 1.8 DIN = 0 to 1, fCLK = 100 kHz, Glitch energy 5 nV–S CS = VDD SNR Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion fss = 480 kSPS,, foouutt = 1 kHz,, 48 47 ddBB THD Total harmonic distortion RL = 10 kW , CL = 100 pF –50 –48 SFDR Spurious free dynamic range 50 62 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns twH SCLK pulse width high 25 ns twL SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 10 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns PARAMETER MEASUREMENT INFORMATION twL twH SCLK X 1 2 3 4 5 15 16 X tsu(D) th(D) DIN X D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 4.5 4.5 4 4 mA Fast Mode mA Fast Mode – Supply Current – IDD 32..2355 Slow Mode – Supply Current – IDD 23..2355 Slow Mode 1.5 1.5 1 VVrDeDf == I5n tV. 2 V 1 VVrDeDf == I3n tV. 1 V Input Code = 1023 (Both DACs) Input Code = 1023 (Both DACs) 0.5 0.5 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 2 Figure 3 POWER DOWN SUPPLY CURRENT OUTPUT VOLTAGE vs vs TIME LOAD CURRENT 2.6 2.064 2.4 VDD = 3 V – mA 2.2 2.062 Fast Mode VInrpeuf t= C Inotd. e1 =V 4095 nt 2 e ply Curr 11..86 age – V 2.06 Slow Mode Sup 1.4 Volt 2.058 n 1.2 ut w p Do 1 Out 2.056 wer 0.8 – Po 0.6 VO2.054 – D 0.4 D 2.052 I 0.2 0 2.05 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 3.5 4 t – Time – m s Source Current – mA Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 4.128 3 VDD = 5 V VDD = 3 V Fast Mode Vref = Int. 2 V Vref = Int. 1 V 4.126 Input Code = 4095 2.5 Input Code = 0 Output Voltage – V 444..11.122224 Slow Mode Output Voltage – V 1.25 Fast Mode – – 1 VO4.118 VO 0.5 4.116 Slow Mode 4.114 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current – mA Sink Current – mA Figure 6 Figure 7 OUTPUT VOLTAGE TOTAL HARMONIC DISTORTION AND NOISE vs vs LOAD CURRENT FREQUENCY 5 B 0 VDD = 5 V – d VDD = 5 V 4.5 VInrpeuf t= C Inotd. e2 =V 0 oise –10 VOruetfp =u t1 F Vu ldl cS +c a1l eV p/p Sinewave 4 N –20 d V n e – 3.5 Fast Mode on a –30 Output Voltag 2.235 monic Distorti –––456000 – r Slow Mode a O 1.5 H –70 V al 1 Tot –80 Fast Mode – 0.5 +N –90 Slow Mode D 0 TH –100 0 0.5 1 1.5 2 2.5 3 3.5 4 100 1000 10000 100000 Sink Current – mA f – Frequency – Hz Figure 8 Figure 9 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY 0 VDD = 5 V –10 Vref = 1 V dc + 1 V p/p Sinewave B d Output Full Scale – –20 n o rti –30 o st Di –40 c oni –50 m r Ha –60 al ot –70 Slow Mode T – D –80 H T Fast Mode –90 –100 100 1000 10000 100000 f – Frequency – Hz Figure 10 DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE B S 0.20 L – 0.15 y arit 0.10 e n nli 0.05 o N –0.00 al nti –0.05 e er –0.10 Diff –0.15 – NL –0.2 D 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 1.0 B LS 0.8 y – 0.6 rit 0.4 a e n 0.2 nli –0.0 o N al –0.2 gr –0.4 e nt –0.6 L – I –0.8 N –1.0 I 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code Figure 12 APPLICATION INFORMATION general function The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: CODE 2 REF [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to 0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI, and Microwire. TMS320 TLV5626 SPI TLV5626 Microwire TLV5626 DSP FSX CS I/O CS I/O CS DX DIN MOSI DIN SO DIN CLKX SCLK SCK SCLK SK SCLK Figure 13. Three-Wire Interface 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: 1 fsclkmax(cid:1)twhmin(cid:0)twlmin(cid:1)20 MHz The maximum update rate is: 1 fupdatemax(cid:1) (cid:1)1.25 MHz 16 (cid:2)twhmin(cid:0)twlmin(cid:3) The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626 has to be considered, too. data format The 16-bit data word for the TLV5626 consists of two parts: (cid:0) Program bits (D15..D12) (cid:0) New data (D11..D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1 SPD PWR R0 12 Data bits SPD: Speed control bit 1 → fast mode 0 →slow mode PWR: Power control bit 1 → power down 0 → normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value 0 0 0 0 If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF0 X: don’t care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. examples of operation: (cid:0) Set DAC A output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 2. Write new DAC A value and update DAC A output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 New DAC A output value 0 0 0 0 The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. (cid:0) Set DAC B output, select fast mode, select external reference: 3. Select external reference (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4. Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 New BUFFER content and DAC B output value 0 0 0 0 X = Don’t care The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION examples of operation: (continued) (cid:0) Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: 1. Set reference voltage to 1.024 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 2. Write data for DAC B to BUFFER: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 New DAC B value 0 0 0 0 X = Don’t care 3. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 New DAC A value 0 0 0 0 X = Don’t care Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. (cid:0) Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0 V DAC Code Negative Offset Figure 14. Effect of Negative Offset (single supply) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (E ) ZS Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (E ) G Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) M 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–8° 0.044 (1,12) A 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX 0.004 (0,10) PINS ** 8 14 16 DIM 0.197 0.344 0.394 A MAX (5,00) (8,75) (10,00) 0.189 0.337 0.386 A MIN (4,80) (8,55) (9,80) 4040047/D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty TLV5626CD ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626CDG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626CDR ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626CDRG4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626ID ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626IDG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626IDR ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLV5626IDRG4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) TLV5626CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5626IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV5626CDR SOIC D 8 2500 346.0 346.0 29.0 TLV5626IDR SOIC D 8 2500 346.0 346.0 29.0 PackMaterials-Page2

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