(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 features D OR DGK PACKAGE (TOP VIEW) (cid:1) 8-Bit Voltage Output DAC (cid:1) Programmable Internal Reference DIN 1 8 VDD (cid:1) Programmable Settling Time: SCLK 2 7 OUT 1 µs in Fast Mode, CS 3 6 REF 3.5 µs in Slow Mode FS 4 5 AGND (cid:1) Compatible With TMS320 and SPI Serial Ports (cid:1) Differential Nonlinearity...<0.2 LSB (cid:1) Monotonic Over Temperature applications (cid:1) Digital Servo Control Loops (cid:1) Digital Offset and Gain Adjustment (cid:1) Industrial Process Control (cid:1) Machine and Motion Control Devices (cid:1) Mass Storage Devices description The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 8 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5624 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC MSOP (D) (DGK) 0°C to 70°C TLV5624CD TLV5624CDGK −40°C to 85°C TLV5624ID TLV5624IDGK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. (cid:13)(cid:15)(cid:11)(cid:19)(cid:26)(cid:23)(cid:1)(cid:18)(cid:11)(cid:22) (cid:19)(cid:21)(cid:1)(cid:21) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’(cid:8) Copyright  2002−2004, Texas Instruments Incorporated (cid:13)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #,’ #’(cid:31)!$ (cid:30)(cid:29) (cid:1)’-"$ (cid:18)(cid:28)$#(cid:31)&!’(cid:28)#$ $#"(cid:28)+"(cid:31)+ ."(cid:31)(cid:31)"(cid:28)#/(cid:8) (cid:13)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)0 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*/ (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)0 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$(cid:8) WWW.TI.COM 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 functional block diagram REF PGA With Output Enable Voltage Bandgap Power Power-On and Speed Reset Control 2 2 2-Bit Control Latch DIN Serial SCLK Interface and 8 8 CS Control 8-Bit x2 OUT DAC FS Latch Terminal Functions TERMINAL II//OO//PP DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input FS 4 I Frame sync input OUT 7 O DAC A analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (V to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V + 0.3 V DD Operating free-air temperature range, T :TLV5624C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A TLV5624I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT VDD = 5 V 4.5 5 5.5 SSuuppppllyy vvoollttaaggee,, VVDDDD VV VDD = 3 V 2.7 3 3.3 Power on reset, POR 0.55 2 V DVDD = 2.7 V 2 HHiigghh--lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee,, VVIIHH VV DVDD = 5.5 V 2.4 DVDD = 2.7 V 0.6 LLooww--lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee,, VVIILL VV DVDD = 5.5 V 1 Reference voltage, Vref to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD−1.5 V Reference voltage, Vref to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD−1.5 V Load resistance, RL 2 kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz TLV5624C 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA °°CC TLV5624I −40 85 NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD−0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. WWW.TI.COM 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT No load, Fast 2.3 3.3 IIDDDD PPoowweerr ssuuppppllyy ccuurrrreenntt AAllll iinnppuuttss == AAGGNNDD oorr VVDDDD,, mmAA DAC latch = 0x800 Slow 1.5 1.9 Power down supply current See Figure 8 0.01 10 µA Zero scale, See Note 2 −65 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo ddBB Full scale, See Note 3 −65 NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 8 bits INL Integral nonlinearity, end point adjusted See Note 4 ±0.3 ±0.5 LSB DNL Differential nonlinearity See Note 5 ±0.07 ±0.2 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 ±20 mV EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C % full EG Gain error See Note 8 ±0.6 scale V EG TC Gain error temperature coefficient See Note 9 10 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 255. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 255. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) − EZS(Tmin)]/Vref × 106/(Tmax − Tmin). 8. Gain error is the deviation from the ideal output (2Vref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin). output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage RL = 10 kΩ 0 VDD−0.4 V % full Output load regulation accuracy VO = 4.096 V, 2.048 V RL = 2 kΩ ±0.10 ±0.25 scale V reference pin configured as output (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vref(OUTL) Low reference voltage 1.003 1.024 1.045 V Vref(OUTH) High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V Iref(source) Output source current 1 mA Iref(sink) Output sink current −1 mA Load capacitance 1 10 ωF PSRR Power supply rejection ratio −65 dB 4 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) reference pin configured as input (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 0 VDD−1.5 V RI Input resistance 10 MΩ CI Input capacitance 5 pF Fast 1.3 MHz RReeffeerreennccee iinnppuutt bbaannddwwiiddtthh RREEFF == 00..22 VVpppp ++ 11..002244 VV ddcc Slow 525 kHz Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) −80 dB NOTE 10:Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V −1 µA Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ttss((FFSS)) OOuuttppuutt sseettttlliinngg ttiimmee,, ffuullll ssccaallee RRSeLLe == N 11o00t ekk ΩΩ11,, CCLL == 110000 ppFF,, FSaloswt 3.15 37 µss ttss((CCCC)) OOuuttppuutt sseettttlliinngg ttiimmee,, ccooddee ttoo ccooddee RRSeLLe == N 11o00t ekk ΩΩ12,, CCLL == 110000 ppFF,, FSaloswt 0.15 1.25 µss SSRR SSlleeww rraattee RRLL == 1100 kkΩΩ,, CCLL == 110000 ppFF,, Fast 8 VV//µss See Note 13 Slow 1.5 DIN = 0 to 1, fCLK = 100 kHz, Glitch energy 5 nV−S CS = VDD SNR Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion ffss == 448800 kkSSPPSS,, ffoouutt == 11 kkHHzz,, 48 47 THD Total harmonic distortion RRLL == 1100 kkΩ,, CCLL == 110000 ppFF −50 −48 ddBB Spurious free dynamic range 50 62 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. WWW.TI.COM 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 digital input timing requirements MIN NOM MAX UNIT tsu(CS−FS) Setup time, CS low before FS falling edge 10 ns tsu(FS-CK) Setup time, FS low before first negative SCLK edge 8 ns Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising tsu(C16-FS) edge of FS 10 ns Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising tsu(C16-CS) edge. If FS is used instead of 16th positive edge to update DAC, then setup time between 10 ns FS rising edge and CS rising edge. twH SCLK pulse duration high 25 ns twL SCLK pulse duration low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns tH(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) FS pulse duration high 25 ns PARAMETER MEASUREMENT INFORMATION twL twH SCLK X 1 2 3 4 5 15 16 X tsu(D) th(D) DIN X D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(FS-CK) tsu(C16-FS) FS Figure 1. Timing Diagram 6 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 2.071 4.135 VDD = 3 V, REF = Int. 1 V, Input Code = 255 2.0705 VDD = 5 V, REF = Int. 2 V, Input Code = 255 4.134 2.07 2.0695 Fast Voltage − V 22..00668958 Slow Fast Voltage − V 44..113323 Slow Output 2.068 Output 4.131 2.0675 2.067 4.13 2.0665 2.066 4.129 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current − mA Source Current − mA Figure 2 Figure 3 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 3 5 VDD = 3 V, REF = Int. 1 V, VDD = 5 V, REF = Int. 2 V, Input Code = 0 4.5 Input Code = 0 2.5 4 3.5 V 2 V − − e e 3 g Fast g olta 1.5 olta 2.5 Fast V V ut ut p p 2 ut ut O 1 O 1.5 1 0.5 0.5 Slow Slow 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current − mA Sink Current − mA Figure 4 Figure 5 WWW.TI.COM 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs TEMPERATURE TEMPERATURE 3 3 VDD = 5 V, REF = 2 V, VDD = 3 V, REF = 1 V, Input Code = 255 Input Code = 255 2.5 2.5 Fast Mode mA mA Fast Mode nt − 2 nt − 2 e e urr urr C C ply 1.5 Slow Mode ply 1.5 p p Slow Mode u u S S 1 1 0.5 0.5 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 t − Temperature − °C t − Temperature − °C Figure 6 Figure 7 POWER DOWN SUPPLY CURRENT TOTAL HARMONIC DISTORTION AND NOISE vs vs TIME FREQUENCY 2 B 0 d A 1.8 e − −10 VVrDeDf == 15 VV dc + 1 V p/p Sinewave m s nt − 1.6 d Noi −20 Output Full Scale e n urr 1.4 n a −30 C o ply 1.2 orti −40 p st Su 1 Di −50 n c w ni o 0.8 o −60 D m wer 0.6 Har −70 Slow Mode − Po 0.4 Total −80 Fast Mode D − ID 0.2 +N −90 D 0 TH −100 0 10 20 30 40 50 60 70 80 100 1000 10000 100000 t − Time − µs f − Frequency − Hz Figure 8 Figure 9 8 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY 0 VDD = 5 V −10 Vref = 1 V dc + 1 V p/p Sinewave B d Output Full Scale − −20 n o rti −30 o st Di −40 c oni −50 m r Ha −60 al ot −70 Slow Mode T − D −80 H T Fast Mode −90 −100 100 1000 10000 100000 f − Frequency − Hz Figure 10 DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE B S 0.20 L − 0.15 y arit 0.10 e n nli 0.05 o N −0.00 al nti −0.05 e er −0.10 Diff −0.15 − NL −0.20 D 0 32 64 96 128 160 192 224 256 Digital Output Code Figure 11 WWW.TI.COM 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.50 B S L − rity 0.25 a e n nli 0.00 o N al r g e −0.25 nt − I L N −0.50 I 0 32 64 96 128 160 192 224 256 Digital Output Code Figure 12 APPLICATION INFORMATION general function The TLV5624 is an 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: CODE 2REF [V] 2n where REF is the reference voltage and CODE is the digital input value within the range 0 to 2n−1, where 10 n = 8 (bits). The 16-bit word, consisting of control bits and a new DAC value, is illustrated in the data format section. A power on reset initially resets the internal latches to a defined state (all bits zero). serial interface The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5624 can be used in two basic modes: (cid:1) Four wire (with chip select) (cid:1) Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). Figure 13 shows an example with two TLV5624s connected directly to a TMS320 DSP. 10 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) TLV5624 TLV5624 CS FS DIN SCLK CS FS DIN SCLK TMS320 DSP XF0 XF1 FSX DX CLKX Figure 13. TMS320 Interface If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows an example of how to connect the TLV5624 to TMS320, SPI or Microwire using only three pins. TMS320 TLV5624 SPI TLV5624 Microwire TLV5624 DSP FSX FS I/O FS I/O FS DX DIN MOSI DIN SO DIN CLKX SCLK SCK SCLK SK SCLK CS CS CS Figure 14. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5624. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the 16th falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f (cid:1) 1 (cid:1)20MHz sclkmax t (cid:2)t whmin wlmin The maximum update rate is: fupdatemax(cid:1)16(cid:3)t 1(cid:2)t (cid:4)(cid:1)1.25MHz whmin wlmin Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5624 has to be considered, too. WWW.TI.COM 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION data format The 16-bit data word for the TLV5624 consists of two parts: (cid:1) Program bits (D15..D12) (cid:1) New data (D11..D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1 SPD PWR R0 8 Data bits 0 0 0 0 SPD: Speed control bit 1 → fast mode 0 →slow mode PWR: Power control bit 1 → power down 0 → normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC 0 1 Reserved 1 0 Reserved 1 1 Write data to control register The meaning of the 12 data bits depends on the selected register. For the DAC register, bits D11...D4 determine the new DAC output value: data bits: DAC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value 0 0 0 0 If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF2 X: don’t care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External NOTE: A 0.1µF bypass capacitor must be installed on the reference pin (pin 6). If internal reference is used a 10 µF capacitor must also be installed for reference voltage stability. CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. 12 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION Example: (cid:1) Set DAC output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 2. Write new DAC value and update DAC output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 New DAC output value 0 0 0 0 The DAC output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 15. Output Voltage 0 V DAC Code Negative Offset Figure 15. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. WWW.TI.COM 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:6)(cid:8)(cid:9)(cid:10)(cid:3) (cid:1)(cid:11) (cid:4)(cid:8)(cid:4)(cid:10)(cid:3) (cid:2)(cid:11)(cid:12) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:16)(cid:10)(cid:17)(cid:18)(cid:1) (cid:19)(cid:18)(cid:20)(cid:18)(cid:1)(cid:21)(cid:2)(cid:10)(cid:1)(cid:11)(cid:10)(cid:21)(cid:22)(cid:21)(cid:2)(cid:11)(cid:20) (cid:23)(cid:11)(cid:22)(cid:3)(cid:14)(cid:15)(cid:1)(cid:14)(cid:15) (cid:12)(cid:18)(cid:1)(cid:24) (cid:18)(cid:22)(cid:1)(cid:14)(cid:15)(cid:22)(cid:21)(cid:2) (cid:15)(cid:14)(cid:25)(cid:14)(cid:15)(cid:14)(cid:22)(cid:23)(cid:14) (cid:21)(cid:22)(cid:19) (cid:13)(cid:11)(cid:12)(cid:14)(cid:15) (cid:19)(cid:11)(cid:12)(cid:22) SLAS235B − JULY 1999 − REVISED APRIL 2004 APPLICATION INFORMATION power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 16 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 0.1 µF 3 6 4 5 Figure 16. Power-Supply Bypassing definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (E ) ZS Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (E ) G Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 14 WWW.TI.COM

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV5624CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 5624C & no Sb/Br) TLV5624CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 5624C & no Sb/Br) TLV5624CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADR & no Sb/Br) TLV5624CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADR & no Sb/Br) TLV5624ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 5624I & no Sb/Br) TLV5624IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADS & no Sb/Br) TLV5624IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADS & no Sb/Br) TLV5624IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADS & no Sb/Br) TLV5624IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 5624I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV5624CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV5624CDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 TLV5624IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 TLV5624IDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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