(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 (cid:1) (cid:1) 8-Bit Voltage Output DAC Buffered High-Impedance Reference Input (cid:1) (cid:1) Programmable Settling Time vs Power Monotonic Over Temperature Consumption (cid:1) Available in MSOP Package 3 µs in Fast Mode 9 µs in Slow Mode applications (cid:1) Ultra Low Power Consumption: (cid:1) Digital Servo Control Loops 900 µW Typ in Slow Mode at 3 V (cid:1) Digital Offset and Gain Adjustment 2.1 mW Typ in Fast Mode at 3 V (cid:1) (cid:1) Industrial Process Control Differential Nonlinearity...<0.2 LSB (cid:1) (cid:1) Machine and Motion Control Devices Compatible With TMS320 and SPI Serial (cid:1) Ports Mass Storage Devices (cid:1) Power-Down Mode description D OR DGK PACKAGE (TOP VIEW) The TLV5623 is a 8-bit voltage output digital-to- analog converter (DAC) with a flexible 4-wire DIN 1 8 VDD serial interface. The 4-wire serial interface allows SCLK 2 7 OUT glueless interface to TMS320, SPI, QSPI, and CS 3 6 REFIN Microwire serial ports. The TLV5623 is pro- FS 4 5 AGND grammed with a 16-bit serial string containing 4 control and 8 data bits. Developed for a wide range of supply voltages, the TLV5623 can operate from 2.7 V to 5.5 V. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a ClassAB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C to 70°C. The TLV5623I is characterized for operation from −40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE† MSOP (D) (DGK) 0°C to 70°C TLV5623CD TLV5623CDGK −40°C to 85°C TLV5623ID TLV5623IDGK †Available in tape and reel as the TLV5623CDR and the TLV5623IDR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:16)(cid:18)(cid:14)(cid:21)(cid:27)(cid:8)(cid:1)(cid:10)(cid:14)(cid:24) (cid:21)(cid:23)(cid:1)(cid:23) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$((cid:11) Copyright  2002 − 2004, Texas Instruments Incorporated (cid:16)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $-( $(!"% (cid:31)(cid:30) (cid:1)(.#% (cid:10)(cid:29)%$!’"((cid:29)$% %$#(cid:29),#!, /#!!#(cid:29)$0(cid:11) (cid:16)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)1 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+0 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)1 (cid:31)(cid:30) #++ )#!#"($(!%(cid:11) WWW.TI.COM 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 functional block diagram _ 6 REFIN + 1 Serial Input 10 8 DIN Register 8-Bit Data 8 7 x2 OUT Latch 2 SCLK 3 16 Cycle Update CS Timer 4 FS Power-On 2 Reset Speed/Power-Down Logic Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 5 Analog ground CS 3 I Chip select. Digital input used to enable and disable inputs, active low. DIN 1 I Serial digital data input FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. OUT 7 O DAC analog output REFIN 6 I Reference analog input voltage SCLK 2 I Serial digital clock input VDD 8 Positive power supply 2 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (V to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V + 0.3 V DD Operating free-air temperature range, T :TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT VDD = 5 V 4.5 5 5.5 V SSuuppppllyy vvoollttaaggee,, VVDDDD VDD = 3 V 2.7 3 3.3 V DVDD = 2.7 V 2 V HHiigghh--lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee,, VVIIHH DVDD = 5.5 V 2.4 V DVDD = 2.7 V 0.6 V LLooww--lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee,, VVIILL DVDD = 5.5 V 1 V Reference voltage, Vref to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD−1.5 V Reference voltage, Vref to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD−1.5 V Load resistance, RL 2 10 kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz TLV5623C 0 70 °C OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA TLV5623I −40 85 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 5 V, VREF = 2.048 V, Fast 0.9 1.35 mA NNoo llooaadd,, All inputs = AGND or VDD, Slow 0.4 0.6 mA DAC latch = 0x800 IIDDDD PPoowweerr ssuuppppllyy ccuurrrreenntt VDD = 3 V, VREF = 1.024 V Fast 0.7 1.1 mA NNoo llooaadd,, All inputs = AGND or VDD, Slow 0.3 0.45 mA DAC latch = 0x800 Power down supply current (see Figure 12) 1 µA Zero scale See Note 2 −68 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo ddBB Full scale See Note 3 −68 Power on threshold voltage, POR 2 V NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax] WWW.TI.COM 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) static DAC specifications R = 10 kΩ, C = 100 pF L L PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 8 bits INL Integral nonlinearity See Note 4 ±0.3 ±0.5 LSB DNL Differential nonlinearity See Note 5 ±0.07 ±0.2 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 ±10 mV EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C % of EG Gain error See Note 8 ±0.6 FS voltage Gain-error temperature coefficient See Note 9 10 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 255. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 255. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) − EZS(Tmin)]/Vref × 106/(Tmax − Tmin). 8. Gain error is the deviation from the ideal output (2Vref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin). output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Voltage output range RL = 10 kΩ 0 VDD−0.1 V % of FS Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ ±0.1 ±0.25 voltage reference input (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 0 VDD−1.5 V RI Input resistance 10 MΩ CI Input capacitance 5 pF Slow 525 kHz RReeffeerreennccee iinnppuutt bbaannddwwiiddtthh RREEFFIINN == 00..22 VVpppp ++ 11..002244 VV ddcc Fast 1.3 MHz REFIN = 1 Vpp at 1 kHz + 1.024 V dc Reference feed through −75 dB (see Note 10) NOTE 10:Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD ±1 µA IIL Low-level digital input current VI = 0 V ±1 µA CI Input capacitance 3 pF 4 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ttss((FFSS)) OOuuttppuutt sseettttlliinngg ttiimmee,, ffuullll ssccaallee RRSeLLe == N 11o00t ekk ΩΩ11,, CCLL == 110000 ppFF,, FSaloswt 39 52.05 µss RRLL == 1100 kkΩΩ,, CCLL == 110000 ppFF,, Fast 1 µs ttss((CCCC)) OOuuttppuutt sseettttlliinngg ttiimmee,, ccooddee ttoo ccooddee See Note 12 Slow 2 µs SSRR SSlleeww rraattee RRLL == 1100 kkΩΩ,, CCLL == 110000 ppFF,, Fast 3.6 VV//µss See Note 13 Slow 0.9 Glitch energy Code transition from 0x7F0 to 0x800 10 nV−s S/N Signal to noise 57 dB S/(N+D) Signal to noise + distortion ffss == 440000 KKSSPPSS ffoouutt == 11..11 kkHHzz,, 49 dB RRLL == 1100 kkΩΩ, CCLL == 110000 ppFF,, THD Total harmonic distortion −50 dB BBWW == 2200 kkHHzz Spurious free dynamic range 60 dB NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS−FS) Setup time, CS low before FS↓ 10 ns tsu(FS−CK) Setup time, FS low before first negative SCLK edge 8 ns Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising tsu(C16−FS) edge of FS 10 ns Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising tsu(C16−CS) edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup 10 ns time is between the FS rising edge and CS rising edge. twH Pulse duration, SCLK high 25 ns twL Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) Pulse duration, FS high 20 ns WWW.TI.COM 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION twL twH ÎÎÎÎÎ ÎÎÎ SCLK ÎÎÎÎÎ1 2 3 4 5 15 16 ÎÎÎ tsu(D) th(D) ÎÎÎÎ ÎÎÎÎ DIN D15 D14 D13 D12 D1 D0 ÎÎÎÎ ÎÎÎÎ tsu(FS-CK) tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(C16-FS) FS Figure 1. Timing Diagram 6 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 2.004 4.01 3 V Slow Mode, SOURCE VDD = 3 V, VDD = 5 V, Vref = 1 V, Vref = 2 V, 2.002 Full Scale 4.005 5 V Slow Mode, SOURCE Full Scale 2 3 V Fast Mode, SOURCE 4 V V − − 5 V Fast Mode, SOURCE e e ag 1.998 ag 3.995 olt olt V V ut 1.996 ut 3.99 p p ut ut O O − 1.994 − 3.985 O O V V 1.992 3.98 1.990 3.975 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 0 0.02 0.04 0.1 0.2 0.4 1 2 4 Load Current − mA Load Current − mA Figure 2 Figure 3 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 0.2 0.35 VDD = 3 V, VDD = 5 V, 0.18 Vref = 1 V, Vref = 2 V, Zero Code 0.3 Zero Code 0.16 V 0.14 V 0.25 − 3 V Slow Mode, SINK − ge 0.12 ge 5 V Slow Mode, SINK a a 0.2 Volt 0.1 Volt utput 0.08 utput 0.15 O 3 V Fast Mode, SINK O 5 V Fast Mode, SINK − 0.06 − O O 0.1 V V 0.04 0.05 0.02 0 0 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 0 0.02 0.04 0.1 0.2 0.4 1 2 4 Load Current − mA Load Current − mA Figure 4 Figure 5 WWW.TI.COM 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 1 1 VDD = 3 V, VDD = 5 V, Vref = 1 V, Vref = 2 V, Full Scale Full Scale Fast Mode A 0.8 A 0.8 m m − − nt Fast Mode nt e e urr urr y C 0.6 y C 0.6 pl pl p p u u S S − − D D D 0.4 D 0.4 I I Slow Mode Slow Mode 0.2 0.2 −55 −40 −25 0 25 40 70 85 125 −55 −40 −25 0 25 40 70 85 125 TA − Free-Air Temperature − C° TA − Free-Air Temperature − C° Figure 6 Figure 7 TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY 0 0 Vref = 1 V dc + 1 V p/p Sinewave, Vref = 1 V dc + 1 V p/p Sinewave, dB −10 Output Full Scale B −10 Output Full Scale on − −20 n − d −20 orti rtio onic Dist −−−3400 nic Disto −−−3400 m o m r a r H −50 a Total otal H −50 HD − −60 Fast Mode D − T −60 Slow Mode T −70 TH −70 −80 −80 0 5 10 20 30 50 100 0 5 10 20 30 50 100 f − Frequency − kHz f − Frequency − kHz Figure 8 Figure 9 8 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION AND NOISE TOTAL HARMONIC DISTORTION AND NOISE vs vs FREQUENCY FREQUENCY 0 0 B B − d Vref = 1 V dc + 1 V p/p Sinewave, − d Vref = 1 V dc + 1 V p/p Sinewave, e −10 Output Full Scale e −10 Output Full Scale s s oi oi N N d −20 d −20 n n A A n n o −30 o −30 orti orti Dist −−40 Dist −−40 c c ni ni o −50 o −50 m m ar Fast Mode ar Slow Mode H H al −60 al −60 ot ot T T − −70 − −70 D D H H T −80 T −80 0 5 10 20 30 50 100 0 5 10 20 30 50 100 f − Frequency − kHz f − Frequency − kHz Figure 10 Figure 11 SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE) 900 800 700 A µ nt − 600 e rr 500 u C y pl 400 p u S − 300 D D I 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 T − Time − ns Figure 12 WWW.TI.COM 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE B S 0.10 L − 0.08 y rit 0.06 a e 0.04 n nli 0.02 o N 0.00 ntial −0.02 e −0.04 r e Diff −0.06 − −0.08 NL −0.10 D 0 64 128 192 255 Digital Output Code Figure 13 INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.5 B LS 0.4 y − 0.3 rit 0.2 a e n 0.1 nli −0.0 o N al −0.1 gr −0.2 e nt −0.3 L − I −0.4 N −0.5 I 0 64 128 192 255 Digital Output Code Figure 14 10 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 APPLICATION INFORMATION general function The TLV5623 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: CODE 2REF [V] 2n where REF is the reference voltage and CODE is the digital input value within the range of 0 to 2n−1, where 10 n = 8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5623 can be used in two basic modes: (cid:1) Four wire (with chip select) (cid:1) Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5623s connected directly to a TMS320 DSP. TLV5623 TLV5623 CS FS DIN SCLK CS FS DIN SCLK TMS320 DSP XF0 XF1 FSX DX CLKX Figure 15. TMS320 Interface WWW.TI.COM 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins. TMS320 TLV5623 SPI TLV5623 Microwire TLV5623 DSP FSX FS SS FS I/O FS DX DIN MOSI DIN SO DIN CLKX SCLK SCLK SCLK SK SCLK CS CS CS Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f (cid:1) 1 (cid:1)20MHz SCLKmax t (cid:2)t wH(min) wL(min) The maximum update rate is: f (cid:1) (cid:3) 1 (cid:4)(cid:1)1.25MHz UPDATEmax 16 t (cid:2)t wH(min) wL(min) The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5623 has to be considered also. data format The 16-bit data word for the TLV5623 consists of two parts: (cid:1) Control bits (D15...D12) (cid:1) New DAC value (D11...D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X SPD PWR X New DAC value (8 bits) 0 0 0 0 X: don’t care SPD: Speed control bit. 1 → fast mode 0 → slow mode PWR: Power control bit. 1 → power down 0 → normal operation In power-down mode, all amplifiers within the TLV5623 are disabled. 12 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 APPLICATION INFORMATION TLV5623 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example how to connect the TLV5623 to a TMS320C203 DSP. The serial interface of the TLV5623 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections. In applications where only one synchronous serial peripheral is used, the interface can be simplified even further by pulling CS low all the time as shown in the figure. TMS320C203 TLV5623 VDD FS FS DX DIN CLKX SCLK OUT REF REFIN CS AGND RLOAD Figure 17. TLV5623 to DSP Interface  TLV5623 interfaced to MCS51 microcontroller hardware interfacing  Figure 18 shows an example of how to connect the TLV5623 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide the chip select and frame sync signals for the TLV5623.  MCS51 Controller TLV5623 VDD RxD SDIN TxD SCLK P3.4 CS P3.5 FS OUT REF REFIN RLOAD AGND  Figure 18. TLV5623 to MCS51 Controller Interface MCS is a registered trademark of Intel Corporation WWW.TI.COM 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19. Output Voltage 0 V DAC Code Negative Offset Figure 19. Effect of Negative Offset (single supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 0.1 µF 3 6 4 5 Figure 20. Power-Supply Bypassing 14 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:10) (cid:6)(cid:11)(cid:12)(cid:13)(cid:3) (cid:1)(cid:14) (cid:4)(cid:11)(cid:4)(cid:13)(cid:3) (cid:2)(cid:14)(cid:15) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:19)(cid:13)(cid:20)(cid:10)(cid:1) (cid:21)(cid:10)(cid:22)(cid:10)(cid:1)(cid:23)(cid:2)(cid:13)(cid:1)(cid:14)(cid:13)(cid:23)(cid:24)(cid:23)(cid:2)(cid:14)(cid:22) (cid:8)(cid:14)(cid:24)(cid:3)(cid:17)(cid:18)(cid:1)(cid:17)(cid:18)(cid:25) (cid:15)(cid:10)(cid:1)(cid:26) (cid:16)(cid:14)(cid:15)(cid:17)(cid:18) (cid:21)(cid:14)(cid:15)(cid:24) SLAS231B − JUNE 1999 − REVISED APRIL 2004 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (E ) ZS Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (E ) G Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. WWW.TI.COM 15

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV5623CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5623 & no Sb/Br) TLV5623CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADT & no Sb/Br) TLV5623CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADT & no Sb/Br) TLV5623CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5623 & no Sb/Br) TLV5623CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5623 & no Sb/Br) TLV5623ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5623 & no Sb/Br) TLV5623IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5623 & no Sb/Br) TLV5623IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADU & no Sb/Br) TLV5623IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADU & no Sb/Br) TLV5623IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADU & no Sb/Br) TLV5623IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5623 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV5623CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5623CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5623IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5623IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV5623CDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 TLV5623CDR SOIC D 8 2500 350.0 350.0 43.0 TLV5623IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 TLV5623IDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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