TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 features applications (cid:1) (cid:1) Dual 12-Bit Voltage Output DAC Digital Servo Control Loops (cid:1) (cid:1) Programmable Settling Time Digital Offset and Gain Adjustment – 3 µs in Fast Mode (cid:1) Industrial Process Control – 10 µs in Slow Mode (cid:1) Machine and Motion Control Devices (cid:1) Compatible With TMS320 and SPI Serial (cid:1) Mass Storage Devices Ports (cid:1) Differential Nonlinearity <0.5 LSB Typ P, D OR JG PACKAGE (TOP VIEW) (cid:1) Monotonic Over Temperature (cid:1) Direct Replacement for TLC5618A (C and I DIN 1 8 VDD Suffixes) SCLK 2 7 OUTB (cid:1) CS 3 6 REF Available in Q-Temp Automotive OUTA 4 5 AGND HighRel Automotive Applications Configuration Control/Print Support FK PACKAGE Qualification to Automotive Standards (TOP VIEW) D description NC DIN NC VDNC The TLV5618A is a dual 12-bit voltage output DAC 3 2 1 20 19 with a flexible 3-wire serial interface. The serial NC 4 18 NC interface is compatible with TMS320, SPI, SCLK 5 17 OUTB QSPI, and Microwire serial ports. It is NC 6 16 NC programmed with a 16-bit serial string containing 4 control and 12 data bits. CS 7 15 REF NC 8 14 NC The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer 9 10 11 12 13 features a Class-AB output stage to improve C A C D C N T N N N stability and reduce settling time. The program- U G O A mable settling time of the DAC allows the designer to optimize speed versus power dissipation. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges. The TLV5618AC is characterized for operation from 0°C to 70°C. The TLV5618AI is characterized for operation from –40°C to 85°C. The TLV5618AQ is characterized for operation from –40°C to 125°C. The TLV5618AM is characterized for operation from –55°C to 125°C. AVAILABLE OPTIONS PACKAGE TA PLASTIC DIP SOIC CERAMIC DIP 20 PAD LCCC (P) (D) (JG) (FK) 0°C to 70°C TLV5618ACP TLV5618ACD — — –40°C to 85°C TLV5618AIP TLV5618AID — — TLV5618AQD –40°C to 125°C — — — TLV5618AQDR –55°C to 125°C — — TLV5618AMJG TLV5618AMFK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 functional block diagram REF AGND VDD Power-On Power and Reset Speed Control 2 x2 OUTA DIN 12 12-Bit 12 DAC A Latch SCLK Serial Interface 12 and Buffer CS Control 12 12 12-Bit DAC B Latch x2 OUTB Terminal Functions TERMINAL II//OO//PP DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs. DIN 1 I Digital serial data input OUTA 4 O DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I Analog reference voltage input SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (V to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V + 0.3 V DD Operating free-air temperature range, T :TLV5618AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A TLV5618AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C TLV5618AQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C TLV5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C‡ POWER RATING POWER RATING POWER RATING D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW ‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for informational purposes only. recommended operating conditions MIN NOM MAX UNIT VDD = 5 V 4.5 5 5.5 SSuuppppllyy vvoollttaaggee, VVDD VV VDD = 3 V 2.7 3 3.3 Power on reset 0.55 2 V VDD = 2.7 V 2 HHiigghh-lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee, VVIH VV VDD = 5.5 V 2.4 VDD = 2.7 V 0.6 LLooww-lleevveell ddiiggiittaall iinnppuutt vvoollttaaggee, VVIL VV VDD = 5.5 V 1 VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 RReeffeerreennccee vvoollttaaggee, VVref ttoo RREEFF tteerrmmiinnaall VV VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 Load resistance, RL 2 kΩ Load capacitance, CL 100 pF Clock frequency, f(CLK) 20 MHz TLV5618AC 0 70 TLV5618AI –40 85 OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTAA °°CC TLV5618AQ –40 125 TLV5618AM –55 125 NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDDDD = 44..55 VV ttoo Fast 1.8 2.5 mmmAAA 555..555 VVV CCC &&& III SSllooww 00.88 11 NNoo llooaadd,, AAllll iinnpuuttss == AAGGNNDD oorr VVDDDD = 22..77 VV ttoo suffixes Fast 1.6 2.2 IIIDDDD PPPooowwweeerrr sssuuupppplllyyy cccuuurrrrrreeennnttt VVDDDD, DDAACC llaattcchh == AAllll oonneess 33.33 VV SSllooww 00.66 00.99 mmAA VVDDDD = 22..77 VV ttoo MM && QQ FFaasstt 11.88 22.33 mmAA 5.5 V suffixes Slow 0.8 1 Power down supply current 1 µA Zero scale, See Note 2 –65 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo ddBB Full scale, See Note 3 –65 NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 bits INL Integral nonlinearity See Note 4 ±2 ±4 LSB DNL Differential nonlinearity See Note 5 ±0.5 ±1 LSB Zero-scale error (offset error at zero EZS See Note 6 ±12 mV scale) Zero-scale-error temperature EZS (TC) See Note 7 3 ppm/°C coefficient VDD = 4.5 V – 5.5 V ±0.29 CC && II ssuuffffiixxeess %% ffullll EEGG GGaaiinn eerrrroorr SSeeee NNoottee 88 VDD = 2.7 V – 3.3 V ±0.6 ssccaallee VV M & Q suffixes VDD = 2.7 V – 5.5 V ±0.6 EG (TC) Gain-error temperature coefficient See Note 9 1 ppm/°C NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero-code and full-scale errors. 5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref ×106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ. 9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref ×106/(Tmax – Tmin). output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage range RL = 10 kΩ 0 VDD–0.4 V Output load regulation accuracy VO = 4.096 V, 2.048 V, ±0.29 % FS RL = 2 kΩ to 10 kΩ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) (continued) reference input PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 0 VDD–1.5 V RI Input resistance 10 MΩ CI Input capacitance 5 pF Fast 1.3 MHz RReeffeerreennccee iinnppuutt bbaannddwwiiddtthh RREEFF == 00.22 VVpp ++ 11.002244 VV ddcc Slow 525 kHz Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB NOTE 10:Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V –1 µA Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Fast 1 3 tts(FS) OOuuttppuutt sseettttlliinngg ttiimmee, ffuullll ssccaallee RRL = 1100 kkΩΩ, CCL = 110000 ppFF, SSeeee NNoottee 1111 µss Slow 3 10 Fast 1 tts(CC) OOuuttppuutt sseettttlliinngg ttiimmee, ccooddee ttoo ccooddee RRL = 1100 kkΩΩ, CCL = 110000 ppFF, SSeeee NNoottee 1122 µss Slow 2 Fast 3 SSRR SSlleeww rraattee RRL = 1100 kkΩΩ, CCL = 110000 ppFF, SSeeee NNoottee 1133 VV//µss Slow 0.5 Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD 5 nV–s SNR Signal-to-noise ratio 76 SINAD Signal-to-noise + distortion ffss == 110022 kkSSPPSS,, ffoouutt == 11 kkHHzz,, RRLL == 1100 kkΩΩ,, 68 ddBB THD Total harmonic distortion CLL = 100 pF –68 SFDR Spurious free dynamic range 72 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 digital input timing requirements MIN NOM MAX UNIT VDD = 5 V 5 CC aanndd II ssuuffffiixxeess nnss ttssuu((CCSS--CCKK)) SSeettuup ttiimmee,, CCSS llooww bbeeffoorree ffiirrsstt nneeggaattiivvee SSCCLLKK eeddggee VDD = 3 V 10 Q and M suffixes 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge before CS rising edge 10 ns tw(H) SCLK pulse width high 25 ns tw(L) SCLK pulse width low 25 ns VDD = 5 V 5 CC aanndd II ssuuffffiixxeess ttssuu((DD)) SSeettuup ttiimmee,, ddaattaa rreeaaddyy bbeeffoorree SSCCLLKK ffaalllliinngg eeddggee VDD = 3 V 10 nnss Q and M suffixes 8 VDD = 5 V 5 CC aanndd II ssuuffffiixxeess thh((DD)) Hold time, data held valid after SCLK fallingg edgge VDD = 3 V 10 ns Q and M suffixes 10 VDD = 5 V 25 tthh((CCSSHH)) HHoolldd ttiimmee, CCSS hhiigghh bbeettwweeeenn ccyycclleess nnss VDD = 3 V 50 timing requirements tw(L) tw(H) SCLK X 1 2 3 4 5 15 16 X tsu(D) th(D) DIN X D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 2.050 4.105 3 V Slow Mode, SOURCE VDD = 5 V 5 V Slow Mode, SOURCE VREF = 2 V 2.048 4.100 Full Scale V 2.046 3 V Fast Mode, SOURCE V 4.095 5 V Fast Mode, SOURCE – – e e g g a a olt 2.044 olt 4.090 V V ut ut p p ut 2.042 ut 4.085 O O – – O O V 2.040 V 4.080 VDD = 3 V VREF = 1 V 2.038 4.075 Full Scale 2.036 4.070 0 –0.01 –0.02 –0.5 –0.1 –0.2 –0.5 –0.8 –1 –2 0 –0.02 –0.04 –0.1 –0.2 –0.4 –0.8 –1 –2 –4 Load Current – mA Load Current – mA Figure 2 Figure 3 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs LOAD CURRENT LOAD CURRENT 0.20 0.35 VDD = 3 V VDD = 5 V 0.18 VREF = 1 V VREF = 2 V Zero Scale 0.30 Zero Scale 0.16 3 V Slow Mode, SINK 5 V Slow Mode, SINK ut Voltage – V 000...111240 ut Voltage – V 00..2250 utp 0.08 utp 0.15 O O – – 5 V Fast Mode, SINK O 0.06 O V 3 V Fast Mode, SINK V 0.10 0.04 0.05 0.02 0.00 0.00 0 0.01 0.02 0.05 0.1 0.2 0.5 0.8 1 2 0 0.02 0.04 0.1 0.2 0.4 0.8 1 2 4 Load Current – mA Load Current – mA Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 1.8 1.8 VDD = 3 V 1.6 VREF = 1 V 1.6 Full Scale Fast Mode Fast Mode VDD = 5 V A 1.4 A 1.4 VREF = 2 V m m Full Scale nt – 1.2 nt – 1.2 e e r r ur 1.0 ur 1.0 C C y y pl 0.8 pl 0.8 p p u u S S – 0.6 Slow Mode – 0.6 Slow Mode D D D D I 0.4 I 0.4 0.2 0.2 0.0 0.0 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TA – Free-Air Temperature – C TA – Free-Air Temperature – C Figure 6 Figure 7 TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY 0 0 B –10 VREF = 1 V + 1 VP/P Sinewave, –10 VREF = 1 V + 1 VP/P Sinewave, d Output Full Scale B Output Full Scale – d n –20 – –20 o n Distorti –30 stortio –30 onic –40 nic Di –40 3 V Slow Mode m o r –50 m –50 Ha 3 V Fast Mode ar Total –60 otal H –60 5 V Slow Mode – T D –70 – –70 H 5 V Fast Mode D T H –80 T –80 –90 –90 1 10 100 1 10 100 f – Frequency – kHz f – Frequency – kHz Figure 8 Figure 9 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs DIGITAL CODE B LS 4.0 – 3.5 r 3.0 ro 2.5 Er 2.0 y 1.5 rit 1.0 a 0.5 e n 0.0 nli –0.5 o –1.0 N –1.5 al –2.0 gr –2.5 nte ––33..50 – I –4.0 NL 0 512 1024 1536 2048 2560 3072 3584 4096 I Digital Code Figure 10 DIFFERENTIAL NONLINEARITY ERROR vs B S DIGITAL CODE L r – 1.00 o rr 0.75 E y rit 0.50 a ne 0.25 nli o 0.00 N al –0.25 nti e –0.50 r e Diff –0.75 – L –1.00 N 0 1024 2048 3072 4096 D Digital Code Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: CODE 2REF [V] 2n Where REF is the reference voltage and CODE is the digital input value within the range of 0 to 2n–1, where 10 n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPI, and Microwire. TMS320 TLV5618A SPI TLV5618A Microwire TLV5618A DSP FSX CS I/O CS I/O CS DX DIN MOSI DIN SO DIN CLKX SCLK SCK SCLK SK SCLK Figure 12. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be performed to program the TLV5618A. After the write operation(s), the holding registers or the control register are updated automatically on the next positive clock edge following the 16th falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f (cid:1) 1 (cid:1)20MHz sclkmax t (cid:2)t whmin wlmin The maximum update rate is: f (cid:1) (cid:3) 1 (cid:4)(cid:1)1.25MHz updatemax 16 t (cid:2)t whmin wlmin Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5618A should also be considered. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION data format The 16-bit data word for the TLV5618A consists of two parts: (cid:1) Program bits (D15..D12) (cid:1) New data (D11..D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1 SPD PWR R0 MSB 12 Data bits LSB SPD: Speed control bit 1 → fast mode 0 →slow mode PWR: Power control bit 1 → power down 0 → normal operation On power up, SPD and PWD are reset to 0 (slow mode and normal operation) The following table lists all possible combinations of register-select bits: register-select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Reserved The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: examples of operation (cid:1) Set DAC A output, select fast mode: Write new DAC A value and update DAC A output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. (cid:1) Set DAC B output, select fast mode: Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. (cid:1) Set DAC A value, set DAC B value, update both simultaneously, select slow mode: 1. Write data for DAC B to BUFFER: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 New DAC B value 2. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 New DAC A value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION examples of operation (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. (cid:1) Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13. Output Voltage 0 V DAC Code Negative Offset Figure 13. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (E ) ZS Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (E ) G Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9955701Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9955701Q2A TLV5618 AMFKB 5962-9955701QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9955701QPA TLV5618AM TLV5618ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618 & no Sb/Br) TLV5618ACDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618 & no Sb/Br) TLV5618ACDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618 & no Sb/Br) TLV5618ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618 & no Sb/Br) TLV5618ACP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TLV5618AC (RoHS) TLV5618AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618 & no Sb/Br) TLV5618AIDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618 & no Sb/Br) TLV5618AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618 & no Sb/Br) TLV5618AIP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 TLV5618AI (RoHS) TLV5618AIPE4 ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 TLV5618AI (RoHS) TLV5618AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9955701Q2A TLV5618 AMFKB TLV5618AMJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 TLV5618AMJG TLV5618AMJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9955701QPA TLV5618AM Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV5618AQD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V5618A & no Sb/Br) TLV5618AQDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM V5618A & no Sb/Br) TLV5618AQDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V5618A & no Sb/Br) TLV5618AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM V5618A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV5618A, TLV5618AM : •Catalog: TLV5618A •Enhanced Product: TLV5618A-EP, TLV5618A-EP •Military: TLV5618AM NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV5618ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5618AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5618AQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5618AQDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV5618ACDR SOIC D 8 2500 350.0 350.0 43.0 TLV5618AIDR SOIC D 8 2500 350.0 350.0 43.0 TLV5618AQDR SOIC D 8 2500 350.0 350.0 43.0 TLV5618AQDRG4 SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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