TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN FEATURES APPLICATIONS 1 • EightVoltageOutputDACsinOnePackage • DigitalServoControlLoops 2 – TLV5610...12-Bit • DigitalOffsetandGainAdjustment – TLV5608...10-Bit • IndustrialProcessControl • MachineandMotionControlDevices – TLV5629...8-Bit • ProgrammableSettlingTimevsPower • MassStorageDevices Consumption DW OR PW PACKAGE – 1m sInFastMode (TOP VIEW) – 3m sInSlowMode DGND 1 20 DV DD • CompatibleWithTMS320andSPI™Serial DIN 2 19 DOUT Ports SCLK 3 18 LDAC • MonotonicOverTemperature FS 4 17 MODE • LowPowerConsumption: PRE 5 16 REF OUTE 6 15 OUTD – 18mWInSlowModeat3-V OUTF 7 14 OUTC – 48mWInFastModeat3-V OUTG 8 13 OUTB • ReferenceInputBuffers OUTH 9 12 OUTA • Power-DownMode AGND 10 11 AVDD • Buffered,HighImpedanceReferenceInputs • DataOutputforDaisy-Chaining DESCRIPTION The TLV5610, TLV5608, and TLV5629 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwireserialports.Itisprogrammedwitha16-bitserialstringcontaining4controland12databits. Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs, andadataoutputwhichcanbeusedtocascademultipledevices. The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be connectedtothesupplyvoltage. Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V, and can operate on two separate analog and digital power supplies. The devices are available in 20-pin SOIC and TSSOPpackages. AVAILABLEOPTIONS PACKAGE T A SMALLOUTLINE(DW) TSSOP(PW) RESOLUTION TLV5610IDW TLV5610IPW 12 -40°Cto85°C TLV5608IDW TLV5608IPW 10 TLV5629IDW TLV5629IPW 8 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola,Inc. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2000–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. FUNCTIONALBLOCKDIAGRAM REF 12/10/8 12/10/8 12/10/8 X2 OUTA DAC A DAC A Holding Latch Latch SCLK DIN DOUT Serial 12 Interface FS 8 OUT MODE DAC B, C, D, E, F, G and H B, C, D, Same as DAC A E, F, G PRE and H LDAC TerminalFunctions TERMINAL I/O DESCRIPTION NAME NO. AGND 10 I Analogground AV 11 I Analogpowersupply DD DGND 1 I Digitalground DIN 2 I Digitalserialdatainput DOUT 19 O Digitalserialdataoutput DV 20 I Digitalpowersupply DD FS 4 I Framesyncinput LoadDAC.TheDACoutputsareonlyupdated,ifthissignalislow.Itisan LDAC 18 I asynchronousinput. MODE 17 I DSP/m Cmodepin.High=m Cmode,NC=DSPmode. PRE 5 I Presetinput REF 16 I Voltagereferenceinput SCLK 3 I Serialclockinput OUTA-OUTH 6-9,12-15 O DACoutputsA,B,C,D,E,F,GandH 2 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) UNIT Supplyvoltage(AV ,DV toGND) 7V DD DD Referenceinputvoltage -0.3VtoAV +0.3V DD Digitalinputvoltagerange -0.3VtoDV +0.3V DD Operatingfree-airtemperaturerange,T -40°Cto85°C A Storagetemperaturerange,T -65°Cto150°C stg Leadtemperature1,6mm(1/16inch)fromcasefor10seconds 260°C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,AV ,DV 5-Voperation 4.5 5 5.5 V DD DD 3-Voperation 2.7 3 3.3 V DV =2.7V 2 DD High-leveldigitalinputvoltage,V V IH DV =5.5V 2.4 DD DV =2.7V 0.6 DD Low-leveldigitalinputvoltage,V V IL DV =5.5V 1 DD Referencevoltage,V AV =5V GND 4.096 AV V ref DD DD AV =3V GND 2.048 AV V DD DD Loadresistance,R 2 kΩ L Loadcapacitance,C 100 pF L Clockfrequency,f 30 MHz CLK Operatingfree-airtemperature,T -40 85 °C A ELECTRICAL CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,supplyvoltages,andreferencevoltages(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWERSUPPLY Fast Noload,V =4.096V,See (1) 16 21 I Powersupplycurrent ref mA DD Slow Allinputs=DVDDorGND 6 8 Powerdownsupplycurrent 0.1 m A POR Poweronthreshold 2 V PSRR Powersupplyrejectionratio Fullscale,See (2) -60 dB (1) I ismeasuredwhilecontinuouslywritingcode2048totheDAC.ForV <DV -0.7VandV >0.7V,supplycurrentincreases. DD IH DD IL (2) PowersupplyrejectionratioatfullscaleismeasuredbyvaryingAV andisgivenby: DD PSRR=20log[(E (AV max)-E (AV min))/V max] G DD G DD DD Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) overrecommendedoperatingfree-airtemperaturerange,supplyvoltages,andreferencevoltages(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT STATICDACSPECIFICATIONS TLV5610 12 Resolution TLV5608 10 Bits TLV5629 8 TLV5610 Code40to4095 ±2 ±6 Integralnonlinearity(INL) TLV5608 V =2V,4V Code20to1023 ±0.5 ±2 LSB ref TLV5629 Code6to255 ±0.3 ±1 TLV5610 Code40to4095 ±0.5 ±1 Differentialnonlinearity(DNL) TLV5608 V =2V,4V Code20to1023 ±0.1 ±1 LSB ref TLV5629 Code6to255 ±0.1 ±1 E Zero-scaleerror(offseterroratzeroscale) ±30 mV ZS E TC Zero-scale-errortemperaturecoefficient 30 m V/°C ZS %ofFS E Gainerror ±0.6 G voltage E TC Gainerrortemperaturecoefficient 10 ppm/°C G OUTPUTSPECIFICATIONS AV - V Voltageoutputrange R =10kΩ 0 DD V O L 0.4 %ofFS Outputloadregulationaccuracy R =2kΩvs10kΩ ±0.3 L voltage REFERENCEINPUT V Referenceinputvoltage 0 AV V I DD R Referenceinputresistance 100 kΩ I C Referenceinputcapacitance 5 pF I V =0.4V +2.048Vdc, Fast ref pp 2.2 Inputcode=0x800 Referenceinputbandwidth MHz V =2V at1kHz+2.048Vdc, Slow Sreeef (3) pp 1.9 Referencefeedthrough -84 dB DIGITALINPUT I High-leveldigitalinputcurrent V =V 1 m A IH I DD I Low-leveldigitalinputcurrent V =0V -1 m A IL I C Inputcapacitance 8 pF I DIGITALOUTPUT V High-leveldigitaloutputvoltage R =10kΩ 2.6 V OH L V Low-leveldigitaloutputvoltage R =10kΩ 0.4 V OL L R =10kΩ,C =20pF,Includes Outputvoltagerisetime L L 7 20 ns propagationdelay (3) ReferencefeedthroughismeasuredattheDACoutputwithaninputcode=0x000. 4 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 ELECTRICAL CHARACTERISTICS (continued) overrecommendedoperatingfree-airtemperaturerange,supplyvoltages,andreferencevoltages(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGOUTPUTDYNAMICPERFORMANCE Fast 1 3 t Outputsettlingtime(fullscale) R =10kΩ,C =100pF,See (4) m s s(FS) L L Slow 3 7 t Outputsettlingtime,codeto Fast R =10kΩ,C =100pF,See (5) 0.5 1 m s s(CC) code Slow L L 1 2 Fast 4 10 SR Slewrate R =10kΩ,C =100pF,See (6) V/m s L L Slow 1 3 Glitchenergy See (7) 4 nV-s Channelcrosstalk 10kHzsine,4V -90 dB PP (4) Settlingtimeisthetimefortheoutputsignaltoremainwithin+0.5LSBofthefinalmeasuredvalueforadigitalinputcodechangeof 0x80to0xFFFand0xFFFto0x080,respectively.Assuredbydesign;nottested. (5) Settlingtimeisthetimefortheoutputsignaltoremainwithin+0.5LSBofthefinalmeasuredvalueforadigitalinputcodechangeofone count.Themaxtimeappliestocodechangesnearzeroscaleorfullscale.Assuredbydesign;nottested. (6) SlewratedeterminesthetimeittakesforachangeoftheDACoutputfrom10%to90%fullscalevoltage. (7) Codetransition:TLV5610-0x7FFto0x800,TLV5608-0x7FCto0x800,TLV5629-0x7F0to0x800 TIMING REQUIREMENTS DIGITALINPUTS MIN NOM MAX UNIT t Setuptime,FSlowbeforenextnegativeSCLKedge 8 ns su(FS-CK) Setuptime,16thnegativeedgeafterFSlowonwhichbitD0issampledbefore tsu(C16-FS) risingedgeofFS.m Cmodeonly 10 ns t m Cmode,setuptime,FShighbefore17thnegativeedgeofSCLK. 10 ns su(FS-C17) t DSPmode,setuptime,SLCKlowbeforeFSlow. 5 ns su(CK-FS) t LDACdurationlow 10 ns wL(LDAC) t SCLKpulsedurationhigh 16 ns wH t SCLKpulsedurationlow 16 ns wL t Setuptime,datareadybeforeSCLKfallingedge 8 ns su(D) t Holdtime,dataheldvalidafterSCLKfallingedge 5 ns h(D) t FSdurationhigh 10 ns wH(FS) t FSdurationlow 10 ns wL(FS) SeeAC t Settlingtime s specs Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION twH twL SCLK X 1 2 3 4 16 17 X th(D) tsu(D) DIN X D15 D14 D13 D12 D1 D0 X † † † † † † DOUT X D15 D14 D13 D12 D1 D0 X tsu(FS - CK) tsu(FS - C17) twH(FS) tsu(C16 - FS) FS (mC mode) tsu(CK - FS) twL(FS) FS X (DSPMode) †Previous input data Figure1.SerialInterfaceTiming twL(LDAC) LDAC ts ±0.5 LSB OUTx Figure2.OutputTiming 6 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 TYPICAL CHARACTERISTICS OUTPUTLOADREGULATION OUTPUTLOADREGULATION 1 1 VDD = 3 V, VDD = 5 V, 0.9 Vref = 2 V, 0.9 Vref = 4 V, Zero Scale Zero Scale 0.8 0.8 V Fast Fast ge − 0.7 e − V 0.7 a g Volt 0.6 olta 0.6 put 0.5 ut V 0.5 Out 0.4 utp 0.4 − − O O V 0.3 O 0.3 V 0.2 0.2 0.1 0.1 Slow Slow 0 0 0 0.5 1 1.5 2 0 0.5 1 1.5 2 Sinking Current − mA Sinking Current − mA Figure3. Figure4. OUTPUTLOADREGULATION OUTPUTLOADREGULATION 2.06 4.12 VDD = 3 V, VDD = 5 V, 2.055 VFurelfl =S c2a Vle, 4.11 Fast VFurelfl =S c4a Vle, Slow Voltage − V 2.20.4055 Fast Voltage − V 44.0.19 Slow Output 2.04 Output 4.08 − − 4.07 O O V 2.035 V 4.06 2.03 4.05 2.025 4.04 −0.05 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 Sourcing Current − mA Sourcing Current − mA Figure5. Figure6. Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) TLV5610 INTEGRALNONLINEARITY vs CODE B 4 S L 3 − rity 2 a ne 1 nli o 0 N al −1 r g nte −2 − I −3 L N I −4 0 1024 2048 3072 4096 Code Figure7. TLV5610 DIFFERENTIALNONLINEARITY vs CODE B S 1.0 L − 0.8 y rit 0.6 a e 0.4 n nli 0.2 o N −0.0 al nti −0.2 re −0.4 e Diff −0.6 − −0.8 L N −1.0 D 0 1024 2048 3072 4096 Code Figure8. 8 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 TYPICAL CHARACTERISTICS (continued) TLV5608 INTEGRALNONLINEARITY vs CODE B 2.0 S L 1.5 − rity 1.0 a ne 0.5 nli o 0.0 N al −0.5 r g nte −1.0 − I −1.5 L N I −2.0 0 256 512 768 1024 Code Figure9. TLV5608 DIFFERENTIALNONLINEARITY vs CODE B S 1.0 L − 0.8 y rit 0.6 a e 0.4 n nli 0.2 o N −0.0 al nti −0.2 re −0.4 e Diff −0.6 − −0.8 L N −1.0 D 0 256 512 768 1024 Code Figure10. Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) TLV5629 INTEGRALNONLINEARITY vs CODE 0.5 B LS 0.4 y − 0.3 rit 0.2 a e n 0.1 onli 0 N al −0.1 gr −0.2 e nt −0.3 − I −0.4 L N −0.5 I 0 50 100 150 200 250 Code Figure11. TLV5629 DIFFERENTIALNONLINEARITY vs CODE B S 0.5 L − 0.4 y rit 0.3 a e 0.2 n nli 0.1 o N 0 ntial −0.1 e −0.2 r e Diff −0.3 − −0.4 NL −0.5 D 0 50 100 150 200 250 Code Figure12. 10 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 APPLICATION INFORMATION GENERAL FUNCTION The TLV5610, TLV5608, and TLV5629 are 8-channel, 12-bit, single-supply DACs, based on a resistor string architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer, a resistorstring,andarail-to-railoutputbuffer. Theoutputvoltage(fullscaledeterminedbyexternalreference)foreachchannelisgivenby: CODE REF [V] 0x1000 (1) where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for theTLV5610,0x000to0xFFCfortheTLV5608,and0x000to0xFF0fortheTLV5629. POWER ON RESET (POR) The built-in power-on-reset circuit controls the output voltage after power up. On power up, all latches including the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low. The DAC outputs may have a small offset error produced by the output buffer. The registers remains at zero until a valid write sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is important to know the state of the outputs of the DAC after power up. All digital inputs must be logic low until the digital and analog supplies are applied. Any logic high voltages applied to the logic input pins when power is not applied to AV and DV , may power the device logic circuit through the overvoltage protection diode causing DD DD an undesired operation. When separate analog (AV ) and digital (DV ) supplies are used, AV must come up DD DD DD firstbeforeDV ,toensurethatthepower-on-resetcircuitoperatescorrectly. DD SERIAL INTERFACE A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an asynchronousinput.Itcanbeheldlowifasimultaneousupdateofalleightchannelsisnotneeded. Fordaisy-chaining,DOUTprovidesthedatasampledonDINwithadelayof16clockcycles. DSP Mode: SCLK FS DIN X D15 D14 D1 D0 E15 E14 E1 E0 X X X F15 F15 m C Mode: SCLK FS DIN X D15 D14 D1 D0 X E15 E14 E1 E0 X X F15 F15 Figure13.DataSampledonDIN Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 SLAS268G–MAY2000–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com DifferencebetweenDSPmode(MODE=N.C.or0)andm C(MODE=1)mode: • In m C mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before the16thfallingclockedge,thedatatransferiscancelled.TheDACisupdatedafterarisingedgeonFS. • InDSPmode,FSneedstostaylowfor20nsandcangohighbeforethe16thfallingclockedge. • In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle. This extrafallingSCLKedgehastohappenatleast5nsbeforeFSgoeslow,t ≥5ns. su(CK-FS) • In m C mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative SCLKedgeisnotallowedtooccurwithin10nsafterFSgoesHIGHtofinishtheWRITEcycle(t ). su(FS-C17) SERIAL CLOCK FREQUENCY AND UPDATE RATE Themaximumserialclockfrequencyisgivenby: f (cid:2) 1 (cid:2)30MHz sclkmax t (cid:1)t whmin wlmin (2) Themaximumupdaterateis: 1 fupdatemax(cid:2) (cid:2)1.95MHz 16(cid:3)twhmin(cid:1)twlmin(cid:4) (3) Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the DAChastobeconsideredalso. DATA FORMAT The16-bitdatawordconsistsoftwoparts: • Addressbits(D150D12) • Databits(D110D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 DATA RegisterMap A3 A2 A1 A0 FUNCTION 0 0 0 0 DACA 0 0 0 1 DACB 0 0 1 0 DACC 0 0 1 1 DACD 0 1 0 0 DACE 0 1 0 1 DACF 0 1 1 0 DACG 0 1 1 1 DACH 1 0 0 0 CTRL0 1 0 0 1 CTRL1 1 0 1 0 Preset 1 0 1 1 Reserved 1 1 0 0 DACAandB 1 1 0 1 DACCandD 1 1 1 0 DACEandF 1 1 1 1 DACGandH 12 SubmitDocumentationFeedback Copyright©2000–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TLV5608TLV5610TLV5629

TLV5608 TLV5610 TLV5629 www.ti.com.................................................................................................................................................... SLAS268G–MAY2000–REVISEDNOVEMBER2008 DAC A-H AND TWO-CHANNEL REGISTERS Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the complementofonechannelbywritingtooneofthefourtwo-channelregisters(DACAandBetc.). TheTLV5610decodesall12databits.TheTLV5608decodesD11toD2(D1andD0areignored).The TLV5629 decodesD11toD4(D3toD0areignored). PRESET TheoutputsoftheDACchannelscanbedrivensimultaneouslytoapredefinedvaluestoredin the preset register by driving the PRE input pin low and asserting the LDAC input pin. The preset register is cleared (set to zero) by the POR circuit after power up. Therefore, it must be written with a predefined value before asserting the PRE pinlow,unlesszeroisthedesiredpresetvalue.ThePREinputisasynchronoustotheclock. CTRL0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X PD DO X X IM PD :Fulldevicepowerdown 0=normal 1=powerdown DO :Digitaloutputenable 0=disable 1=enable IM :Inputmode 0=straightbinary 1=twoscomplement X :Reserved If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to daisy-chainmultipleDACsononeserialbus. CTRL1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X P P P P S S S S GH EF CD AB GH EF CD AB P :PowerdownDAC 0=normal 1=powerdown XY XY S :SpeedDAC 0=slow 1=fast XY XY XY :DACpairAB,CD,EF,orGH In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by settingthePXYbitwithinthedatawordto1. There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting S to 1 and XY slowmodeisselectedbysettingS to0. XY REFERENCE The DAC reference can be sourced externally using precision reference circuits. Since the reference input is buffered,itcanbeconnectedtothesupplyvoltage. BUFFERED AMPLIFIER The DAC outputs are buffered by an amplifier with a gain of two, which are configurable as Class A (fast mode) or Class AB (slow or low-power mode). The output buffers have near rail-to-rail output with short-circuit protection,andcanreliablydrivea2-kΩloadwitha100-pFloadcapacitance. Copyright©2000–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TLV5608TLV5610TLV5629

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV5608IDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5608I & no Sb/Br) TLV5608IDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5608I & no Sb/Br) TLV5608IPW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5608 & no Sb/Br) TLV5608IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5608 & no Sb/Br) TLV5608IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5608 & no Sb/Br) TLV5608IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5608 & no Sb/Br) TLV5610IDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5610I & no Sb/Br) TLV5610IDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5610I & no Sb/Br) TLV5610IPW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5610 & no Sb/Br) TLV5610IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5610 & no Sb/Br) TLV5629IDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5629I & no Sb/Br) TLV5629IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5629I & no Sb/Br) TLV5629IDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5629I & no Sb/Br) TLV5629IPW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5629 & no Sb/Br) TLV5629IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5629 & no Sb/Br) TLV5629IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5629 & no Sb/Br) TLV5629IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TY5629 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV5608IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLV5608IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TLV5610IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLV5610IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TLV5629IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLV5629IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV5608IDWR SOIC DW 20 2000 350.0 350.0 43.0 TLV5608IPWR TSSOP PW 20 2000 350.0 350.0 43.0 TLV5610IDWR SOIC DW 20 2000 350.0 350.0 43.0 TLV5610IPWR TSSOP PW 20 2000 350.0 350.0 43.0 TLV5629IDWR SOIC DW 20 2000 350.0 350.0 43.0 TLV5629IPWR TSSOP PW 20 2000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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