TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Low-Power Mono Audio DAC With Embedded miniDSP and Mono Class-D Speaker Amplifier CheckforSamples:TLV320DAC3120 1 INTRODUCTION – Class-D:2.7V–5.5V(SPKVDD ≥ AVDD) 1.1 Features • 5-mm× 5-mm32-QFNPackage • MonoAudioDACWith95-dBSNR 123 1.2 Applications • Instruction-ProgrammableEmbeddedminiDSP • Supports8-kHzto192-kHzSampleRates • PortableAudioDevices • MonoClass-DBTLSpeakerDriver(2.5WInto • eBook 4Ω or1.6WInto8Ω) • PortableNavigationDevices • MonoHeadphone/LineoutDriver • TwoSingle-EndedInputsWithOutputMixing 1.3 Description andLevelControl • MicrophoneBias The TLV320DAC3120 is a low-power, highly • Built-inDigitalAudioProcessingBlocksWith integrated, high-performance mono DAC with 24-bit User-ProgrammableBiquad,FIRFilters,and monoplayback. DRC The device integrates several analog features, such • DigitalSine-WaveGeneratorforBeepsand as a microphone bias, headphone drivers, and a Clicks(PRB_P25) mono speaker driver capable of driving a 4-Ω load. • ProgrammableDigitalAudioProcessorfor The TLV320DAC3120 has a fully programmable BassBoost/Treble/EQWithuptoSixBiquads miniDSP for digital audio processing. The digital forPlayback audio data format is programmable to work with • PinControlorRegisterControlforDigital popular audio standard protocols (I2S, left/right- PlaybackVolume-ControlSettings justified) in master, slave, DSP, and TDM modes. • IntegratedPLLUsedforProgrammableDigital Bass boost, treble, or EQ can be supported by the AudioProcessor • I2S,Left-Justified,Right-Justified,DSP,and programmable digital-signal processing block. An on- TDMAudioInterfaces chip PLL provides the high-speed clock needed by • I2CControlWithRegisterAuto-Increment the digital signal-processing block. The volume level can be controlled by either a pin control or by register • FullPower-DownControl control. The audio functions are controlled using the • PowerSupplies: I2Cserialbus. – Analog:2.7V–3.6V – DigitalCore:1.65V–1.95V The TLV320DAC3120 is available in a 32-pin QFN – DigitalI/O:1.1V–3.6V package. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. MATLABisatrademarkofTheMathWorks,Inc. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2009–2012,TexasInstrumentsIncorporated specifications per the terms of the Texas Instruments standard warranty. Production processingdoesnotnecessarilyincludetestingofallparameters.

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. AVSS AVDD HPVSS HPVDD SPKVSS SPKVSS SPKVDD SPKVDD VOL/MICDET 7-BitADC P0/R116 Left and Right Audio Output Stage Volume-Control Register Power Management P0/R117 P1/R33–R34 GPIO1 GPIO De-Pop SDA I2C and SCL Soft Start Note: Normally, MCLK is PLLinput; RC CLK however, BCLK or GPIO1 can also be PLLinput. Analog Class-D Speaker MCLK PLL Attenuation Driver 0 dB to–78 dB and Mute 6 dB to 24 dB P0/R63 (0.5-dB steps) (6-dB steps) Digital LData Mono DAC PM1IX/RE3R5 P1/R38 P1/R42 SPKP WCLK Audio R Data Digital Vol S SPKP miniDSP 24 dB to DAC SDIN Processing (L+R)/2 Data Mute SPKM and SPKM BCLK Serial P0/R64 Analog ClassA/B Interface Attenuation Headphone/Lineout 0 dB to–78 dB Driver RESET and Mute 0 dB to 9 dB (0.5-dB steps) (1-dB steps) P1/R36 P1/R40 AIN1 HPOUT P1/R30–R31 AIN2 P1/R46 2 V/2.5 V/AVDD MICBIAS IOVSS IOVDD DVSS DVDD B0360-01 Figure1-1.FunctionalBlockDiagram NOTE Thisdatamanualis designedusingPDFdocument-viewingfeatures thatallowquick access to information. For example, performing a global search on "page 0 / register 27" produces all references to this page and register in a list. This makes is easy to traverse the list and find allinformationrelatedto apage andregister. Note thatthesearch string mustbe of the indicated format. Also, this document includes document hyperlinks to allow the user to quickly find a document reference. To come back to the original page, click the green left arrownearthePDFpagenumberatthebottomofthefile.Thehot-keyforthisfunctionisalt- left arrow on the keyboard. Another way to find information quickly is to use the PDF bookmarks. 2 INTRODUCTION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information OPERATING TRANSPORTMEDIA, PACKAGE PRODUCT PACKAGE TEMPERATURE ORDERINGNUMBER QUANTITY DESIGNATOR RANGE TLV320DAC3120IRHBT Tapeandreel,250 TLV320DAC3120 QFN-32 RHB –40°Cto85°C TLV320DAC3120IRHBR Tapeandreel,3000 2.2 Device Information RHB Package (Top View) D D S D D S V M P V V M S D K K K K K K S D P P P P P P V V S S S S S S D A 24 23 22 21 20 19 18 17 SPKVSS 25 16 AVSS SPKP 26 15 NC HPOUT 27 14 AIN2 HPVDD 28 13 AIN1 TLV320DAC3120 HPVSS 29 12 MICBIAS NC 30 11 VOL/MICDET RESET 31 10 SCL GPIO1 32 9 SDA 1 2 3 4 5 6 7 8 S D D C N K K K VS VD VD N DI CL CL CL O O D W B M I I P0048-12 Table2-1.TERMINALFUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AIN1 13 I Analoginput#1routedtooutputmixer AIN2 14 I Analoginput#2routedtooutputmixer AVDD 17 – Analogpowersupply AVSS 16 – Analogground BCLK 7 I/O Audioserialbitclock DIN 5 I Audioserialdatainput DVDD 3 – Digitalpower–digitalcore DVSS 18 – Digitalground GPIO1 32 I/O General-purposeinput/outputandmultifunctionpin HPOUT 27 O Headphone/lineoutdriveroutput HPVDD 28 – Headphone/linedriverandPLLpower HPVSS 29 – Headphone/linedriverandPLLground IOVDD 2 – Interfacepower IOVSS 1 – Interfaceground MCLK 8 I Exterrnalmasterclock MICBIAS 12 O Micophonebiasvoltage Copyright©2009–2012,TexasInstrumentsIncorporated PACKAGEANDSIGNALDESCRIPTIONS 3 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table2-1.TERMINALFUNCTIONS(continued) TERMINAL I/O DESCRIPTION NAME NO. NC 4,15,30 – Noconnection RESET 31 I Devicereset SCL 10 I/O I2Ccontrol-busclockinput SDA 9 I/O I2Ccontrol-busdatainput SPKM 19,23 O Class-Dspeakerdriverinvertingoutput SPKP 22,26 O Class-Dspeakerdrivernoninvertingoutput SPKVDD 21,24 – Class-Dspeakerdriverpowersupply SPKVSS 20,25 – Class-Dspeakerdriverpower-supplyground VOL/MICDET 11 I Volumecontrolormicrophone/headphone/headsetdetection WCLK 6 I/O Audioserialwordclock 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) VALUE UNIT AVDDtoAVSS –0.3to3.9 V DVDDtoDVSS –0.3to2.5 V HPVDDtoHPVSS –0.3to3.9 V SPKVDDtoSPKVSS –0.3to6 V IOVDDtoIOVSS –0.3to3.9 V Digitalinputvoltage IOVSS–0.3toIOVDD+0.3 V Analoginputvoltage AVSS–0.3toAVDD+0.3 V Operatingtemperaturerange –40to85 °C Storagetemperaturerange –55to150 °C Junctiontemperature(T Max) 105 °C J Powerdissipation (T Max–T )/R W J A θJA QFNpackage R Thermalimpedance(withthermalpadsolderedtoboard) 35 °C/W θJA (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. Table3-1.SystemThermalCharacteristics(1) PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C 2.3W 28.57mW/°C 1W 0.6W (1) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer3-in.×3- in.(7.62-cm×7.62-cm)PCB. 4 ELECTRICALSPECIFICATIONS Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 3.2 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6 DVDD ReferencedtoDVSS(2) 1.65 1.8 1.95 V HPVDD Power-supplyvoltagerange ReferencedtoHPVSS(2) 2.7 3.3 3.6 SPKVDD(1) ReferencedtoSPKVSS(2) 2.7 5.5 IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6 Speakerimpedance Loadappliedacrossclass-Doutputpins(BTL) 4 Ω Headphoneimpedance AC-coupledtoR 16 Ω L Analogaudiofull-scaleinput V AVDD=3.3V,single-ended 0.707 V I voltage RMS Monolineoutputload AC-coupledtoR 10 kΩ impedance L MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz SCL SCLclockfrequency 400 kHz T Operatingfree-airtemperature –40 85 °C A (1) Tominimizebattery-currentleakage,theSPKVDDandSPKVDDvoltagelevelsshouldnotbebelowtheAVDDvoltagelevel. (2) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.2Vmaximumforanycombinationofground signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHPVSSandDVSS. (3) Themaximuminputfrequencyshouldbe50MHzforanydigitalpinusedasageneral-purposeclock. 3.3 Electrical Characteristics At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz, S CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted) S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INTERNALOSCILLATOR—RC_CLK Oscillatorfrequency 8.2 MHz VOLUMECONTROLPIN(ADC);VOL/MICDETpinenabled VOL/MICDETpinconfiguredasvolumecontrol(page 0.5× Inputvoltagerange 0/register116,bitD7=1andpage0/register67, 0 V AVDD bitD7=0) Inputcapacitance 2 pF Volumecontrolsteps 128 Steps MICROPHONEBIAS Page1/register46,bitsD1–D0=10 2.25 2.5 2.75 Voltageoutput V Page1/register46,bitsD1–D0=01 2 At4-mAloadcurrent,page1/register46,bitsD1–D0 5 =10(MICBIAS=2.5V) Voltageregulation mV At4-mAloadcurrent,page1/register46,bitsD1–D0 7 =01(MICBIAS=2V) Copyright©2009–2012,TexasInstrumentsIncorporated ELECTRICALSPECIFICATIONS 5 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com ElectricalCharacteristics(continued) At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz, S CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted) S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DACHEADPHONEOUTPUT,AC-COUPLEDLOAD=16Ω(SINGLE-ENDED), DRIVERGAIN=0dB,PARASITICCAPACITANCE=30pF Full-scaleoutputvoltage Outputcommon-modesetting=1.65V 0.707 Vrms (0dB) SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1) (2) 80 95 dB THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB Totalharmonicdistortion+ THD+N 0-dBFSinput –82 –60 dB noise Muteattenuation 87 dB PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB R =32Ω,THD+N≤–60dB 20 L P Maximumoutputpower mW O R =16Ω,THD+N≤–60dB 60 L DACLINEOUT(HPDriverinLineoutMode) SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB Totalharmonicdistortion+ THD+N 0-dBFSinput,0-dBgain –83 dB noise DACDIGITALINTERPOLATIONFILTERCHARACTERISTICS SeeSection5.6.1.4forDACinterpolationfiltercharacteristics. DACOUTPUTTOCLASS-DSPEAKEROUTPUT;LOAD=4Ω(DIFFERENTIAL),50pF SPKVDD=3.6V,BTLmeasurement,CM=1.8V, DACinput=0dBFS,class-Dgain=6dB,THD≤ 2.3 –16.5dB Outputvoltage Vrms SPKVDD=3.6V,BTLmeasurement,CM=1.8V, DACinput=–2dBFS,class-Dgain=6dB,THD≤ 2.1 –20dB SPKVDD=3.6V,BTLmeasurement,DACinput= Output,common-mode 1.8 V mute,CM=1.8V,class-Dgain=6dB SPKVDD=3.6V,BTLmeasurement,class-Dgain= SNR Signal-to-noiseratio 6dB,measuredasidle-channelnoise,A-weighted 88 dB (withrespecttofull-scaleoutputvalueof2.3Vrms) SPKVDD=3.6V,BTLmeasurement,DACinput=–6 THD Totalharmonicdistortion –65 dB dBFS,CM=1.8V,class-Dgain=6dB Totalharmonicdistortion+ SPKVDD=3.6V,BTLmeasurement,DACinput=–6 THD+N –63 dB noise dBFS,CM=1.8V,class-Dgain=6dB SPKVDD=3.6V,BTLmeasurement,rippleon PSRR Power-supplyrejectionratio –44 dB SPKVDD=200mVp-pat1kHz Muteattenuation 110 dB SPKVDD=3.6V,BTLmeasurement,CM=1.8V, 1 class-Dgain=18dB,THD=10% SPKVDD=4.3V,BTLmeasurement,CM=1.8V, P Maximumoutputpower 1.5 W O class-Dgain=18dB,THD=10% SPKVDD=5.5V,BTLmeasurement,CM=1.8V, 2.5 class-Dgain=18dB,THD=10% (1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera 20-Hzto20-kHzbandwidthusinganaudioanalyzer. (2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. (3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20Xlog(∆V /∆V ). HPL HPVDD 6 ELECTRICALSPECIFICATIONS Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 ElectricalCharacteristics(continued) At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz, S CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted) S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DACOUTPUTTOCLASS-DSPEAKEROUTPUT;LOAD=8Ω(DIFFERENTIAL),50pF SPKVDD=3.6V,BTLmeasurement,CM=1.8V, DACinput=0dBFS,class-Dgain=6dB,THD≤ 2.2 –16.5dB Outputvoltage Vrms SPKVDD=3.6V,BTLmeasurement,CM=1.8V, DACinput=–2dBFS,class-Dgain=6dB,THD≤ 2.1 –20dB SPKVDD=3.6V,BTLmeasurement,DACinput= Output,common-mode 1.8 V mute,CM=1.8V,class-Dgain=6dB SPKVDD=3.6V,BTLmeasurement,class-Dgain= SNR Signal-to-noiseratio 6dB,measuredasidle-channelnoise,A-weighted 87 dB (withrespecttofull-scaleoutputvalueof2.3Vrms) SPKVDD=3.6V,BTLmeasurement,DACinput=–6 THD Totalharmonicdistortion –67 dB dBFS,CM=1.8V,class-Dgain=6dB Totalharmonicdistortion+ SPKVDD=3.6V,BTLmeasurement,DACinput=–6 THD+N –66 dB noise dBFS,CM=1.8V,class-Dgain=6dB PSRR Power-supplyrejectionratio(1) SPKVDD=3.6V,BTLmeasurement,rippleon –44 dB SPKVDD=200mVp-pat1kHz Muteattenuation 110 dB SPKVDD=3.6V,BTLmeasurement,CM=1.8V, 0.7 class-Dgain=18dB,THD=10% SPKVDD=4.3V,BTLmeasurement,CM=1.8V, P Maximumoutputpower 1 W O class-Dgain=18dB,THD=10% SPKVDD=5.5V,BTLmeasurement,CM=1.8V, 1.6 class-Dgain=18dB,THD=10% Output-stageleakagecurrent SPKVDD=4.3V,deviceispowereddown(power- 80 nA fordirectbatteryconnection up-resetcondition) DACPOWERCONSUMPTION DACpowerconsumptionbasedperselectedprocessingblock,seeSection5.4 (1) DACtospeaker-outPSRRisadifferentialmeasurementcalculatedasPSRR=20×log(∆V /∆V ). SPK(P+M) SPKVDD Copyright©2009–2012,TexasInstrumentsIncorporated ELECTRICALSPECIFICATIONS 7 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com ElectricalCharacteristics(continued) At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz, S CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted) S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALINPUT/OUTPUT Logicfamily CMOS 0.7× I =5μA,IOVDD≥1.6V V IH IOVDD V IH I =5μA,IOVDD<1.6V IOVDD IH 0.3× I =5μA,IOVDD≥1.6V –0.3 V IL IOVDD V IL Logiclevel I =5μA,IOVDD<1.6V 0 IL 0.8× V I =2TTLloads V OH OH IOVDD 0.1× V I =2TTLloads V OL OL IOVDD Capacitiveload 10 pF 3.4 Timing Characteristics 3.4.1 I2S/LJF/RJF Timing in Master Mode Allspecificationsat25°C,DVDD=1.8V Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest. WCLK t (WS) t d r BCLK t f t (DI) t (DI) S h DIN T0145-10 PARAMETER IOVDD=1.1V IOVDD=3.3V UNIT MIN MAX MIN MAX t (WS) WCLKdelay 45 20 ns d t(DI) DINsetup 8 6 ns s t (DI) DINhold 8 6 ns h t Risetime 25 10 ns r t Falltime 25 10 ns f Figure3-1.I2S/LJF/RJFTiminginMasterMode 8 ELECTRICALSPECIFICATIONS Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 3.4.2 I2S/LJF/RJF Timing in Slave Mode Allspecificationsat25°C,DVDD=1.8V Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest. WCLK t (WS) t h r t (BCLK) t (WS) H S BCLK t (BCLK) L t (DI) t S f DIN t (DI) h T0145-11 IOVDD=1.1V IOVDD=3.3V PARAMETER UNIT MIN MAX MIN MAX t (BCLK) BCLKhighperiod 35 35 ns H t (BCLK) BCLKlowperiod 35 35 ns L t(WS) WCLKsetup 8 6 ns s t (WS) WCLKhold 8 6 ns h t(DI) DINsetup 8 6 ns s t (DI) DINhold 8 6 ns h t Risetime 4 4 ns r t Falltime 4 4 ns f Figure3-2.I2S/LJF/RJFTiminginSlaveMode Copyright©2009–2012,TexasInstrumentsIncorporated ELECTRICALSPECIFICATIONS 9 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 3.4.3 DSP Timing in Master Mode Allspecificationsat25°C,DVDD=1.8V Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest. WCLK t (WS) t (WS) d d t f BCLK t (DI) t S r DIN t (DI) h T0146-09 IOVDD=1.1V IOVDD=3.3V PARAMETER UNIT MIN MAX MIN MAX t (WS) WCLKdelay 45 20 ns d t(DI) DINsetup 8 8 ns s t (DI) DINhold 8 8 ns h t Risetime 25 10 ns r t Falltime 25 10 ns f Figure3-3.DSPTiminginMasterMode 10 ELECTRICALSPECIFICATIONS Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 3.4.4 DSP Timing in Slave Mode Allspecificationsat25°C,DVDD=1.8V Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest. WCLK t (WS) t (WS) S S t (WS) t (WS) h h t (BCLK) t L f BCLK t (BCLK) t (DI) t H S r DIN t (DI) h T0146-10 IOVDD=1.1V IOVDD=3.3V PARAMETER UNIT MIN MAX MIN MAX t (BCLK) BCLKhighperiod 35 35 ns H t (BCLK) BCLKlowperiod 35 35 ns L t(WS) WCLKsetup 8 8 ns s t (WS) WCLKhold 8 8 ns h t(DI) DINsetup 8 8 ns s t (DI) DINhold 8 8 ns h t Risetime 4 4 ns r t Falltime 4 4 ns f Figure3-4.DSPTiminginSlaveMode Copyright©2009–2012,TexasInstrumentsIncorporated ELECTRICALSPECIFICATIONS 11 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 3.4.5 I2C Interface Timing Allspecificationsat25°C,DVDD=1.8V Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest. SDA t t t t BUF LOW HIGH HD;STA t t r f SCL tHD;STA tSU;DAT tSU;STO tHD;DAT tSU;STA STO STA STA STO T0295-02 PARAMETER Standard-Mode Fast-Mode UNITS MIN TYP MAX MIN TYP MAX f SCLclockfrequency 0 100 0 400 kHz SCL t Holdtime(repeated)STARTcondition. 4 0.8 μs HD;STA Afterthisperiod,thefirstclockpulseis generated. t LOWperiodoftheSCLclock 4.7 1.3 μs LOW t HIGHperiodoftheSCLclock 4 0.6 μs HIGH t SetuptimeforarepeatedSTART 4.7 0.8 μs SU;STA condition t Dataholdtime:ForI2Cbusdevices 0 3.45 0 0.9 μs HD;DAT t Datasetuptime 250 100 ns SU;DAT t SDAandSCLrisetime 1000 20+0.1C 300 ns r b t SDAandSCLfalltime 300 20+0.1C 300 ns f b t Set-uptimeforSTOPcondition 4 0.8 μs SU;STO t BusfreetimebetweenaSTOPand 4.7 1.3 μs BUF STARTcondition C Capacitiveloadforeachbusline 400 400 pF b Figure3-5.I2CInterfaceTiming 12 ELECTRICALSPECIFICATIONS Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 4 TYPICAL PERFORMANCE 4.1 DAC Performance TEXT ADDED FOR SPACING AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY 0 0 AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V DVDD = 1.8 V −40 −40 S S F −60 F −60 B B d d − − e −80 e −80 d d u u plit plit m −100 m −100 A A −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 10 15 20 f − Frequency − kHz f − Frequency − kHz G001 G002 Figure4-1.FFT-DACtoLineOutput Figure4-2.FFT-DACtoHeadphoneOutput TEXTADDEDFORSPACING TEXTADDEDFORSPACING TOTALHARMONICDISTORTION+NOISE vs OUTPUTPOWER 0 B HPVDD = 2.7 V d −10 − CM = 1.35 V e ois −20 N n + −30 stortio −40 HCMPV =D 1D.5 = V 3 V Di c −50 HPVDD = 3.3 V ni CM = 1.65 V o arm −60 HPVDD = 3.6 V H CM = 1.8 V al −70 ot T − −80 IOVDD = 3.3 V N + DVDD = 1.8 V HD −90 Driver Gain = 9 dB T RL = 16 W −100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 PO − Output Power − W G003 Figure4-3.HeadphoneOutputPower Copyright©2009–2012,TexasInstrumentsIncorporated TYPICALPERFORMANCE 13 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 4.2 Class-D Speaker Driver Performance TEXT ADDED FOR SPACING TOTALHARMONICDISTORTION+NOISE TOTALHARMONICDISTORTION+NOISE vs vs OUTPUTPOWER OUTPUTPOWER 0 0 B AVDD = HPVDD = 3.3 V B SPKVDD = 3.3 V d d e − −10 ISOPVKDVDD D= 3=. 35 .V5 V e − −10 s s oi DVDD = 1.8 V oi N N + −20 RL = 4 W + −20 n n o o orti Driver Gain orti SPKVDD = 3.6 V Dist −30 = 24 dB Dist −30 SPKVDD = 4.3 V c c moni −40 Driver Gain moni −40 SPKVDD = 5.5 V ar = 18 dB Driver Gain ar H H otal −50 = 12 dB otal −50 AHVPDVDD D= =3 .33. 3V V T T − − IOVDD = 3.3 V +N −60 Driver Gain +N −60 DVDD = 1.8 V HD = 6 dB HD Driver Gain = 18 dB T T RL = 4 W −70 −70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 PO − Output Power − W PO − Output Power − W G004 G005 Figure4-4.MaxClass-DSpeaker-DriverOutputPower(R =4Ω) Figure4-5.Class-DSpeaker-DriverOutputPower(R =4Ω) L L TEXTADDEDFORSPACING TEXTADDEDFORSPACING TOTALHARMONICDISTORTION+NOISE TOTALHARMONICDISTORTION+NOISE vs vs OUTPUTPOWER OUTPUTPOWER 0 0 B AVDD = HPVDD = 3.3 V B SPKVDD = 3.3 V d d e − −10 ISOPVKDVDD D= 3=. 35 .V5 V e − −10 s s oi DVDD = 1.8 V oi N N + −20 RL = 8 W + −20 n n o o SPKVDD = 3.6 V orti Driver Gain orti st −30 = 18 dB st −30 Di Di SPKVDD = 4.3 V c c moni −40 Driver Gain moni −40 SPKVDD = 5.5 V = 24 dB ar Driver Gain ar H H otal −50 = 12 dB otal −50 AHVPDVDD D= =3 .33. 3V V T T − − IOVDD = 3.3 V N N + −60 Driver Gain + −60 DVDD = 1.8 V HD = 6 dB HD Driver Gain = 18 dB T T RL = 8 W −70 −70 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 PO − Output Power − W PO − Output Power − W G006 G007 Figure4-6.MaxClass-DSpeaker-DriverOutputPower(R =8Ω) Figure4-7.Class-DSpeaker-DriverOutputPower(R =8Ω) L L 14 TYPICALPERFORMANCE Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 4.3 Analog Bypass Performance TEXT ADDED FOR SPACING AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY 0 0 AVDD = HPVDD = 3.3 V AVDD = HPVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V −20 IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V DVDD = 1.8 V −40 −40 S S F −60 F −60 B B d d − − e −80 e −80 d d u u plit plit m −100 m −100 A A −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 10 15 20 f − Frequency − kHz f − Frequency − kHz G008 G009 Figure4-8.FFT-LineInBypasstoLineOutput Figure4-9.FFT-LineInBypasstoHeadphoneOutput Copyright©2009–2012,TexasInstrumentsIncorporated TYPICALPERFORMANCE 15 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 4.4 MICBIAS Performance TEXT ADDED FOR SPACING VOLTAGE vs CURRENT 3.5 3.0 Micbias = AVDD (3.3 V) 2.5 Micbias = 2.5 V V − 2.0 e g Micbias = 2 V a olt V 1.5 − V 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I − Current − mA G010 Figure4-10.MICBIAS 16 TYPICALPERFORMANCE Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration SVDD +3.3VA 0.1mF 22mF 0.1mF 22mF 0.1mF 10mF 0.1mF 10mF SPKVDD SPKVDD SPKVSS SPKVSS HPVDD AVDD AVSS HPVSS GPIO1 SDA SCL or SPKP s s ce MCLK SPKP 8-Wor4-W Pro SPKM Speaker st WCLK SPKM o H SDIN BCLK TLV320DAC3120 RESET To External MIC Circuitry MICBIAS HPL Stereo Analog In AIN1 Headphone HPR Out AVDD AIN2 R1 34.8 kW P1 VOL/MICDET 25 kW DVDD DVSS IOVDD IOVSS R2 1mF 9.76 kW +1.8VD IOVDD AVSS 0.1mF 10mF 0.1mF 10mF S0400-06 Figure5-1.TypicalCircuitConfiguration Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 17 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.2 Overview The TLV320DAC3120 is a highly integrated mono audio DAC for portable computing, communication, and entertainment applications. A register-based architecture eases integration with microprocessor-based systems through standard serial-interface buses. This device contains a two-wire I2C bus interface, which allows full register access. All peripheral functions are controlled through these registers and the onboard statemachines. TheTLV320DAC3120consistsofthefollowingblocks: • miniDSPdigitalsignal-processingblock • AudioDAC • Dynamicrangecompressor(DRC) • Monoheadphone/lineoutamplifier • Class-Dmonoamplifiercapableofdriving4-Ω or8-Ωspeakers • Pin-controlledorregister-controlledvolumelevel • Power-downde-popandpower-upsoftstart • Analoginputs • I2Ccontrolinterface • Power-downcontrolblock Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C interfaceisusedtowritetothecontrolregisterstoconfigurethedevice. The I2C address assigned to the TLV320DAC3120 is 0011000. This device always operates in an I2C slave mode. All registers are 8-bit, and all writable registers have readback capability. The device auto- increments to support sequential addressing and can be used with I2C fast mode. Once the device is reset,allappropriateregistersareupdatedbythehostprocessortoconfigurethedeviceasneededbythe user. 5.2.1 Device Initialization 5.2.1.1 Reset The TLV320DAC3120 internal logic must be initialized to a known condition for proper device function. To initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. ItisrecommendedthatwhiletheDVDDsupplyisbeingpoweredup,theRESETpinbepulledlow. The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the device. 5.2.1.2 DeviceStart-UpLockoutTimes After the TLV320DAC3120 is initialized through hardware reset at power-up or software reset, the internal memories are initialized to default values. This initialization takes place within 1 ms after pulling the RESET signal high. During this initialization phase, no register-read or register-write operation should be performed on the DAC coefficient buffers. Also, no block within the codec should be powered up during theinitializationphase. 5.2.1.3 PLLStart-Up Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up command of the PLL and before the clocks are available to the codec. This delay is to ensure stable operationofthePLLandclock-dividerlogic. 18 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.2.1.4 Power-StageReset The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has occurred. Using this reset re-enables the output stage without resetting all of the registers in the device. Each of the two power stages has its own dedicated reset bit. The headphone power-stage reset is performed by setting page 1 / register 31, bit D7 for HPOUT. The speaker power-stage reset is performed bysettingpage1/register32,bitD7forSPKPandSPKM. 5.2.1.5 SoftwarePowerDown By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of theregistersettingsaremaintainedaslongaspowerisstillbeingappliedtothedevice. 5.2.2 Audio Analog I/O The TLV320DAC3120 features a mono audio DAC. It supports a wide range of analog interfaces to supportdifferentheadsetsandanalogoutputs.TheTLV320DAC3120interfacestooutputdrivers(8-Ω,16- Ω,32-Ω). 5.3 miniDSP The TLV320DAC3120 features a miniDSP core which is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access to the digital stereo audio stream, offering the possibility for advanced, very low-group- delay DSP algorithms. The miniDSP has 1024 programmable instructions, 896 data memory locations, and 512 programmable coefficients (in the adaptive mode, each bank has 256 programmable coefficients). 5.3.1 Software Software development for the TLV320DAC3120 is supported through TI's comprehensive PurePath™ Studio software development environment, a powerful, easy-to-use tool designed specifically to simplify software development on Texas Instruments miniDSP audio platforms. The graphical development environment consists of a library of common audio functions that can be dragged and dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse. See the TLV320DAC3120 product folder on www.ti.com to learnmoreaboutPurePathStudioandthelateststatusonavailable,ready-to-useDSPalgorithms. 5.4 Digital Processing Low-Power Modes The TLV320DAC3120 device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The choice of processing blocks, PRB_P4 to PRB_P22 for mono playback and PRB_R4 to PRB_R18 for mono recording, also influences the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice amongconfigurationshavingadifferentbalanceofpower-optimizationandsignal-processingcapabilities. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 19 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.4.1 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR=128,ProcessingBlock=PRB_P12(InterpolationFilterB) Powerconsumption=15.4mW Table5-1.PRB_P12AlternativeProcessingBlocks,15.4mW ProcessingBlock Filter EstimatedPowerChange(mW) PRB_P4 A 0.57 PRB_P5 A 1.48 PRB_P6 A 1.08 PRB_P13 B 0.56 PRB_P14 B 0.27 PRB_P15 B 0.89 PRB_P16 B 0.31 DOSR=64,ProcessingBlock=PRB_P12(InterpolationFilterB) Powerconsumption=15.54mW Table5-2.PRB_P12AlternativeProcessingBlocks,15.54mW ProcessingBlock Filter EstimatedPowerChange(mW) PRB_P4 A 0.37 PRB_P5 A 1.23 PRB_P6 A 1.15 PRB_P13 B 0.43 PRB_P14 B 0.13 PRB_P15 B 0.85 PRB_P16 B 0.21 5.4.2 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR=768,ProcessingBlock=PRB_P12(InterpolationFilterB) Powerconsumption=14.49mW Table5-3.PRB_P12AlternativeProcessingBlocks,14.49mW ProcessingBlock Filter EstimatedPowerChange(mW) PRB_P4 A –0.04 PRB_P5 A 0.2 PRB_P6 A –0.01 PRB_P13 B 0.1 PRB_P14 B 0.05 PRB_P15 B –0.03 PRB_P16 B 0.07 20 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 DOSR=384,ProcessingBlock=PRB_P12(InterpolationFilterB) Powerconsumption=14.42mW Table5-4.PRB_P12AlternativeProcessingBlocks,14.42mW ProcessingBlock Filter EstimatedPowerChange(mW) PRB_P4 A 0.16 PRB_P5 A 0.3 PRB_P6 A 0.2 PRB_P13 B 0.15 PRB_P14 B 0.07 PRB_P15 B 0.18 PRB_P16 B 0.09 5.5 Analog Signals TheTLV320DAC3120analogsignalsconsistof: • Microphonebias(MICBIAS) • Analog inputs AIN1 and AIN2, which can be used to pass-through or mix analog signals to output stages • Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the DAC,AIN1,AIN2,oramixofthethree 5.5.1 MICBIAS The TLV320DAC3120 includes a microphone bias circuit which can source up to 4 mA of current, and is programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 / register46,bitsD1–D0.ThisfunctionalityisshowninTable5-5. Table5-5.MICBIASSettings D1 D0 FUNCTIONALITY 0 0 MICBIASoutputispowereddown. 0 1 MICBIASoutputispoweredto2V. 1 0 MICBIASoutputispoweredto2.5V. 1 1 MICBIASoutputispoweredtoAVDD. Duringnormaloperation,MICBIAScanbesetto2.5Vforbetterperformance.However,dependingonthe model of microphone that is selected, optimal performance might be obtained at another setting, so the performanceatagivensettingshouldbeverified. The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumptionoccurswhenMICBIASissetatAVDD. 5.5.2 Analog Inputs AIN1 and AIN2 AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 / register35providescontrolsignalsfordeterminingthesignalsroutedthroughtheoutputmixer.Theoutput of the output mixer then can be attenuated or amplified through the class-D and/or headphone/lineout drivers. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 21 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6 Audio DAC and Audio Analog Outputs The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include mono headphone/lineout and mono class-D speaker outputs. Because the TLV320DAC3120 contains a mono DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right channelsas[(L+R)÷2],selectedbypage0/register63,bitsD5–D4.SeeFigure1-1forthesignalflow. 5.6.1 DAC The TLV320DAC3120 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and observed in the signal images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320DAC3120allowsthesystemdesignertoprogramtheoversamplingratesoverawiderangefrom1 to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates. The TLV320DAC3120 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, dependingonrequiredfrequencyresponse,groupdelay,andsamplingrate. DAC power up is controlled by writing to page 0 / register 63, bit D7 for the mono channel. The mono- channelDACclippingflagisprovidedasaread-onlybitonpage0/register39,bitD7. 5.6.1.1 DACProcessingBlocks The TLV320DAC3120 implements signal-processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processingtheymayuseandwhichinterpolationfilterisapplied. The choices among these processing blocks allows the system designer to balance power conservation and signal-processing flexibility. Table 5-6gives an overview of all available processing blocks of the DAC channel and their properties. The resource-class column gives an approximate indication of power consumptionforthedigital(DVDD)supply;however,basedontheout-of-bandnoisespectrum,theanalog powerconsumptionofthedrivers(HPVDD)maydiffer. Thesignal-processingblocksavailableare: • First-orderIIR • Scalablenumberofbiquadfilters The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. Theavailablefirst-orderIIRandbiquadfiltershavefullyuser-programmablecoefficients. 22 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table5-6.Overview–DACPredefinedProcessingBlocks Processing First-Order Numberof Resource InterpolationFilter Channel DRC BlockNo. IIRAvailable Biquads Class PRB_P4 A Mono No 3 No 4 PRB_P5 A Mono Yes 6 Yes 6 PRB_P6 A Mono Yes 6 No 6 PRB_P12 B Mono Yes 0 No 3 PRB_P13 B Mono No 4 Yes 4 PRB_P14 B Mono No 4 No 4 PRB_P15 B Mono Yes 6 Yes 6 PRB_P16 B Mono Yes 6 No 4 PRB_P20 C Mono Yes 0 No 2 PRB_P21 C Mono Yes 4 Yes 3 PRB_P22 C Mono Yes 4 No 2 PRB_P25 A Mono Yes 5 Yes 12 5.6.1.2 DACProcessingBlocks– SignalChainDetails 5.6.1.2.1 ThreeBiquads,FilterA ´ BiQuad BiQuad BiQuad Interp. to A B C FilterA from Modulator Interface Digital Volume Ctrl Figure5-2.SignalChainforPRB_P4 5.6.1.2.2 SixBiquads,First-OrderIIR,DRC,FilterAorB Interp. ´ BiQuad BiQuad BiQuad BiQuad BiQuad BiQuad IIR Filter to A B C D E F from A,B Modulator Interface Digital HPF DRC Volume Ctrl Figure5-3.SignalChainforPRB_P5andPRB_P15 5.6.1.2.3 SixBiquads,First-OrderIIR,FilterAorB Interp. ´ IIR BiQuad BiQuad BiQuad BiQuad BiQuad BiQuad Filter to A B C D E F Modulator from A,B Interface Digital Volume Ctrl Figure5-4.SignalChainforPRB_P6andPRB_P16 Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 23 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6.1.2.4 IIR,FilterBorC Interp. ´ IIR Filter to Modulator from B,C Interface Digital Volume Ctrl Figure5-5.SignalChainforPRB_P12andPRB_P20 5.6.1.2.5 FourBiquads,DRC,FilterB ´ BiQuad BiQuad BiQuad BiQuad Interp. to A B C D Filter B from Modulator Interface Digital Volume HPF DRC Ctrl Figure5-6.SignalChainforPRB_P13 5.6.1.2.6 FourBiquads,FilterB ´ BiQuad BiQuad BiQuad BiQuad Interp. to A B C D Filter B Modulator from Interface Digital Volume Ctrl Figure5-7.SignalChainforPRB_P14 5.6.1.2.7 FourBiquads,First-OrderIIR,DRC,FilterC ´ BiQuad BiQuad BiQuad BiQuad Interp. IIR to A B C D Filter C Modulator from Interface Digital Volume HPF DRC Ctrl Figure5-8.SignalChainforPRB_P21 5.6.1.2.8 FourBiquads,First-OrderIIR,FilterC ´ BiQuad BiQuad BiQuad BiQuad Interp. IIR to A B C D Filter C modulator from Interface Digital Volume Ctrl Figure5-9.SignalChainforPRB_P22 24 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.6.1.2.9 FiveBiquads,DRC,BeepGenerator,FilterA from BiQuad BiQuad BiQuad BiQuad BiQuad Interp. ´ + IIR to Interface B C D E F FilterA Modulator HPF DRC Digital Volume Ctrl ´ Beep Volume Ctrl Beep Gen. Figure5-10.SignalChainforPRB_P25 Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 25 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6.1.3 DACUser-ProgrammableFilters Depending on the selected processing block, different types and orders of digital filtering are available. Up tosixbiquadsectionsareavailableforspecificprocessingblocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptivefilteringischosen,thecoefficientbankscanbeswitchedinrealtime. When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed foreitherreadorwrite. However, the TLV320DAC3120 offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients can be updated through the host and activated without stopping and restarting the DAC. This enables advanced adaptive filteringapplications. In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC is running and adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the coefficientbuffersatthenextstartofasamplingperiod.Thisbitissetbackto0aftertheswitchoccurs.At thesametime,page8/register1,bitD1toggles. Theflaginpage8/register1,bitD1indicateswhichofthetwobuffersisactuallyinuse. Page8/register1,bitD1=0:bufferAisinusebytheDACengine;bitD1=1:bufferBisinuse. While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardlessofthebuffertowhichthecoefficientshavebeenwritten. Table5-7.Adaptive-ModeFilter-CoefficientBufferSwitching DACPoweredUp Page8,Reg1,BitD1 CoefficientBufferin I2CWritesto Updates Use No 0 None Page8,Reg2–3,bufferA Page8,Reg2–3,bufferA No 0 None Page12,Reg2–3,buffer Page12,Reg2–3,bufferB B Yes 0 BufferA Page8,Reg2–3,bufferA Page12,Reg2–3,bufferB Yes 0 BufferA Page12,Reg2–3,buffer Page12,Reg2–3,bufferB B Yes 1 BufferB Page8,Reg2–3,bufferA Page8,Reg2–3,bufferA Yes 1 BufferB Page12,Reg2–3,buffer Page8,Reg2–3,bufferA B The user-programmable coefficients for the DAC processing blocks are defined on pages 8 and 9 for bufferAandpages12and13forbufferB. The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a rangefrom–1.0(0x8000)to0.999969482421875(0x7FFF)asshowninFigure5-11. –15 2 Bit –4 2 Bit Largest Positive Number: = 0.111111111111111111 –1 = 0.999969482421875 = 1.0–1 LSB 2 Bit Largest Negative Number: Fraction = 1.000010000100001000 Point = 0x8000 =–1.0 (by definition) Sign Bit S .. .xxxxxxxxxxxxxxxxxx Figure5-11. 26 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.6.1.3.1 First-OrderIIRSection TheIIRisoffirstorderanditstransferfunctionisgivenby N +Nz-1 H(z)= 0 1 215 -D z-1 1 (1) Thefrequencyresponseforthefirst-orderIIRsectionwithdefaultcoefficientsisflat. Table5-8.DACIIRFilterCoefficients DACCoefficient, Filter FilterCoefficient Default(Reset)Values MonoChannel First-orderIIR N0 Page9/registers2–3 0x7FFF(decimal1.0–LSBvalue) N1 Page9/registers4–5 0x0000 D1 Page9/registers6–7 0x0000 5.6.1.3.2 BiquadSection Thetransferfunctionofeachofthebiquadfiltersisgivenby N +2´Nz-1+N z-2 H(z)= 0 1 2 215 -2´D z-1-D z-2 1 2 (2) Table5-9.DACBiquadFilterCoefficients Filter Coefficient MonoDACChannel Default(Reset)Values BiquadA N0 Page8/registers2–3 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers4–5 0x0000 N2 Page8/registers6–7 0x0000 D1 Page8/registers8–9 0x0000 D2 Page8/registers10–11 0x0000 BiquadB N0 Page8/registers12–13 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers14–15 0x0000 N2 Page8/registers16–17 0x0000 D1 Page8/registers18–19 0x0000 D2 Page8/registers20–21 0x0000 BiquadC N0 Page8/registers22–23 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers24–25 0x0000 N2 Page8/registers26–27 0x0000 D1 Page8/registers28–29 0x0000 D2 Page8/registers30–31 0x0000 BiquadD N0 Page8/registers32–33 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers34–35 0x0000 N2 Page8/registers36–37 0x0000 D1 Page8/registers38–39 0x0000 D2 Page8/registers40–41 0x0000 BiquadE N0 Page8/registers42–43 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers44–45 0x0000 N2 Page8/registers46–47 0x0000 D1 Page8/registers48–49 0x0000 D2 Page8/registers50–51 0x0000 Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 27 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table5-9.DACBiquadFilterCoefficients(continued) Filter Coefficient MonoDACChannel Default(Reset)Values BiquadF N0 Page8/registers52–53 0x7FFF(decimal1.0–LSBvalue) N1 Page8/registers54–55 0x0000 N2 Page8/registers56–57 0x0000 D1 Page8/registers58–59 0x0000 D2 Page8/registers60–61 0x0000 5.6.1.4 DACInterpolationFilterCharacteristics 5.6.1.4.1 InterpolationFilterA FilterAisdesignedforanf upto48kspswithaflatpassbandof0kHz–20kHz. S Table5-10.SpecificationforDACInterpolationFilterA Parameter Condition Value(Typical) Unit Filter-gainpassband 0…0.45f ±0.015 dB S Filter-gainstopband 0.55f …7.455f –65 dB S S Filtergroupdelay 21/f s S DAC Channel Response for Interpolation FilterA (Red Line Corresponds to–65 dB) 0 –10 –20 B d–30 – e–40 d u nit–50 g a–60 M –70 –80 –90 1 2 3 4 5 6 7 Frequency Normalized to f S Figure5-12.FrequencyResponseofDACInterpolationFilterA 5.6.1.4.2 InterpolationFilterB Filter B is specifically designed for an f up to 96 ksps. Thus, the flat pass-band region easily covers the S requiredaudiobandof0kHz–20kHz. Table5-11.SpecificationforDACInterpolationFilterB Parameter Condition Value(Typical) Unit Filter-gainpassband 0…0.45f ±0.015 dB S Filter-gainstopband 0.55f …3.45f –58 dB S S Filtergroupdelay 18/f s S 28 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 DAC Channel Response for Interpolation Filter B (Red Line Corresponds to–58 dB) 0 –10 –20 B d ––30 e d u–40 nit g–50 a M –60 –70 –80 0.5 1 1.5 2 2.5 3 3.5 Frequency Normalized to f S Figure5-13.FrequencyResponseofChannelInterpolationFilterB 5.6.1.4.3 InterpolationFilterC Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × f S (correspondsto80kHz),morethansufficientforaudioapplications. DAC Channel Response for Interpolation Filter C (Red Line Corresponds to–43 dB) 0 –10 B–20 d – e–30 d u nit–40 g a M–50 –60 –70 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Frequency Normalized to f S Figure5-14.FrequencyResponseofDACInterpolationFilterC Table5-12.SpecificationforDACInterpolationFilterC Parameter Condition Value(Typical) Unit Filter-gainpassband 0…0.35f ±0.03 dB S Filter-gainstopband 0.6f …1.4f –43 dB S S Filtergroupdelay 13/f s S Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 29 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6.2 DAC Digital-Volume Control The DAC has a digital volume-control block which implements programmable gain. Each channel has an independentvolumecontrolthatcanbevariedfrom24dBto–63.5dBin0.5-dBsteps.Themono-channel DACvolumecanbecontrolledbywritingtopage0/register65,bitsD7–D0.DACmutingandsettingupa master gain control to control the mono channel is done by writing to page 0 / register 64, bits D3 and D1. The gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of soft- stepping can be slowed to one step per two input samples by writing to page 0 / register 63, bits D1–D0. Note that the default source for volume-control level settings is controlled by register writes to page 0 / register 65. Use of the VOL/MICDET pin to control the DAC volume is ignored until the volume-control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This functionality is showninFigure1-1. During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This may be important if the host must mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host via a read- only register, page 0 / register 38, bit D4 for the mono channel. This information alerts the host when the part has completed the soft-stepping, and the actual volume has reached the desired volume level. The soft-steppingfeaturecanbedisabledbywritingtopage0/register63,bitsD1–D0. If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an internaloscillator.) 5.6.3 Volume-Control Pin Therangeofvoltagesusedbythe7-bitSARADCisshownintheElectricalCharacteristicstable. The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page0/register116,bitD7=0.Soft-steppingthevolumelevelissetupbywritingtopage0/register63, bitsD1–D0. When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and updates the digital volume control. (It overwrites the current value of the volume control.) The new volume setting which has been applied due to a change of voltage on the volume control pin can be read on page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source can be selected on page 0 / register 116, bit D6. The update rate can be programmed on page 0 / register 116, bits D2–D0 for this 7- bitSARADC. TheVOL/MICDETpingainmappingisshowninTable5-13. Table5-13.VOL/MICDETPinGainMapping VOL/MICDETPINSAROUTPUT DIGITALGAINAPPLIED 0 18dB 1 17.5dB 2 17dB : : 35 0.5dB 36 0.0dB 37 –0.5dB : : 89 –26.5dB 30 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table5-13.VOL/MICDETPinGainMapping(continued) VOL/MICDETPINSAROUTPUT DIGITALGAINAPPLIED 90 –27dB 91 –28dB : : 125 –62dB 126 –63dB 127 Mute TheVOL/MICDETpinconnectionandfunctionalityareshowninFigure1-1. As shown in Table 5-13, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB, and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied totheVOL/MICDETpin.ThiscanbedonebyincreasingthevalueofR2relativetothevalueof(P1+R1), so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed AVDD/2 (see Figure 5-1). The recommended values for R1, R2, and P1 for several maximum gains are shown in Table 5-14. Note that In typical applications, R1 should not be 0 Ω, as the VOL/MICDET pin shouldnotexceedAVDD/2forproperADCoperation. Table5-14.VOL/MICDETPinGainScaling ADCVOLTAGE R1 P1 R2 DIGITALGAINRANGE forAVDD=3.3V (kΩ) (kΩ) (kΩ) (dB) (V) 25 25 0 0Vto1.65V 18dBto–63dB 33 25 7.68 0.386Vto1.642V 3dBto–63dB 34.8 25 9.76 0.463Vto1.649V 0dBto–63dB 5.6.4 Dynamic Range Compression Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome this problem, DRC in the TLV320DAC3120 continuously monitors the output of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear as well as soundinglouderduringnominalperiods. The DRC functionality in the TLV320DAC3120 is implemented by a combination of processing blocks in theDACchannelasdescribedinSection5.6.1.2. DRCcanbedisabledbywritingtopage0/register68,bitsD6–D5. DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in DRC. Also, most of the information about signal energy is concentrated in the low-frequency regionoftheinputsignal. To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the DRClow-passfilter.Thesefiltersareimplementedasfirst-orderIIRfiltersgivenby N +Nz-1 H (z)= 0 1 HPF 215 -D z-1 1 (3) Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 31 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com N +Nz-1 H (z)= 0 1 LPF 215 -D z-1 1 (4) The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable throughregisterwriteasgiveninTable5-15. 32 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table5-15.DRCHPFandLPFCoefficients Coefficient Location HPFN0 C71page9/registers14to15 HPFN1 C72page9/registers16to17 HPFD1 C73page9/registers18to19 LPFN0 C74page9/registers20to21 LPFN1 C75page9/registers22to23 LPFD1 C76page9/registers24to25 The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_f , S andalow-passfilterwithacutoffat0.00033× DAC_f . S The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The absolutevalueoftheDRC-LPFfilterisusedforenergyestimationwithintheDRC. The gain in the DAC digital volume control is controlled by page 0 / registers 65 and 66. When the DRC is enabled, the applied gain is a function of the digital volume-control register setting and the output of the DRC. TheDRCparametersaredescribedinsectionsthatfollow. 5.6.4.1 DRCThreshold The DRC threshold represents the level of the DAC playback signal at which the gain compression becomes active. The output of the digital volume control in the DAC is compared with the set threshold. The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the outputsignal. TherecommendedDRCthresholdvalueis–24dB. When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44, bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits D3–D2. 5.6.4.2 DRCHysteresis DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window around the programmed DRC threshold that must be exceeded for disabled DRC to become enabled, or enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC hysteresis is set to 3 dB, then if the gain compression in DRC is inactive, the output of the DAC digital volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly, when the gain compression in the DRC is active, the output of the DAC digital volume control must fall below–15dBFSforgaincompressionintheDRCtobedeactivated.TheDRChysteresisfeatureprevents the rapid activation and de-activation of gain compression in DRC in cases when the output of the DAC digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By programmingtheDRChysteresisas0dB,thehysteresisactionisdisabled. TherecommendedvalueofDRChysteresisis3dB. 5.6.4.3 DRCHoldTime DRC hold time is intended to slow the start of decay for a specified period of time in response to a decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0 throughprogrammingpage0/register69,bitsD6–D3=0000. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 33 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6.4.4 DRCAttackRate When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain appliedintheDACdigitalvolumecontrolisprogressivelyreducedtopreventthesignalfromsaturatingthe channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4. Attack rates can be programmed from 4-dB gain change per sample period to 1.2207e–5-dB gain change persampleperiod. Attack rates should be programmed such that before the output of the DAC digital volume control can clip, the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and too- slowattackratesmaynotbeabletopreventtheinputsignalfromclipping. TherecommendedDRCattackratevalueis1.9531e–4dBpersampleperiod. 5.6.4.5 DRCDecayRate When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from 1.5625e–3 dB per sample period to 4.7683e–7 dB per sample period. If the decay rates are programmed too high, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, thentheoutputmaybeperceivedastoolowforalongtimeafterthepeaksignalhaspassed. TherecommendedValueofDRCattackrateis2.4414e–5dBpersampleperiod. 5.6.4.6 ExampleSetupforDRC • DACvolgain=12dB • Threshold=–24dB • Hysteresis=3dB • Holdtime=0ms • Attackrate=1.9531e–4dBpersampleperiod • Decayrate=2.4414e–5dBpersampleperiod Script #Go to Page 0 w 30 00 00 #DAC => 12 db gain mono w 30 41 18 #DAC => DRC Enabled, Threshold = - 24 db, Hysteresis = 3 dB w 30 44 7F #DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' w 30 45 00 #Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e- 5 dB/Frame w 30 46 B6 #Go to Page 9 w 30 00 09 #DRC HPF w 30 0E 7F AB 80 55 7F 56 #DRC LPF W 30 14 00 11 00 11 7F DE 5.6.4.7 HeadsetDetection The TLV320DAC3120 includes extensive capability to monitor a headphone, microphone, or headset jack, to determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired to the plug. The device also includes the capability to detect a button press, even, for example, when starting calls on mobile phones with headsets. Figure 5-15 shows the circuit configurationtoenablethisfeature. 34 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 g g Hpout s s HPOUT Micpga m m VOL/MICDET Micbias MICBIAS S0403-01 Figure5-15.JackConnectionsforHeadsetDetection This feature is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed via page 0 / register 67, bits D4–D2. For improved button-press detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register 67, bitsD1–D0. The TLV320DAC3120 also provides feedback to the user when a button press or a headset insertion/removal event is detected through register-readable flags or an interrupt on the I/O pins. The value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected. Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320DAC3120 also provides an interrupt feature whereby the events can trigger the INT1 and/or INT2 interrupts. These interrupteventscanberoutedtooneofthedigitaloutputpins.SeeSection5.6.4.8fordetails. The TLV320DAC3120 not only detects a headset-insertion event, but also is able to distinguish between the different headsets inserted, such as stereo headphones or cellular headphones. After the headset- detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of headset inserted. Table5-16.Headset-DetectionBlockRegisters Register Description Page0/register67,bitD1 Headset-detectionenable/disable Page0/register67,bitsD4–D2 Debounceprogrammabilityforheadsetdetection Page0/register67,bitsD1–D0 Debounceprogrammabilityforbuttonpress Page0/register44,bitD5 Stickyflagforbutton-pressevent Page0/register44,bitD4 Stickyflagforheadset-insertionor-removalevent Page0/register46,bitD5 Statusflagforbutton-pressevent Page0/register46,bitD4 Statusflagforheadsetinsertionandremoval Page0/register67,bitsD6–D5 Flagsfortypeofheadsetdetected Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 35 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com The headset detection block requires AVDD to be powered. The headset-detection feature in the TLV320DAC3120 is achieved with very low power overhead, requiring less than 20 μA of additional currentfromtheAVDDsupply. 5.6.4.8 Interrupts Some specific events in the TLV320DAC3120, which may require host-processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320DAC3120 has two defined interrupts, INT1 and INT2, that can be configured by programming page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be triggeredbyoneormanyevents,suchas: • Headsetdetection • Buttonpress • DACDRCsignalexceedingthreshold • NoisedetectedbyAGC • Overcurrentconditioninheadphonedrivers/speakerdrivers • DataoverflowintheDACprocessingblocksandfilters • DCmeasurementdataavailable Each of these INT1 and INT2 interrupts can be routed to output pin GPIO1. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and page 0 / register 49, bit D0. If the user configures the interrupts as a series of pulses, the events triggerthestartofpulsesthatstopwhentheflagregistersinpage0/register44,page0/register45,and page0/register50arereadbytheusertodeterminethecauseoftheinterrupt. 5.6.5 Key-Click Functionality With Beep Generator (PRB_P25) A special algorithm has been included in the digital signal processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. This functionality is intended for generating key-click sounds for user feedback. The sine-wave generator is very flexible (see Table 5-17) and is completely register programmable. Programming page 0 / register 71 through page 0 / register 79 (8 bits each) completelycontrolsthefunctionalityofthisgeneratorandallowsfordifferentiatingsounds. The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of sinewaveintheaudiobandtobegenerated,uptof /2. S The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through page0/register75.Theresolution(bit)intheregistersofthesine-burstlengthisonesampletime,sothis allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports 16,777,215 sample times. (For example, if f is set at 48 kHz, and the register value equals 96,000d S (017700h),thenthesineburstlastsexactly2seconds.)Thedefaultsettingsforthetonegenerator,based on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five cycles(5ms). Table5-17.BeepGeneratorRegisterLocations(Page00h) BEEPLENGTH SINE COSINE LEFTBEEPCONTROL RIGHTBEEPCONTROL MSB MID LSB MSB LSB MSB LSB REGISTER 71 72 73 74 75 76 77 78 79 36 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table5-18.ExampleBeep-GeneratorSettingsfora1000-HzTone BEEPFREQUENCY BEEPLENGTH SINE COSINE SAMPLERATE MSB MID LSB MSB LSB MSB LSB Hz Hz (hex) (hex) (hex) (hex) (hex) (hex) (hex) 1000(1) 0 0 EE 10 D8 7E E3 48,000 (1) Thesearethedefaultsettings. Tworegistersareusedtocontroltheleftsine-wavevolumeandtherightsine-wavevolumeindependently. The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right channels of the beep generator can be set up by writing to page 0 / register 72, bits D7–D6. The default volumecontrolsettingis2dB,whichprovidesthemaximumtone-generatoroutputlevel. For generating other tones, the three tone-generator coefficients can be found by running the following scriptusingMATLAB™: Sine = dec2hex(round(sin(2*pi*Fin/Fs)*2^15)) Cosine = dec2hex(round(cos(2*pi*Fin/Fs)*2^15)) Beep Length = dec2hex(floor(Fs*Cycle/Fin)) where, f =Beepfrequencydesired in f =Samplerate S Cycle=Numberofbeep(sinewave)cyclesthatareneeded dec2hex=Decimaltohexadecimalconversionfunction NOTES: 1. f shouldbelessthanf /4. in S 2. Forthesineandcosinevalues,ifthenumberofbitsislessthanthefull16-bitvalue,thentheunused MSBsmustbewrittenas0s. 3. Forthebeep-lengthvalues,ifnumberofbitsislessthanthefull24-bitvalue,thentheunusedMSBs mustbewrittenas0s. Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has already been set by the DAC volume control. Therefore, once the key-click volume level is set, the key- click volume is not affected by the DAC volume control, which is the main control available to the end user.ThisfunctionalityisshowninFigure1-1. Following the DAC, the signal can be further scaled by the analog output volume control and power- amplifierlevelcontrol. The beep generator is used for the key-click function. A single beep is generated by writing to page 0 / register 71, bit D7. After the programmed beep length has finished, register 71, bit D7 is reset back to zero. 5.6.6 Programming DAC Digital Filter Coefficients The digital filter coefficients must be programmed through the I2C interface. All digital filtering for the DAC signal path must be loaded into the RAM before the DAC is powered on. (Note that default ALLPASS filter coefficients for programmable biquads are located in boot ROM. The boot ROM automatically loads the default values into the RAM following a hardware reset (toggling the RESET pin) or after a software reset. After resetting the device, loading boot ROM coefficients into the digital filters requires 100 μs of programming time. During this time, reading or writing to page 8 through page 15 for updating DAC filter coefficient values is not permitted. (The DAC should not be powered up until after all of the DAC configurationshavebeendonebythesystemmicroprocessor.) Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 37 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.6.7 Updating DAC Digital Filter Coefficients During PLAY When it is required to update the DAC digital filter coefficients during play, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the DAC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 5-16. ThevaluesfortimeslistedinFigure5-16areconservativeandshouldbeusedforsoftwarepurposes. There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For details,seeSection5.6.1.3. Play -Paused Volume Ramp Down Soft Mute DAC Volume Ramp Down WAITTime (A) Wait (A) ms For f = 32 kHz® Wait 25 ms (min) S DAC Power Down For fS= 48 kHz® Wait 20 ms (min) Update Digital Filter DAC Volume Ramp UpTime (B) Coefficients Forf = 32 kHz® 25 ms S DAC Power UP For fS= 48 kHz® 20 ms Wait 20 ms RestorePrevious Volume Level (Ramp) in (B) ms Play -Continue F0024-02 Figure5-16.ExampleFlowForUpdatingDACDigitalFilterCoefficientsDuringPlay 38 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.6.8 Digital Mixing and Routing The TLV320DAC3120 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital audio data. The first mixer/multiplexer can be used to select input data for the mono DAC from left channel, right channel, or a mix of the left and right channels [(L + R) / 2]. This digital routing can beconfiguredbywritingtopage0/register63,bitsD5–D4fortheDACmonochannel. 5.6.9 Analog Audio Routing The TLV320DAC3120 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TLV320DAC3120 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs other than the selected ones can be powered downforoptimalpowerconsumption. 5.6.9.1 AnalogOutputVolumeControl The output volume control can be used to fine-tune the level of the mixer amplifier signal supplied to the headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels for each of the four output drivers. This volume control can also be used as part of the output pop-noise reductionscheme.ThisfeatureisavailableeveniftheDACispowereddown. 5.6.9.2 HeadphoneAnalogOutputVolumeControl For the headphone outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, as shown in Table 5-19. This volume control includes soft-stepping logic. Routing the DAC output signal to the analog volume control is done by writing to page 1 / register35,bitsD7–D6. Changing the analog volume for the headphone is controlled by writing to page 1 / register 36, bits D6–D0. Routing the signal from the output of the analog volume control to the input of the headphone poweramplifierisdonebywritingtopage1/register36,bitD7. Theanalogvolume-controlsoft-steppingtimeisbasedonthesettinginpage0/register63,bitsD1–D0. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 39 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table5-19.AnalogVolumeControlforHeadphoneandSpeakerOutputs(forD7=1)(1) RegisterValue AnalogGain RegisterValue AnalogGain RegisterValue AnalogGain RegisterValue AnalogGain (D6–D0) (dB) (D6–D0) (dB) (D6–D0) (dB) (D6–D0) (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.0 34 –17.0 64 –32.1 94 –47.4 5 –2.5 35 –17.5 65 –32.6 95 –47.9 6 –3.0 36 –18.1 66 –33.1 96 –48.2 7 –3.5 37 –18.6 67 –33.6 97 –48.7 8 –4.0 38 –19.1 68 –34.1 98 –49.3 9 –4.5 39 –19.6 69 –34.6 99 –50.0 10 –5.0 40 –20.1 70 –35.2 100 –50.3 11 –5.5 41 –20.6 71 –35.7 101 –51.0 12 –6.0 42 –21.1 72 –36.2 102 –51.4 13 –6.5 43 –21.6 73 –36.7 103 –51.8 14 –7.0 44 –22.1 74 –37.2 104 –52.2 15 –7.5 45 –22.6 75 –37.7 105 –52.7 16 –8.0 46 –23.1 76 –38.2 106 –53.7 17 –8.5 47 –23.6 77 –38.7 107 –54.2 18 –9.0 48 –24.1 78 –39.2 108 –55.3 19 –9.5 49 –24.6 79 –39.7 109 –56.7 20 –10.0 50 –25.1 80 –40.2 110 –58.3 21 –10.5 51 –25.6 81 –40.7 111 –60.2 22 –11.0 52 –26.1 82 –41.2 112 –62.7 23 –11.5 53 –26.6 83 –41.7 113 –64.3 24 –12.0 54 –27.1 84 –42.1 114 –66.2 25 –12.5 55 –27.6 85 –42.7 115 –68.7 26 –13.0 56 –28.1 86 –43.2 116 –72.2 27 –13.5 57 –28.6 87 –43.8 117–127 –78.3 28 –14.0 58 –29.1 88 –44.3 29 –14.5 59 –29.6 89 –44.8 (1) MutewhenD7=0andD6–D0=127(0x7F). 5.6.9.3 Class-DSpeakerAnalogOutputVolumeControl For the speaker outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, as seen in Table 5-19. The implementation includes soft-stepping logic. Routing the DAC output signal to the analog volume control is done by writing to page 1 / register 35, bits D7–D6. Changing the analog volume for the speaker is controlled by writing to page 1 / register 38, bitsD6–D0. Routing the signal from the output of the analog volume control to the input of the speaker amplifier is donebywritingtopage1/register38,bitD7. Theanalogvolume-controlsoft-steppingtimeisbasedonthesettinginpage0/register63,bitsD1–D0. 5.6.10 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functionalblockdiagram,Figure1-1. 40 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.6.10.1 HeadphoneDrivers The TLV320DAC3120 features a mono headphone driver (HPOUT) that can deliver up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load. The headphones are used in a single-ended configuration where an ac-coupling (dc-blocking) capacitor is connected between the device output pins and the headphones. The headphone driver also supports 32-Ω and 10-kΩ loads without changing any controlregistersettings. The headphone drivers can be configured to optimize the power consumption in the lineout-drive mode by writing11topage1/register44,bitsD2–D1. The output common mode of the headphone/lineout drivers can be programmed to 1.35 V, 1.5 V, 1.65 V, or1.8Vbysettingpage1/register31,bitsD4–D3.Thecommon-modevoltageshouldbeset≤ AVDD/2. The headphone driver can be powered on by writing to page 1 / register 31, bit D7. The HPOUT output driver gain can be controlled by writing to page 1 / register 40, bits D6–D3, and it can be muted by writing topage1/register40,bitD2. The TLV320DAC3120 has a short-circuit protection feature for the headphone drivers, which is always enabled to provide protection. The output condition of the headphone driver during short circuit can be programmedbywritingtopage1/register31,bitD1.IfD1=0whenashortcircuitisdetected,thedevice limits the maximum current to the load. If D1 = 1 when a short circuit is detected, the device powers down the output driver. The default condition for headphones is the current-limiting mode. In case of a short circuit on either channel, the output is disabled and a status flag is provided as read-only bits on page 1 / register 31, bit D0. If shutdown mode is enabled, then as soon as the short circuit is detected, page 1 / register 31, bit D7 (for HPLOUT) clears automatically. Next, the device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated headphone power-stage reset can also be used to re-enable the output stage,andthatkeepsalloftheotherdevicesettings.Theheadphonepowerstageresetisdonebysetting page 1 / register 31, bit D7 for HPLOUT. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more thanthreetimes)isnotrecommended,asthiscouldleadtooverheating. 5.6.10.2 SpeakerDrivers TheTLV320DAC3120hasanintegratedclass-Dmonospeakerdriver(SPKP/SPKM)capableofdrivingan 8-Ω or 4-Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolute-maximumvoltageof6V. The speaker driver is capable of supplying 400 mW per channel with a 3.6-V power supply. Through the use of digital mixing, the device can connect one or both digital audio playback data channels to either speakerdriver;thisalsoallowsdigitalchannelswappingifneeded. The class-D speaker driver can be powered on by writing to page 1 / register 32, bit D7. The class-D output-driver gain can be controlled by writing to page 1 / register 42, bits D4–D3, and it can be muted by writingtopage1/register42,bitD2. The TLV320DAC3120 has a short-circuit protection feature for the speaker drivers that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In case of a short circuit, the output is disabled and a status flag is provided as a read-only bit on page 1 / register 32, bitD0. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 41 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The speaker power-stage reset is done by setting page 1 / register 32, bit D7 for SPKP and SPKM. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended,asthiscouldleadtooverheating. To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD voltagelevel. The TLV320DAC3120 has a thermal protection (OTP) feature for the speaker drivers which is always enabled to provide protection. If the device is overheated, then the output stops switching. When the device cools down, the output resumes switching. An overtemperature status flag is provided as a read- only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die temperaturecanbecontrolledatthesystem/boardlevel,thenovertemperaturedoesnotoccur. 5.6.11 Audio Output-Stage Power Configurations After the device has been configured (following a RESET) and the circuitry has been powered up, the audiooutputstagecanbepoweredupandpowereddownbyregistercontrol. These functions soft-start automatically. By using these register controls, it is possible to turn all four stagesonatthesametimewithoutturningtwoofthemoff. SeeTable5-20forregistercontrolofaudiooutputstagepowerconfigurations. Table5-20.AudioOutputStagePowerConfigurations AudioOutputPins DesiredFunction Page1/Register,BitValue HPOUT Power-downHPOUTdriver Page1/register31,bitD7=0 HPOUT Power-upHPOUTdriver Page1/register31,bitD7=1 SPKP/SPKM Power-downclass-Ddriver Page1/register32,bitD7=0 SPKP/SPKM Power-upclass-Ddriver Page1/register32,bitD7=1 5.7 CLOCK Generation and PLL The TLV320DAC3120 supports a wide range of options for generating clocks for the DAC sections as well as interface and other control blocks as shown in Figure 5-17. The clocks for the DAC require a source reference clock. This clock can be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO1 pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKINvalueonpage0/register4,bitsD1–D0.TheCODEC_CLKINcanthenberoutedthrough highly-flexibleclockdividersshowninFigure5-17togeneratethevariousclocksrequiredfortheDACand the miniDSP section. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the TLV320DAC3120 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TLV320DAC3120 provides several programmable clock dividers to help achieveavarietyofsamplingratesfortheDACandclocksfortheminiDSPsections. 42 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 BCLK DIN MCLK GPIO1 PLL_CLKIN PLL ´(R´J.D)/P BCLK MCLK GPIO1 PLL_CLK CODEC_CLKIN ¸NDAC NDAC= 1, 2, ..., 127, 128 To DAC miniDSP DAC_CLK Clock Generation ¸MDAC MDAC= 1, 2, ..., 127, 128 DAC_MOD_CLK ¸DOSR DOSR= 1, 2, ..., 1023, 1024 DAC_f S B0357-06 Figure5-17.ClockDistributionTree CODEC_CLKIN DAC_MOD_CLK= NDAC´MDAC CODEC_CLKIN DAC_f = S NDAC´MDAC´DOSR (5) Table5-21.CODECCLKINClockDividers Divider Bits NDAC Page0/register11,bitsD6–D0 MDAC Page0/register12,bitsD6–D0 DOSR Page0/register13,bitsD1–D0andpage0/register14,bitsD7–D0 Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 43 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, these clocks must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shut-down. During this shutdown sequence, the NDACandMDACdividersmustnotbepowereddown,orelseaproperlow-powershutdownmaynottake place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 / register 37, bit D3. When both the flags indicate power-down, the MDAC divider may be powered down, followed bytheNDACdivider. Ingeneral,alltherootclockdividersshouldbepowereddownonlyafterthechildclockdividershavebeen powereddownforproperoperation. The TLV320DAC3120 also has options for routing some of the internal clocks to the GPIO1 output pin to beusedasgeneral-purposeclocksinthesystem.ThefeatureisshowninFigure5-19. DAC_CLK DAC_MOD_CLK BDIV_CLKIN ÷N N = 1, 2, ..., 127, 128 BCLK B0362-01 Figure5-18.BCLKOutputOptions In the mode when TLV320DAC3120 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0 / register 30, bits D6–D0 from 1 to 128 (see Figure 5-18). The BDIV_CLKIN can itself be configured to be one of DAC_CLK (DAC DSP clock) or DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page0/register29,bitsD1-D0.Additionally,ageneral-purposeclockcanbedrivenoutonGPIO1. This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. The CDIV_CLKIN can itself be programmed as one of the clocks among the list shown in Figure 5-19. This can be controlled by programmingthemultiplexerinpage0/register25,bitsD2–D0. 44 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 PLL_CLK DAC_MOD_CLK MCLK BCLK DIN DAC_CLK CDIV_CLKIN ÷ M M = 1, 2, ..., 127, 128 GPIO1 (CLKOUT) B0363-01 Figure5-19.General-PurposeClockOutputOptions Table5-22.MaximumTLV320DAC3120ClockFrequencies Clock DVDD≥1.65V CODEC_CLKIN ≤110MHz DAC_CLK(DACDSPclock) ≤49.152MHz DAC_miniDSP_CLK ≤49.152MHzwithDRCdisabled ≤48MHzwithDRCenabled DAC_MOD_CLK 6.758MHz DAC_f 0.192MHz S BDIV_CLKIN 55MHz CDIV_CLKIN 100MHzwhenMisodd 110MHzwhenMiseven 5.7.1 PLL For lower power consumption, it is best to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks, then it is necessary to use the on-board PLL. The TLV320DAC3120 fractional PLL can be used to generate an internal master clock used to produce the processing clocks needed by the DAC and miniDSP. The programmability of this PLL allows operation from a wide variety of clocks that may be availableinthesystem. The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable generation of required sampling rates with fine resolution. The PLL can be turned on by writing to page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock PLL_CLK is given by the following equation: PLL_CLKIN´R´J.D PLL_CLK= P (6) where R=1,2,3,...,16(page0/register5,defaultvalue=1) J=1,2,3,…,63,(page0/register6,defaultvalue=4) D=0,1,2,…,9999(page0/register7and8,defaultvalue=0) P=1,2,3,…,8(page0/register5,defaultvalue=1) Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 45 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 / register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0, andtheLSBportionisprogrammedviapage0/register8,bitsD7–D0.ForproperupdateoftheD-divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. Unless thewritetopage0/register8iscompleted,thenewvalueofDdoesnottakeeffect. WhenthePLLisenabled,thefollowingconditionsmustbesatisfied. • WhenthePLLisenabledandD=0,thefollowingconditionsmustbesatisfiedforPLL_CLKIN: PLL_CLKIN 512kHz£ £20MHz P (7) 80MHz≤(PLL_CLKIN×J.D×R/P)≤110 MHz (8) 4≤R×J≤259 (9) • WhenthePLLisenabledandD≠ 0,thefollowingconditionsmustbesatisfiedforPLL_CLKIN: PLL_CLKIN 10MHz£ £20MHz P (10) 80MHz≤(PLL_CLKIN×J.D×R/P)≤110 MHz (11) R=1 (12) The PLL can be powered up independently from the DAC blocks, and can also be used as a general- purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available typicallyafter10ms. The clocks for codec and various signal processing blocks, CODEC_CLKIN can be generated from MCLK input,BCLKinput,GPIOinputorPLL_CLK(page0/register4,bitD1-D0). If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last. Table 5-23 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to achieveasampleratef ofeither44.1kHzor48kHz. S 46 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table5-23.PLLExampleConfigurations PLL_CLKIN(MHz) PLLP PLLR PLLJ PLLD MDAC NDAC DOSR f =44.1kHz S 2.8224 1 3 10 0 3 5 128 5.6448 1 3 5 0 3 5 128 12 1 1 7 560 3 5 128 13 1 1 6 3504 6 3 104 16 1 1 5 2920 3 5 128 19.2 1 1 4 4100 3 5 128 48 4 1 7 560 3 5 128 f =48kHz S 2.048 1 3 14 0 7 2 128 3.072 1 4 7 0 7 2 128 4.096 1 3 7 0 7 2 128 6.144 1 2 7 0 7 2 128 8.192 1 4 3 0 4 4 128 12 1 1 7 1680 7 2 128 16 1 1 5 3760 7 2 128 19.2 1 1 4 4800 7 2 128 48 4 1 7 1680 7 2 128 5.7.2 Timer The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce logics and interrupts. The MCLK divider must be set such a way that the divider output is ~1 MHz for the timerstobeclosertotheprogrammedvalue. Powered on if internal oscillator is selected Internal Oscillator ÷8 0 Used for de-bounce time for Interval timers headset detection logic, various power up timers and for generation of interrupts MCLK Programmable 1 Divider P3/R16, Bits D6-D0 P3/R16, Bit D7 Figure5-20.IntervalTimerClockSelection Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 47 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.8 Digital Audio and Control Interface 5.8.1 Digital Audio Interface Audio data is transferred between the host processor and the TLV320DAC3120 via the digital audio data serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified data options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicatewithmultipledeviceswithinasystemdirectly. NOTE The TLV320AIC3102 has a mono DAC, which inputs the mono data from the digital audio data serial interface as the left channel, the right channel, or a mix of the left and right channelsas(L+R)÷2(page0/register63,bitsD5–D4).SeeFigure1-1forthesignalflow oftheDACblocks. The audio bus of the TLV320DAC3120 can be configured for left- or right-justified, I2S, DSP, or TDM modesofoperation,wherecommunicationwithstandardtelephonyPCMinterfacesissupportedwithinthe TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected DACsamplingfrequencies. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 / register 30 (see Figure 5-17). The number of bit-clock pulses in a frame may need adjustment to accommodate various word lengths as well as to support the case when multiple TLV320DAC3120s maysharethesameaudiobus. The TLV320DAC3120 also includes a feature to offset the position of start of data transfer with respect to the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page0/register28. The TLV320DAC3120 also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the modeofaudiointerfacechosen.Thiscanbeconfiguredviapage0/register29,bitD3. By default, when the word clocks and bit clocks are generated by the TLV320DAC3120, these clocks are active only when the DAC is powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, orwhenwordclocksorbitclocksareusedinthesystemasgeneral-purposeclocks. 5.8.1.1 Right-JustifiedMode The audio interface of the TLV320DAC3120 can be put into right-justified mode by programming page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid ontherisingedgeofthebitclockprecedingtherisingedgeofthewordclock. 48 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 1/f S WCLK BCLK Left Channel Right Channel DIN 0 n–1 n–2 n–3 2 1 0 n–1 n–2 n–3 2 1 0 MSB LSB T0149-05 Figure5-21.TimingDiagramforRight-JustifiedMode For right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the programmedwordlengthofthedata. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 49 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 5.8.1.2 Left-JustifiedMode The audio interface of the TLV320DAC3120 can be put into left-justified mode by programming page 0 / register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid ontherisingedgeofthebitclockfollowingtherisingedgeofthewordclock. WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-22.TimingDiagramforLeft-JustifiedMode WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-23.TimingDiagramforLeft-JustifiedModeWithOffset=1 WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-24.TimingDiagramforLeft-JustifiedModeWithOffset=0andInvertedBitClock For left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. Also, the programmed offset value should be less than the number ofbitclocksperframebyatleasttheprogrammedwordlengthofthedata. 5.8.1.3 I2SMode The audio interface of the TLV320DAC3120 can be put into I2S mode by programming page 0 / register 27, bits D7–D6 = to 00. In I2S mode, the MSB of the left channel is valid on the second rising edgeofthebitclockafterthefallingedgeofthewordclock.Similarly,theMSBoftherightchannelisvalid onthesecondrisingedgeofthebitclockaftertherisingedgeofthewordclock. 50 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-25.TimingDiagramforI2SMode WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N DATA - 5 4 3 2 1 0 - 5 4 3 2 1 0 - 5 1 1 1 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-26.TimingDiagramforI2SModeWithOffset=2 WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-27.TimingDiagramforI2SModeWithOffset=0andBitClockInverted For I2S mode, the number of bit clocks per channel should be greater than or equal to the programmed word length of the data. Also the programmed offset value should be less than the number of bit clocks perframebyatleasttheprogrammedwordlengthofthedata. 5.8.1.4 DSPMode The audio interface of the TLV320DAC3120 can be put into DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the fallingedgeofthebitclock. Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 51 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-28.TimingDiagramforDSPMode WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) LD(n) = n'th sample of left channel data RD(n) = n'th sample of right channel data Figure5-29.TimingDiagramforDSPModeWithOffset=1 WORD LEFTCHANNEL RIGHTCHANNEL CLOCK BIT CLOCK N N N N N N N N N DATA - - - 3 2 1 0 - - - 3 2 1 0 - - - 3 1 2 3 1 2 3 1 2 3 LD(n) RD(n) LD(n+1) Figure5-30.TimingDiagramforDSPModeWithOffset=0andBitClockInverted For DSP mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. Also, the programmed offset value should be less than the number ofbitclocksperframebyatleasttheprogrammedwordlengthofthedata. 52 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 5.8.1.5 PrimaryandSecondaryDigitalAudioInterfaceSelection The audio serial interface on the TLV320DAC3120 has I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. Table 5-24 shows the primary and secondary audio interface selection and registers. Figure 5-31 is a high-level diagram showing the general signal flow and multiplexing for the primary and secondary audio interfaces. For detailedinformation,seethetablesofregisterdefinitions(Section6). Table5-24.PrimaryandSecondaryAudioInterfaceSelection DesiredPin Possible Page0Registers Comment Function Pins PrimaryWCLK R27/D2=1 PrimaryWCLKisoutputfromcodec WCLK (OUT) R33/D5–D4 SelectsourceofprimaryWCLK(DAC_fsorsecondaryWCLK) PrimaryWCLK(IN) WCLK R27/D2=0 PrimaryWCLKisinputtocodec PrimaryBCLK R27/D3=1 PrimaryBCLKisoutputfromcodec BCLK (OUT) R33/D7 SelectsourceofprimaryWCLK(internalBCLKorsecondaryBCLK) PrimaryBCLK(IN) BCLK R27/D3=0 PrimaryBCLKisinputtocodec PrimaryDIN(IN) DIN R32/D0 SelectDINtointernalinterface(0=primaryDIN;1=secondaryDIN) R31/D4–D2=000 SecondaryWCLKobtainedfromGPIO1pin SecondaryWCLK GPIO1 R51/D5–D2=1001 GPIO1issecondaryWCLKoutput. (OUT) R33/D3–D2 SelectsourceofSecondaryWCLK(DAC_f orprimaryWCLK) S SecondaryWCLK R31/D4–D2=000 SecondaryWCLKobtainedfromGPIO1pin GPIO1 (IN) R51/D5–D2=0001 GPIO1enabledassecondaryinput R31/D7–D5=000 SecondaryBCLKobtainedfromGPIO1pin SecondaryBCLK GPIO1 R51/D5–D2=1000 GPIO1issecondaryBCLKoutput. (OUT) R33/D6 SelectsourceofsecondaryBCLK(primaryBCLKorinternalBCLK) SecondaryBCLK R31/D7–D5=000 SecondaryBCLKobtainedfromGPIO1pin GPIO1 (IN) R51/D5–D2=0001 GPIO1enabledassecondaryinput R31/D1–D0=00 SecondaryDINobtainedfromGPIO1pin SecondaryDIN(IN) GPIO1 R51/D5–D2=0001 GPIO1enabledassecondaryinput Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 53 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com S_BCLK BCLK BCLK BCLK BCLK_OUT BCLK_INT S_BCLK WCLK S_WCLK WCLK WCLK Primary DAC_fS DAC_WCLK_INT DAiugditiaol Audio S_WCLK Serial Processor Interface DOUT DIN DIN DIN_INT S_DIN DIN BCLK2 GPIO1 S_BCLK BCLK BCLK BCLK_OUT WCLK2 GPIO1 S_WCLK WCLK BCLK_OUT WCLK Clock DAC_f Secondary S DAC_f Generation Audio S Processor GPIO1 S_DIN DOUT DIN B0375-01 Figure5-31.AudioSerialInterfaceMultiplexing 5.8.2 Control Interface TheTLV320DAC3120controlinterfacesupportstheI2Ccommunicationprotocol. 5.8.2.1 I2CControlMode The TLV320DAC3120 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously,thereisnodrivercontention. 54 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 CommunicationontheI2Cbusalwaystakesplacebetweentwodevices,oneactingasthemasterandthe other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320DAC3120 can onlyactasaslavedevice. An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock. AlldataistransmittedacrosstheI2Cbusingroupsofeightbits.TosendabitontheI2Cbus,theSDAline is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is 0, while a HIGH indicatesthebitis1). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line clockstheSDAbitintothereceivershiftregister. The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the dataline. Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communicationistakingplace,thebusisactive.Onlymasterdevicescanstartcommunicationonthebus. Normally,thedatalineisonlyallowedtochangestatewhiletheclocklineisLOW.Ifthedatalinechanges state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP conditioniswhentheclocklineisHIGHandthedatalinegoesfromLOWtoHIGH. After the master issues a START condition, it sends a byte that selects the slave device for communication. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishestoreadfromorwritetotheslavedevice. Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (8 data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished readingabyte,itpullsSDALOWtoacknowledgethistotheslave.Itthensendsaclockpulsetoclockthe bit.(Rememberthatthemasteralwaysdrivestheclockline.) A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it will receive a not-acknowledge because nodeviceispresentatthataddresstopullthelineLOW. When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP conditionisissued,thebusbecomesidleagain.AmastermayalsoissueanotherSTARTcondition.When aSTARTconditionisissuedwhilethebusisactive,itiscalledarepeatedSTARTcondition. The TLV320DAC3120 can also respond to and acknowledge a general call, which consists of the master issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be enabledviapage0/register34,bitD5. SCL SDA DA(6) DA(0) RA(7) RA(0) D(7) D(0) Start 7-bit DeviceAddress Write Slave 8-bit RegisterAddress Slave 8-bit Register Data Slave Stop (M) (M) (M) Ack (M) Ack (M) Ack (M) (S) (S) (S) (M) => SDAControlled by Master (S) => SDAControlled by Slave Figure5-32.I2CWrite Copyright©2009–2012,TexasInstrumentsIncorporated APPLICATIONINFORMATION 55 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com SCL SDA DA(6) DA(0) RA(7) RA(0) DA(6) DA(0) D(7) D(0) Start 7-bit DeviceAddress Write Slave 8-bit RegisterAddress Slave Repeat 7-bit DeviceAddress Read Slave 8-bit Register Data Master Stop (M) (M) (M) Ack (M) Ack Start (M) (M) Ack (S) NoAck (M) (S) (S) (M) (S) (M) (M) => SDAControlled by Master (S) => SDAControlled by Slave Figure5-33.I2CRead In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incrementalregister. Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmitforthenext8clocksthedataofthenextincrementalregister. 56 APPLICATIONINFORMATION Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 6 REGISTER MAP 6.1 TLV320DAC3120 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However,someregisterscontainstatusinformationordata,andareavailableforreadingonly. The TLV320DAC3120 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. Page 0 is the default home page after RESET. Page control is done by writing a new page value into register 0 of the currentpage. The control registers for the TLV320DAC3120 are described in detail as follows. All registers are 8 bits in width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit. Pages 0, 1, 3, 8–11, 12–15, and 64–95 are available for use; however, all other pages and registers are reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device functionalityfailurecanoccur. Table6-1.SummaryofRegisterMap PageNumber Description 0 Page0isthedefaultpageonpowerup.Configurationforserialinterface,digitalI/O,clocking,DACsettings,etc. 1 ConfigurationforanalogDAC,outputdrivers,volumecontrols,etc. Register16controlstheMCLKdividerthatcontrolstheinterruptpulseduration,debouncetiming,anddetectionblock 3 clock. 8–11 DACbuffer-AfilterandDRCcoefficients,miniDSPgeneral-purposebuffer-Acoefficients 12–15 DACbuffer-BfilterandDRCcoefficients,miniDSPgeneral-purposebufferB-coefficients 64–95 DACinstuctionRAMlocations 6.2 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs Page0/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected Page0/Register1:SoftwareReset READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D1 R/W 0000000 Reserved.Writeonlyzerostothesebits. D0 R/W 0 0:Don'tcare 1:Self-clearingsoftwareresetforcontrolregister Page0/Register2:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R XXXXXXXX Reserved.Donotwritetothisregister. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 57 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register3:OTFLAG READ/ RESET BIT DESCRIPTION WRITE VALUE D7-D2 R XXXXXX Reserved.Donotwritetothesebits. D1 R 1 0:Overtemperatureprotectionflag(active-low).Validonlyifspeakeramplifierispoweredup 1:Normaloperation D0 R/W X Reserved.Donotwritetothesebits. Page0/Register4:Clock-GenMuxing(1) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 Reserved.Writeonlyzerostothesebits. D3–D2 R/W 00 00:PLL_CLKIN=MCLK(devicepin) 01:PLL_CLKIN=BCLK(devicepin) 10:PLL_CLKIN=GPIO1(devicepin) 11:PLL_CLKIN=DIN(canbeusedforthesystemwhereDACisnotused) D1–D0 R/W 00 00:CODEC_CLKIN=MCLK(devicepin) 01:CODEC_CLKIN=BCLK(devicepin) 10:CODEC_CLKIN=GPIO1(devicepin) 11:CODEC_CLKIN=PLL_CLK(generatedon-chip) (1) SeeSection5.7formoredetailsonclockgenerationmutiplexinganddividers. Page0/Register5:PLLPandR-VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:PLLispowereddown. 1:PLLispoweredup. D6–D4 R/W 001 000:PLLdividerP=8 001:PLLdividerP=1 010:PLLdividerP=2 ... 110:PLLdividerP=6 111:PLLdividerP=7 D3–D0 R/W 0001 0000:PLLmultiplierR=16 0001:PLLmultiplierR=1 0010:PLLmultiplierR=2 ... 1110:PLLmultiplierR=14 1111:PLLmultiplierR=15 Page0/Register6:PLLJ-VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 Reserved.Writeonlyzerostothesebits. D5–D0 R/W 000100 000000:Donotuse(reserved) 000001:PLLmultiplierJ=1 000010:PLLmultiplierJ=2 ... 111110:PLLmultiplierJ=62 111111:PLLmultiplierJ=63 Table6-2. Page0/Register7:PLLD-VALMSB(1) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 Reserved.Writeonlyzerostothesebits. D5–D0 R/W 000000 PLLfractionalmultiplierD-ValMSBbitsD[13:8] (1) Notethatthisregisterwillbeupdatedonlywhenpage0/Register8iswrittenimmediatelyafterpage0/Register7. 58 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register8:PLLD-VALLSB(1) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 PLLfractionalmultiplierD-ValLSBbitsD[7:0] (1) Notethatpage0/Register8mustbewrittenimmediatelyafterpage0/Register7. Page0/Registers9–10:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlyzerostothesebits. Page0/Register11:DACNDAC_VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:DACNDACdividerispowereddown. 1:DACNDACdividerispoweredup. D6–D0 R/W 0000001 0000000:DACNDACdivider=128 0000001:DACNDACdivider=1 0000010:DACNDACdivider=2 ... 1111110:DACNDACdivider=126 1111111:DACNDACdivider=127 Page0/Register12:DACMDAC_VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:DACMDACdividerispowereddown. 1:DACMDACdividerispoweredup. D6–D0 R/W 0000001 0000000:DACMDACdivider=128 0000001:DACMDACdivider=1 0000010:DACMDACdivider=2 ... 1111110:DACMDACdivider=126 1111111:DACMDACdivider=127 Page0/Register13:DACDOSR_VALMSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D2 R/W 000000 Reserved D1–D0 R/W 00 DACOSRvalueDOSR(9:8) Page0/Register14:DACDOSR_VALLSB(1) (2) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 10000000 DACOSRValueDOSR(7:0) 00000000:DACOSR(7:0)=1024(MSBpage0/register13,bitsD1–D0=00) 00000001:DACOSR(7:0)=1(MSBpage0/register13,bitsD1–D0=00) 00000010:DACOSR(7:0)=2(MSBpage0/register13,bitsD1–D0=00) ... 11111110:DACOSR(7:0)=1022(MSBpage0/register13,bitsD1–D0=11) 11111111:DACOSR(7:0)=1023(MSBpage0/register13,bitsD1–D0=11) (1) DACOSRshouldbeanintegralmultipleoftheinterpolationintheDACminiDSPengine(specifiedinregister16). (2) Notethatpage0/register14mustbewrittentoimmediatelyafterwritingtopage0/register13. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 59 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register15:DACIDAC_VAL(1) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 10000000 00000000:NumberofinstructionforDACminiDSPengine,IDAC=1024 00000001:NumberofinstructionforDACminiDSPengine,IDAC=4 00000010:NumberofinstructionforDACminiDSPengine,IDAC=8 ... 11111101:NumberofinstructionforDACminiDSPengine,IDAC=1012 11111110:NumberofinstructionforDACminiDSPengine,IDAC=1016 11111111:NumberofinstructionforDACminiDSPengine,IDAC=1020 (1) IDACshouldbeanintegralmultipleoftheinterpolationintheDACminiDSPengine(specifiedinregister16). Page0/Register16:DACminiDSPEngineInterpolation READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 Reserved.Donotwritetotheseregisters. D3–D0 R/W 1000 0000:InterpolationratioinDACminiDSPengine=16 0001:InterpolationratioinDACminiDSPengine=1 0010:InterpolationratioinDACminiDSPengine=2 ... 1101:InterpolationratioinDACminiDSPengine=13 1110:InterpolationratioinDACminiDSPengine=14 1111:InterpolationratioinDACminiDSPengine=15 Page0/Registers17–24:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwritetotheseregisters. Page0/Registers25:CLKOUTMUX READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D3 R/W 00000 Reserved D2–D0 R/W 000 000:CDIV_CLKIN=MCLK(devicepin) 001:CDIV_CLKIN=BCLK(devicepin) 010:CDIV_CLKIN=DIN(canbeusedforthesystemswhereDACisnotrequired) 011:CDIV_CLKIN=PLL_CLK(generatedon-chip) 100:CDIV_CLKIN=DAC_CLK(DACDSPclock-generatedon-chip) 101:CDIV_CLKIN=DAC_MOD_CLK(generatedon-chip) 110:Reserved 111:Reserved Page0/Registers26:CLKOUTM_VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:CLKOUTMdividerispowereddown. 1:CLKOUTMdividerispoweredup. D6–D0 R/W 0000001 0000000:CLKOUTdividerM=128 0000001:CLKOUTdividerM=1 0000010:CLKOUTdividerM=2 ... 1111110:CLKOUTdividerM=126 1111111:CLKOUTdividerM=127 60 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register27:CodecInterfaceControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 00:Codecinterface=I2S 01:CodecInterface=DSP 10:Codecinterface=RJF 11:Codecinterface=LJF D5–D4 R/W 00 00:Codecinterfacewordlength=16bits 01:Codecinterfacewordlength=20bits 10:Codecinterfacewordlength=24bits 11:Codecinterfacewordlength=32bits D3 R/W 0 0:BCLKisinput. 1:BCLKisoutput. D2 R/W 0 0:WCLKisinput. 1:WCLKisoutput. D1 R/W 0 Reserved D0 R/W 0 Reserved Page0/Register28:Data-SlotOffsetProgrammability READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 Offset(MeasuredWithRespecttoWCLKRisingEdgeinDSPMode) 00000000:Offset=0BCLKs 00000001:Offset=1BCLK 00000010:Offset=2BCLKs ... 11111110:Offset=254BCLKs 11111111:Offset=255BCLKs Page0/Register29:CodecInterfaceControl2 READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 Reserved D5 R/W 0 Reserved D4 R/W 0 Reserved D3 R/W 0 0:BCLKisnotinverted(validforbothprimaryandsecondaryBCLK). 1:BCLKisinverted(validforbothprimaryandsecondaryBCLK). D2 R/W 0 BCLKandWCLKActiveEvenWithCodecPoweredDown(ValidforBothPrimaryandSecondary BCLK) 0:Disabled 1:Enabled D1–D0 R/W 00 00:BDIV_CLKIN=DAC_CLK(DACDSPclock-generatedon-chip) 01:BDIV_CLKIN=DAC_MOD_CLK(generatedon-chip) 10:Reserved 11:Reserved Page0/Register30:BCLKN_VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:BCLKN-dividerispowereddown. 1:BCLKN-dividerispoweredup. D6–D0 R/W 0000001 0000000:BCLKdividerN=128 0000001:BCLKdividerN=1 0000010:BCLKdividerN=2 ... 1111110:BCLKdividerN=126 1111111:BCLKdividerN=127 Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 61 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register31:CodecSecondaryInterfaceControl1 READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D5 R/W 000 000:SecondaryBCLKisobtainedfromGPIO1pin. 001–111:Reserved. D4–D2 R/W 000 000:SecondaryWCLKisobtainedfromGPIO1pin. 001–111:Reserved. D1–D0 R/W 00 00:SecondaryDINisobtainedfromtheGPIO1pin. 01–11:Reserved.10:Reserved. Page0/Register32:CodecSecondaryInterfaceControl2 READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 Reserved D3 R/W 0 0:PrimaryBCLKisfedtocodecserial-interfaceandClockGenblocks. 1:SecondaryBCLKisfedtocodecserial-interfaceandClockGenblocks. D2 R/W 0 0:PrimaryWCLKisfedtocodecserial-interfaceblock. 1:SecondaryWCLKisfedtocodecserial-interfaceblock. D1 R/W 0 Reserved D0 R/W 0 0:PrimaryDINisfedtocodecserial-interfaceblock. 1:SecondaryDINisfedtocodecserial-interfaceblock. Page0/Register33:CodecSecondaryInterfaceControl3 READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:PrimaryBCLKoutput=internallygeneratedBCLKclock 1:PrimaryBCLKoutput=secondaryBCLK D6 R/W 0 0:SecondaryBCLKoutput=primaryBCLK 1:SecondaryBCLKoutput=internallygeneratedBCLKclock D5–D4 R/W 00 00:PrimaryWCLKoutput=internallygeneratedDAC_f S 01:Reserved 10:PrimaryWCLKoutput=secondaryWCLK 11:Reserved D3–D2 R/W 00 00:SecondaryWCLKoutput=primaryWCLK 01:SecondaryWCLKoutput=internallygeneratedDAC_f clock S 10:Reserved 11:Reserved D1 R/W 0 Reserved D0 R/W 0 Reserved Page0/Register34:I2CBusCondition READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 Reserved.Writeonlytheresetvaluetothesebits. D5 R/W 0 0:I2Cgeneral-calladdressisignored. 1:DeviceacceptsI2Cgeneral-calladdress. D4–D0 R/W 00000 Reserved.Writeonlyzerostothesebits. Page0/Register35ThroughPage0/Register36:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7– R XXXXXXXX Reserved.Writeonlyzerostothesebits. 62 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register37:DACFlagRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R 0 0:DACpowereddown 1:DACpoweredup D6 R/W X Reserved.Writeonlyzerotothisbit. D5 R 0 0:HPOUTdriverpowereddown 1:HPOUTdriverpoweredup D4 R 0 0:Class-Ddriverpowereddown 1:Class-Ddriverpoweredup D3 R 0 Reserved. D2 R/W X Reserved.Writeonlyzerotothisbit. D1 R 0 Reserved. D0 R 0 Reserved. Page0/Register38:DACFlagRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D5 R/W XXX Reserved.Donotwritetothesebits. D4 R 0 0:DACPGAappliedgain≠programmedgain 1:DACPGAappliedgain=programmedgain D3–D1 R/W XXX Reserved.Writeonlyzerostothesebits. D0 R 0 Reserved. Page0/Register39:OverflowFlags READ/ RESET BIT DESCRIPTION WRITE VALUE D7(1) R 0 DACOverflowFlag 0:Overflowhasnotoccurred. 1:Overflowhasoccurred. D6(1) R 0 Reserved. D5(1) R 0 DACBarrelShifterOutputOverflowFlag 0:Overflowhasnotoccurred. 1:Overflowhasoccurred. D4 R/W 0 Reserved.Writeonlyzerostothesebits. D3 R 0 Reserved.Writeonlyzerostothesebits. D2 R/W 0 Reserved.Writeonlyzerotothisbit. D1 R 0 Reserved.Writeonlyzerostothesebits. D0 R/W 0 Reserved.Writeonlyzerotothisbit. (1) StickyflagbIts.Theseareread-onlybits.Theyareautomaticallyclearedoncetheyarereadandaresetonlyifthesourcetriggeroccurs again. Page0/Registers40–43:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlytheresetvaluetothesebits. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 63 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register44:InterruptFlags—DAC READ/ RESET BIT DESCRIPTION WRITE VALUE D7(1) R 0 0:NoshortcircuitisdetectedatHPOUT/class-Ddriver. 1:ShortcircuitisdetectedatHPOUT/class-Ddriver. D6(1) R 0 Reserved D5(1) R X 0:Noheadsetbuttonpressed 1:Headsetbuttonpressed D4(1) R X 0:Noheadsetinsertion/removalisdetected. 1:Headsetinsertion/removalisdetected. D3(1) R 0 0:DACsignalpowerislesthanorequaltothesignalthresholdofDRC. 1:DACsignalpowerisabovethesignalthresholdofDRC. D2(1) R 0 Reserved. D1(1) R 0 DACminiDSPEngineStandardInterrupt-PortOutput 0:Reada0fromStandardInterrupt-Port 1:Reada1fromStandardInterrupt-Port D0(1) R 0 DACminiDSPEngineAuxilliaryInterrupt-PortOutput 0:Reada0fromAuxilliaryInterrupt-Port 1:Reada1fromAuxilliaryInterrupt-Port (1) StickyflagbIts.Theseareread-onlybits.Theyareautomaticallyclearedoncetheyarereadandaresetonlyifthesourcetriggeroccurs again. Page0/Register45:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlytheresetvaluetothesebits. Page0/Register46:InterruptFlags–DAC READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R 0 0:NoshortcircuitdetectedatHPOUT/class-Ddriver 1:ShortcircuitdetectedatHPOUT/class-Ddriver D6 R 0 Reserved D5 R X 0:Noheadsetbuttonpressed 1:Headsetbuttonpressed D4 R X 0:Headsetremovaldetected 1:Headsetinsertiondetected D3 R 0 0:DACsignalpowerisbelowsignalthresholdofDRC. 1:DACsignalpowerisabovesignalthresholdofDRC. D2 R 0 Reserved. D1 R 0 DACminiDSPEngineStandardInterruptPortOutput 0:Reada0fromStandardInterrupt-Port 1:Raeda1fromStandardInterrupt-Port D0 R 0 DACminiDSPEngineAuxiliaryInterruptPortOutput 0:Reada0fromAuxilliaryInterrupt-Port 1:Reada1fromAuxilliaryInterrupt-Port Page0/Register47:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlytheresetvaluetothesebits. 64 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register48:INT1ControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Headset-insertiondetectinterruptisnotusedinthegenerationofINT1interrupt. 1:Headset-insertiondetectinterruptisusedinthegenerationofINT1interrupt. D6 R/W 0 0:Button-pressdetectinterruptisnotusedinthegenerationofINT1interrupt. 1:Button-pressdetectinterruptisusedinthegenerationofINT1interrupt. D5 R/W 0 0:DACDRCsignal-powerinterruptisnotusedinthegenerationofINT1interrupt. 1:DACDRCsignal-powerinterruptisusedinthegenerationofINT1interrupt. D4 R/W 0 Reserved D3 R/W 0 0:Short-circuitinterruptisnotusedinthegenerationofINT1interrupt. 1:Short-circuitinterruptisusedinthegenerationofINT1interrupt. D2 R/W 0 0:Engine-generatedinterruptisnotusedinthegenerationofINT1interrupt. 1:Engine-generatedinterruptisusedinthegenerationofINT1interrupt. D1 R/W 0 Reserved D0 R/W 0 0:INT1isonlyonepulse(active-high)oftypical2-msduration. 1:INT1ismultiplepulses(active-high)oftypical2-msdurationand4-msperiod,untilflagregisters44 and45arereadbytheuser. Page0/Register49:INT2ControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Headset-insertiondetectinterruptisnotusedinthegenerationofINT2interrupt. 1:Headset-insertiondetectinterruptisusedinthegenerationofINT2interrupt. D6 R/W 0 0:Button-pressdetectinterruptisnotusedinthegenerationofINT2interrupt. 1:Button-pressdetectinterruptisusedinthegenerationofINT2interrupt. D5 R/W 0 0:DACDRCsignal-powerinterruptisnotusedinthegenerationofINT2interrupt. 1:DACDRCsignal-powerinterruptisusedinthegenerationofINT2interrupt. D4 R/W 0 Reserved D3 R/W 0 0:Short-circuitinterruptisnotusedinthegenerationofINT2interrupt. 1:Short-circuitinterruptisusedinthegenerationofINT2interrupt. D2 R/W 0 0:Engine-generatedinterruptisnotusedinthegenerationofINT2interrupt. 1:Engine-generatedinterruptisusedinthegenerationofINT2interrupt. D1 R/W 0 Reserved D0 R/W 0 0:INT2isonlyonepulse(active-high)oftypical2-msduration. 1:INT2ismultiplepulses(active-high)oftypical2-msdurationand4-msperiod,untilflagregisters44 and45arereadbytheuser. Page0/Register50:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7-D0 R/W 00000000 Reserved.Writeonlyresetvalues. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 65 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register51:GPIO1In/OutPinControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W XX Reserved.Donotwriteanyvalueotherthanresetvalue. D5–D2 R/W 0000 0000:GPIO1disabled(inputandoutputbufferspowereddown) 0001:GPIO1isininputmode(canbeusedassecondaryBCLKinput,secondaryWCLKinput, secondaryDINinput,inputorinClockGenblock). 0010:GPIO1isusedasgeneral-purposeinput(GPI). 0011:GPIO1output=general-purposeoutput 0100:GPIO1output=CLKOUToutput 0101:GPIO1output=INT1output 0110:GPIO1output=INT2output 0111:Reserved 1000:GPIO1output=secondaryBCLKoutputforcodecinterface 1001:GPIO1output=secondaryWCLKoutputforcodecinterface 1010:Reserved 1011:Reserved 1100:Reserved 1101:Reserved 1110:Reserved 1111:Reserved D1 R X GPIO1inputbuffervalue D0 R/W 0 0:GPIO1general-purposeoutputvalue=0 1:GPIO1general-purposeoutputvalue=1 Page0/Register52:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XX Reserved.Donotwriteanyvalueotherthanresetvalue. Page0/Register53:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00001001 Reserved Page0/Register54:DIN(INPin)Control READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D3 R/W 00000 Reserved D2–D1 R/W 01 00:DINdisabled(inputbufferpowereddown) 01:DINenabled(canbeusedasDINforcodecinterfaceorinClockGenblock) 10:DINisusedasgeneral-purposeinput(GPI) 11:Reserved D0 R X DINinput-buffervalue Page0/Register55ThroughPage0/Register58:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 Reserved Page0/Register59:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlyzerostothesebits. 66 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register60:DACInstructionSet READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D5 R/W 000 Reserved.Writeonlydefaultvalue. D4–D0 R/W 00001 00000:DACminiDSPisusedforsignalprocessing. 00001–00011:Reserved.Donotuse 00100:DACsignal-processingblockPRB_P4 00101:DACsignal-processingblockPRB_P5 00110:DACsignal-processingblockPRB_P6 00111–01011:Reserved.Donotuse 01100:DACsignal-processingblockPRB_P12 01101:DACsignal-processingblockPRB_P13 01110:DACsignal-processingblockPRB_P14 01111:DACsignal-processingblockPRB_P15 10000:DACsignal-processingblockPRB_P16 10001–10011:Reserved.Donotuse. 10100:DACsignal-processingblockPRB_P20 10101:DACsignal-processingblockPRB_P21 10110:DACsignal-processingblockPRB_P22 10111–11000:Reserved.Donotuse. 11001:DACSignalProcessingBlockPRB_P25 11010–11111:Reserved.Donotuse. Page0/Register61:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00001000 Reserved.Writeonlydefaultvalues. Page0/Register62:ProgrammableInstructionMode-ControlBits READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 Reserved D6 R/W 0 Reserved D5 R/W 0 Reserved D4 R/W 0 Reserved D3 R/W 0 Reserved D2 R/W 0 DACminiDSPengineauxiliarycontrolbitA,whichcanbeusedforconditionalinstructionslikeJMP D1 R/W 0 DACminiDSPengineauxiliarycontrolbitB,whichcanbeusedforconditionalinstructionslikeJMP D0 R/W 0 0:ResetDACminiDSPinstructioncounteratthestartofthenewframe. 1:DonotresetDACminiDSPinstructioncounteratthestartofthenewframe. Page0/Register63:DACData-PathSetup READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:DACispowereddown. 1:DACispoweredup. D6 R/W 0 Reserved. D5–D4 R/W 01 00:DACdatapath=off 01:DACdatapath=leftdata 10:DACdatapath=rightdata 11:DACdatapath=leftandrightdata((L+R)/2) D3–D2 R/W 01 Reserved. D1–D0 R/W 00 00:DACchannelvolumecontrolsoft-steppingisenabledforonesteppersampleperiod. 01:DACchannelvolumecontrolsoft-steppingisenabledforonesteppertwosampleperiods. 10:DACchannelvolumecontrolsoft-steppingisdisabled. 11:Reserved.Donotwritethissequencetothesebits. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 67 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register64:DACVOLUMECONTROL READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 Reserved.Writeonlyzerostothesebits. D3 R/W 1 0:DACnotmuted 1:DACmuted D2 R/W 1 Reserved. D1–D0 R/W 00 Reserved.Alwayswriteresetvalue. Page0/Register65:DACVolumeControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 127to49:Reserved.Donotwritethesesequencestothesebits. 48:DACDigitalgain=24dB 47:DACDigitalgain=23.5dB 46:DACDigitalgain=23dB ... 36:DACDigitalgain=18dB 35:DACDigitalgain=17.5dB 34:DACDigitalgain=17dB ... 1:DACDigitalgain=0.5dB 0:DACDigitalgain=0dB –1:DACDigitalgain=–0.5dB ... –126:DACDigitalgain=–63dB –127:DACDigitalgain=–63.5dB –128:Reserved Page0/Register66:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 Reserved.writeonlyresetvalues. Page0/Register67:HeadsetDetection READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Headsetdetectiondisabled 1:Headsetdetectionenabled D6–D5 R XX 00:Noheadsetdetected 01:Headsetwithoutmicrophoneisdetected 10:Reserved 11:Headsetwithmicrophoneisdetected D4–D2 R/W 000 DebounceProgrammingforGlitchRejectionDuringHeadsetDetection(1) 000:16ms(sampledwith2-msclock) 001:32ms(sampledwith4-msclock) 010:64ms(sampledwith8-msclock) 011:128ms(sampledwith16-msclock) 100:256ms(sampledwith32-msclock) 101:512ms(sampledwith64-msclock) 110:Reserved 111:Reserved D1–D0 R/W 00 DebounceProgrammingforGlitchRejectionDuringHeadsetButton-PressDetection 00:0ms 01:8ms(sampledwith1-msclock) 10:16ms(sampledwith2-msclock) 11:32ms(sampledwith4-msclock) (1) Notethatthesetimesaregeneratedusingthe1MHzreferenceclockwhichisdefinedinpage3/register16. 68 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register68:DRCControl1 READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 Reserved.Writeonlytheresetvaluetothesebits. D6 R/W 0 0:DRCdisabled 1:DRCenabled D5 R/W 0 Reserved.Writeonlyresetvalue. D4–D2 R/W 011 000:DRCthreshold=–3dB 001:DRCthreshold=–6dB 010:DRCthreshold=–9dB 011:DRCthreshold=–12dB 100:DRCthreshold=–15dB 101:DRCthreshold=–18dB 110:DRCthreshold=–21dB 111:DRCthreshold=–24dB D1–D0 R/W 11 00:DRChysteresis=0dB 01:DRChysteresis=1dB 10:DRChysteresis=2dB 11:DRChysteresis=3dB Page0/Register69:DRCControl2 READ/ RESET BIT DESCRIPTION WRITE VALUE D R 0 Reserved.Writeonlytheresetvaluetothesebits. D6–D3 R/W 0111 DRCHoldProgrammability 0000:DRCHoldDisabled 0001:DRCHoldTime=32DACWordClocks 0010:DRCHoldTime=64DACWordClocks 0011:DRCHoldTime=128DACWordClocks 0100:DRCHoldTime=256DACWordClocks 0101:DRCHoldTime=512DACWordClocks ... 1110:DRCHoldTime=4*32768DACWordClocks 1111:DRCHoldTime=5*32768DACWordClocks D2-D0 000 Reserved.Writeonlytheresetvaluetothesebits. Page0/Register70:DRCControl3 READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 0000:DRCattackrate=4dBperDACWordClock 0001:DRCattackrate=2dBperDACWordClock 0010:DRCattackrate=1dBperDACWordClock ... 1110:DRCattackrate=2.4414e–5dBperDACWordClock 1111:DRCattackrate=1.2207e–5dBperDACWordClock D3–D0 R/W 0000 0000:DRCdecayrate=1.5625e–2dBperDACWordClock 0001:DRCdecayrate=7.8125e–3dBperDACWordClock 0010:DRCdecayrate=3.9062e–3dBperDACWordClock ... 1110:DRCdecayrate=9.5367e–7dBperDACWordClock 1111:DRCdecayrate=4.7683e–7dBperDACWordClock Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 69 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page0/Register71(0x47):BeepGenerator (1) READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Beepgeneratorisdisabled. 1:Beepgeneratorisenabled(self-clearingbasedonbeepduration). D6 R/W 0 Reserved.Writeonlyresetvalue. D5–D0 R/W 000000 000000:Beepvolumecontrol=2dB 000001:Beepvolumecontrol=1dB 000010:Beepvolumecontrol=0dB 000011:Beepvolumecontrol=–1dB ... 111110:Beepvolumecontrol=–60dB 111111:Beepvolumecontrol=–61dB (1) ThebeepgeneratorisonlyavailableinPRB_P25DACprocessingmode. Page0/Register72:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 0 Reserved. Page0/Register73(0x49):BeepLengthMSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 8MSBsoutof24bitsforthenumberofsamplesforwhichthebeepmustbegenerated. Page0/Register74(0x4A):BeepLengthMiddleBits READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 8middlebitsoutof24bitsforthenumberofsamplesforwhichthebeepmustbegenerated. Page0/Register75(0x4B):BeepLengthLSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 11101110 8LSBsoutof24bitsforthenumberofsamplesforwhichbeepneedtobegenerated. Page0/Register76(0x4C):BeepSin(x)MSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00010000 8MSBsoutof16bitsforsin(2π×f /f ),wheref isthebeepfrequencyandf istheDACsamplerate. in S in S Page0/Register77(0x4D):BeepSin(x)LSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 11011000 8LSBsoutof16bitsforsin(2π×f /f ),wheref isthebeepfrequencyandf istheDACsamplerate. in S in S Page0/Register78(0x4E):BeepCos(x)MSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 01111110 8MSBsoutof16bitsforcos(2π×f /f ),wheref isthebeepfrequencyandf istheDACsamplerate. in S in S Page0/Register79(0x4F):BeepCos(x)LSB READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 11100011 8LSBsoutof16bitsforcos(2π×f /f ),wheref isthebeepfrequencyandf istheDACsamplerate. in S in S 70 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page0/Register80-115:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 0 Reserved. Page0/Register116:VOL/MICDET-PinSARADC– VolumeControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:DACvolumecontroliscontrolledbycontrolregister.(7-bitVolADCispowereddown) 1:DACvolumecontroliscontrolledbypin. D6 R/W 0 0:Internalon-chipRCoscillatorisusedforthe7-bitVolADCforpinvolumecontrol. 1:MCLKisusedforthe7-bitVolADCforpinvolumecontrol. D5–D4 R/W 00 00:NohysteresisforvolumecontrolADCoutput 01:Hysteresisof±1bit 10:Hysteresisof±2bits 11:Reserved.Donotwritethissequencetothesebits. D3 R/W 0 Reserved.Writeonlyresetvalue. D2–D0 R/W 000 Throughputofthe7-bitVolADCforpinvolumecontrol,frequencybasedon MCLKorinternaloscillator. MCLK=12MHz InternalOscillatorSource 000:Throughput= 15.625Hz 10.68Hz 001:Throughput= 31.25Hz 21.35Hz 010:Throughput= 62.5Hz 42.71Hz 011:Throughput= 125Hz 8.2Hz 100:Throughput= 250Hz 170Hz 101:Throughput= 500Hz 340Hz 110:Throughput= 1kHz 680Hz 111:Throughput= 2kHz 1.37kHz Note:Thesevaluesarebasedonanominaloscillator frequencyof8.2MHz.Valueswillscaletotheactual oscillatorfrequency. Page0/Register117:VOL/MICDET-PinGain READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 Reserved.Writeonlyzerotothisbit. D6–D0 R XXXXXXX 0000000:Gainappliedbypinvolumecontrol=18dB 0000001:Gainappliedbypinvolumecontrol=17.5dB 0000010:Gainappliedbypinvolumecontrol=17dB ... 0100011:Gainappliedbypinvolumecontrol=0.5dB 0100100:Gainappliedbypinvolumecontrol=0dB 0100101:Gainappliedbypinvolumecontrol=–0.5dB ... 1011001:Gainappliedbypinvolumecontrol=–26.5dB 1011010:Gainappliedbypinvolumecontrol=–27dB 1011011:Gainappliedbypinvolumecontrol=–28dB ... 1111101:Gainappliedbypinvolumecontrol=–62dB 1111110:Gainappliedbypinvolumecontrol=–63dB 1111111:Reserved. Page0/Registers118to127:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwritetotheseregisters. 6.3 Control Registers, Page 1: DAC Routing, Power-Controls and MISC Logic Related Programmabilities Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 71 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page1/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected Page1/Registers1–29:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwritetotheseregisters. Page1/Register30:HeadphoneandSpeakerAmplifierErrorControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D2 R/W 000000 Reserved D1 R/W 0 0:ResetHPOUTpower-upcontrolbitonshort-circuitdetectionifpage-1,register31,D1=1. 1:HPOUTpower-upcontrolbitsremainunchangedonshort-circuitdetection. D0 R/W 0 0:ResetSPLandSPRpower-upcontrolbitsonshort-circuitdetection. 1:SPLandSPRpower-upcontrolbitsremainunchangedonshort-circuitdetection. Page1/Register31:HeadphoneDrivers READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:HPOUToutputdriverispowereddown. 1:HPOUToutputdriverispoweredup. D6 R/W 0 Reserved D5 R/W 0 Reserved.Writeonlyzerotothisbit. D4–D3 R/W 0 00:Outputcommon-modevoltage=1.35V 01:Outputcommon-modevoltage=1.5V 10:Outputcommon-modevoltage=1.65V 11:Outputcommon-modevoltage=1.8V D2 R/W 1 Reserved.Writeonly1tothisbit. D1 R/W 0 0:Ifshort-circuitprotectionisenabledforheadphonedriverandshortcircuitdetected,devicelimitsthe maximumcurrenttotheload. 1:Ifshort-circuitprotectionisenabledforheadphonedriverandshortcircuitdetected,devicepowers downtheoutputdriver. D0 R 0 0:Shortcircuitisnotdetectedontheheadphonedriver. 1:Shortcircuitisdetectedontheheadphonedriver. Page1/Register32:Class-DSpeakerAmplifier READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Class-Doutputdriverispowereddown. 1:Class-Doutputdriverispoweredup. D6 R/W 0 Reserved.Writeonlyresetvalues. D5–D1 R/W 00011 Reserved.Writeonlyresetvalues. D0 R 0 0:Shortcircuitisnotdetectedontheclass-Ddriver.Validonlyifclass-Damplifierispoweredup.For short-circuitflagstickybit,seepage0/register44. 1:Shortcircuitisdetectedontheclass-Ddriver.Validonlyifclass-Dampispowered-up.Forshort- circuitflagstickybit,seepage0/register44. 72 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page1/Register33:HPOutputDriversPOPRemovalSettings READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Ifpowerdownsequenceisactivatedbydevicesoftwarepowerdownusingpage1/register46,bit D7,thenpowerdowntheDACsimultaneouslywiththeHPandSPamplifiers. 1:Ifpowerdownsequenceisactivatedbydevicesoftwarepowerdownusingpage1/register46,bit D7,thenpowerdownDAConlyafterHPandSPamplifiersarecompletelypowereddown.Thisisto optimizepower-downPOP. D6–D3 R/W 0111 0000:Driverpower-ontime=0μs 0001:Driverpower-ontime=15.3μs 0010:Driverpower-ontime=153μs 0011:Driverpower-ontime=1.53ms 0100:Driverpower-ontime=15.3ms 0101:Driverpower-ontime=76.2ms 0110:Driverpower-ontime=153ms 0111:Driverpower-ontime=304ms 1000:Driverpower-ontime=610ms 1001:Driverpower-ontime=1.22s 1010:Driverpower-ontime=3.04s 1011:Driverpower-ontime=6.1s 1100–1111:Reserved.Donotwritethesesequencestothesebits. NOTE:Thesevaluesarebasedontypicaloscillatorfrequencyof8.2MHz.Scaleaccordingtotheactual oscillatorfrequency. D2–D1 R/W 11 00:Driverramp-upsteptime=0ms 01:Driverramp-upsteptime=0.98ms 10:Driverramp-upsteptime=1.95ms 11:Driverramp-upsteptime=3.9ms NOTE:Thesevaluesarebasedontypicaloscillatorfrequencyof8.2MHz.Scaleaccordingtotheactual oscillatorfrequency. D0 R/W 0 0:Weaklydrivenoutputcommon-modevoltageisgeneratedfromresistordivideroftheAVDDsupply. 1:Reserved. Page1/Register34:OutputDriverPGARamp-DownPeriodControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 Reserved.Writeonlytheresetvaluetothisbit. D6–D4 R/W 000 SpeakerPower-UpWaitTime(DurationBasedonUsingInternalOscillator) 000:Waittime=0ms 001:Waittime=3.04ms 010:Waittime=7.62ms 011:Waittime=12.2ms 100:Waittime=15.3ms 101:Waittime=19.8ms 110:Waittime=24.4ms 111:Waittime=30.5ms NOTE:Thesevaluesarebasedontypicaloscillatorfrequencyof8.2MHz.Scaleaccordingtotheactual oscillatorfrequency. D3–D0 R/W 0000 Reserved.Writeonlytheresetvaluetothesebits. Page1/Register35:DACOutputMixerRouting READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 00:DACisnotroutedanywhere. 01:DACisroutedtothemixeramplifier. 10:DACisrouteddirectlytotheHPOUTdriver. 11:Reserved D5 R/W 0 0:AIN1inputisnotroutedtothemixeramplifier. 1:AIN1inputisroutedtothemixeramplifier. D4 0 0:AIN2inputisnotroutedtothemixeramplifier. 1:AIN2inputisroutedtothemixeramplifier. D3–D0 R/W 0000 Reserved Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 73 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page1/Register36:AnalogVoltoHPOUT READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:AnalogvolumecontrolisnotroutedtoHPOUToutputdriver. 1:AnalogvolumecontrolisroutedtoHPOUToutputdriver. D6–D0 R/W 1111111 Analogvolumecontrolgain(non-linear)fortheHPOUToutputdriver,0dBto–78dB.SeeTable5-19. Page1/Register37:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7-D0 R/W 01111111 Reserved Page1/Register38:AnalogVoltoClass-DOutputDriver READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Analogvolumecontroloutputisnotroutedtoclass-Doutputdriver. 1:Analogvolumecontroloutputisroutedtoclass-Doutputdriver. D6–D0 R/W 1111111 Analogvolumecontroloutputgain(non-linear)fortheclass-Doutputdriver,0dBto–78dB.See Table5-19. Page1/Register39:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 01111111 Reserved Page1/Register40:HPOUTDriver READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 Reserved.Writeonlyzerotothisbit. D6–D3 R/W 0000 0000:HPOUTdriverPGA=0dB 0001:HPOUTdriverPGA=1dB 0010:HPOUTdriverPGA=2dB ... 1000:HPOUTdriverPGA=8dB 1001:HPOUTdriverPGA=9dB 1010–1111:Reserved.Donotwritethesesequencestothesebits. D2 R/W 0 0:HPOUTdriverismuted. 1:HPOUTdriverisnotmuted. D1 R/W 1 0:HPOUTdriverisweaklydriventoacommonmodeduringpowerdown.(1) 1:HPOUTdriverishigh-impedanceduringpowerdown. D0 R 0 0:NotallprogrammedgainstoHPOUThavebeenappliedyet. 1:AllprogrammedgainstoHPOUThavebeenapplied. (1) IfD1isprogrammedas0,Page1/Register33D0mustbesetto0. Page1/Register41:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwritetothisregister. 74 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Page1/Register42:Class-DOutputDriver READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D5 R/W 000 Reserved.Writeonlyzerostothesebits. D4–D3 R/W 00 00:Class-Ddriveroutputstagegain=6dB 01:Class-Ddriveroutputstagegain=12dB 10:Class-Ddriveroutputstagegain=18dB 11:Class-Ddriveroutputstagegain=24dB D2 R/W 0 0:Class-Ddriverismuted. 1:Class-Ddriverisnotmuted. D1 R/W 0 Reserved.Writeonlyzerotothisbit. D0 R 0 0:Notallprogrammedgainstoclass-Ddriverhavebeenappliedyet. 1:Allprogrammedgainstoclass-Ddriverhavebeenapplied. Page1/Register43:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwitetothisregister. Page1/Register44:HPDriverControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D5 R/W 000 Debouncetimefortheheadsetshort-circuitdetection MCLK/DIV(Page3/ (1) register16)=1-MHz InternalOscillatorSource Source 000:Debouncetime= 0μs 0μs 001:Debouncetime= 8μs 7.8μs 010:Debouncetime= 16μs 15.6μs 011:Debouncetime= 32μs 31.2μs 100:Debouncetime= 64μs 62.4μs 101:Debouncetime= 128μs 124.9μs 110:Debouncetime= 256μs 250μs 111:Debouncetime= 512μs 500μs Note:Thesevaluesarebasedonanominaloscillator frequencyof8.2MHz.Valueswillscaletotheactual oscillatorfrequency. D4–D3 R/W 00 00:DefaultmodefortheDAC 01:DACperformanceincreasedbyincreasingthecurrent 10:Reserved 11:DACperformanceincreasedfurtherbyincreasingthecurrentagain D2 R/W 0 0:HPOUToutputdriverisprogrammedasheadphonedriver. 1:HPOUToutputdriverisprogrammedaslineoutdriver. D1–D0 R/W 0 Reserved.Writeonlyzerostothesebits. (1) Theclockusedforthedebouncehasaclockperiod=debounceduration/8. Page1/Register45:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Donotwritetotheseregisters. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 75 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page1/Register46:MICBIAS READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:Devicesoftwarepowerdownisnotenabled. 1:Devicesoftwarepowerdownisenabled. D6–D4 R/W 000 Reserved.Writeonlyzerostothesebits. D3 R/W 0 0:ProgrammedMICBIASisnotpoweredupifheadsetdetectionisenabledbutheadsetisnotinserted. 1:ProgrammedMICBIASispoweredupevenifheadsetisnotinserted. D2 R/W 0 Reserved.Writeonlyzerotothisbit. D1–D0 R/W 00 00:MICBIASoutputispowereddown. 01:MICBIASoutputispoweredto2V. 10:MICBIASoutputispoweredto2.5V. 11:MICBIASoutputispoweredtoAVDD. Page1/Registers47–49:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlytheresetvaluetothesebits. Table6-3. Page1/Register50:InputCMSettings READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0:AIN1inputisfloatingifitisnotusedforanalogbypass. 1:AIN1inputisconnectedtoCMinternallyifitisnotusedforanalogbypass. D6 R/W 0 0:AIN2inputisfloatingifitisnotusedforanalogbypass. 1:AIN2inputisconnectedtoCMinternallyifitisnotusedforanalogbypass. D5–D0 R/W 000000 Reserved.Writeonlyzerostothesebits. Table6-4. Page1/Registers51–127:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlytheresetvaluetothesebits. 6.4 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer Defaultvaluesshownforthispageonlybecomevalid100μsfollowingahardwareorsoftwarereset. Page3/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected The only register used in page 3 is register 16. The remaining page 3 registers are reserved and should notbewrittento. 76 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-5. Page3/Register16:MCLKDividerforProgrammableDelayTimer READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 1 0:Internaloscillatorisusedforprogrammabledelaytimer. 1:ExternalMCLK(1)isusedforprogrammabledelaytimer. D6–D0 R/W 0000000 MCLKDividertoGenerate1-MHzClockfortheProgrammableDelayTimer 0000000:MCLKdivider=128 0000001:MCLKdivider=1 0000010:MCLKdivider=2 ... 1111110:MCLKdivider=126 1111111:MCLKdivider=127 (1) Externalclockisusedonlytocontrolthedelayprogrammedbetweentheconversionsandnotusedfordoingtheactualconversion.This featureisprovidedincaseamoreaccuratedelayisdesiredsincetheinternaloscillatorfrequencyvariesfromdevicetodevice. 6.5 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63) Defaultvaluesshownforthispageonlybecomevalid100μsfollowingahardwareorsoftwarereset. Page8/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected The remaining page-8 registers are either reserved registers or are used for setting coefficients for the variousfiltersintheTLV320DAC3120.Reservedregistersshouldnotbewrittento. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-6 is a list of the page-8 registers, excepting the previouslydescribedregister0. Page8/Register1:DACCoefficientRAMControl READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D4 R/W 0000 Reserved.Writeonlytheresetvalue. D3 R 0 DACminiDSPgeneratedflagfortogglingMSBofcoefficientRAMaddress(onlyusedinnon-adaptive mode) D2 R/W 0 DACAdaptiveFilteringControl 0:AdaptivefilteringdisabledinDACminiDSP 1:AdaptivefilteringenabledinDACminiDSP D1 R 0 DACAdaptiveFilterBufferControlFlag 0:Inadaptivefiltermode,DACminiDSPaccessesDACcoefficientBufferAandtheexternalcontrol interfaceaccessesDACcoefficientBufferB 1:Inadaptivefiltermode,DACminiDSPaccessesDACcoefficientBufferBandtheexternalcontrol interfaceaccessesDACcoefficientBufferA D0 R/W 0 DACAdaptiveFilterBufferSwitchControl 0:DACcoefficientbuffersarenotswitchedatthenextframeboundary. 1:DACcoefficientbuffersareswitchedatthenextframeboundary,ifadaptivefilteringmodeisenabled. Thisbitself-clearsonswitching. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 77 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-6.Page-8Registers REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientN0(15:8)forleftDAC-programmablebiquadAorCoefficientC1(15:8)ofDAC 2 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadAorCoefficientC1(7:0)ofDAC 3 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadAorCoefficientC2(15:8)ofDAC 4 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadAorCoefficientC2(7:0)ofDAC 5 00000000 miniDSP(DACBufferA) CoefficientN2(15:8)forleftDAC-programmablebiquadAorCoefficientC3(15:8)ofDAC 6 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadAorCoefficientC3(7:0)ofDAC 7 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadAorCoefficientC4(15:8)ofDAC 8 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablebiquadAorCoefficientC4(7:0)ofDAC 9 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadAorCoefficientC5(15:8)ofDAC 10 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadAorCoefficientC5(7:0)ofDAC 11 00000000 miniDSP(DACBufferA) CoefficientN0(15:8)forleftDAC-programmablebiquadBorCoefficientC6(15:8)ofDAC 12 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadBorCoefficientC6(7:0)ofDAC 13 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadBorCoefficientC7(15:8)ofDAC 14 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadBorCoefficientC7(7:0)ofDAC 15 00000000 miniDSP(DACBufferA) CoefficientN2(15:8)forleftDAC-programmablebiquadBorCoefficientC8(15:8)ofDAC 16 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadBorCoefficientC8(7:0)ofDAC 17 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadBorCoefficientC9(15:8)ofDAC 18 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablebiquadBorCoefficientC9(7:0)ofDAC 19 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadBorCoefficientC10(15:8)ofDAC 20 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadBorCoefficientC10(7:0)ofDAC 21 00000000 miniDSP(DACBufferA) CoefficientN0(15:8)forleftDAC-programmablebiquadCorCoefficientC11(15:8)ofDAC 22 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadCorCoefficientC11(7:0)ofDAC 23 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadCorCoefficientC12(15:8)ofDAC 24 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadCorCoefficientC12(7:0)ofDAC 25 00000000 miniDSP(DACBufferA) CoefficientN2(15:8)forleftDAC-programmablebiquadCorCoefficientC13(15:8)ofDAC 26 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadCorCoefficientC13(7:0)ofDAC 27 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadCorCoefficientC14(15:8)ofDAC 28 00000000 miniDSP(DACBufferA) 78 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-6.Page-8Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientD1(7:0)forleftDAC-programmablebiquadCorCoefficientC14(7:0)ofDAC 29 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadCorCoefficientC15(15:8)ofDAC 30 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadCorCoefficientC15(7:0)ofDAC 31 00000000 miniDSP(DACBufferA) CoefficientN0(15:8)forleftDAC-programmablebiquadDorCoefficientC16(15:8)ofDAC 32 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadDorCoefficientC16(7:0)ofDAC 33 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadDorCoefficientC17(15:8)ofDAC 34 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadDorCoefficientC17(7:0)ofDAC 35 00000000 miniDSP(DACBufferA) CoefficientN2(15:8)forleftDAC-programmablebiquadDorCoefficientC18(15:8)ofDAC 36 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadDorCoefficientC18(7:0)ofDAC 37 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadDorCoefficientC19(15:8)ofDAC 38 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablebiquadDorCoefficientC19(7:0)ofDAC 39 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadDorCoefficientC20(15:8)ofDAC 40 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadDorCoefficientC20(7:0)ofDAC 41 00000000 miniDSP(DACBufferA) CoefficientN0(15:8)forleftDAC-programmablebiquadEorCoefficientC21(15:8)ofDAC 42 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadEorCoefficientC21(7:0)ofDAC 43 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadEorCoefficientC22(15:8)ofDAC 44 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadEorCoefficientC22(7:0)ofDAC 45 00000000 miniDSP(DACBufferA) CoefficientN2(15:8)forleftDAC-programmablebiquadEorCoefficientC23(15:8)ofDAC 46 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadEorCoefficientC23(7:0)ofDAC 47 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadEorCoefficientC24(15:8)ofDAC 48 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablebiquadEorCoefficientC24(7:0)ofDAC 49 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadEorCoefficientC25(15:8)ofDAC 50 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadEorCoefficientC25(7:0)ofDAC 51 00000000 miniDSP(DACBufferA) CoefficientN0(15:8)forleftDAC-programmablebiquadForCoefficientC26(15:8)ofDAC 52 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablebiquadForCoefficientC26(7:0)ofDAC 53 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablebiquadForCoefficientC27(15:8)ofDAC 54 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablebiquadForCoefficientC27(7:0)ofDAC 55 00000000 miniDSP(DACBufferA) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 79 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-6.Page-8Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientN2(15:8)forleftDAC-programmablebiquadForCoefficientC28(15:8)ofDAC 56 00000000 miniDSP(DACBufferA) CoefficientN2(7:0)forleftDAC-programmablebiquadForCoefficientC28(7:0)ofDAC 57 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablebiquadForCoefficientC29(15:8)ofDAC 58 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablebiquadForCoefficientC29(7:0)ofDAC 59 00000000 miniDSP(DACBufferA) CoefficientD2(15:8)forleftDAC-programmablebiquadForCoefficientC30(15:8)ofDAC 60 00000000 miniDSP(DACBufferA) CoefficientD2(7:0)forleftDAC-programmablebiquadForCoefficientC30(7:0)ofDAC 61 00000000 miniDSP(DACBufferA) 62 00000000 CoefficientC31(15:8)ofDACminiDSP(DACBufferA) 63 00000000 CoefficientC31(7:0)ofDACminiDSP(DACBufferA) CoefficientC32(15:8)ofDACminiDSP(DACBufferA)—alsousedforthe3DPGAfor 64 00000000 PRB_P23,PRB_P24andPRB_P25 CoefficientC32(7:0)ofDACminiDSP(DACBufferA)—alsousedforthe3DPGAfor 65 00000000 PRB_P23,PRB_P24andPRB_P25 66 01111111 Reserved. 67 11111111 Reserved. 68 00000000 Reserved. 69 00000000 Reserved. 70 00000000 Reserved. 71 00000000 Reserved. 72 00000000 Reserved. 73 00000000 Reserved. 74 00000000 Reserved. 75 00000000 Reserved. 76 01111111 Reserved. 77 11111111 Reserved. 78 00000000 Reserved. 79 00000000 Reserved. 80 00000000 Reserved. 81 00000000 Reserved. 82 00000000 Reserved. 83 00000000 Reserved. 84 00000000 Reserved. 85 00000000 Reserved. 86 01111111 Reserved. 87 11111111 Reserved. 88 00000000 Reserved. 89 00000000 Reserved. 90 00000000 Reserved. 91 00000000 Reserved. 92 00000000 Reserved. 93 00000000 Reserved. 94 00000000 Reserved. 95 00000000 Reserved. 96 01111111 Reserved. 80 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-6.Page-8Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 97 11111111 Reserved. 98 00000000 Reserved. 99 00000000 Reserved. 100 00000000 Reserved. 101 00000000 Reserved. 102 00000000 Reserved. 103 00000000 Reserved. 104 00000000 Reserved. 105 00000000 Reserved. 106 01111111 Reserved. 107 11111111 Reserved. 108 00000000 Reserved. 109 00000000 Reserved. 110 00000000 Reserved. 111 00000000 Reserved. 112 00000000 Reserved. 113 00000000 Reserved. 114 00000000 Reserved. 115 00000000 Reserved. 116 01111111 Reserved. 117 11111111 Reserved. 118 00000000 Reserved. 119 00000000 Reserved. 120 00000000 Reserved. 121 00000000 Reserved. 122 00000000 Reserved. 123 00000000 Reserved. 124 00000000 Reserved. 125 00000000 Reserved. 126 00000000 Reserved. 127 00000000 Reserved. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 81 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com 6.6 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127) Defaultvaluesshownforthispageonlybecomevalid100μsfollowingahardwareorsoftwarereset. Page9/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected The remaining page-9 registers are either reserved registers or are used for setting coefficients for the variousfiltersintheTLV320DAC3120.Reservedregistersshouldnotbewrittento. The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-7 is a list of the page-9 registers, excepting the previouslydescribedregister0. Table6-7.Page-9Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 XXXXXXXX Reserved.Donotwritetothisregister. CoefficientN0(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC65(15:8)ofDAC 2 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC65(7:0)ofDAC 3 11111111 miniDSP(DACBufferA) CoefficientN1(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC66(15:8)ofDAC 4 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC66(7:0)ofDAC 5 00000000 miniDSP(DACBufferA) CoefficientD1(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC67(15:8)ofDAC 6 00000000 miniDSP(DACBufferA) CoefficientD1(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC67(7:0)ofDAC 7 00000000 miniDSP(DACBufferA) 8 01111111 Reserved. 9 11111111 Reserved. 10 00000000 Reserved. 11 00000000 Reserved. 12 00000000 Reserved. 13 00000000 Reserved. CoefficientN0(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC71(15:8)ofDAC 14 01111111 miniDSP(DACBufferA) CoefficientN0(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC71(7:0)ofDACminiDSP 15 11110111 (DACBufferA) CoefficientN1(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC72(15:8)ofDAC 16 10000000 miniDSP(DACBufferA) CoefficientN1(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC72(7:0)ofDACminiDSP 17 00001001 (DACBufferA) CoefficientD1(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC73(15:8)ofDAC 18 01111111 miniDSP(DACBufferA) 82 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-7.Page-9Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientD1(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC73(7:0)ofDACminiDSP 19 11101111 (DACBufferA) CoefficientN0(15:8)forDRCfirst-orderlow-passfilterorCoefficientC74(15:8)ofDAC 20 00000000 miniDSP(DACBufferA) CoefficientN0(7:0)forDRCfirst-orderlow-passfilterorCoefficientC74(7:0)ofDACminiDSP 21 00010001 (DACBufferA) CoefficientN1(15:8)forDRCfirst-orderlow-passfilterorCoefficientC75(15:8)ofDAC 22 00000000 miniDSP(DACBufferA) CoefficientN1(7:0)forDRCfirst-orderlow-passfilterorCoefficientC75(7:0)ofDACminiDSP 23 00010001 (DACBufferA) CoefficientD1(15:8)forDRCfirst-orderlow-passfilterorCoefficientC76(15:8)ofDAC 24 01111111 miniDSP(DACBufferA) CoefficientD1(7:0)forDRCfirst-orderlow-passfilterorCoefficientC76(7:0)ofDACminiDSP 25 11011110 (DACBufferA) 26 00000000 CoefficientC77(15:8)ofDACminiDSP(DACBufferA) 27 00000000 CoefficientC77(7:0)ofDACminiDSP(DACBufferA) 28 00000000 CoefficientC78(15:8)ofDACminiDSP(DACBufferA) 29 00000000 CoefficientC78(7:0)ofDACminiDSP(DACBufferA) 30 00000000 CoefficientC79(15:8)ofDACminiDSP(DACBufferA) 31 00000000 CoefficientC79(7:0)ofDACminiDSP(DACBufferA) 32 00000000 CoefficientC80(15:8)ofDACminiDSP(DACBufferA) 33 00000000 CoefficientC80(7:0)ofDACminiDSP(DACBufferA) 34 00000000 CoefficientC81(15:8)ofDACminiDSP(DACBufferA) 35 00000000 CoefficientC81(7:0)ofDACminiDSP(DACBufferA) 36 00000000 CoefficientC82(15:8)ofDACminiDSP(DACBufferA) 37 00000000 CoefficientC82(7:0)ofDACminiDSP(DACBufferA) 38 00000000 CoefficientC83(15:8)ofDACminiDSP(DACBufferA) 39 00000000 CoefficientC83(7:0)ofDACminiDSP(DACBufferA) 40 00000000 CoefficientC84(15:8)ofDACminiDSP(DACBufferA) 41 00000000 CoefficientC84(7:0)ofDACminiDSP(DACBufferA) 42 00000000 CoefficientC85(15:8)ofDACminiDSP(DACBufferA) 43 00000000 CoefficientC85(7:0)ofDACminiDSP(DACBufferA) 44 00000000 CoefficientC86(15:8)ofDACminiDSP(DACBufferA) 45 00000000 CoefficientC86(7:0)ofDACminiDSP(DACBufferA) 46 00000000 CoefficientC87(15:8)ofDACminiDSP(DACBufferA) 47 00000000 CoefficientC87(7:0)ofDACminiDSP(DACBufferA) 48 00000000 CoefficientC88(15:8)ofDACminiDSP(DACBufferA) 49 00000000 CoefficientC88(7:0)ofDACminiDSP(DACBufferA) 50 00000000 CoefficientC89(15:8)ofDACminiDSP(DACBufferA) 51 00000000 CoefficientC89(7:0)ofDACminiDSP(DACBufferA) 52 00000000 CoefficientC90(15:8)ofDACminiDSP(DACBufferA) 53 00000000 CoefficientC90(7:0)ofDACminiDSP(DACBufferA) 54 00000000 CoefficientC91(15:8)ofDACminiDSP(DACBufferA) 55 00000000 CoefficientC91(7:0)ofDACminiDSP(DACBufferA) 56 00000000 CoefficientC92(15:8)ofDACminiDSP(DACBufferA) 57 00000000 CoefficientC92(7:0)ofDACminiDSP(DACBufferA) 58 00000000 CoefficientC93(15:8)ofDACminiDSP(DACBufferA) 59 00000000 CoefficientC93(7:0)ofDACminiDSP(DACBufferA) 60 00000000 CoefficientC94(15:8)ofDACminiDSP(DACBufferA) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 83 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-7.Page-9Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 61 00000000 CoefficientC94(7:0)ofDACminiDSP(DACBufferA) 62 00000000 CoefficientC95(15:8)ofDACminiDSP(DACBufferA) 63 00000000 CoefficientC95(7:0)ofDACminiDSP(DACBufferA) 64 00000000 CoefficientC96(15:8)ofDACminiDSP(DACBufferA) 65 00000000 CoefficientC96(7:0)ofDACminiDSP(DACBufferA) 66 00000000 CoefficientC97(15:8)ofDACminiDSP(DACBufferA) 67 00000000 CoefficientC97(7:0)ofDACminiDSP(DACBufferA) 68 00000000 CoefficientC98(15:8)ofDACminiDSP(DACBufferA) 69 00000000 CoefficientC98(7:0)ofDACminiDSP(DACBufferA) 70 00000000 CoefficientC99(15:8)ofDACminiDSP(DACBufferA) 71 00000000 CoefficientC99(7:0)ofDACminiDSP(DACBufferA) 72 00000000 CoefficientC100(15:8)ofDACminiDSP(DACBufferA) 73 00000000 CoefficientC100(7:0)ofDACminiDSP(DACBufferA) 74 00000000 CoefficientC101(15:8)ofDACminiDSP(DACBufferA) 75 00000000 CoefficientC101(7:0)ofDACminiDSP(DACBufferA) 76 00000000 CoefficientC102(15:8)ofDACminiDSP(DACBufferA) 77 00000000 CoefficientC102(7:0)ofDACminiDSP(DACBufferA) 78 00000000 CoefficientC103(15:8)ofDACminiDSP(DACBufferA) 79 00000000 CoefficientC103(7:0)ofDACminiDSP(DACBufferA) 80 00000000 CoefficientC104(15:8)ofDACminiDSP(DACBufferA) 81 00000000 CoefficientC104(7:0)ofDACminiDSP(DACBufferA) 82 00000000 CoefficientC105(15:8)ofDACminiDSP(DACBufferA) 83 00000000 CoefficientC105(7:0)ofDACminiDSP(DACBufferA) 84 00000000 CoefficientC106(15:8)ofDACminiDSP(DACBufferA) 85 00000000 CoefficientC106(7:0)ofDACminiDSP(DACBufferA) 86 00000000 CoefficientC107(15:8)ofDACminiDSP(DACBufferA) 87 00000000 CoefficientC107(15:8)ofDACminiDSP(DACBufferA) 88 00000000 CoefficientC108(7:0)ofDACminiDSP(DACBufferA) 89 00000000 CoefficientC108(7:0)ofDACminiDSP(DACBufferA) 90 00000000 CoefficientC109(15:8)ofDACminiDSP(DACBufferA) 91 00000000 CoefficientC109(7:0)ofDACminiDSP(DACBufferA) 92 00000000 CoefficientC110(15:8)ofDACminiDSP(DACBufferA) 93 00000000 CoefficientC110(7:0)ofDACminiDSP(DACBufferA) 94 00000000 CoefficientC111(15:8)ofDACminiDSP(DACBufferA) 95 00000000 CoefficientC111(7:0)ofDACminiDSP(DACBufferA) 96 00000000 CoefficientC112(15:8)ofDACminiDSP(DACBufferA) 97 00000000 CoefficientC112(7:0)ofDACminiDSP(DACBufferA) 98 00000000 CoefficientC113(15:8)ofDACminiDSP(DACBufferA) 99 00000000 CoefficientC113(7:0)ofDACminiDSP(DACBufferA) 100 00000000 CoefficientC114(15:8)ofDACminiDSP(DACBufferA) 101 00000000 CoefficientC114(7:0)ofDACminiDSP(DACBufferA) 102 00000000 CoefficientC11515:8)ofDACminiDSP(DACBufferA) 103 00000000 CoefficientC115(7:0)ofDACminiDSP(DACBufferA) 104 00000000 CoefficientC116(15:8)ofDACminiDSP(DACBufferA) 105 00000000 CoefficientC116(7:0)ofDACminiDSP(DACBufferA) 106 00000000 CoefficientC117(15:8)ofDACminiDSP(DACBufferA) 107 00000000 CoefficientC117(7:0)ofDACminiDSP(DACBufferA) 84 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-7.Page-9Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 108 00000000 CoefficientC118(15:8)ofDACminiDSP(DACBufferA) 109 00000000 CoefficientC118(7:0)ofDACminiDSP(DACBufferA) 110 00000000 CoefficientC119(15:8)ofDACminiDSP(DACBufferA) 111 00000000 CoefficientC119(7:0)ofDACminiDSP(DACBufferA) 112 00000000 CoefficientC120(15:8)ofDACminiDSP(DACBufferA) 113 00000000 CoefficientC120(7:0)ofDACminiDSP(DACBufferA) 114 00000000 CoefficientC121(15:8)ofDACminiDSP(DACBufferA) 115 00000000 CoefficientC121(7:0)ofDACminiDSP(DACBufferA) 116 00000000 CoefficientC122(15:8)ofDACminiDSP(DACBufferA) 117 00000000 CoefficientC122(7:0)ofDACminiDSP(DACBufferA) 118 00000000 CoefficientC123(15:8)ofDACminiDSP(DACBufferA) 119 00000000 CoefficientC123(7:0)ofDACminiDSP(DACBufferA) 120 00000000 CoefficientC124(15:8)ofDACminiDSP(DACBufferA) 121 00000000 CoefficientC124(7:0)ofDACminiDSP(DACBufferA) 122 00000000 CoefficientC125(15:8)ofDACminiDSP(DACBufferA) 123 00000000 CoefficientC125(7:0)ofDACminiDSP(DACBufferA) 124 00000000 CoefficientC126(15:8)ofDACminiDSP(DACBufferA) 125 00000000 CoefficientC126(7:0)ofDACminiDSP(DACBufferA) 126 00000000 CoefficientC127(15:8)ofDACminiDSP(DACBufferA) 127 00000000 CoefficientC127(7:0)ofDACminiDSP(DACBufferA) 6.7 Control Registers, Page 10: DAC Programmable Coefficients RAM Buffer A (129:191) Table6-8.Page-10Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 XXXXXXXX Reserved.Donotwritetothisregister. 2 00000000 CoefficientC129(15:8)ofDACminiDSP(DACBufferA) 3 00000000 CoefficientC129(7:0)ofDACminiDSP(DACBufferA) 4 00000000 CoefficientC130(15:8)ofDACminiDSP(DACBufferA) 5 00000000 CoefficientC130(7:0)ofDACminiDSP(DACBufferA) 6 00000000 CoefficientC131(15:8)ofDACminiDSP(DACBufferA) 7 00000000 CoefficientC131(7:0)ofDACminiDSP(DACBufferA) 8 00000000 CoefficientC132(15:8)ofDACminiDSP(DACBufferA) 9 00000000 CoefficientC132(7:0)ofDACminiDSP(DACBufferA) 10 00000000 CoefficientC133(15:8)ofDACminiDSP(DACBufferA) 11 00000000 CoefficientC133(7:0)ofDACminiDSP(DACBufferA) 12 00000000 CoefficientC134(15:8)ofDACminiDSP(DACBufferA) 13 00000000 CoefficientC134(7:0)ofDACminiDSP(DACBufferA) 14 00000000 CoefficientC135(15:8)ofDACminiDSP(DACBufferA) 15 00000000 CoefficientC135(7:0)ofDACminiDSP(DACBufferA) 16 00000000 CoefficientC136(15:8)ofDACminiDSP(DACBufferA) 17 00000000 CoefficientC136(7:0)ofDACminiDSP(DACBufferA) 18 00000000 CoefficientC137(15:8)ofDACminiDSP(DACBufferA) 19 00000000 CoefficientC137(7:0)ofDACminiDSP(DACBufferA) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 85 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-8.Page-10Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 20 00000000 CoefficientC138(15:8)ofDACminiDSP(DACBufferA) 21 00000000 CoefficientC138(7:0)ofDACminiDSP(DACBufferA) 22 00000000 CoefficientC139(15:8)ofDACminiDSP(DACBufferA) 23 00000000 CoefficientC139(7:0)ofDACminiDSP(DACBufferA) 24 00000000 CoefficientC140(15:8)ofDACminiDSP(DACBufferA) 25 00000000 CoefficientC140(7:0)ofDACminiDSP(DACBufferA) 26 00000000 CoefficientC141(15:8)ofDACminiDSP(DACBufferA) 27 00000000 CoefficientC141(7:0)ofDACminiDSP(DACBufferA) 28 00000000 CoefficientC142(15:8)ofDACminiDSP(DACBufferA) 29 00000000 CoefficientC142(7:0)ofDACminiDSP(DACBufferA) 30 00000000 CoefficientC143(15:8)ofDACminiDSP(DACBufferA) 31 00000000 CoefficientC143(7:0)ofDACminiDSP(DACBufferA) 32 00000000 CoefficientC144(15:8)ofDACminiDSP(DACBufferA) 33 00000000 CoefficientC144(7:0)ofDACminiDSP(DACBufferA) 34 00000000 CoefficientC145(15:8)ofDACminiDSP(DACBufferA) 35 00000000 CoefficientC145(7:0)ofDACminiDSP(DACBufferA) 36 00000000 CoefficientC146(15:8)ofDACminiDSP(DACBufferA) 37 00000000 CoefficientC146(7:0)ofDACminiDSP(DACBufferA) 38 00000000 CoefficientC147(15:8)ofDACminiDSP(DACBufferA) 39 00000000 CoefficientC147(7:0)ofDACminiDSP(DACBufferA) 40 00000000 CoefficientC148(15:8)ofDACminiDSP(DACBufferA) 41 00000000 CoefficientC148(7:0)ofDACminiDSP(DACBufferA) 42 00000000 CoefficientC149(15:8)ofDACminiDSP(DACBufferA) 43 00000000 CoefficientC149(7:0)ofDACminiDSP(DACBufferA) 44 00000000 CoefficientC150(15:8)ofDACminiDSP(DACBufferA) 45 00000000 CoefficientC150(7:0)ofDACminiDSP(DACBufferA) 46 00000000 CoefficientC151(15:8)ofDACminiDSP(DACBufferA) 47 00000000 CoefficientC151(7:0)ofDACminiDSP(DACBufferA) 48 00000000 CoefficientC152(15:8)ofDACminiDSP(DACBufferA) 49 00000000 CoefficientC152(7:0)ofDACminiDSP(DACBufferA) 50 00000000 CoefficientC153(15:8)ofDACminiDSP(DACBufferA) 51 00000000 CoefficientC153(7:0)ofDACminiDSP(DACBufferA) 52 00000000 CoefficientC154(15:8)ofDACminiDSP(DACBufferA) 53 00000000 CoefficientC154(7:0)ofDACminiDSP(DACBufferA) 54 00000000 CoefficientC155(15:8)ofDACminiDSP(DACBufferA) 55 00000000 CoefficientC155(7:0)ofDACminiDSP(DACBufferA) 56 00000000 CoefficientC156(15:8)ofDACminiDSP(DACBufferA) 57 00000000 CoefficientC156(7:0)ofDACminiDSP(DACBufferA) 58 00000000 CoefficientC157(15:8)ofDACminiDSP(DACBufferA) 59 00000000 CoefficientC157(7:0)ofDACminiDSP(DACBufferA) 60 00000000 CoefficientC158(15:8)ofDACminiDSP(DACBufferA) 61 00000000 CoefficientC158(7:0)ofDACminiDSP(DACBufferA) 62 00000000 CoefficientC159(15:8)ofDACminiDSP(DACBufferA) 63 00000000 CoefficientC159(7:0)ofDACminiDSP(DACBufferA) 64 00000000 CoefficientC160(15:8)ofDACminiDSP(DACBufferA) 65 00000000 CoefficientC160(7:0)ofDACminiDSP(DACBufferA) 66 00000000 CoefficientC161(15:8)ofDACminiDSP(DACBufferA) 86 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-8.Page-10Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 67 00000000 CoefficientC161(7:0)ofDACminiDSP(DACBufferA) 68 00000000 CoefficientC162(15:8)ofDACminiDSP(DACBufferA) 69 00000000 CoefficientC162(7:0)ofDACminiDSP(DACBufferA) 70 00000000 CoefficientC163(15:8)ofDACminiDSP(DACBufferA) 71 00000000 CoefficientC163(7:0)ofDACminiDSP(DACBufferA) 72 00000000 CoefficientC164(15:8)ofDACminiDSP(DACBufferA) 73 00000000 CoefficientC164(7:0)ofDACminiDSP(DACBufferA) 74 00000000 CoefficientC165(15:8)ofDACminiDSP(DACBufferA) 75 00000000 CoefficientC165(7:0)ofDACminiDSP(DACBufferA) 76 00000000 CoefficientC166(15:8)ofDACminiDSP(DACBufferA) 77 00000000 CoefficientC166(7:0)ofDACminiDSP(DACBufferA) 78 00000000 CoefficientC167(15:8)ofDACminiDSP(DACBufferA) 79 00000000 CoefficientC167(7:0)ofDACminiDSP(DACBufferA) 80 00000000 CoefficientC168(15:8)ofDACminiDSP(DACBufferA) 81 00000000 CoefficientC168(7:0)ofDACminiDSP(DACBufferA) 82 00000000 CoefficientC169(15:8)ofDACminiDSP(DACBufferA) 83 00000000 CoefficientC169(7:0)ofDACminiDSP(DACBufferA) 84 00000000 CoefficientC170(15:8)ofDACminiDSP(DACBufferA) 85 00000000 CoefficientC170(7:0)ofDACminiDSP(DACBufferA) 86 00000000 CoefficientC171(15:8)ofDACminiDSP(DACBufferA) 87 00000000 CoefficientC171(7:0)ofDACminiDSP(DACBufferA) 88 00000000 CoefficientC172(15:8)ofDACminiDSP(DACBufferA) 89 00000000 CoefficientC172(7:0)ofDACminiDSP(DACBufferA) 90 00000000 CoefficientC173(15:8)ofDACminiDSP(DACBufferA) 91 00000000 CoefficientC173(7:0)ofDACminiDSP(DACBufferA) 92 00000000 CoefficientC174(15:8)ofDACminiDSP(DACBufferA) 93 00000000 CoefficientC174(7:0)ofDACminiDSP(DACBufferA) 94 00000000 CoefficientC175(15:8)ofDACminiDSP(DACBufferA) 95 00000000 CoefficientC175(7:0)ofDACminiDSP(DACBufferA) 96 00000000 CoefficientC176(15:8)ofDACminiDSP(DACBufferA) 97 00000000 CoefficientC176(7:0)ofDACminiDSP(DACBufferA) 98 00000000 CoefficientC177(15:8)ofDACminiDSP(DACBufferA) 99 00000000 CoefficientC177(7:0)ofDACminiDSP(DACBufferA) 100 00000000 CoefficientC178(15:8)ofDACminiDSP(DACBufferA) 101 00000000 CoefficientC178(7:0)ofDACminiDSP(DACBufferA) 102 00000000 CoefficientC179(15:8)ofDACminiDSP(DACBufferA) 103 00000000 CoefficientC179(7:0)ofDACminiDSP(DACBufferA) 104 00000000 CoefficientC180(15:8)ofDACminiDSP(DACBufferA) 105 00000000 CoefficientC180(7:0)ofDACminiDSP(DACBufferA) 106 00000000 CoefficientC181(15:8)ofDACminiDSP(DACBufferA) 107 00000000 CoefficientC181(7:0)ofDACminiDSP(DACBufferA) 108 00000000 CoefficientC182(15:8)ofDACminiDSP(DACBufferA) 109 00000000 CoefficientC182(7:0)ofDACminiDSP(DACBufferA) 110 00000000 CoefficientC183(15:8)ofDACminiDSP(DACBufferA) 111 00000000 CoefficientC183(7:0)ofDACminiDSP(DACBufferA) 112 00000000 CoefficientC184(15:8)ofDACminiDSP(DACBufferA) 113 00000000 CoefficientC184(7:0)ofDACminiDSP(DACBufferA) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 87 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-8.Page-10Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 114 00000000 CoefficientC185(15:8)ofDACminiDSP(DACBufferA) 115 00000000 CoefficientC185(7:0)ofDACminiDSP(DACBufferA) 116 00000000 CoefficientC186(15:8)ofDACminiDSP(DACBufferA) 117 00000000 CoefficientC186(7:0)ofDACminiDSP(DACBufferA) 118 00000000 CoefficientC187(15:8)ofDACminiDSP(DACBufferA) 119 00000000 CoefficientC187(7:0)ofDACminiDSP(DACBufferA) 120 00000000 CoefficientC188(15:8)ofDACminiDSP(DACBufferA) 121 00000000 CoefficientC188(7:0)ofDACminiDSP(DACBufferA) 122 00000000 CoefficientC189(15:8)ofDACminiDSP(DACBufferA) 123 00000000 CoefficientC189(7:0)ofDACminiDSP(DACBufferA) 124 00000000 CoefficientC190(15:8)ofDACminiDSP(DACBufferA) 125 00000000 CoefficientC190(7:0)ofDACminiDSP(DACBufferA) 126 00000000 CoefficientC191(15:8)ofDACminiDSP(DACBufferA) 127 00000000 CoefficientC191(7:0)ofDACminiDSP(DACBufferA) 6.8 Control Registers, Page 11: DAC Programmable Coefficients RAM Buffer A (193:255) Table6-9.Page-11Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 XXXXXXXX Reserved.Donotwritetothisregister. 2 00000000 CoefficientC193(15:8)ofDACminiDSP(DACBufferA) 3 00000000 CoefficientC193(7:0)ofDACminiDSP(DACBufferA) 4 00000000 CoefficientC194(15:8)ofDACminiDSP(DACBufferA) 5 00000000 CoefficientC194(7:0)ofDACminiDSP(DACBufferA) 6 00000000 CoefficientC195(15:8)ofDACminiDSP(DACBufferA) 7 00000000 CoefficientC195(7:0)ofDACminiDSP(DACBufferA) 8 00000000 CoefficientC196(15:8)ofDACminiDSP(DACBufferA) 9 00000000 CoefficientC196(7:0)ofDACminiDSP(DACBufferA) 10 00000000 CoefficientC197(15:8)ofDACminiDSP(DACBufferA) 11 00000000 CoefficientC197(7:0)ofDACminiDSP(DACBufferA) 12 00000000 CoefficientC198(15:8)ofDACminiDSP(DACBufferA) 13 00000000 CoefficientC198(7:0)ofDACminiDSP(DACBufferA) 14 00000000 CoefficientC199(15:8)ofDACminiDSP(DACBufferA) 15 00000000 CoefficientC199(7:0)ofDACminiDSP(DACBufferA) 16 00000000 CoefficientC200(15:8)ofDACminiDSP(DACBufferA) 17 00000000 CoefficientC200(7:0)ofDACminiDSP(DACBufferA) 18 00000000 CoefficientC201(15:8)ofDACminiDSP(DACBufferA) 19 00000000 CoefficientC201(7:0)ofDACminiDSP(DACBufferA) 20 00000000 CoefficientC202(15:8)ofDACminiDSP(DACBufferA) 21 00000000 CoefficientC202(7:0)ofDACminiDSP(DACBufferA) 22 00000000 CoefficientC203(15:8)ofDACminiDSP(DACBufferA) 23 00000000 CoefficientC203(7:0)ofDACminiDSP(DACBufferA) 24 00000000 CoefficientC204(15:8)ofDACminiDSP(DACBufferA) 25 00000000 CoefficientC204(7:0)ofDACminiDSP(DACBufferA) 88 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-9.Page-11Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 26 00000000 CoefficientC205(15:8)ofDACminiDSP(DACBufferA) 27 00000000 CoefficientC205(7:0)ofDACminiDSP(DACBufferA) 28 00000000 CoefficientC206(15:8)ofDACminiDSP(DACBufferA) 29 00000000 CoefficientC206(7:0)ofDACminiDSP(DACBufferA) 30 00000000 CoefficientC207(15:8)ofDACminiDSP(DACBufferA) 31 00000000 CoefficientC207(7:0)ofDACminiDSP(DACBufferA) 32 00000000 CoefficientC208(15:8)ofDACminiDSP(DACBufferA) 33 00000000 CoefficientC208(7:0)ofDACminiDSP(DACBufferA) 34 00000000 CoefficientC209(15:8)ofDACminiDSP(DACBufferA) 35 00000000 CoefficientC209(7:0)ofDACminiDSP(DACBufferA) 36 00000000 CoefficientC210(15:8)ofDACminiDSP(DACBufferA) 37 00000000 CoefficientC210(7:0)ofDACminiDSP(DACBufferA) 38 00000000 CoefficientC211(15:8)ofDACminiDSP(DACBufferA) 39 00000000 CoefficientC211(7:0)ofDACminiDSP(DACBufferA) 40 00000000 CoefficientC212(15:8)ofDACminiDSP(DACBufferA) 41 00000000 CoefficientC212(7:0)ofDACminiDSP(DACBufferA) 42 00000000 CoefficientC213(15:8)ofDACminiDSP(DACBufferA) 43 00000000 CoefficientC213(7:0)ofDACminiDSP(DACBufferA) 44 00000000 CoefficientC214(15:8)ofDACminiDSP(DACBufferA) 45 00000000 CoefficientC214(7:0)ofDACminiDSP(DACBufferA) 46 00000000 CoefficientC215(15:8)ofDACminiDSP(DACBufferA) 47 00000000 CoefficientC215(7:0)ofDACminiDSP(DACBufferA) 48 00000000 CoefficientC216(15:8)ofDACminiDSP(DACBufferA) 49 00000000 CoefficientC216(7:0)ofDACminiDSP(DACBufferA) 50 00000000 CoefficientC217(15:8)ofDACminiDSP(DACBufferA) 51 00000000 CoefficientC217(7:0)ofDACminiDSP(DACBufferA) 52 00000000 CoefficientC218(15:8)ofDACminiDSP(DACBufferA) 53 00000000 CoefficientC218(7:0)ofDACminiDSP(DACBufferA) 54 00000000 CoefficientC219(15:8)ofDACminiDSP(DACBufferA) 55 00000000 CoefficientC219(7:0)ofDACminiDSP(DACBufferA) 56 00000000 CoefficientC220(15:8)ofDACminiDSP(DACBufferA) 57 00000000 CoefficientC220(7:0)ofDACminiDSP(DACBufferA) 58 00000000 CoefficientC221(15:8)ofDACminiDSP(DACBufferA) 59 00000000 CoefficientC221(7:0)ofDACminiDSP(DACBufferA) 60 00000000 CoefficientC222(15:8)ofDACminiDSP(DACBufferA) 61 00000000 CoefficientC222(7:0)ofDACminiDSP(DACBufferA) 62 00000000 CoefficientC223(15:8)ofDACminiDSP(DACBufferA) 63 00000000 CoefficientC223(7:0)ofDACminiDSP(DACBufferA) 64 00000000 CoefficientC224(15:8)ofDACminiDSP(DACBufferA) 65 00000000 CoefficientC224(7:0)ofDACminiDSP(DACBufferA) 66 00000000 CoefficientC225(15:8)ofDACminiDSP(DACBufferA) 67 00000000 CoefficientC225(7:0)ofDACminiDSP(DACBufferA) 68 00000000 CoefficientC226(15:8)ofDACminiDSP(DACBufferA) 69 00000000 CoefficientC226(7:0)ofDACminiDSP(DACBufferA) 70 00000000 CoefficientC227(15:8)ofDACminiDSP(DACBufferA) 71 00000000 CoefficientC227(7:0)ofDACminiDSP(DACBufferA) 72 00000000 CoefficientC228(15:8)ofDACminiDSP(DACBufferA) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 89 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-9.Page-11Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 73 00000000 CoefficientC228(7:0)ofDACminiDSP(DACBufferA) 74 00000000 CoefficientC229(15:8)ofDACminiDSP(DACBufferA) 75 00000000 CoefficientC229(7:0)ofDACminiDSP(DACBufferA) 76 00000000 CoefficientC230(15:8)ofDACminiDSP(DACBufferA) 77 00000000 CoefficientC230(7:0)ofDACminiDSP(DACBufferA) 78 00000000 CoefficientC231(15:8)ofDACminiDSP(DACBufferA) 79 00000000 CoefficientC231(7:0)ofDACminiDSP(DACBufferA) 80 00000000 CoefficientC232(15:8)ofDACminiDSP(DACBufferA) 81 00000000 CoefficientC232(7:0)ofDACminiDSP(DACBufferA) 82 00000000 CoefficientC233(15:8)ofDACminiDSP(DACBufferA) 83 00000000 CoefficientC233(7:0)ofDACminiDSP(DACBufferA) 84 00000000 CoefficientC234(15:8)ofDACminiDSP(DACBufferA) 85 00000000 CoefficientC234(7:0)ofDACminiDSP(DACBufferA) 86 00000000 CoefficientC235(15:8)ofDACminiDSP(DACBufferA) 87 00000000 CoefficientC235(7:0)ofDACminiDSP(DACBufferA) 88 00000000 CoefficientC236(15:8)ofDACminiDSP(DACBufferA) 89 00000000 CoefficientC236(7:0)ofDACminiDSP(DACBufferA) 90 00000000 CoefficientC237(15:8)ofDACminiDSP(DACBufferA) 91 00000000 CoefficientC237(7:0)ofDACminiDSP(DACBufferA) 92 00000000 CoefficientC238(15:8)ofDACminiDSP(DACBufferA) 93 00000000 CoefficientC238(7:0)ofDACminiDSP(DACBufferA) 94 00000000 CoefficientC239(15:8)ofDACminiDSP(DACBufferA) 95 00000000 CoefficientC239(7:0)ofDACminiDSP(DACBufferA) 96 00000000 CoefficientC240(15:8)ofDACminiDSP(DACBufferA) 97 00000000 CoefficientC240(7:0)ofDACminiDSP(DACBufferA) 98 00000000 CoefficientC241(15:8)ofDACminiDSP(DACBufferA) 99 00000000 CoefficientC241(7:0)ofDACminiDSP(DACBufferA) 100 00000000 CoefficientC242(15:8)ofDACminiDSP(DACBufferA) 101 00000000 CoefficientC242(7:0)ofDACminiDSP(DACBufferA) 102 00000000 CoefficientC243(15:8)ofDACminiDSP(DACBufferA) 103 00000000 CoefficientC243(7:0)ofDACminiDSP(DACBufferA) 104 00000000 CoefficientC244(15:8)ofDACminiDSP(DACBufferA) 105 00000000 CoefficientC244(7:0)ofDACminiDSP(DACBufferA) 106 00000000 CoefficientC245(15:8)ofDACminiDSP(DACBufferA) 107 00000000 CoefficientC245(7:0)ofDACminiDSP(DACBufferA) 108 00000000 CoefficientC246(15:8)ofDACminiDSP(DACBufferA) 109 00000000 CoefficientC246(7:0)ofDACminiDSP(DACBufferA) 110 00000000 CoefficientC247(15:8)ofDACminiDSP(DACBufferA) 111 00000000 CoefficientC247(7:0)ofDACminiDSP(DACBufferA) 112 00000000 CoefficientC248(15:8)ofDACminiDSP(DACBufferA) 113 00000000 CoefficientC248(7:0)ofDACminiDSP(DACBufferA) 114 00000000 CoefficientC249(15:8)ofDACminiDSP(DACBufferA) 115 00000000 CoefficientC249(7:0)ofDACminiDSP(DACBufferA) 116 00000000 CoefficientC250(15:8)ofDACminiDSP(DACBufferA) 117 00000000 CoefficientC250(7:0)ofDACminiDSP(DACBufferA) 118 00000000 CoefficientC251(15:8)ofDACminiDSP(DACBufferA) 119 00000000 CoefficientC251(7:0)ofDACminiDSP(DACBufferA) 90 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-9.Page-11Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 120 00000000 CoefficientC252(15:8)ofDACminiDSP(DACBufferA) 121 00000000 CoefficientC252(7:0)ofDACminiDSP(DACBufferA) 122 00000000 CoefficientC253(15:8)ofDACminiDSP(DACBufferA) 123 00000000 CoefficientC253(7:0)ofDACminiDSP(DACBufferA) 124 00000000 CoefficientC254(15:8)ofDACminiDSP(DACBufferA) 125 00000000 CoefficientC254(7:0)ofDACminiDSP(DACBufferA) 126 00000000 CoefficientC255(15:8)ofDACminiDSP(DACBufferA) 127 00000000 CoefficientC255(7:0)ofDACminiDSP(DACBufferA) 6.9 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63) Table6-10.Page-12Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 00000000 Reserved.Donotwritetothisregister. CoefficientNO(15:8)forleftDAC-programmablebiquadAorCoefficientC1(15:8)ofDAC 2 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadAorCoefficientC1(7:0)ofDAC 3 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadAorCoefficientC2(15:8)ofDAC 4 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadAorCoefficientC2(7:0)ofDAC 5 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadAorCoefficientC3(15:8)ofDAC 6 00000000 miniDSP(DACBufferB) CoefficientN2(7:0)forleftDAC-programmablebiquadAorCoefficientC3(7:0)ofDAC 7 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadAorCoefficientC4(15:8)ofDAC 8 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadAorCoefficientC4(7:0)ofDAC 9 00000000 miniDSP(DACBufferB) CoefficientD2(15:8)forleftDAC-programmablebiquadAorCoefficientC5(15:8)ofDAC 10 00000000 miniDSP(DACBufferB) CoefficientD2(7:0)forleftDAC-programmablebiquadAorCoefficientC5(7:0)ofDAC 11 00000000 miniDSP(DACBufferB) CoefficientNO(15:8)forleftDAC-programmablebiquadBorCoefficientC6(15:8)ofDAC 12 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadBorCoefficientC6(7:0)ofDAC 13 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadBorCoefficientC7(15:8)ofDAC 14 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadBorCoefficientC7(7:0)ofDAC 15 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadBorCoefficientC8(15:8)ofDAC 16 00000000 miniDSP(DACBufferB) CoefficientN2(7:0)forleftDAC-programmablebiquadBorCoefficientC8(7:0)ofDAC 17 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadBorCoefficientC9(15:8)ofDAC 18 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadBorCoefficientC9(7:0)ofDAC 19 00000000 miniDSP(DACBufferB) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 91 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-10.Page-12Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientD2(15:8)forleftDAC-programmablebiquadBorCoefficientC10(15:8)ofDAC 20 00000000 miniDSP(DACBufferB) CoefficientD2(7:0)forleftDAC-programmablebiquadBorCoefficientC10(7:0)ofDAC 21 00000000 miniDSP(DACBufferB) CoefficientNO(15:8)forleftDAC-programmablebiquadCorCoefficientC11(15:8)ofDAC 22 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadCorCoefficientC11(7:0)ofDAC 23 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadCorCoefficientC12(15:8)ofDAC 24 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadCorCoefficientC12(7:0)ofDAC 25 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadCorCoefficientC13(15:8)ofDAC 26 00000000 miniDSP(DACBufferB) CoefficientN2(7:0)forleftDAC-programmablebiquadCorCoefficientC13(7:0)ofDAC 27 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadCorCoefficientC14(15:8)ofDAC 28 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadCorCoefficientC14(7:0)ofDAC 29 00000000 miniDSP(DACBufferB) CoefficientD2(15:8)forleftDAC-programmablebiquadCorCoefficientC15(15:8)ofDAC 30 00000000 miniDSP(DACBufferB) CoefficientD2(7:0)forleftDAC-programmablebiquadCorCoefficientC15(7:0)ofDAC 31 00000000 miniDSP(DACBufferB) CoefficientNO(15:8)forleftDAC-programmablebiquadDorCoefficientC16(15:8)ofDAC 32 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadDorCoefficientC16(7:0)ofDAC 33 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadDorCoefficientC17(15:8)ofDAC 34 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadDorCoefficientC17(7:0)ofDAC 35 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadDorCoefficientC18(15:8)ofDAC 36 00000000 miniDSP(DACBufferB) CoefficientN2(7:0)forleftDAC-programmablebiquadDorCoefficientC18(7:0)ofDAC 37 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadDorCoefficientC19(15:8)ofDAC 38 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadDorCoefficientC19(7:0)ofDAC 39 00000000 miniDSP(DACBufferB) CoefficientD2(15:8)forleftDAC-programmablebiquadDorCoefficientC20(15:8)ofDAC 40 00000000 miniDSP(DACBufferB) CoefficientD2(17:0)forleftDAC-programmablebiquadDorCoefficientC20(7:0)ofDAC 41 00000000 miniDSP(DACBufferB) CoefficientNO(15:8)forleftDAC-programmablebiquadEorCoefficientC21(15:8)ofDAC 42 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadEorCoefficientC21(7:0)ofDAC 43 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadEorCoefficientC22(15:8)ofDAC 44 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadEorCoefficientC22(7:0)ofDAC 45 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadEorCoefficientC23(15:8)ofDAC 46 00000000 miniDSP(DACBufferB) 92 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-10.Page-12Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER CoefficientN2(7:0)forleftDAC-programmablebiquadEorCoefficientC23(7:0)ofDAC 47 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadEorCoefficientC24(15:8)ofDAC 48 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadEorCoefficientC24(7:0)ofDAC 49 00000000 miniDSP(DACBufferB) CoefficientD2(15:8)forleftDAC-programmablebiquadEorCoefficientC25(15:8)ofDAC 50 00000000 miniDSP(DACBufferB) CoefficientD2(7:0)forleftDAC-programmablebiquadEorCoefficientC25(7:0)ofDAC 51 00000000 miniDSP(DACBufferB) CoefficientNO(15:8)forleftDAC-programmablebiquadForCoefficientC26(15:8)ofDAC 52 01111111 miniDSP(DACBufferB) CoefficientNO(7:0)forleftDAC-programmablebiquadForCoefficientC26(7:0)ofDAC 53 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablebiquadForCoefficientC27(15:8)ofDAC 54 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablebiquadForCoefficientC27(7:0)ofDAC 55 00000000 miniDSP(DACBufferB) CoefficientN2(15:8)forleftDAC-programmablebiquadForCoefficientC28(15:8)ofDAC 56 00000000 miniDSP(DACBufferB) CoefficientN2(7:0)forleftDAC-programmablebiquadForCoefficientC28(7:0)ofDAC 57 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablebiquadForCoefficientC29(15:8)ofDAC 58 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablebiquadForCoefficientC29(7:0)ofDAC 59 00000000 miniDSP(DACBufferB) CoefficientD2(15:8)forleftDAC-programmablebiquadForCoefficientC30(15:8)ofDAC 60 00000000 miniDSP(DACBufferB) CoefficientD2(7:0)forleftDAC-programmablebiquadForCoefficientC30(7:0)ofDAC 61 00000000 miniDSP(DACBufferB) 62 00000000 CoefficientC31(15:8)ofDACminiDSP(DACBufferB) 63 00000000 CoefficientC31(7:0)ofDACminiDSP(DACBufferB) CoefficientC32(15:8)ofDACminiDSP(DACBufferB)–alsousedforthe3DPGAfor 64 00000000 PRB_P23,PRB_P24andPRB_P25 CoefficientC32(7:0)ofDACminiDSP(DACBufferB)–alsousedforthe3DPGAfor 65 00000000 PRB_P23,PRB_P24andPRB_P25 66 01111111 Reserved. 67 11111111 Reserved. 68 00000000 Reserved. 69 00000000 Reserved. 70 00000000 Reserved. 71 00000000 Reserved. 72 00000000 Reserved. 73 00000000 Reserved. 74 00000000 Reserved. 75 00000000 Reserved. 76 01111111 Reserved. 77 11111111 Reserved. 78 00000000 Reserved. 79 00000000 Reserved. 80 00000000 Reserved. 81 00000000 Reserved. Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 93 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-10.Page-12Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 82 00000000 Reserved. 83 00000000 Reserved. 84 00000000 Reserved. 85 00000000 Reserved. 86 01111111 Reserved. 87 11111111 Reserved. 88 00000000 Reserved. 89 00000000 Reserved. 90 00000000 Reserved. 91 00000000 Reserved. 92 00000000 Reserved. 93 00000000 Reserved. 94 00000000 Reserved. 95 00000000 Reserved. 96 01111111 Reserved. 97 11111111 Reserved. 98 00000000 Reserved. 99 00000000 Reserved. 100 00000000 Reserved. 101 00000000 Reserved. 102 00000000 Reserved. 103 00000000 Reserved. 104 00000000 Reserved. 105 00000000 Reserved. 106 01111111 Reserved. 107 11111111 Reserved. 108 00000000 Reserved. 109 00000000 Reserved. 110 00000000 Reserved. 111 00000000 Reserved. 112 00000000 Reserved. 113 00000000 Reserved. 114 00000000 Reserved. 115 00000000 Reserved. 116 01111111 Reserved. 117 11111111 Reserved. 118 00000000 Reserved. 119 00000000 Reserved. 120 00000000 Reserved. 121 00000000 Reserved. 122 00000000 Reserved. 123 00000000 Reserved. 124 00000000 Reserved. 125 00000000 Reserved. 126 00000000 Reserved. 127 00000000 Reserved. 94 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 6.10 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127) Table6-11.Page-13Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 00000000 Reserved.Donotwritetothisregister. CoefficientN0(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC65(15:8)ofDAC 2 01111111 miniDSP(DACBufferB) CoefficientN0(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC65(7:0)ofDAC 3 11111111 miniDSP(DACBufferB) CoefficientN1(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC66(15:8)ofDAC 4 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC66(7:0)ofDAC 5 00000000 miniDSP(DACBufferB) CoefficientD1(15:8)forleftDAC-programmablefirst-orderIIRorCoefficientC67(15:8)ofDAC 6 00000000 miniDSP(DACBufferB) CoefficientD1(7:0)forleftDAC-programmablefirst-orderIIRorCoefficientC67(7:0)ofDAC 7 00000000 miniDSP(DACBufferB) 8 01111111 Reserved. 9 11111111 Reserved. 10 00000000 Reserved. 11 00000000 Reserved. 12 00000000 Reserved. 13 00000000 Reserved. CoefficientN0(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC71(15:8)ofDAC 14 01111111 miniDSP(DACBufferB) CoefficientN0(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC71(7:0)ofDACminiDSP 15 11110111 (DACBufferB) CoefficientN1(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC72(15:8)ofDAC 16 10000000 miniDSP(DACBufferB) CoefficientN1(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC72(7:0)ofDACminiDSP 17 00001001 (DACBufferB) CoefficientD1(15:8)forDRCfirst-orderhigh-passfilterorCoefficientC73(15:8)ofDAC 18 01111111 miniDSP(DACBufferB) CoefficientD1(7:0)forDRCfirst-orderhigh-passfilterorCoefficientC73(7:0)ofDACminiDSP 19 11101111 (DACBufferB) CoefficientN0(15:8)forDRCfirst-orderlow-passfilterorCoefficientC74(15:8)ofDAC 20 00000000 miniDSP(DACBufferB) CoefficientN0(7:0)forDRCfirst-orderlow-passfilterorCoefficientC74(7:0)ofDACminiDSP 21 00010001 (DACBufferB) CoefficientN1(15:8)forDRCfirst-orderlow-passfilterorCoefficientC75(15:8)ofDAC 22 00000000 miniDSP(DACBufferB) CoefficientN1(7:0)forDRCfirst-orderlow-passfilterorCoefficientC75(7:0)ofDACminiDSP 23 00010001 (DACBufferB) CoefficientD1(15:8)forDRCfirst-orderlow-passfilterorCoefficientC76(15:8)ofDAC 24 01111111 miniDSP(DACBufferB) CoefficientD1(7:0)forDRCfirst-orderlow-passfilterorCoefficientC76(7:0)ofDACminiDSP 25 11011110 (DACBufferB) 26 00000000 CoefficientC77(15:8)ofDACminiDSP(DACBufferB) 27 00000000 CoefficientC77(7:0)ofDACminiDSP(DACBufferB) 28 00000000 CoefficientC78(15:8)ofDACminiDSP(DACBufferB) 29 00000000 CoefficientC78(7:0)ofDACminiDSP(DACBufferB) 30 00000000 CoefficientC79(15:8)ofDACminiDSP(DACBufferB) 31 00000000 CoefficientC79(7:0)ofDACminiDSP(DACBufferB) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 95 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-11.Page-13Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 32 00000000 CoefficientC80(15:8)ofDACminiDSP(DACBufferB) 33 00000000 CoefficientC80(7:0)ofDACminiDSP(DACBufferB) 34 00000000 CoefficientC81(15:8)ofDACminiDSP(DACBufferB) 35 00000000 CoefficientC81(7:0)ofDACminiDSP(DACBufferB) 36 00000000 CoefficientC82(15:8)ofDACminiDSP(DACBufferB) 37 00000000 CoefficientC82(7:0)ofDACminiDSP(DACBufferB) 38 00000000 CoefficientC83(15:8)ofDACminiDSP(DACBufferB) 39 00000000 CoefficientC83(7:0)ofDACminiDSP(DACBufferB) 40 00000000 CoefficientC84(15:8)ofDACminiDSP(DACBufferB) 41 00000000 CoefficientC84(7:0)ofDACminiDSP(DACBufferB) 42 00000000 CoefficientC85(15:8)ofDACminiDSP(DACBufferB) 43 00000000 CoefficientC85(7:0)ofDACminiDSP(DACBufferB) 44 00000000 CoefficientC86(15:8)ofDACminiDSP(DACBufferB) 45 00000000 CoefficientC86(7:0)ofDACminiDSP(DACBufferB) 46 00000000 CoefficientC87(15:8)ofDACminiDSP(DACBufferB) 47 00000000 CoefficientC87(7:0)ofDACminiDSP(DACBufferB) 48 00000000 CoefficientC88(15:8)ofDACminiDSP(DACBufferB) 49 00000000 CoefficientC88(7:0)ofDACminiDSP(DACBufferB) 50 00000000 CoefficientC89(15:8)ofDACminiDSP(DACBufferB) 51 00000000 CoefficientC89(7:0)ofDACminiDSP(DACBufferB) 52 00000000 CoefficientC90(15:8)ofDACminiDSP(DACBufferB) 53 00000000 CoefficientC90(7:0)ofDACminiDSP(DACBufferB) 54 00000000 CoefficientC91(15:8)ofDACminiDSP(DACBufferB) 55 00000000 CoefficientC91(7:0)ofDACminiDSP(DACBufferB) 56 00000000 CoefficientC92(15:8)ofDACminiDSP(DACBufferB) 57 00000000 CoefficientC92(7:0)ofDACminiDSP(DACBufferB) 58 00000000 CoefficientC93(15:8)ofDACminiDSP(DACBufferB) 59 00000000 CoefficientC93(7:0)ofDACminiDSP(DACBufferB) 60 00000000 CoefficientC94(15:8)ofDACminiDSP(DACBufferB) 61 00000000 CoefficientC94(7:0)ofDACminiDSP(DACBufferB) 62 00000000 CoefficientC95(15:8)ofDACminiDSP(DACBufferB) 63 00000000 CoefficientC95(7:0)ofDACminiDSP(DACBufferB) 64 00000000 CoefficientC96(15:8)ofDACminiDSP(DACBufferB) 65 00000000 CoefficientC96(7:0)ofDACminiDSP(DACBufferB) 66 00000000 CoefficientC97(15:8)ofDACminiDSP(DACBufferB) 67 00000000 CoefficientC97(7:0)ofDACminiDSP(DACBufferB) 68 00000000 CoefficientC98(15:8)ofDACminiDSP(DACBufferB) 69 00000000 CoefficientC98(7:0)ofDACminiDSP(DACBufferB) 70 00000000 CoefficientC99(15:8)ofDACminiDSP(DACBufferB) 71 00000000 CoefficientC99(7:0)ofDACminiDSP(DACBufferB) 72 00000000 CoefficientC100(15:8)ofDACminiDSP(DACBufferB) 73 00000000 CoefficientC100(7:0)ofDACminiDSP(DACBufferB) 74 00000000 CoefficientC101(15:8)ofDACminiDSP(DACBufferB) 75 00000000 CoefficientC101(7:0)ofDACminiDSP(DACBufferB) 76 00000000 CoefficientC102(15:8)ofDACminiDSP(DACBufferB) 77 00000000 CoefficientC102(7:0)ofDACminiDSP(DACBufferB) 78 00000000 CoefficientC103(15:8)ofDACminiDSP(DACBufferB) 96 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-11.Page-13Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 79 00000000 CoefficientC103(7:0)ofDACminiDSP(DACBufferB) 80 00000000 CoefficientC104(15:8)ofDACminiDSP(DACBufferB) 81 00000000 CoefficientC104(7:0)ofDACminiDSP(DACBufferB) 82 00000000 CoefficientC105(15:8)ofDACminiDSP(DACBufferB) 83 00000000 CoefficientC105(7:0)ofDACminiDSP(DACBufferB) 84 00000000 CoefficientC106(15:8)ofDACminiDSP(DACBufferB) 85 00000000 CoefficientC106(7:0)ofDACminiDSP(DACBufferB) 86 00000000 CoefficientC107(15:8)ofDACminiDSP(DACBufferB) 87 00000000 CoefficientC107(7:0)ofDACminiDSP(DACBufferB) 88 00000000 CoefficientC108(15:8)ofDACminiDSP(DACBufferB) 89 00000000 CoefficientC108(7:0)ofDACminiDSP(DACBufferB) 90 00000000 CoefficientC109(15:8)ofDACminiDSP(DACBufferB) 91 00000000 CoefficientC109(7:0)ofDACminiDSP(DACBufferB) 92 00000000 CoefficientC110(15:8)ofDACminiDSP(DACBufferB) 93 00000000 CoefficientC110(7:0)ofDACminiDSP(DACBufferB) 94 00000000 CoefficientC111(15:8)ofDACminiDSP(DACBufferB) 95 00000000 CoefficientC111(7:0)ofDACminiDSP(DACBufferB) 96 00000000 CoefficientC112(15:8)ofDACminiDSP(DACBufferB) 97 00000000 CoefficientC112(7:0)ofDACminiDSP(DACBufferB) 98 00000000 CoefficientC113(15:8)ofDACminiDSP(DACBufferB) 99 00000000 CoefficientC113(7:0)ofDACminiDSP(DACBufferB) 100 00000000 CoefficientC114(15:8)ofDACminiDSP(DACBufferB) 101 00000000 CoefficientC114(7:0)ofDACminiDSP(DACBufferB) 102 00000000 CoefficientC115(15:8)ofDACminiDSP(DACBufferB) 103 00000000 CoefficientC116(7:0)ofDACminiDSP(DACBufferB) 104 00000000 CoefficientC117(15:8)ofDACminiDSP(DACBufferB) 105 00000000 CoefficientC117(7:0)ofDACminiDSP(DACBufferB) 106 00000000 CoefficientC118(15:8)ofDACminiDSP(DACBufferB) 107 00000000 CoefficientC118(7:0)ofDACminiDSP(DACBufferB) 108 00000000 CoefficientC119(15:8)ofDACminiDSP(DACBufferB) 109 00000000 CoefficientC119(7:0)ofDACminiDSP(DACBufferB) 110 00000000 CoefficientC120(15:8)ofDACminiDSP(DACBufferB) 111 00000000 CoefficientC120(7:0)ofDACminiDSP(DACBufferB) 112 00000000 CoefficientC121(15:8)ofDACminiDSP(DACBufferB) 113 00000000 CoefficientC121(7:0)ofDACminiDSP(DACBufferB) 114 00000000 CoefficientC122(15:8)ofDACminiDSP(DACBufferB) 115 00000000 CoefficientC122(7:0)ofDACminiDSP(DACBufferB) 116 00000000 CoefficientC123(15:8)ofDACminiDSP(DACBufferB) 117 00000000 CoefficientC123(7:0)ofDACminiDSP(DACBufferB) 118 00000000 CoefficientC123(15:8)ofDACminiDSP(DACBufferB) 119 00000000 CoefficientC123(7:0)ofDACminiDSP(DACBufferB) 120 00000000 CoefficientC124(15:8)ofDACminiDSP(DACBufferB) 121 00000000 CoefficientC124(7:0)ofDACminiDSP(DACBufferB) 122 00000000 CoefficientC125(15:8)ofDACminiDSP(DACBufferB) 123 00000000 CoefficientC125(7:0)ofDACminiDSP(DACBufferB) 124 00000000 CoefficientC126(15:8)ofDACminiDSP(DACBufferB) 125 00000000 CoefficientC126(7:0)ofDACminiDSP(DACBufferB) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 97 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-11.Page-13Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 126 00000000 CoefficientC127(15:8)ofDACminiDSP(DACBufferB) 127 00000000 CoefficientC127(7:0)ofDACminiDSP(DACBufferB) 6.11 Control Registers, Page 14: DAC Programmable Coefficients RAM Buffer B (129:191) Table6-12.Page-14Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 XXXXXXXX Reserved.Donotwritetothisregister. 2 00000000 CoefficientC129(15:8)ofDACminiDSP(DACBufferB) 3 00000000 CoefficientC129(7:0)ofDACminiDSP(DACBufferB) 4 00000000 CoefficientC130(15:8)ofDACminiDSP(DACBufferB) 5 00000000 CoefficientC130(7:0)ofDACminiDSP(DACBufferB) 6 00000000 CoefficientC131(15:8)ofDACminiDSP(DACBufferB) 7 00000000 CoefficientC131(7:0)ofDACminiDSP(DACBufferB) 8 00000000 CoefficientC132(15:8)ofDACminiDSP(DACBufferB) 9 00000000 CoefficientC132(7:0)ofDACminiDSP(DACBufferB) 10 00000000 CoefficientC133(15:8)ofDACminiDSP(DACBufferB) 11 00000000 CoefficientC133(7:0)ofDACminiDSP(DACBufferB) 12 00000000 CoefficientC134(15:8)ofDACminiDSP(DACBufferB) 13 00000000 CoefficientC134(7:0)ofDACminiDSP(DACBufferB) 14 00000000 CoefficientC135(15:8)ofDACminiDSP(DACBufferB) 15 00000000 CoefficientC135(7:0)ofDACminiDSP(DACBufferB) 16 00000000 CoefficientC136(15:8)ofDACminiDSP(DACBufferB) 17 00000000 CoefficientC136(7:0)ofDACminiDSP(DACBufferB) 18 00000000 CoefficientC137(15:8)ofDACminiDSP(DACBufferB) 19 00000000 CoefficientC137(7:0)ofDACminiDSP(DACBufferB) 20 00000000 CoefficientC138(15:8)ofDACminiDSP(DACBufferB) 21 00000000 CoefficientC138(7:0)ofDACminiDSP(DACBufferB) 22 00000000 CoefficientC139(15:8)ofDACminiDSP(DACBufferB) 23 00000000 CoefficientC139(7:0)ofDACminiDSP(DACBufferB) 24 00000000 CoefficientC140(15:8)ofDACminiDSP(DACBufferB) 25 00000000 CoefficientC140(7:0)ofDACminiDSP(DACBufferB) 26 00000000 CoefficientC141(15:8)ofDACminiDSP(DACBufferB) 27 00000000 CoefficientC141(7:0)ofDACminiDSP(DACBufferB) 28 00000000 CoefficientC142(15:8)ofDACminiDSP(DACBufferB) 29 00000000 CoefficientC142(7:0)ofDACminiDSP(DACBufferB) 30 00000000 CoefficientC143(15:8)ofDACminiDSP(DACBufferB) 31 00000000 CoefficientC143(7:0)ofDACminiDSP(DACBufferB) 32 00000000 CoefficientC144(15:8)ofDACminiDSP(DACBufferB) 33 00000000 CoefficientC144(7:0)ofDACminiDSP(DACBufferB) 34 00000000 CoefficientC145(15:8)ofDACminiDSP(DACBufferB) 35 00000000 CoefficientC145(7:0)ofDACminiDSP(DACBufferB) 36 00000000 CoefficientC146(15:8)ofDACminiDSP(DACBufferB) 37 00000000 CoefficientC146(7:0)ofDACminiDSP(DACBufferB) 98 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-12.Page-14Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 38 00000000 CoefficientC147(15:8)ofDACminiDSP(DACBufferB) 39 00000000 CoefficientC147(7:0)ofDACminiDSP(DACBufferB) 40 00000000 CoefficientC148(15:8)ofDACminiDSP(DACBufferB) 41 00000000 CoefficientC148(7:0)ofDACminiDSP(DACBufferB) 42 00000000 CoefficientC149(15:8)ofDACminiDSP(DACBufferB) 43 00000000 CoefficientC149(7:0)ofDACminiDSP(DACBufferB) 44 00000000 CoefficientC150(15:8)ofDACminiDSP(DACBufferB) 45 00000000 CoefficientC150(7:0)ofDACminiDSP(DACBufferB) 46 00000000 CoefficientC151(15:8)ofDACminiDSP(DACBufferB) 47 00000000 CoefficientC151(7:0)ofDACminiDSP(DACBufferB) 48 00000000 CoefficientC152(15:8)ofDACminiDSP(DACBufferB) 49 00000000 CoefficientC152(7:0)ofDACminiDSP(DACBufferB) 50 00000000 CoefficientC153(15:8)ofDACminiDSP(DACBufferB) 51 00000000 CoefficientC153(7:0)ofDACminiDSP(DACBufferB) 52 00000000 CoefficientC154(15:8)ofDACminiDSP(DACBufferB) 53 00000000 CoefficientC154(7:0)ofDACminiDSP(DACBufferB) 54 00000000 CoefficientC155(15:8)ofDACminiDSP(DACBufferB) 55 00000000 CoefficientC155(7:0)ofDACminiDSP(DACBufferB) 56 00000000 CoefficientC156(15:8)ofDACminiDSP(DACBufferB) 57 00000000 CoefficientC156(7:0)ofDACminiDSP(DACBufferB) 58 00000000 CoefficientC157(15:8)ofDACminiDSP(DACBufferB) 59 00000000 CoefficientC157(7:0)ofDACminiDSP(DACBufferB) 60 00000000 CoefficientC158(15:8)ofDACminiDSP(DACBufferB) 61 00000000 CoefficientC158(7:0)ofDACminiDSP(DACBufferB) 62 00000000 CoefficientC159(15:8)ofDACminiDSP(DACBufferB) 63 00000000 CoefficientC159(7:0)ofDACminiDSP(DACBufferB) 64 00000000 CoefficientC160(15:8)ofDACminiDSP(DACBufferB) 65 00000000 CoefficientC160(7:0)ofDACminiDSP(DACBufferB) 66 00000000 CoefficientC161(15:8)ofDACminiDSP(DACBufferB) 67 00000000 CoefficientC161(7:0)ofDACminiDSP(DACBufferB) 68 00000000 CoefficientC162(15:8)ofDACminiDSP(DACBufferB) 69 00000000 CoefficientC162(7:0)ofDACminiDSP(DACBufferB) 70 00000000 CoefficientC163(15:8)ofDACminiDSP(DACBufferB) 71 00000000 CoefficientC163(7:0)ofDACminiDSP(DACBufferB) 72 00000000 CoefficientC164(15:8)ofDACminiDSP(DACBufferB) 73 00000000 CoefficientC164(7:0)ofDACminiDSP(DACBufferB) 74 00000000 CoefficientC165(15:8)ofDACminiDSP(DACBufferB) 75 00000000 CoefficientC165(7:0)ofDACminiDSP(DACBufferB) 76 00000000 CoefficientC166(15:8)ofDACminiDSP(DACBufferB) 77 00000000 CoefficientC166(7:0)ofDACminiDSP(DACBufferB) 78 00000000 CoefficientC167(15:8)ofDACminiDSP(DACBufferB) 79 00000000 CoefficientC167(7:0)ofDACminiDSP(DACBufferB) 80 00000000 CoefficientC168(15:8)ofDACminiDSP(DACBufferB) 81 00000000 CoefficientC168(7:0)ofDACminiDSP(DACBufferB) 82 00000000 CoefficientC169(15:8)ofDACminiDSP(DACBufferB) 83 00000000 CoefficientC169(7:0)ofDACminiDSP(DACBufferB) 84 00000000 CoefficientC170(15:8)ofDACminiDSP(DACBufferB) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 99 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-12.Page-14Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 85 00000000 CoefficientC170(7:0)ofDACminiDSP(DACBufferB) 86 00000000 CoefficientC171(15:8)ofDACminiDSP(DACBufferB) 87 00000000 CoefficientC171(7:0)ofDACminiDSP(DACBufferB) 88 00000000 CoefficientC172(15:8)ofDACminiDSP(DACBufferB) 89 00000000 CoefficientC172(7:0)ofDACminiDSP(DACBufferB) 90 00000000 CoefficientC173(15:8)ofDACminiDSP(DACBufferB) 91 00000000 CoefficientC173(7:0)ofDACminiDSP(DACBufferB) 92 00000000 CoefficientC174(15:8)ofDACminiDSP(DACBufferB) 93 00000000 CoefficientC174(7:0)ofDACminiDSP(DACBufferB) 94 00000000 CoefficientC175(15:8)ofDACminiDSP(DACBufferB) 95 00000000 CoefficientC175(7:0)ofDACminiDSP(DACBufferB) 96 00000000 CoefficientC176(15:8)ofDACminiDSP(DACBufferB) 97 00000000 CoefficientC176(7:0)ofDACminiDSP(DACBufferB) 98 00000000 CoefficientC177(15:8)ofDACminiDSP(DACBufferB) 99 00000000 CoefficientC177(7:0)ofDACminiDSP(DACBufferB) 100 00000000 CoefficientC178(15:8)ofDACminiDSP(DACBufferB) 101 00000000 CoefficientC178(7:0)ofDACminiDSP(DACBufferB) 102 00000000 CoefficientC179(15:8)ofDACminiDSP(DACBufferB) 103 00000000 CoefficientC179(7:0)ofDACminiDSP(DACBufferB) 104 00000000 CoefficientC180(15:8)ofDACminiDSP(DACBufferB) 105 00000000 CoefficientC180(7:0)ofDACminiDSP(DACBufferB) 106 00000000 CoefficientC181(15:8)ofDACminiDSP(DACBufferB) 107 00000000 CoefficientC181(7:0)ofDACminiDSP(DACBufferB) 108 00000000 CoefficientC182(15:8)ofDACminiDSP(DACBufferB) 109 00000000 CoefficientC182(7:0)ofDACminiDSP(DACBufferB) 110 00000000 CoefficientC183(15:8)ofDACminiDSP(DACBufferB) 111 00000000 CoefficientC183(7:0)ofDACminiDSP(DACBufferB) 112 00000000 CoefficientC184(15:8)ofDACminiDSP(DACBufferB) 113 00000000 CoefficientC184(7:0)ofDACminiDSP(DACBufferB) 114 00000000 CoefficientC185(15:8)ofDACminiDSP(DACBufferB) 115 00000000 CoefficientC185(7:0)ofDACminiDSP(DACBufferB) 116 00000000 CoefficientC186(15:8)ofDACminiDSP(DACBufferB) 117 00000000 CoefficientC186(7:0)ofDACminiDSP(DACBufferB) 118 00000000 CoefficientC187(15:8)ofDACminiDSP(DACBufferB) 119 00000000 CoefficientC187(7:0)ofDACminiDSP(DACBufferB) 120 00000000 CoefficientC188(15:8)ofDACminiDSP(DACBufferB) 121 00000000 CoefficientC188(7:0)ofDACminiDSP(DACBufferB) 122 00000000 CoefficientC189(15:8)ofDACminiDSP(DACBufferB) 123 00000000 CoefficientC189(7:0)ofDACminiDSP(DACBufferB) 124 00000000 CoefficientC190(15:8)ofDACminiDSP(DACBufferB) 125 00000000 CoefficientC190(7:0)ofDACminiDSP(DACBufferB) 126 00000000 CoefficientC191(15:8)ofDACminiDSP(DACBufferB) 127 00000000 CoefficientC191(7:0)ofDACminiDSP(DACBufferB) 100 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 6.12 Control Registers, Page 15: DAC Programmable Coefficients RAM Buffer B (193:255) Table6-13.Page-15Registers REGISTER RESETVALUE REGISTERNAME NUMBER 1 XXXXXXXX Reserved.Donotwritetothisregister. 2 00000000 CoefficientC193(15:8)ofDACminiDSP(DACBufferB) 3 00000000 CoefficientC193(7:0)ofDACminiDSP(DACBufferB) 4 00000000 CoefficientC194(15:8)ofDACminiDSP(DACBufferB) 5 00000000 CoefficientC194(7:0)ofDACminiDSP(DACBufferB) 6 00000000 CoefficientC195(15:8)ofDACminiDSP(DACBufferB) 7 00000000 CoefficientC195(7:0)ofDACminiDSP(DACBufferB) 8 00000000 CoefficientC196(15:8)ofDACminiDSP(DACBufferB) 9 00000000 CoefficientC196(7:0)ofDACminiDSP(DACBufferB) 10 00000000 CoefficientC197(15:8)ofDACminiDSP(DACBufferB) 11 00000000 CoefficientC197(7:0)ofDACminiDSP(DACBufferB) 12 00000000 CoefficientC198(15:8)ofDACminiDSP(DACBufferB) 13 00000000 CoefficientC198(7:0)ofDACminiDSP(DACBufferB) 14 00000000 CoefficientC199(15:8)ofDACminiDSP(DACBufferB) 15 00000000 CoefficientC199(7:0)ofDACminiDSP(DACBufferB) 16 00000000 CoefficientC200(15:8)ofDACminiDSP(DACBufferB) 17 00000000 CoefficientC200(7:0)ofDACminiDSP(DACBufferB) 18 00000000 CoefficientC201(15:8)ofDACminiDSP(DACBufferB) 19 00000000 CoefficientC201(7:0)ofDACminiDSP(DACBufferB) 20 00000000 CoefficientC202(15:8)ofDACminiDSP(DACBufferB) 21 00000000 CoefficientC202(7:0)ofDACminiDSP(DACBufferB) 22 00000000 CoefficientC203(15:8)ofDACminiDSP(DACBufferB) 23 00000000 CoefficientC203(7:0)ofDACminiDSP(DACBufferB) 24 00000000 CoefficientC204(15:8)ofDACminiDSP(DACBufferB) 25 00000000 CoefficientC204(7:0)ofDACminiDSP(DACBufferB) 26 00000000 CoefficientC205(15:8)ofDACminiDSP(DACBufferB) 27 00000000 CoefficientC205(7:0)ofDACminiDSP(DACBufferB) 28 00000000 CoefficientC206(15:8)ofDACminiDSP(DACBufferB) 29 00000000 CoefficientC206(7:0)ofDACminiDSP(DACBufferB) 30 00000000 CoefficientC207(15:8)ofDACminiDSP(DACBufferB) 31 00000000 CoefficientC207(7:0)ofDACminiDSP(DACBufferB) 32 00000000 CoefficientC208(15:8)ofDACminiDSP(DACBufferB) 33 00000000 CoefficientC208(7:0)ofDACminiDSP(DACBufferB) 34 00000000 CoefficientC209(15:8)ofDACminiDSP(DACBufferB) 35 00000000 CoefficientC209(7:0)ofDACminiDSP(DACBufferB) 36 00000000 CoefficientC210(15:8)ofDACminiDSP(DACBufferB) 37 00000000 CoefficientC210(7:0)ofDACminiDSP(DACBufferB) 38 00000000 CoefficientC211(15:8)ofDACminiDSP(DACBufferB) 39 00000000 CoefficientC211(7:0)ofDACminiDSP(DACBufferB) 40 00000000 CoefficientC212(15:8)ofDACminiDSP(DACBufferB) 41 00000000 CoefficientC212(7:0)ofDACminiDSP(DACBufferB) 42 00000000 CoefficientC213(15:8)ofDACminiDSP(DACBufferB) 43 00000000 CoefficientC213(7:0)ofDACminiDSP(DACBufferB) Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 101 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Table6-13.Page-15Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 44 00000000 CoefficientC214(15:8)ofDACminiDSP(DACBufferB) 45 00000000 CoefficientC214(7:0)ofDACminiDSP(DACBufferB) 46 00000000 CoefficientC215(15:8)ofDACminiDSP(DACBufferB) 47 00000000 CoefficientC215(7:0)ofDACminiDSP(DACBufferB) 48 00000000 CoefficientC216(15:8)ofDACminiDSP(DACBufferB) 49 00000000 CoefficientC216(7:0)ofDACminiDSP(DACBufferB) 50 00000000 CoefficientC217(15:8)ofDACminiDSP(DACBufferB) 51 00000000 CoefficientC217(7:0)ofDACminiDSP(DACBufferB) 52 00000000 CoefficientC218(15:8)ofDACminiDSP(DACBufferB) 53 00000000 CoefficientC218(7:0)ofDACminiDSP(DACBufferB) 54 00000000 CoefficientC219(15:8)ofDACminiDSP(DACBufferB) 55 00000000 CoefficientC219(7:0)ofDACminiDSP(DACBufferB) 56 00000000 CoefficientC220(15:8)ofDACminiDSP(DACBufferB) 57 00000000 CoefficientC220(7:0)ofDACminiDSP(DACBufferB) 58 00000000 CoefficientC221(15:8)ofDACminiDSP(DACBufferB) 59 00000000 CoefficientC221(7:0)ofDACminiDSP(DACBufferB) 60 00000000 CoefficientC222(15:8)ofDACminiDSP(DACBufferB) 61 00000000 CoefficientC222(7:0)ofDACminiDSP(DACBufferB) 62 00000000 CoefficientC223(15:8)ofDACminiDSP(DACBufferB) 63 00000000 CoefficientC223(7:0)ofDACminiDSP(DACBufferB) 64 00000000 CoefficientC224(15:8)ofDACminiDSP(DACBufferB) 65 00000000 CoefficientC224(7:0)ofDACminiDSP(DACBufferB) 66 00000000 CoefficientC225(15:8)ofDACminiDSP(DACBufferB) 67 00000000 CoefficientC225(7:0)ofDACminiDSP(DACBufferB) 68 00000000 CoefficientC226(15:8)ofDACminiDSP(DACBufferB) 69 00000000 CoefficientC226(7:0)ofDACminiDSP(DACBufferB) 70 00000000 CoefficientC227(15:8)ofDACminiDSP(DACBufferB) 71 00000000 CoefficientC227(7:0)ofDACminiDSP(DACBufferB) 72 00000000 CoefficientC228(15:8)ofDACminiDSP(DACBufferB) 73 00000000 CoefficientC228(7:0)ofDACminiDSP(DACBufferB) 74 00000000 CoefficientC229(15:8)ofDACminiDSP(DACBufferB) 75 00000000 CoefficientC229(7:0)ofDACminiDSP(DACBufferB) 76 00000000 CoefficientC230(15:8)ofDACminiDSP(DACBufferB) 77 00000000 CoefficientC230(7:0)ofDACminiDSP(DACBufferB) 78 00000000 CoefficientC231(15:8)ofDACminiDSP(DACBufferB) 79 00000000 CoefficientC231(7:0)ofDACminiDSP(DACBufferB) 80 00000000 CoefficientC232(15:8)ofDACminiDSP(DACBufferB) 81 00000000 CoefficientC232(7:0)ofDACminiDSP(DACBufferB) 82 00000000 CoefficientC233(15:8)ofDACminiDSP(DACBufferB) 83 00000000 CoefficientC233(7:0)ofDACminiDSP(DACBufferB) 84 00000000 CoefficientC234(15:8)ofDACminiDSP(DACBufferB) 85 00000000 CoefficientC234(7:0)ofDACminiDSP(DACBufferB) 86 00000000 CoefficientC235(15:8)ofDACminiDSP(DACBufferB) 87 00000000 CoefficientC235(7:0)ofDACminiDSP(DACBufferB) 88 00000000 CoefficientC236(15:8)ofDACminiDSP(DACBufferB) 89 00000000 CoefficientC236(7:0)ofDACminiDSP(DACBufferB) 90 00000000 CoefficientC237(15:8)ofDACminiDSP(DACBufferB) 102 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 Table6-13.Page-15Registers(continued) REGISTER RESETVALUE REGISTERNAME NUMBER 91 00000000 CoefficientC237(7:0)ofDACminiDSP(DACBufferB) 92 00000000 CoefficientC238(15:8)ofDACminiDSP(DACBufferB) 93 00000000 CoefficientC238(7:0)ofDACminiDSP(DACBufferB) 94 00000000 CoefficientC239(15:8)ofDACminiDSP(DACBufferB) 95 00000000 CoefficientC239(7:0)ofDACminiDSP(DACBufferB) 96 00000000 CoefficientC240(15:8)ofDACminiDSP(DACBufferB) 97 00000000 CoefficientC240(7:0)ofDACminiDSP(DACBufferB) 98 00000000 CoefficientC241(15:8)ofDACminiDSP(DACBufferB) 99 00000000 CoefficientC241(7:0)ofDACminiDSP(DACBufferB) 100 00000000 CoefficientC242(15:8)ofDACminiDSP(DACBufferB) 101 00000000 CoefficientC242(7:0)ofDACminiDSP(DACBufferB) 102 00000000 CoefficientC243(15:8)ofDACminiDSP(DACBufferB) 103 00000000 CoefficientC243(7:0)ofDACminiDSP(DACBufferB) 104 00000000 CoefficientC244(15:8)ofDACminiDSP(DACBufferB) 105 00000000 CoefficientC244(7:0)ofDACminiDSP(DACBufferB) 106 00000000 CoefficientC245(15:8)ofDACminiDSP(DACBufferB) 107 00000000 CoefficientC245(7:0)ofDACminiDSP(DACBufferB) 108 00000000 CoefficientC246(15:8)ofDACminiDSP(DACBufferB) 109 00000000 CoefficientC246(7:0)ofDACminiDSP(DACBufferB) 110 00000000 CoefficientC247(15:8)ofDACminiDSP(DACBufferB) 111 00000000 CoefficientC247(7:0)ofDACminiDSP(DACBufferB) 112 00000000 CoefficientC248(15:8)ofDACminiDSP(DACBufferB) 113 00000000 CoefficientC248(7:0)ofDACminiDSP(DACBufferB) 114 00000000 CoefficientC249(15:8)ofDACminiDSP(DACBufferB) 115 00000000 CoefficientC249(7:0)ofDACminiDSP(DACBufferB) 116 00000000 CoefficientC250(15:8)ofDACminiDSP(DACBufferB) 117 00000000 CoefficientC250(7:0)ofDACminiDSP(DACBufferB) 118 00000000 CoefficientC251(15:8)ofDACminiDSP(DACBufferB) 119 00000000 CoefficientC251(7:0)ofDACminiDSP(DACBufferB) 120 00000000 CoefficientC252(15:8)ofDACminiDSP(DACBufferB) 121 00000000 CoefficientC252(7:0)ofDACminiDSP(DACBufferB) 122 00000000 CoefficientC253(15:8)ofDACminiDSP(DACBufferB) 123 00000000 CoefficientC253(7:0)ofDACminiDSP(DACBufferB) 124 00000000 CoefficientC254(15:8)ofDACminiDSP(DACBufferB) 125 00000000 CoefficientC254(7:0)ofDACminiDSP(DACBufferB) 126 00000000 CoefficientC255(15:8)ofDACminiDSP(DACBufferB) 127 00000000 CoefficientC255(7:0)ofDACminiDSP(DACBufferB) 6.13 Control Registers, Page 64: DAC DSP Engine Instruction RAM (0:31) Page64/Register0:PageControlRegister READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 00000000 00000000:Page0selected 00000001:Page1selected ... 11111110:Page254selected 11111111:Page255selected Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 103 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Page64/Register1:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlythedefaultvaluetothisregister Page64/Register2:Inst_0(23:16) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXX InstructionInst_0(23:16)ofDACminiDSP Page64/Register3:Inst_0(15:8) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX InstructionInst_0(15:8)ofDACminiDSP Page64/Register4:Inst_0(7:0) READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX InstructionInst_0(7:0)ofDACminiDSP 104 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012 6.13.1 Page 64 / Register 5 Through Page 64 / Register 97 The remaining unreserved registers on page 32 are arranged in groups of three, with each group containing the bits of one instruction. The arrangement is the same as that of registers 2–4 for Instruction 0.Registers5–7,8–10,11–13,...,95–97containinstructions1,2,3,...,31,respectively. Page64/Register98ThroughPage64/Register127:Reserved READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W XXXXXXXX Reserved.Writeonlythedefaultvaluetothisregister 6.14 Control Registers, Pages 65–95: DAC DSP Engine Instruction RAM (32:63) Through (992:1023) The structuring of the registers within pages 65–95 is identical to that of page 64. Only the instruction numbersdiffer.Therangeofinstructionswithineachpageislistedinthefollowingtable. Page Instructions 65 32to63 66 64to95 67 96to127 68 128to159 69 160to191 70 192to223 71 224to255 72 256to287 73 288to319 74 320to351 75 352to383 76 384to415 77 416to447 78 448to479 79 480to511 80 512to543 81 544to575 82 576to607 83 608to639 84 640to671 85 672to703 86 704to735 87 736to767 88 768to799 89 800to831 90 832to863 91 864to895 92 896to927 93 928to959 94 960to991 95 992to1023 Copyright©2009–2012,TexasInstrumentsIncorporated REGISTERMAP 105 SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

TLV320DAC3120 SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromOriginal(November,2009)toRevisionA Page • AddedextrabulletpointtoFeatures. .......................................................................................... 1 • ChangedRegister36toregister35insection5.5.2. ...................................................................... 21 • AddedextrarowtotheendofTable5-6. .................................................................................... 23 • Addedsubsection5.6.1.2.9andimage. ...................................................................................... 25 • Addedsection5.6.7fromSLAS644CafterInterruptssection. .......................................................... 36 • AddedD6–D0totheRegisterValuecolumnheadingandchangedAnalogAttenuationtoAnalogGain. ..... 40 • DeletedAnalogVolumeControlforHeadphoneandSpeakerOutputs(forD7=0)tableandaddedtable notetoD7=1table. .............................................................................................................. 40 • Changedpage0topage1insection5.6.9.1. ............................................................................... 41 • AddedTimersectionandimageafterPLLsection. ....................................................................... 47 • Changedlastlineto"10111-11000:Reserved.Donotuse.""11001:DACSignalProcessingBlock PRB_P25""11010-11111:Reserved.Donotuse." ......................................................................... 67 • AddedBeepGeneratorbitregistersfromDAC3100(Page0/Register71,and73-79)............................. 70 • Addedreservedtables. .......................................................................................................... 71 • ChangedD0=1toReservedinPage1/Register33. ...................................................................... 73 • Removedextraneouscross-referencesfordeletedtable................................................................. 74 • AddedfootnotetoPage1/Register40:HPOUTDriver................................................................... 74 • Changedregisters66-127toReservedinTable6-6. ...................................................................... 81 • Changedregisters8-13toReservedinTable6-7. ......................................................................... 82 • Changedregisters66-127toReservedinTable6-10. ..................................................................... 94 • Changedregisters8-13toReservedinTable6-11. ........................................................................ 95 106 REGISTERMAP Copyright©2009–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TLV320DAC3120

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV320DAC3120IRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC3120 & no Sb/Br) TLV320DAC3120IRHBT ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC3120 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Apr-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV320DAC3120IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TLV320DAC3120IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Apr-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV320DAC3120IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320DAC3120IRHBT VQFN RHB 32 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 5.1 B 4.9 PIN 1 INDEX AREA 5.1 (0.1) 4.9 SIDE WALL DETAIL OPTIONAL ME20.000TAL THICKNESS C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 3.45 0.1 (0.2) TYP 9 16 EXPOSED THERMAL PAD 28X 0.5 8 17 SEE SIDE WALL DETAIL 2X 33 SYMM 3.5 0.3 32X 0.2 24 0.1 C A B 1 0.05 C 32 25 PIN 1 ID SYMM (OPTIONAL) 0.5 32X 0.3 4223442/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.45) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (1.475) 28X (0.5) 33 SYMM (4.8) ( 0.2) TYP VIA 8 17 (R0.05) TYP 9 16 (1.475) (4.8) LAND PATTERN EXAMPLE SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (R0.05) TYP (0.845) 32 25 32X (0.6) 1 24 32X (0.25) 28X (0.5) (0.845) SYMM 33 (4.8) 8 17 METAL TYP 9 16 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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