TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Class-D Speaker Amplifier CheckforSamples:TLV320AIC3263 FEATURES • ThreeIndependentDigitalAudioSerial 1 InterfaceswithSeparateI/OPowerVoltages • StereoAudioDACwith101dBSNR 2 – TDMandmonoPCMsupportonallAudio • 2.7mWStereo48kHzDACPlayback SerialInterfaces • StereoAudioADCwith93dBSNR – 8-channelInputandOutputonAudioSerial • 6.1mWStereo48kHzADCRecord Interface1 • 8-192kHzPlaybackandRecord • ProgrammablePLL,plusLow-Frequency • 30mWDirectPathTMHeadphoneDriver Clocking EliminatesLargeOutputDC-Blocking • Programmable12-BitSARADC Capacitors • SPIandI2CControlInterfaces • 128mWDifferentialReceiverOutputDriver • 4.81mmx4.81mmx0.625mm81-BallWCSP • Class-DSpeakerDriver (DSBGA)Package – 1.7W(8Ω ,5.5V,10%THDN) AIC3262 – 1.4W(8Ω ,5.5V,1%THDN) APPLICATIONS • StereoLineOutputs • MobileHandsets • PowerTune™-AdjustsPowerversusSNR • Tablets,eBooks • ExtensiveSignalProcessingOptions • PortableNavigationDevices(PND) • EightSingle-Endedor4Fully-Differential • PortableMediaPlayer(PMP) AnalogInputs • PortableGamingSystems • AnalogMicrophoneInputs,andUpto4 • PortableComputing SimultaneousDigitalMicrophoneChannels • ActiveNoiseCancellation(ANC) • LowPowerAnalogBypassMode • SpeakerProtection • Fully-programmableEnhancedminiDSPwith PurePathTMStudioSupport • AdvancedDSPalgorithms – ExtensiveAlgorithmSupportforVoiceand AudioApplications 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerTuneisatrademarkofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com DESCRIPTION The TLV320AIC3263 (also referred to as the AIC3263) is a flexible, highly-integrated, low-power, low-voltage stereo audio codec. The AIC3263 features four digital microphone inputs, plus programmable outputs, PowerTune capabilities, enhanced fully-programmable miniDSP, predefined and parameterizable signal processingblocks,integratedPLL,andflexibledigitalaudiointerfaces.Extensiveregister-basedcontrolofpower, input and output channel configuration, gains, effects, pin-multiplexing and clocks are included, allowing the devicetobepreciselytargetedtoitsapplication. LOL -6...29dB VREF_SAR Int. -78...0dB (1-dB Steps) VBAT VINB1ALT/AUX1 SAR Ref. IN1L-78...0dB RREECCPM IN1R/AUX2 ADC LOR SETENMSOPR TEMP IN1R-78...0dB (6-6d.B..3 S0tdeBps) -78...0dB -6dB SPKP SPKM -12, -6, 0dB LOL RIGHT_ IN1L/AUX1 –12, –6, 0dB -78...0dB CH_IN LOR IN2L –12, –6, 0dB AGC DRC Vol. Ctrl. -78...0dB (1--6d.B.. 1S4tdeBps) IN3L –12, –6, 0dB IN4L –6 dB ALeDfCt tPL SPAigrDonCca.l SPDigrAonCca.l LDeAftC+– HPL 0=47.5dB Gain Adj. -78...0dB (0.5-dB Steps) –36...0dB MAL LOL miniDSP Dmigin iMDiSxePr Audio ASRC HPVSS_SENSE –36...0dB Volume Interface DVigo lMumixeer MAR LOR 0=47.5dB (0.5-dB Steps) Gain Adj. -78...0dB IN4R –6 dB RAiDghCt tPR SPAigrDonCca.l SPDigrAonCca.l RDiAghCt+– HPR IN3R –12, –6, 0dB IN2R –12, –6, 0dB AGC DRC Vol. Ctrl. -6...14dB (1-dB Steps) IN1R/AUX2 –12, –6, 0dB -12, -6, 0dB -6dB Low Freq Clocking SPI_SREELESCETT CoSnPtrIo /l BI2Clock PLL MDicig. i(txa4l)IntCertrrulpt ATuedrtiioa rIyFSAecuodniod aIFry AudPior iImntaerryface MICDET Detection MICBIAS Mic MICBIAS_EXT Bias CPhuamrgpe Supplies Pin Muxing / Clock Routing VREF_AUDIO Ref VNEGCPFCMCPFCPCPVSSCPVDD_18SVDDSPK_VMICBIAS_VDDRECVDD_33IOVDD1IOVDD2IOVDD3AVDD1_18AVDD2_18AVDD4_18AVDD_18HVDD_18DVDDSVSSRECVSSIOVSSAVSSAVSS1AVSS2AVSS3AVSS4DVSS SCLSDAI2C_ADDR_SCLKGPO1 MCLKGPIO1 GPIO2GPIO5 GPIO6DOUT3DIN3 WCLK3 BCLK3 GPIO3GPIO4DOUT2 DIN2 WCLK2 BCLK2 DOUT1 DIN1 WCLK1 BCLK1 Figure1. SimplifiedBlockDiagram 2 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. DESCRIPTION (CONTINUED) The TLV320AIC3263 features two fully-programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software programmable. Targeted miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP filteringareloadedintothedeviceafterpower-up. Combined with the advanced PowerTune technology, the device can execute operations from 8kHz mono voice playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications. The record path of the TLV320AIC3263 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations which cover single-ended and differential setups, as well as floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise thatmaybeintroducedbymechanicalcoupling,suchasopticalzoominginadigitalcamera.Therecordpathcan also be configured for up to two stereo (such as up to 4) simultaneous digital microphone Pulse Density Modulation(PDM)interfacestypicallyusedat64Fsor128Fs. Theplaybackpathofferssignalprocessingblocksforfilteringandeffects;headphone,line,receiver,andClass-D speaker output; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The playback path contains two high-power DirectPathTM headphone output drivers which eliminate the need for ac coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In addition,playbackaudiocanberoutedtoanintegratedClass-Dspeakerdriveroradifferentialreceiveramplifier. The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade- off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern whilelowestpossiblenoiseisimportant.WithPowerTunetheTLV320AIC3263canaddressbothcases. TherequiredinternalclockoftheTLV320AIC3263canbederivedfrommultiplesources,includingtheMCLKpin, the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal PLL, where the input to the PLL again can be derived from similar pins. Although using the internal fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. To enable even lower clockfrequencies,anintegratedlow-frequencyclockmultipliercanalsobeusedasaninputtothePLL. The TLV320AIC3263 has a 12-bit SAR ADC converter that supports system voltage measurements. These system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or VBATpins),or,alternatively,anon-chiptemperaturesensorthatcanbereadbytheSARADC. The device also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF, LJF, and mono PCM formats. This enables three simultaneous digital playback and record paths to three independent digital audio buses or chips. Additionally, the general purpose interrupt pins can be used to connect to a fourth digital audio bus, allowing the end system to easily switch in this fourth audio bus to one of the three Digital Audio Serial Interfaces. Each of the three Digital Audio Serial Interfaces can be run using separate power voltagestoenableeasyintegrationwithseparatechipswithdifferentI/Ovoltages. Thedeviceisavailableinthe4.81mmx4.81mmx0.625mm81-BallWCSP(DSBGA)Package. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Package and Signal Descriptions Packaging/Ordering Information OPERATING PACKAGE ORDERING TRANSPORTMEDIA, PRODUCT(1) PACKAGE TEMPERATURE DESIGNATOR NUMBER QUANTITY RANGE WCSP-81 TLV320AIC3263IYZFT TapeandReel,250 TLV320AIC3263 YZF –40°Cto85°C (DSBGA) TLV320AIC3263IYZFR TapeandReel,3000 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderonwww.ti.com. Pin Assignments space space WCSPPackage (Top View) J DVDD WCLK2 WCLK3 BCLK3 SDA IOVSS DVDD WCLK1 DIN1 H IOVDD2 DIN2 DIN3 IOVDD3 GPIO5 SCL IOVDD1 DOUT1 BCLK1 G BCLK2 IOVSS DOUT3 GPO1 GPIO6 RESET GPIO2 GPIO1 MCLK F DVSS GPIO4 GPIO3 SSPEIL_ECT IAS2DCCDL_KR_ DVSS A_1V8DD IN2R IN2L E DVSS DOUT2 DVDD AVSS2 AVSS3 AVSS1 AVSS IN3L IN3R D DVSS VBAT LOR HSEPNVSSSE_ IN4R IANU1XR2/ IANU1XL/1 VSRAREF_ VARUEDFIO_ C SPK_V SPKM A_1V8DD4 LOL A_1V8DD2 MICBIAS M_EICXBTIAS A_1V8DD1 IN4L B SVSS SVDD CPFCP CPVSS HPL H_1V8DD RECM RECP MICDET A SPKP AVSS4 C_1P8VDD CPFCM VNEG HPR R_3E3CVDDRECVSSM_VICDBDIAS 9 8 7 6 5 4 3 2 1 Figure2. WCSP-81(DSBGA)(YZF)PackageBallAssignments,TopView 4 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table1.TERMINALFUNCTIONS– 81BallWCSP(YZF)Package WCSP(YZF) POWER BALL NAME I/O/P DESCRIPTION DOMAIN LOCATION A1 MICBIAS_VDD P Analog PowerSupplyforMicbias A2 RECVSS P Analog ReceiverDriverGround A3 RECVDD_33 P Analog 3.3VPowerSupplyforReceiverDriver A4 HPR O Analog RightHeadphoneOutput A5 VNEG I/O Analog ChargePumpNegativeSupply A6 CPFCM I/O Analog ChargePumpFlyingCapacitorMterminal A7 CPVDD_18 P Analog PowerSupplyInputforChargePump A8 AVSS4 P Analog AnalogGroundforClass-D A9 SPKP O Speaker LeftChannelPsideClass-DOutput B1 MICDET I/O Analog HeadsetDetectionPin B2 RECP O Analog ReceiverDriverPsideOutput B3 RECM O Analog ReceiverDriverMsideOutput B4 HVDD_18 P Analog HeadphoneAmpPowerSupply B5 HPL O Analog LeftHeadphoneOutput B6 CPVSS P Analog ChargePumpGround B7 CPFCP I/O Analog ChargePumpFlyingCapacitorPTerminal B8 SVDD P Speaker Class-DOutputStagePowerSupply B9 SVSS P Speaker Class-DOutputStageGround C1 IN4L I Analog AnalogInput4Left C2 AVDD1_18 P Analog 1.8VAnalogPowerSupply C3 MICBIAS_EXT O Analog OutputBiasVoltageforHeadsetMicrophone. C4 MICBIAS O Analog OutputBiasVoltageforMicrophonetobeusedforon-boardMicrophones C5 AVDD2_18 P Analog 1.8VAnalogPowerSupply C6 LOL O Analog LeftLineOutput C7 AVDD4_18 P Analog 1.8VAnalogPowerSupplyforClass-D C8 SPKM O Speaker MsideClass-DOutput C9 SPK_V P Speaker Class-DOutputStagePowerSupply(ConnecttoSVDDthroughaResistor) D1 VREF_AUDIO O Analog AnalogReferenceFilterOutput SARADCVoltageReferenceInputorInternalSARADCVoltageReference D2 VREF_SAR I/O Analog BypassCapacitorPin AnalogInput1Left,Auxiliary1InputtoSARADC D3 IN1L/AUX1 I Analog (SpecialFunction:LeftChannelHighImpedanceInputforCapacitiveSensor Measurement) AnalogInput1Right,Auxiliary2InputtoSARADC D4 IN1R/AUX2 I Analog (SpecialFunction:RightChannelHighImpedanceInputforCapacitive SensorMeasurement) D5 IN4R I Analog AnalogInput4Right D6 HPVSS_SENSE I Analog HeadphoneGroundSenseTerminal D7 LOR O Analog RightLineOutput D8 VBAT I Speaker BatteryMonitorVoltageInput D9 DVSS P Digital DigitalGround E1 IN3R I Analog AnalogInput3Right E2 IN3L I Analog AnalogInput3Left E3 AVSS P Analog AnalogGround E4 AVSS1 P Analog AnalogGround E5 AVSS3 P Analog AnalogGround E6 AVSS2 P Analog AnalogGround E7 DVDD P Digital 1.8VDigitalPowerSupply Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table1.TERMINALFUNCTIONS– 81BallWCSP(YZF)Package(continued) WCSP(YZF) POWER BALL NAME I/O/P DESCRIPTION DOMAIN LOCATION Primary: AudioSerialDataBus2DataOutput E8 DOUT2 O IOVDD2 Secondary: SeeTable8 E9 DVSS P Digital DigitalGround F1 IN2L I Analog AnalogInput2Left F2 IN2R I Analog AnalogInput2Right F3 AVDD_18 P Analog 1.8VAnalogPowerSupply F4 DVSS P Digital DigitalGround Primary:(SPI_SELECT=1) SPISerialClock F5 I2C_ADDR_SCLK I IOVDD1 Secondary:(SPI_SELECT=0) I2CAddressBit(I2C_ADDR) ControlInterfaceSelect F6 SPI_SELECT I IOVDD1 SPI_SELECT=‘1’:SPIInterfaceselected SPI_SELECT=‘0’:I2CInterfaceselected MultiFunctionDigitalIO3 F7 GPIO3 I/O IOVDD2 SeeTable9 MultiFunctionDigitalIO4 F8 GPIO4 I/O IOVDD2 SeeTable9 F9 DVSS P Digital DigitalGround G1 MCLK I IOVDD1 MasterClockInput MultiFunctionDigitalIO1 G2 GPIO1 I/O IOVDD1 SeeTable9 MultiFunctionDigitalIO2 G3 GPIO2 I/O IOVDD1 SeeTable9 G4 RESET I IOVDD1 ActiveLowReset MultiFunctionDigitalIO6 G5 GPIO6 I/O IOVDD1 SeeTable9 MultifunctionDigitalOutput1 Primary:(SPI_SELECT=1) G6 GPO1 O IOVDD1 SerialDataOutput Secondary:(SPI_SELECT=0) SeeTable9 Primary: AudioSerialDataBus3DataOutput G7 DOUT3 O IOVDD3 Secondary: SeeTable9 Commonfor G8 IOVSS P allIO DigitalI/OBufferGround Domains Primary: AudioSerialDataBus2BitClock G9 BCLK2 I/O IOVDD2 Secondary: SeeTable8 6 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table1.TERMINALFUNCTIONS– 81BallWCSP(YZF)Package(continued) WCSP(YZF) POWER BALL NAME I/O/P DESCRIPTION DOMAIN LOCATION Primary: AudioSerialDataBus1BitClock H1 BCLK1 I/O IOVDD1 Secondary: SeeTable8 Primary: AudioSerialDataBus1DataOutput H2 DOUT1 O IOVDD1 Secondary: SeeTable8 H3 IOVDD1 P IOVDD1 DigitalI/OBufferSupply1 I2CInterfaceSerialClock(SPI_SELECT=0) H4 SCL I/O IOVDD1 SPIinterfacemodechip-selectsignal(SPI_SELECT=1) MultifunctionDigitalIO5 H5 GPIO5 I/O IOVDD1 SeeTable8 H6 IOVDD3 P IOVDD3 DigitalI/OBufferSupply3 Primary: AudioSerialDataBus3DataInput H7 DIN3 I IOVDD3 Secondary: SeeTable9 Primary: AudioSerialDataBus2DataInput H8 DIN2 I IOVDD2 Secondary: SeeTable8 H9 IOVDD2 P IOVDD2 DigitalI/OBufferSupply2 Primary: AudioSerialDataBus1DataInput J1 DIN1 I IOVDD1 Secondary: SeeTable8 Primary: AudioSerialDataBus1WordClock J2 WCLK1 I/O IOVDD1 Secondary: SeeTable8 J3 DVDD P Digital 1.8VDigitalPowerSupply Commonfor J4 IOVSS P allIO DigitalI/OBufferGround Domains I2Cinterfacemodeserialdatainput(SPI_SELECT=0) J5 SDA I/O IOVDD1 SPIinterfacemodeserialdatainput(SPI_SELECT=1) Primary: AudioSerialDataBus3BitClock J6 BCLK3 I/O IOVDD3 Secondary: SeeTable9 Primary: AudioSerialDataBus3WordClock J7 WCLK3 I/O IOVDD3 Secondary: SeeTable9 Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table1.TERMINALFUNCTIONS– 81BallWCSP(YZF)Package(continued) WCSP(YZF) POWER BALL NAME I/O/P DESCRIPTION DOMAIN LOCATION Primary: AudioSerialDataBus2WordClock J8 WCLK2 I/O IOVDD2 Seccondary: SeeTable8 J9 DVDD P Digital 1.8VDigitalPowerSupply 8 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) VALUE UNIT AVDD1_18,AVDD2_18,AVDD4_18,AVDD_18toAVSS1,AVSS2,AVSS4,AVSSrespectively(2) –0.3to2.2 V RECVDD_33toRECVSS –0.3to3.9 V DVDDtoDVSS –0.3to2.2 V IOVDDxtoIOVSS –0.3to3.9 V HVDD_18toAVSS –0.3to2.2 V CPVDD_18toCPVSS –0.3to2.2 V SVDDtoSVSS,SPK_VtoSVSS,andMICBIAS_VDDtoAVSS3(3) –0.3to6.0 V DigitalInputvoltagetoground IOVSS–0.3toIOVDDx+ V 0.3 Analoginputvoltagetoground AVSS–0.3toAVDDx_18 V +0.3 VBAT –0.3to6 V Operatingtemperaturerange –40to85 °C Storagetemperaturerange –55to125 °C Junctiontemperature(T Max) 105 °C J Powerdissipation (T Max–TA)/θ W J JA θ Junction-to-ambientthermalresistance 39.1 °C/W JA WCSP-81(DSBGA) θJCtopJunction-to-case(top)thermalresistance 0.1 package(YZF) θ Junction-to-boardthermalresistance 12.0 JB Psi Junction-to-topcharacterizationparameter 0.7 JT Psi Junction-to-boardcharacterizationparameter 11.5 JB (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) It'srecommendedtokeepallAVDDx_18supplieswithin±50mVofeachother. (3) It'srecommendedtokeepSVDDandSPK_Vsupplieswithin±50mVofeachother. Recommended Operating Conditions MIN NOM MAX UNIT AVDD1_18, PowerSupplyVoltageRange ReferencedtoAVSS1,AVSS2,AVSS4,AVSS 1.5(2) 1.8 1.95 V AVDD2_18, respectively(1)Itisrecommendedtoconnecteach AVDD4_18, ofthesesuppliestoasinglesupplyrail. AVDD_18 RECVDD_33 ReferencedtoRECVSS 1.65(3) 3.3 3.6 IOVDD1, ReferencedtoIOVSS(1) 1.1 3.6 IOVDD2, IOVDD3 DVDD(4) PowerSupplyVoltageRange ReferencedtoDVSS(1) 1.26 1.8 1.95 CPVDD_18 PowerSupplyVoltageRange ReferencedtoCPVSS (1) 1.26 1.8 1.95 V HVDD_18 ReferencedtoAVSS(1) Ground-centered 1.5(3) 1.8 1.95 Configuration Unipolar 1.65(3) 1.95 Configuration (1) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.1Vmax,foranycombinationofground signals.AVDDx_18arewithin+/-0.05Vofeachother.SVDDandSPK_Varewithin+/-0.05Vofeachother. (2) ForoptimalperformancewithCM=0.9V,minAVDD=1.8V. (3) MinimumvoltageforHVDD_18shouldbegreaterthanorequaltoAVDD2_18. (4) AtDVDDvalueslowerthan1.65V,thePLLandSARADCdonotfunction.PleaseseetableinSLAU475,MaximumTLV320AIC3263 ClockFrequenciesfordetailsonmaximumclockfrequencies. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Recommended Operating Conditions (continued) MIN NOM MAX UNIT SVDD(1) PowerSupplyVoltageRange ReferencedtoSVSS(1) 2.7 5.5 V SPK_V(1) PowerSupplyVoltageRange ReferencedtoSVSS(1) 2.7 5.5 V MICBIAS_VD PowerSupplyVoltageRange ReferencedtoAVSS3(1) 2.7 5.5 V D VREF_SAR Externalvoltagereferencefor ReferencedtoAVSS 1.8 AVDDx_18 V SAR PLLInputFrequency(5) Clockdividerusesfractionaldivide 10 20 MHz (D>0),P=1,PLL_CLKIN_DIV=1,DVDD≥1.65V (RefertotableinSLAU475,Maximum TLV320AIC3263ClockFrequencies) Clockdividerusesintegerdivide 0.512 20 MHz (D=0),P=1,PLL_CLKIN_DIV=1,DVDD≥1.65V (RefertotableinSLAU475,Maximum TLV320AIC3263ClockFrequencies) MCLK MasterClockFrequency MCLK;MasterClockFrequency;IOVDD≥1.65V 50 MHz MCLK;MasterClockFrequency;IOVDD≥1.1V 33 SCL SCLClockFrequency 400 kHz LOL,LOR Stereolineoutputload 0.6 10 kΩ resistance HPL,HPR Stereoheadphoneoutputload Single-endedconfiguration 14.4 16 Ω resistance SPKP-SPKM Speakeroutputload Differential 7.2 8 Ω resistance RECP-RECM Receiveroutputresistance Differential 24.4 32 Ω C Chargepumpinputcapacitor 10 µF IN (CPVDDtoCPVSSterminals) C Chargepumpoutputcapacitor TypeX7R 2.2 µF O (VNEGterminal) C Chargepumpflyingcapacitor TypeX7R 2.2 µF F (CPFCPtoCPFCMterminals) TOPR OperatingTemperatureRange –40 85 °C (5) ThePLLInputFrequencyreferstoclockfrequencyafterPLL_CLKIN_DIVdivider.Frequencieshigherthan20MHzcanbesentasan inputtothisPLL_CLKIN_DIVandreducedinfrequencypriortoinputtothePLL. 10 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, SAR ADC T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SARADCInputs Analog Inputvoltagerange 0 VREF_SAR V Input Inputimpedance IN1L/AUX1orIN1R/AUX2Selected 1÷(f×C )(1) kΩ SAR_IN Inputcapacitance,C 25 pF SAR_IN Inputleakagecurrent 1 µA Battery VBATInputvoltagerange 2.2 5.5 V Input VBATInputimpedance VBAT(Batterymeasurement) 5 kΩ selected(2) VBATInputcapacitance 25 pF VBATInputleakagecurrent 1 µA SARADCConversion Resolution Programmable:8-bit,10-bit,12-bit 8 12 Bits Nomissingcodes 12-bitresolution 11 Bits IN1L/ Integrallinearity ±1 LSB 12-bitresolution,SARADCclock= AUX1 InternalOscillatorClock,Conversion Offseterror clock=InternalOscillator/4,External ±1 LSB Reference=1.8V(3) Gainerror -0.09 % Noise DCvoltageappliedtoIN1L/AUX1=1V, ±1 LSB SARADCclock=InternalOscillator Clock,Conversionclock=Internal Oscillator/4,ExternalReference= 1.8V(4)(3) VBAT Accuracy 12-bitresolution,SARADCclock= 2 % InternalOscillatorClock,Conversion Offseterror ±2 LSB clock=InternalOscillator/4,Internal Gainerror Reference=1.25V 1.5 % Noise DCvoltageappliedtoVBAT=3.6V,12- ±0.5 LSB bitresolution,SARADCclock=Internal OscillatorClock,Conversionclock= InternalOscillator/4,InternalReference =1.25V ConversionRate Normalconversionoperation 12-bitresolution,SARADCclock=12 119 kHz MHzExternalClock,Conversionclock= ExternalClock/4,ExternalReference= 1.8V(3).WithFastSPIreadingofdata. High-speedconversion 8-bitresolution,SARADCclock=12 250 kHz operation MHzExternalClock,InternalConversion clock=ExternalClock(Conversion accuracyisreduced.),External Reference=1.8V(3).WithFastSPI readingofdata. VoltageReference-VREF_SAR Voltagerange InternalVREF_SAR 1.25±0.05 V ExternalVREF_SAR 1.25 AVDDx_18 V ReferenceNoise CM=0.9V,C =1μF 46 μV ref RMS DecouplingCapacitor 1 μF (1) SARinputimpedanceisdependentonthesamplingfrequency(fdesignatedinHz),andthesamplingcapacitorisC =25pF. SAR_IN (2) WhenVBATisnotbeingsampled/converted.WhenVBATisbeingsampled,effectiveinputimpedancetoGNDis5.24kΩ. (3) WhenutilizingExternalSARreference,thisexternalreferenceshouldberestrictedV ≤AVDD_18andAVDD2_18. EXT_SAR_REF (4) Noisefromexternalreferencevoltageisexcludedfromthismeasurement. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, ADC T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIOADC(CM=0.9V) (1) (2) Inputsignallevel(0dB) Single-ended,CM=0.9V 0.5 V RMS 1kHzsinewaveinput,Single-endedConfiguration IN2RtoRightADCandIN2LtoLeftADC,R =20kΩ,f =48kHz, in s DeviceSetup AOSR=128,MCLK=256*f,PLLDisabled;AGC=OFF, s ChannelGain=0dB,ProcessingBlock=PRB_R1, PowerTune=PTM_R4 Inputsac-shortedtoground 85 94 Signal-to-noiseratio,A- IN1R,IN3R,IN4ReachexclusivelyroutedinseparateteststoRight 94 SNR weighted(1) (2) ADCandac-shortedtoground dB IN1L,IN3L,IN4LeachexclusivelyroutedinseparateteststoLeft ADCandac-shortedtoground DynamicrangeA- –60dBfull-scale,1-kHzinputsignal 94 dB DR weighted(1) (2) –3dBfull-scale,1-kHzinputsignal –89 –75 dB IN1R,IN3R,IN4ReachexclusivelyroutedinseparateteststoRight –88 TotalHarmonic ADC THD+N DistortionplusNoise IN1L,IN3L,IN4LeachexclusivelyroutedinseparateteststoLeft ADC –3dBfull-scale,1-kHzinputsignal 1kHzsinewaveinputat-3dBFS,Single-endedconfiguration 0.02 dB R =20Kf =48kHz,AOSR=128,MCLK=256*f,PLLDisabled GainError in s s AGC=OFF,ChannelGain=0dB,ProcessingBlock=PRB_R1, PowerTune=PTM_R4,CM=0.9V 1kHzsinewaveinputat-3dBFS,Single-endedconfiguration 110 dB InputChannel IN1LroutedtoLeftADC,IN1RroutedtoRightADC,R =20K Separation in AGC=OFF,AOSR=128,ChannelGain=0dB,CM=0.9V 1kHzsinewaveinputat–3dBFSonIN2L,IN2Linternallynotrouted. 112 dB InputPinCrosstalk IN1LroutedtoLeftADC,ac-coupledtoground 1kHzsinewaveinputat–3dBFSonIN2R,IN2Rinternallynot routed. IN1RroutedtoRightADC,ac-coupledtoground Single-endedconfigurationR =20kΩ,AOSR=128Channel in Gain=0dB,CM=0.9V 217Hz,100mVppsignalonAVDD_18,AVDDx_18 59 dB PSRR Single-endedconfiguration,Rin=20kΩ,ChannelGain=0dB; CM=0.9V (1) Ratioofoutputlevelwith1-kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20-Hzto20-kHzbandwidthusinganaudioanalyzer. (2) Allperformancemeasurementsdonewithpre-analyzer20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesucha filtermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-pass filterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues 12 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, ADC (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIOADC(CM=0.75V) Inputsignallevel(0dB) Single-ended,CM=0.75V,AVDD_18,AVDDx_18=1.5V 0.375 V RMS 1kHzsinewaveinput,Single-endedConfiguration IN2RtoRightADCandIN2LtoLeftADC,R =20K,f =48kHz, in s DeviceSetup AOSR=128,MCLK=256*f,PLLDisabled;AGC=OFF, s ChannelGain=0dB,ProcessingBlock=PRB_R1, PowerTune=PTM_R4 SNR Signal-to-noiseratio,A- Inputsac-shortedtoground 91 dB weighted (3) (4) IN1R,IN3R,IN4ReachexclusivelyroutedinseparateteststoRight 91 dB ADCandac-shortedtoground IN1L,IN3L,IN4LeachexclusivelyroutedinseparateteststoLeft ADCandac-shortedtoground DR DynamicrangeA- –60dBfull-scale,1-kHzinputsignal 92 dB weighted(3) (4) THD+N TotalHarmonic –3dBfull-scale,1-kHzinputsignal –85 dB DistortionplusNoise (3) Ratioofoutputlevelwith1-kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20-Hzto20-kHzbandwidthusinganaudioanalyzer. (4) Allperformancemeasurementsdonewithpre-analyzer20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesucha filtermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-pass filterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, ADC (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIOADC(DifferentialInput,CM=0.9V) Inputsignallevel(0dB) Differential,CM=0.9V,AVDD_18,AVDDx_18=1.8V 1 V RMS 1kHzsinewaveinput,DifferentialConfiguration IN1L,IN1RRoutedtoRightADC,IN2L,IN2RRoutedtoLeftADC DeviceSetup R =20kΩ,f =48kHz,AOSR=128,MCLK=256*f, in s s PLLDisabled,AGC=OFF,ChannelGain=0dB, ProcessingBlock=PRB_R1,PowerTune=PTM_R4 SNR Signal-to-noiseratio,A- Inputsac-shortedtoground 94 dB weighted (5) (6) DR DynamicrangeA- –60dBfull-scale,1-kHzinputsignal 95 dB weighted(5) (6) THD+N TotalHarmonic –3dBfull-scale,1-kHzinputsignal –89 dB DistortionplusNoise 1kHzsinewaveinputat-3dBFS,Differentialconfiguration 0.04 dB R =20kΩ,f =48kHz,AOSR=128,MCLK=256*f,PLLDisabled GainError in s s AGC=OFF,ChannelGain=0dB,ProcessingBlock=PRB_R1, PowerTune=PTM_R4,CM=0.9V 1kHzsinewaveinputat-3dBFS,Differentialconfiguration 108 dB InputChannel IN1L/IN1RdifferentialsignalroutedtoRightADC, Separation IN2L/IN2RdifferentialsignalroutedtoLeftADC,R =20kΩ in AGC=OFF,AOSR=128,ChannelGain=0dB,CM=0.9V 1kHzsinewaveinputat–3dBFSonIN2L/IN2R,IN2L/IN2Rinternally 110 dB InputPinCrosstalk notrouted. IN1L/IN1RdifferentiallyroutedtoRightADC,ac-coupledtoground 1kHzsinewaveinputat–3dBFSonIN2L/IN2R,IN2L/IN2Rinternally notrouted. IN3L/IN3RdifferentiallyroutedtoLeftADC,ac-coupledtoground DifferentialconfigurationR =20kΩ,AOSR=128ChannelGain=0dB, in CM=0.9V 217Hz,100mVppsignalonAVDD_18,AVDDx_18 52 dB PSRR Differentialconfiguration,Rin=20K,ChannelGain=0dB;CM=0.9V AUDIOADC IN1-IN3,Single-Ended,Rin=10K,PGAgainsetto0dB 0 dB IN1-IN3,Single-Ended,Rin=10K,PGAgainsetto47.5dB 47.5 dB IN1-IN3,Single-Ended,Rin=20K,PGAgainsetto0dB –6 dB ADCprogrammablegain IN1-IN3,Single-Ended,Rin=20K,PGAgainsetto47.5dB 41.5 dB amplifiergain IN1-IN3,Single-Ended,Rin=40K,PGAgainsetto0dB –12 dB IN1-IN3,Single-Ended,Rin=40K,PGAgainsetto47.5dB 35.5 dB IN4,Single-Ended,Rin=20K,PGAgainsetto0dB –6 dB IN4,Single-Ended,Rin=20K,PGAgainsetto47.5dB 41.5 dB ADCprogrammablegain 1-kHztone 0.5 dB amplifierstepsize (5) Ratioofoutputlevelwith1-kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20-Hzto20-kHzbandwidthusinganaudioanalyzer. (6) Allperformancemeasurementsdonewithpre-analyzer20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesucha filtermayresultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-pass filterremovesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues 14 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, Bypass Outputs T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGBYPASSTORECEIVERAMPLIFIER,DIRECTMODE Load=32Ω(differential),56pF; InputCM=0.9V;OutputCM=1.65V; DeviceSetup IN1LroutedtoRECPandIN1Rroutedto RECM; ChannelGain=0dB Fullscaledifferentialinputvoltage(0dB) 1 V RMS GainError 707mVrms(-3dBFS),1-kHzinputsignal –0.7 dB Noise,A-weighted(1) IdleChannel,IN1LandIN1Rac-shortedto 12 μV RMS ground THD+N TotalHarmonicDistortionplusNoise 707mVrms(-3dBFS),1-kHzinputsignal –89 dB ANALOGBYPASSTOHEADPHONEAMPLIFIER,PGAMODE Load=16Ω(single-ended),56pF;HVDD_18 =3.3V InputCM=0.9V;OutputCM=1.65V DeviceSetup IN1LroutedtoADCPGA_L,ADCPGA_L routedthroughMALtoHPL;andIN1Rrouted toADCPGA_R,ADCPGA_Rroutedthrough MARtoHPR;R =20K;ChannelGain=0dB in Fullscaledifferentialinputvoltage(0dB) 0.5 V RMS GainError 446mVrms(-1dBFS),1-kHzinputsignal -1.1 dB Noise,A-weighted(1) IdleChannel,IN1LandIN1Rac-shortedto 6.0 μV RMS ground THD+N TotalHarmonicDistortionplusNoise 446mVrms(-1dBFS),1-kHzinputsignal -83 dB ANALOGBYPASSTOHEADPHONEAMPLIFIER(GROUND-CENTEREDCIRCUITCONFIGURATION),PGAMODE Load=16Ω(single-ended),56pF; InputCM=0.9V; IN1LroutedtoADCPGA_L,ADCPGA_L DeviceSetup routedthroughMALtoHPL;andIN1Rrouted toADCPGA_R,ADCPGA_Rroutedthrough MARtoHPR;R =20K;ChannelGain=0dB in Fullscaleinputvoltage(0dB) 0.5 V RMS GainError 446mVrms(-1dBFS),1-kHzinputsignal –1.0 dB Noise,A-weighted(1) IdleChannel,IN1LandIN1Rac-shortedto 11 μV RMS ground THD+N TotalHarmonicDistortionplusNoise 446mVrms(-1dBFS),1-kHzinputsignal -71 dB (1) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, Bypass Outputs (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGBYPASSTOLINE-OUTAMPLIFIER,PGAMODE Load=10KOhm(single-ended),56pF; InputandOutputCM=0.9V; IN1LroutedtoADCPGA_LandIN1Rrouted DeviceSetup toADCPGA_R;Rin=20k ADCPGA_LroutedthroughMALtoLOLand ADCPGA_RroutedthroughMARtoLOR; ChannelGain=0dB Fullscaleinputvoltage(0dB) 0.5 V RMS GainError 446mVrms(-1dBFS),1-kHzinputsignal –0.9 dB IdleChannel, 5.9 μV RMS IN1LandIN1Rac-shortedtoground Noise,A-weighted (2) ChannelGain=40dB, 3.0 μV RMS Inputsac-shortedtoground,InputReferred ANALOGBYPASSTOLINE-OUTAMPLIFIER,DIRECTMODE Load=10KOhm(single-ended),56pF; InputandOutputCM=0.9V; DeviceSetup IN1LroutedtoLOLandIN1RroutedtoLOR; ChannelGain=0dB Fullscaleinputvoltage(0dB) 0.5 V RMS GainError 446mVrms(-1dBFS),1-kHzinputsignal –0.4 dB IdleChannel, 3.0 μV Noise,A-weighted(2) RMS IN1LandIN1Rac-shortedtoground (2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues 16 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, Microphone Interface T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT MICROPHONEBIAS(MICBIASorMICBIAS_EXT) Biasvoltage CM=0.9V,MICBIAS_VDD=3.3V MicbiasMode0 1.80 V MicbiasMode1 2.00 V MicbiasMode2 2.15 V MicbiasMode3 2.49 V MicbiasMode4(1) 2.85 V MicbiasMode5(1) 3.00 V CM=0.75V,MICBIAS_VDD=3.3V MicbiasMode0 1.50 V MicbiasMode1 1.67 V MicbiasMode2 1.79 V MicbiasMode3 2.08 V MicbiasMode4 2.37 V MicbiasMode5 2.50 V OutputNoise CM=0.9V,MicbiasMode2,A-weighted,20Hz 10.04 μV RMS to20kHzbandwidth, Currentload=0mA. 70.99 nV/√Hz CurrentSourcing MicbiasMode0,1,2,3,4,or5(CM=0.9V) 8 mA MaximumLineCapacitance MicbiasMode0,1,2,3,4,or5(CM=0.9V)(2) 10 pF 217Hz,100mVppsignalonAVDDx_18, 48 DVDD,IOVDDx,MICBIAS_VDD=3.6V, dB CM=0.75V 217Hz,100mVppsignalonMICBIAS_VDD, 90 dB PSRR MICBIAS_VDD=3.6V,CM=0.75V 1kHz,100mVppsignalonAVDDx_18,DVDD, 47 dB IOVDDx,MICBIAS_VDD=3.6V,CM=0.75V 1kHz,100mVppsignalonMICBIAS_VDD, 85 dB MICBIAS_VDD=3.6V (1) WithCommonModevoltageof0.9V,theMICBIAS_VDDvoltagemustbeatminimum3.05VtoutilizeMicbiasMode4,andminimumof 3.2VtoutilizeMicbiasMode5. (2) AnexplicitexternalcapacitorshouldnotbeplacedonMICBIASorMICBIAS_EXTlines. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, Audio DAC Outputs T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIODAC–STEREOSINGLE-ENDEDLINEOUTPUT Load=10kΩ(single-ended),56pF InputandOutputCM=0.9V DOSR=128, DeviceSetup MCLK=256*f, s ChannelGain=0dB, ProcessingBlock=PRB_P1, PowerTune=PTM_P4 Fullscaleoutputvoltage(0dB) 0.5 V RMS SNR Signal-to-noiseratioA-weighted(1) (2) AllzerosfedtoDACinput 85 101 dB DR Dynamicrange,A-weighted (1) (2) –60dB1kHzinputfull-scalesignal,Wordlength=20 102 dB bits THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal –92 –70 dB DACGainError –3dBfull-scale,1-kHzinputsignal 0.1 dB DACMuteAttenuation Mute 125 dB DACchannelseparation –1dB,1kHzsignal,betweenleftandrightLineout 108 dB 100mVpp,1kHzsignalappliedtoAVDD_18, 81 dB AVDDx_18 DACPSRR 100mVpp,217HzsignalappliedtoAVDD_18, 79 dB AVDDx_18 AUDIODAC–STEREOSINGLE-ENDEDLINEOUTPUT Load=10kΩ(single-ended),56pF InputandOutputCM=0.75V;AVDD_18,AVDDx_18, HVDD_18=1.5V DOSR=128 DeviceSetup MCLK=256*fs ChannelGain=0dB ProcessingBlock=PRB_P1 PowerTune=PTM_P4 Fullscaleoutputvoltage(0dB) 0.375 V RMS SNR Signal-to-noiseratio,A-weighted (1) AllzerosfedtoDACinput 100 dB (2) DR Dynamicrange,A-weighted (1) (2) –60dB1kHzinputfull-scalesignal,Wordlength=20 99 dB bits THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -90 dB (1) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (2) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. 18 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, Audio DAC Outputs (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIODAC–MONODIFFERENTIALLINEOUTPUT Load=10kΩ(differential),56pF InputandOutputCM=0.9V,LOLsignalroutedto LORamplifier DeviceSetup DOSR=128,MCLK=256*fs, ChannelGain=0dB, ProcessingBlock=PRB_P1, PowerTune=PTM_P4 Fullscaleoutputvoltage(0dB) 1 V RMS SNR Signal-to-noiseratioA-weighted(3) (4) AllzerosfedtoDACinput 101 dB DR Dynamicrange,A-weighted (3) (4) –60dB1kHzinputfull-scalesignal, 101 dB THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -91 dB DACGainError –3dBfull-scale,1-kHzinputsignal -0.03 dB DACMuteAttenuation Mute 124 dB 100mVpp,1kHzsignalappliedtoAVDD_18, 63 dB AVDDx_18 DACPSRR 100mVpp,217HzsignalappliedtoAVDD_18, 63 dB AVDDx_18 (3) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (4) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, Audio DAC Outputs (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIODAC–STEREOSINGLE-ENDEDHEADPHONEOUTPUT(GROUND-CENTEREDCIRCUITCONFIGURATION) Load=16Ω(single-ended),56pF, InputCM=0.9V; DOSR=128,MCLK=256*f, s DeviceSetup ChannelGain=0dB, ProcessingBlock=PRB_P1, PowerTune=PTM_P3, HeadphoneOutputStrength=100% Output1 Outputvoltage 0.5 V RMS SNR Signal-to-noiseratio,A-weighted (5) AllzerosfedtoDACinput 83 94 dB (6) DR Dynamicrange,A-weighted (5) (6) –60dB1kHzinputfull-scalesignal 94 dB THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -75 -60 dB DACGainError –3dB,1kHzinputfullscalesignal 0.03 dB DACMuteAttenuation Mute 130 dB DACchannelseparation –3dB,1kHzsignal,betweenleftandrightHPout 80 dB 100mVpp,1kHzsignalappliedtoAVDD_18, 59 dB AVDD1x_18 DACPSRR 100mVpp,217HzsignalappliedtoAVDD_18, 63 dB AVDD1x_18 PowerDelivered THDN≤-40dB,Load=16Ω 22 mW Output2 Outputvoltage Load=16Ω(single-ended),ChannelGain=5dB 0.8 V RMS SNR Signal-to-noiseratio,A-weighted(5) (6) AllzerosfedtoDACinput,Load=16Ω 95 dB PowerDelivered THDN≤-40dB,Load=16Ω 25 mW Output3 Outputvoltage Load=32Ω(single-ended),ChannelGain=5dB 0.9 V RMS SNR Signal-to-noiseratio,A-weighted(5) (6) AllzerosfedtoDACinput,Load=32Ω 97 dB PowerDelivered THDN≤-40dB,Load=32Ω 22 mW (5) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (6) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. 20 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, Audio DAC Outputs (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIODAC–STEREOSINGLE-ENDEDHEADPHONEOUTPUT(UNIPOLARCIRCUITCONFIGURATION) Load=16Ω(single-ended),56pF InputandOutputCM=0.9V,DOSR=128, MCLK=256*f,ChannelGain=0dB DeviceSetup s ProcessingBlock=PRB_P1 PowerTune=PTM_P4 HeadphoneOutputControl=100% Fullscaleoutputvoltage(0dB) 0.5 V RMS SNR Signal-to-noiseratio,A-weighted(7) (8) AllzerosfedtoDACinput 99 dB DR Dynamicrange,A-weighted (7) (8) –60dB1kHzinputfull-scalesignal,PowerTune= 99 dB PTM_P4 THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -89 -65 dB DACGainError –3dB,1kHzinputfullscalesignal -0.16 dB DACMuteAttenuation Mute 126 dB DACchannelseparation –1dB,1kHzsignal,betweenleftandrightHPout 119 dB 100mVpp,1kHzsignalappliedtoAVDD_18, 65 dB AVDD1x_18 DACPSRR 100mVpp,217HzsignalappliedtoAVDD_18, 78 dB AVDD1x_18 R =16Ω 16 L PowerDelivered THDN≤-40dB,InputCM=0.9V, mW OutputCM=0.9V (7) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (8) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, Audio DAC Outputs (continued) T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AUDIODAC–STEREOSINGLE-ENDEDHEADPHONEOUTPUT(UNIPOLARCIRCUITCONFIGURATION) Load=16Ω(single-ended),56pF, InputandOutputCM=0.75V;AVDD_18,AVDDx_18, HVDD_18=1.5V, DOSR=128,MCLK=256*f, DeviceSetup s ChannelGain=0dB, ProcessingBlock=PRB_P1, PowerTune=PTM_P4 HeadphoneOutputControl=100% Fullscaleoutputvoltage(0dB) 0.375 V RMS SNR Signal-to-noiseratio,A-weighted(9) AllzerosfedtoDACinput 99 dB (10) DR Dynamicrange,A-weighted (9) (10) -60dB1kHzinputfull-scalesignal 99 dB THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -90 dB AUDIODAC–MONODIFFERENTIALRECEIVEROUTPUT Load=32Ω(differential),56pF, OutputCM=1.65V, AVDDx_18=1.8V,DOSR=128 MCLK=256*f,LeftDACroutedtoRECP,RECM, DeviceSetup s Channel(ReceiverDriver)Gain=6dBforfullscale outputsignal, ProcessingBlock=PRB_P4, PowerTune=PTM_P4 Fullscaleoutputvoltage(0dB) 2 V RMS SNR Signal-to-noiseratio,A-weighted(9) AllzerosfedtoDACinput 87 102 dB (10) DR Dynamicrange,A-weighted (9) (10) –60dB1kHzinputfull-scalesignal 102 dB THD+N TotalHarmonicDistortionplusNoise –3dBfull-scale,1-kHzinputsignal -91 –70 dB 100mVpp,1kHzsignalappliedtoAVDD_18, 64 dB AVDD1x_18 DACPSRR 100mVpp,217HzsignalappliedtoAVDD_18, 64 dB AVDD1x_18 R =32Ω 123 mW L PowerDelivered THDN≤-40dB,InputCM=0.9V, OutputCM=1.65V (9) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (10) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. 22 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Electrical Characteristics, Class-D Outputs T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DACOUTPUTtoCLASS-DSPEAKEROUTPUT;Load=8Ω(Differential),56pF+33µH SVDD=3.6,BTLmeasurement,DACinput=0dBFS, Outputvoltage 2.64 V class-Dgain=12dB,THD+N≤–20dB,CM=0.9V RMS SVDD=3.6V,BTLmeasurement,class-Dgain=6dB, measuredasidle-channelnoise,A-weighted(with SNR Signal-to-noiseratio respecttofull-scaleoutputvalueof2Vrms)(1)(2), 91 dB CM=0.9V SVDD=3.6V,BTLmeasurement,DACinput=0dBFS, THD Totalharmonicdistortion -70 dB class-Dgain=6dB,CM=0.9V Totalharmonicdistortion SVDD=3.6V,BTLmeasurement,DACinput=0dBFS, THD+N -70 dB +noise class-Dgain=6dB,CM=0.9V SVDD=3.6V,BTLmeasurement,rippleonSVDD= 64 dB Power-supplyrejection 200mVp-pat1kHz,CM=0.9V PSRR ratio SVDD=3.6V,BTLmeasurement,rippleonSVDD= 64 dB 200mVp-pat217Hz,CM=0.9V Muteattenuation AnalogMuteOnly 92 dB SVDD=3.6V 0.72 THD+N=10%,f=1kHz, Class-DGain=12dB,CM= SVDD=4.2V 0.99 0.9V,R =8Ω L SVDD=5.5V 1.68 P Maximumoutputpower W O SVDD=3.6V 0.58 THD+N=1%,f=1kHz, Class-DGain=12dB,CM= SVDD=4.2V 0.79 0.9V,R =8Ω L SVDD=5.5V 1.36 DACOUTPUTtoCLASS-DSPEAKEROUTPUT;Load=8Ω(Differential),56pF+33µH SVDD=5.0V,BTLmeasurement,DACinput=0dBFS, Outputvoltage 3.40 V class-Dgain=12dB,THD+N≤–20dB,CM=0.9V RMS SVDD=5.0V,BTLmeasurement,class-Dgain=6dB, measuredasidle-channelnoise,A-weighted(with SNR Signal-to-noiseratio respecttofull-scaleoutputvalueof2Vrms)(1) (2), 92 CM=0.9V SVDD=5.0V,BTLmeasurement,DACinput=0dBFS, THD Totalharmonicdistortion -72 class-Dgain=6dB,CM=0.9V Totalharmonicdistortion SVDD=5.0V,BTLmeasurement,DACinput=0dBFS, THD+N -72 +noise class-Dgain=6dB,CM=0.9V SVDD=5.0V,BTLmeasurement,rippleonSVDD= 60 Power-supplyrejection 200mVp-pat1kHz,CM=0.9V PSRR ratio SVDD=5.0V,BTLmeasurement,rippleonSVDD= 60 200mVp-pat217Hz,CM=0.9V Muteattenuation AnalogMuteOnly 93 dB THD+N=10%,f=1kHz, P Maximumoutputpower Class-DGain=12dB,CM= SVDD=5.0V 1.40 W O 0.9V,R =8Ω L (1) Ratioofoutputlevelwith1kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera 20Hzto20kHzbandwidthusinganaudioanalyzer. (2) Allperformancemeasurementsdonewith20kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Electrical Characteristics, Misc. T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFERENCE-VREF_AUDIO CMMode=0(0.9V) 0.9 ReferenceVoltageSettings V CMMode=1(0.75V) 0.75 ReferenceNoise CM=0.9V,A-weighted,20Hzto20kHzbandwidth, 1.62 μVRMS Cref=1μF DecouplingCapacitor 1 μF miniDSP(1) miniDSPclockfrequency-ADC DVDD=1.26V 37.5 MHz miniDSPclockfrequency-DAC DVDD=1.26V 35.0 MHz miniDSPclockfrequency-ADC DVDD=1.65V 63 MHz miniDSPclockfrequency-DAC DVDD=1.65V 59.0 MHz miniDSPclockfrequency-ADC DVDD=1.71V 69 MHz miniDSPclockfrequency-DAC DVDD=1.71V 62.5 MHz ShutdownPower CoarseAVddsupplyturnedoff,AllExternalanalog DeviceSetup suppliespoweredandsetavailable,Noexternal digitalinputistoggled,registervaluesareretained. P(total)(2) Sumofallsupplycurrents,allsuppliesat1.8V 9.8 μW exceptforSVDD=SPK_V=MICBIAS_VDD=3.6V andRECVDD_33=3.3V I(DVDD) 2.6 μA I(IOVDD1,IOVDD2,IOVDD3) 0.15 μA I(AVDD1_18,AVDD2_18,AVDD4_18, 1.15 μA AVDD_18,HVDD_18,CPVDD_18) I(RECVDD_33) 0.15 μA I(SVDD,SPK_V,MICBIAS_VDD) 0.5 μA (1) miniDSPclockspeedisspecifiedbydesignandnottestedinproduction. (2) Forfurtherdetailsonplaybackandrecordingpowerconsumption,refertoPowerTunesectioninSLAU475. Electrical Characteristics, Logic Levels, IOVDDx T =25°C;AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,DVDD,IOVDDx=1.8V;RECVDD_33=3.3V;SVDD,SPK_V, A MICBIAS_VDD=3.6V;f (Audio)=48kHz;AudioWordLength=20bits;C =1μFonVREF_SARandVREF_AUDIOpins; S ext PLLdisabledunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT LOGICFAMILY CMOS V LogicLevel I =5μA,IOVDDx>1.65V 0.7×IOVDDx V IH IH I =5μA,1.2V≤IOVDDx<1.65V 0.9×IOVDDx V IH I =5μA,IOVDDx<1.2V IOVDDx V IH V I =5μA,IOVDDx>1.65V –0.3 0.3×IOVDDx V IL IL I =5μA,1.2V≤IOVDDx<1.65V 0.1×IOVDDx V IL I =5μA,IOVDDx<1.2V 0 V IL V I =3mAload,IOVDDx>1.65V 0.8×IOVDDx V OH OH I =1mAload,IOVDDx<1.65V 0.8×IOVDDx V OH V I =3mAload,IOVDDx>1.65V 0.1×IOVDDx V OL OL I =1mAload,IOVDDx<1.65V 0.1×IOVDDx V OL CapacitiveLoad 10 pF 24 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Interface Timing Note:Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest.Theaudioserialinterfacetiming specificationsareappliedtoAudioSerialInterface1,AudioSerialInterface2andAudioSerialInterface3. TypicalTimingCharacteristics—AudioDataSerialInterfaceTiming(I2S) WCLKrepresentsWCLK1pinforAudioSerialInterface1BCLKrepresentsBCLK1pinforAudioSerialInterface1DOUT representsDOUT1pinforAudioSerialInterface1DINrepresentsDIN1pinforAudioSerialInterface1Specificationsareat 25°CwithDVDD=1.8VandIOVDDx=1.8V. WCLK t d(WS) BCLK t t d(DO-BCLK) d(DO-WS) DOUT tS(DI) th(DI) DIN Figure3. I2S/LJF/RJFTiminginMasterMode Table2.I2S/LJF/RJFTiminginMasterMode(seeFigure3) PARAMETER IOVDDx=1.8V IOVDDx=3.3V UNITS MIN MAX MIN MAX t (WS) WCLKdelay 22 20 ns d t (DO-WS) WCLKtoDOUTdelay(ForLJFModeonly) 22 20 ns d t (DO-BCLK) BCLKtoDOUTdelay 22 20 ns d t(DI) DINsetup 4 4 ns s t (DI) DINhold 4 4 ns h t BCLKRisetime 10 8 ns r t BCLKFalltime 10 8 ns f Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com WCLK t h(WS) t BCLK tL(BCLK) tH(BCLK) td(DsO(W-WS)S) td(DO-BCLK) DOUT t t h(DI) s(DI) DIN Figure4. I2S/LJF/RJFTiminginSlaveMode Table3.I2S/LJF/RJFTiminginSlaveMode(seeFigure4) PARAMETER IOVDDx=1.8V IOVDDx=3.3V UNITS MIN MAX MIN MAX t (BCLK) BCLKhighperiod 30 30 ns H t (BCLK) BCLKlowperiod 30 30 L t (WS) WCLKsetup 4 4 s t (WS) WCLKhold 4 4 h t (DO-WS) WCLKtoDOUTdelay(ForLJFmodeonly) 22 20 d t (DO-BCLK) BCLKtoDOUTdelay 22 20 d t(DI) DINsetup 4 4 s t (DI) DINhold 4 4 h t BCLKRisetime 5 4 r t BCLKFalltime 5 4 f 26 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 TypicalDSPTimingCharacteristics Specificationsareat25°CwithDVDD=1.8V. WCLK td(WS) td(WS) BCLK t d(DO-BCLK) DOUT ts(DI) th(DI) DIN Figure5. DSP/MonoPCMTiminginMasterMode Table4.DSP/MonoPCMTiminginMasterMode(seeFigure5) PARAMETER IOVDDx=1.8V IOVDDx=3.3V UNITS MIN MAX MIN MAX t (WS) WCLKdelay 22 20 ns d t (DO-BCLK) BCLKtoDOUTdelay 22 20 ns d t(DI) DINsetup 4 4 ns s t (DI) DINhold 4 4 ns h t BCLKRisetime 10 8 ns r t BCLKFalltime 10 8 ns f WCLK th(ws) ts(ws) th(ws) th(ws) BCLK t tL(BCLK) H(BCLK) t d(DO-BCLK) DOUT ts(DI) th(DI) DIN Figure6. DSP/MonoPCMTiminginSlaveMode Table5.DSP/MonoPCMTiminginSlaveMode(seeFigure6) PARAMETER IOVDDx=1.8V IOVDDx=3.3V UNITS MIN MAX MIN MAX t (BCLK) BCLKhighperiod 30 30 ns H t (BCLK) BCLKlowperiod 30 30 ns L t(WS) WCLKsetup 4 4 ns s t (WS) WCLKhold 4 4 ns h t (DO-BCLK) BCLKtoDOUTdelay 22 20 ns d t(DI) DINsetup 5 5 ns s t (DI) DINhold 5 5 ns h t BCLKRisetime 5 4 ns r t BCLKFalltime 5 4 ns f Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com I2CInterfaceTiming Figure7. I2CInterfaceTimingDiagram Table6.I2CInterfaceTiming(seeFigure7) PARAMETER TESTCONDITION Standard-Mode Fast-Mode UNITS MIN TYP MAX MIN TYP MAX f SCLclockfrequency 0 100 0 400 kHz SCL t Holdtime(repeated)START 4.0 0.8 μs HD;STA condition.Afterthisperiod,thefirst clockpulseisgenerated. t LOWperiodoftheSCLclock 4.7 1.3 μs LOW t HIGHperiodoftheSCLclock 4.0 0.6 μs HIGH t SetuptimeforarepeatedSTART 4.7 0.8 μs SU;STA condition t Dataholdtime:ForI2Cbus 0 3.45 0 0.9 μs HD;DAT devices t Dataset-uptime 250 100 ns SU;DAT t SDAandSCLRiseTime 1000 20+0.1C 300 ns r b t SDAandSCLFallTime 300 20+0.1C 300 ns f b t Set-uptimeforSTOPcondition 4.0 0.8 μs SU;STO t BusfreetimebetweenaSTOP 4.7 1.3 μs BUF andSTARTcondition C Capacitiveloadforeachbusline 400 400 pF b 28 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 SPIInterfaceTiming SS=SCLpin,SCLK=I2C_ADDR_SCLKpin,MISO=GPO1pin,andMOSI=SDApin.Specificationsareat25°Cwith DVDD=1.8V. SS t S t td tLead tsck Lag t t SCLK t f r sckl t sckh t v(DOUT) t MISO dis MSBOUT BIT6...1 LSBOUT t a t t su hi MOSI MSBIN BIT6...1 LSBIN Figure8. SPIInterfaceTimingDiagram TimingRequirements(SeeFigure8) Specificationsareat25°CwithDVDD=1.8V. Table7.SPIInterfaceTiming PARAMETER TESTCONDITION IOVDD1=1.8V IOVDD1=3.3V UNITS MIN TYP MAX MIN TYP MAX t SCLKPeriod(1) 50 40 ns sck t SCLKPulsewidthHigh 25 20 ns sckh t SCLKPulsewidthLow 25 20 ns sckl t EnableLeadTime 25 20 ns lead t EnableTrailTime 25 20 ns trail t SequentialTransferDelay 25 20 ns d;seqxfr t SlaveDOUT(MISO)accesstime 25 20 ns a t SlaveDOUT(MISO)disabletime 25 20 ns dis t DIN(MOSI)datasetuptime 8 8 ns su t DIN(MOSI)dataholdtime 8 8 ns h;DIN t DOUT(MISO)datavalidtime 20 14 ns v;DOUT t SCLKRiseTime 4 4 ns r t SCLKFallTime 4 4 ns f (1) Theseparametersarebasedoncharacterizationandarenottestedinproduction. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Typical Characteristics Device Power Consumption Device power consumption largely depends on PowerTune configuration. For information on device power consumption,seetheTLV320AIC3263ApplicationReferenceGuide,literaturenumberSLAU475. Typical Performance AudioADCPerformance ADCSNR vs ADCSINGLEENDEDINPUTTOADCFFT@-3dBr CHANNELGAIN vs Input-Referred FREQUENCY 0 Rin = 10k, DE 110 Rin = 20k, DE −20 Rin = 40k, DE 105 S) −40 F B) 100 dB −60 R (d de ( SN 95 Rin = 10k, SE plitu −80 Rin = 20k, SE m A−100 90 Rin = 40k, SE −120 85 −140 −10 0 10 20 30 40 50 0.02 0.1 1 10 20 Channel Gain (dB) Frequency (kHz) G001 G002 Figure9. Figure10. ADCDIFFERENTIALINPUTTOADCFFT@-3dBr vs FREQUENCY 0 −20 S) −40 F B d −60 e ( d plitu −80 m A−100 −120 −140 0.02 0.1 1 10 20 Frequency (kHz) G003 Figure11. AudioDACPerformance 30 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 DACTOHEADPHONEOUTPUT(GCHP)FFTAMPLITUDE DACTOLINEOUTPUTFFTAMPLITUDE@-3dBFS @-3dBFS vs vs FREQUENCY FREQUENCY 10kΩLoad 16ΩLoad 0 0 −20 −20 −40 −40 Br) Br) e (d −60 e (d −60 d d u u plit −80 plit −80 m m A A −100 −100 −120 −120 −140 −140 0.02 0.1 1 10 20 0.02 0.1 1 10 20 Frequency (kHz) Frequency (kHz) G004 G005 Figure12. Figure13. DACDIRECTTODIFFERENTIALRECEIVEROUTPUTFFT DACTOHEADPHONEOUTPUT(GCHP)FFTAMPLITUDE AMPLITUDE@-3dBFS-NEWROUTINGCOMPAREDTO @-3dBFS AIC3262 vs vs FREQUENCY FREQUENCY 32ΩLoad 32ΩLoad 0 20 −20 0 −20 −40 Br) Br) −40 e (d −60 e (d d d −60 u u mplit −80 mplit −80 A A −100 −100 −120 −120 −140 −140 0.02 0.1 1 10 20 0.02 0.1 1 10 20 Frequency (kHz) Frequency (kHz) G006 G007 Figure14. Figure15. TOTALHARMONICDISTORTION+NOISE TOTALHARMONICDISTORTION+NOISE vs vs HEADPHONE(GCHP)OUTPUTPOWER DIFFERENTIALRECEIVEROUTPUTPOWER 9dBGain 32ΩLoad-DACDIRECTPATH dB) 0 0 Cm=0.75V,Gain=6dB oise ( −10 CHMVD=D0.=7C5vP,V32DODh=m1.,5V −10 RECVDD=1.65 CRMEC=V0.D9DV,=G1a.8inV=6dB +N −20 −20 n o −30 Harmonic Distorti −−−−65430000 CHCHMVMVDD==DD00..==99CCvv,,PP13VV62OODDDDhhmm==11,,..88VV THD_N (dB) −−−−76540000 CRCRMEMECC==VV11..DD56DDV5V,==G,33GaV.3ianVi=n=6d9BdB Total −70 CHMVD=D0.=7C5vP,V16DODh=m1.,5V −80 CRMEC=V1.D2D5V=,2G.5aVin=6dB, − −80 −90 N D H −90 −100 T 0 10 20 30 40 50 60 70 0 20 40 60 80 100 120 140 160 180 200 220 242050 Output Power (mW) Output Power (mW) G008 G009 Figure16. Figure17. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com DIFFERENTIALRECEIVERSNRANDOUTPUTPOWER(DACDIRECTPATH) vs OUTPUTCOMMONMODESETTING 32ΩLoad 120 150 B) atioi (d 110 SNR 125 W) R 100 100 m se d ( To Noi 90 75 elivere gnal 80 Output Power 50 wer d Si o − P R 70 25 N S 60 0 0.8 1.0 1.2 1.4 1.6 Output Common Mode Setting (V) G010 Figure18. Class-DDriverPerformance TOTALHARMONICDISTORTION+NOISE TOTALHARMONICDISTORTION+NOISE vs vs OUTPUTPOWER OUTPUTPOWER DifferentGainSettings,8ΩLoad,SVDD=SPK_V=3.6V DifferentSVDD/SPK_VSupplies,8ΩLoad,12dBGain B) 0 B) 10 d d oise ( −10 oise ( 0 GSVaiDnD ==122.d7BV 132.6dVB 142.2dVB 152.0dVB 158.5dVB N N n+ −20 n+ −10 o o orti −30 24dB orti −20 st st Di Di −30 c −40 c oni 12dB oni −40 m −50 m Har 18dB 30dB Har −50 al −60 al −60 ot ot −T −70 −T −70 N N D 6dB D H −80 H −80 T 0 200 400 600 800 1000 1200 T 0 500 1000 1500 2000 2500 Output Power (mW) Output Power (mW) G011 G012 Figure19. Figure20. TOTALHARMONICDISTORTION+NOISE vs Efficiency Frequency vs DifferentSVDD/SPK_VSupplies,8ΩLoad,OutputPower= OutputPower 500mW DifferentSVDD/SPK_V,8ΩLoad,12dBGain B) −40 100 d se ( 4.2V 3.6V 90 oi −50 N 80 + n o 70 orti −60 %) Dist y ( 60 c −70 nc 50 otal Harmoni −−9800 5.0V 5.5V Efficie 234000 T − 10 N D H−100 0 T 0.02 0.1 1 10 20 0 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) Ouput power (mW) G013 G014 Figure21. Figure22. 32 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 MICBIASPerformance MICBIASMODE1,2,3,4,5,CM=0.9V,MICBIAS_VDD=3.6V vs MICBIASLOADCURRENT 4 3.5 1.8V 2.0V 2.16V 2.5V 2.85V 3.0V 3 2.5 V) e ( 2 ag 1.5 olt 1 V as 0.5 cbi 0 Mi −0.5 −1 −1.5 −2 0 5 10 15 20 25 30 35 40 45 50 Micbias load (mA) G015 Figure23. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Application Overview Typical Circuit Configuration Figure 24 shows a typical circuit configuration for a system utilizing TLV320AIC3263. Note that while this circuit configuration shows all three Audio Serial Interfaces connected to a single Host Processor, it is also quite common for these Audio Serial Interfaces to connect to separate devices (such as Host Processor on Audio SerialInterface1,andmodemsand/orBluetoothdevicesontheotheraudioserialinterfaces). Note:VBATisusedfor System voltagemeasurement. Battery HOST PROCESSOR BATT_VDD Audio Audio Audio Interface1 Interface2 Interface3 1 F 1 F 1 F VREF_SAR VBAT ELECT GPIO6_SCLK GPO1SDA SCLGPIO3GPIO4 MCLKGPIO5 BCLK1 WCLK1DIN1 DOUT1 RESETGPIO1GPIO2 BCLK2WCLK2 DIN2 DOUT2 BCLK3WCLK3 DIN3DOUT3 LLOORL 1 F Lineout VREF_AUDIO S R 1 F PI_ DD +1.8VA S A _ CPVDD_18 1 F I2C 0.1 F 10 F Analog_In1 IN1R/AUX2 CPVSS 1 F CPFCP Analog_In2 IN2L 2.2 F 1 F CPFCM X7RType Analog_In3 IN2R VNEG 1 F 2.2 F X7RType Analog_In4 IN3L 1 F 32 Analog_In5 IN3R RECP Receiver RECM 1 F Analog_In6 IN4R MICDET 2.2k 1 F MICBIAS_EXT Analog_In7 IN4L 0.1 F ToInternal IN1L/AUX1 MICBIAS Mic HPL BATT_VDD MICBIAS_VDD HPR Headset 1 F 0.1 F HPVSS_SENSE AVSS3 AGND at Connector RECVSS 1 F 8 SPKP RECVDD_33 SPKM 0.1 F +3.3VA SPK_V 0.1 F 01.01 FF DDVVDSSDIOVDD1 IOVSS IOVDD2 IOVDD3 HVDD_18 AVDD1_18 AVDD2_18 AVDD4_18 AVDD_18 AVSS1AVSS2AVSS4AVSSSVSSSVDD 2 0.11FF +1.8VD1 10 F 0.1 F 1 F 1 F 0.1 F 1 F 0.1 F 10 F0.1 F0.1 F0.1 F0.1 F +1.8VD2 +1.8VD3 BATT_VDD +1.8VA Figure24. TypicalCircuitConfiguration Device Connections Digital Pins Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a defaultfunction,andalsocanbereprogrammedtocoveralternativefunctionsforvariousapplications. 34 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 The fixed-function pins are hardware-control pins RESET and SPI_SELECT pin. Depending on the state of SPI_SELECT, four pins SCL, SDA, GPO1, and I2C_ADDR_SCLK are configured for either I2C or SPI protocol. Only in I2C mode, I2C_ADDR_SCLK provide two possible I2C addresses for the TLV320AIC3263, while this pin receivestheSPISCLKwhenthedeviceissettoSPImode. OtherdigitalIOpinscanbeconfiguredforvariousfunctionsviaregistercontrol. Analog Pins Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are powereddownbydefault.Theblockscanbepoweredupwithfinegranularityaccordingtotheapplicationneeds. The possible analog routings of analog input pins to ADCs and output amplifiers as well as the routing from DACstooutputamplifierscanbeseenintheAnalogRoutingDiagram. Multifunction Pins Table 8 show the possible allocation of pins for specific functions. The PLL input, for example, can be programmedtobeanyof9pins(MCLK,BCLK1,DIN1,BCLK2,BCLK3,GPIO1,GPIO2,GPIO3,GPIO6). Table8.MultifunctionPinAssignmentsforPinsMCLK,GPIO5,WCLK1,BCLK1,DIN1,DOUT1,WCLK2, BCLK2,DIN2,andDOUT2 1 2 3 4 5 6 7 8 9 10 PinFunction MCLK GPIO5 WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2 A INT1Output E E E E B INT2Output E E E E D CLOCKOUTOutput E E E E E ADC_MOD_CLOCKOutput E E E E F SingleDOUTforASI1(All E E,D Channels) F SingleDOUTforASI2 E E,D F SingleDOUTforASI3 E G MultipleDOUTsforASI1(L1, E R1) G MultipleDOUTsforASI1(L2, E R2) G MultipleDOUTsforASI1(L3, E R3) G MultipleDOUTsforASI1(L4, E R4) I GeneralPurposeOutput(via E(1) E E E Reg) F SingleDINforASI1(All E,D(2) Channels) F SingleDINforASI2 E,D F SingleDINforASI3 H MultipleDINsforASI1(L1, E R1) H MultipleDINsforASI1(L2, E R2) H MultipleDINsforASI1(L3, E E R3) H MultipleDINsforASI1(L4, E E R4) J DigitalMicData E E E (1) E:Thepinisexclusivelyusedforthisfunction,nootherfunctioncanbeimplementedwiththesamepin(suchasifDOUT1hasbeen allocatedforGeneralPurposeOutput,itcannotbeusedastheINT1outputatthesametime) (2) D:DefaultFunction Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table8.MultifunctionPinAssignmentsforPinsMCLK,GPIO5,WCLK1,BCLK1,DIN1,DOUT1,WCLK2, BCLK2,DIN2,andDOUT2(continued) 1 2 3 4 5 6 7 8 9 10 PinFunction MCLK GPIO5 WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2 K InputtoPLL_CLKIN S(3),D S(4) S S(4) L InputtoADC_CLKIN S(3),D S S(4) S(4) M InputtoDAC_CLKIN S(3),D S S(4) S(4) N InputtoCDIV_CLKIN S(3),D S S S S O InputtoLFR_CLKIN S(3),D S S S S S P InputtoHF_CLK S(3) Q InputtoREF_1MHz_CLK S(3) R GeneralPurposeInput(via E E E E E Reg) S ISRInterruptforminiDSP E (viaReg) T WCLKOutputforASI1 E U WCLKInputforASI1 S,D V BCLKOutputforASI1 E W BCLKInputforASI1 S(4),D X WCLKOutputforASI2 E Y WCLKInputforASI2 S,D Z BCLKOutputforASI2 E AA BCLKInputforASI2 S(4),D BB WCLKOutputforASI3 CC WCLKInputforASI3 DD BCLKOutputforASI3 EE BCLKInputforASI3 (3) S(3):TheMCLKpincouldbechosentodrivethePLL,ADCClock,DACClock,CDIVClock,LFRClock,HFClock,andREF_1MHz_CLK inputssimultaneously (4) S(4):TheBCLK1orBCLK2pinscouldbechosentodrivethePLL,ADCClock,DACClock,andaudiointerfacebitclockinputs simultaneously Table9.MultifunctionPinAssignmentsforPinsWCLK3,BCLK3,DIN3,DOUT3,GPIO1,GPIO2,GPO1, I2C_ADDR_SCL,GPIO6,GPIO3,andGPIO4 11 12 13 14 15 16 17 18 19 20 21 PinFunction WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ I2C_ADD GPIO6 GPIO3 GPIO4 MISO(1) R_SCL A INT1Output E E E B INT2Output E E E D CLOCKOUTOutput E E E E ADC_MOD_CLOCK E E E E E E E Output F SingleDOUTforASI1 E E (AllChannels) F SingleDOUTforASI2 F SingleDOUTforASI3 E,D G MultipleDOUTsfor ASI1(L1,R1) G MultipleDOUTsfor E E E ASI1(L2,R2) G MultipleDOUTsfor E E E E E ASI1(L3,R3) (1) GPO1canonlybeutilizedforfunctionsdefinedinthistablewhenpartutilizesI2Cforcontrol.InSPImode,thispinservesasMISO. 36 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table9.MultifunctionPinAssignmentsforPinsWCLK3,BCLK3,DIN3,DOUT3,GPIO1,GPIO2,GPO1, I2C_ADDR_SCL,GPIO6,GPIO3,andGPIO4(continued) 11 12 13 14 15 16 17 18 19 20 21 PinFunction WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ I2C_ADD GPIO6 GPIO3 GPIO4 MISO(1) R_SCL G MultipleDOUTsfor E E E E ASI1(L4,R4) I GeneralPurpose E(2) E E E E E Output(viaReg) F SingleDINforASI1 E (AllChannels) F SingleDINforASI2 E F SingleDINforASI3 E,D E H MultipleDINsforASI1 (L1,R1) H MultipleDINsforASI1 E E E (L2,R2) H MultipleDINsforASI1 E E E E E (L3,R3) H MultipleDINsforASI1 E E E E (L4,R4) J DigitalMicData E E E E E E E E K InputtoPLL_CLKIN S(3) S(3) S(3) S(3) S(3) L InputtoADC_CLKIN S(3) S(3) S(3) S(3) S(3) M InputtoDAC_CLKIN S(3) S(3) S(3) S(3) S(3) N InputtoCDIV_CLKIN S S O InputtoLFR_CLKIN S S S S S S P InputtoHF_CLK Q Inputto REF_1MHz_CLK R GeneralPurpose E E E E E E E Input(viaReg) S ISRInterruptfor E E E miniDSP(viaReg) T WCLKOutputfor E E ASI1 U WCLKInputforASI1 E V BCLKOutputforASI1 E W BCLKInputforASI1 E X WCLKOutputfor E ASI2 Y WCLKInputforASI2 E Z BCLKOutputforASI2 E AA BCLKInputforASI2 E BB WCLKOutputfor E E ASI3 CC WCLKInputforASI3 S,D(4) E DD BCLKOutputforASI3 E E EE BCLKInputforASI3 S,D E FF ADCBCLKInputfor E E E E E ASI1 (2) E:Thepinisexclusivelyusedforthisfunction,nootherfunctioncanbeimplementedwiththesamepin(suchasifWCLK3hasbeen allocatedforGeneralPurposeOutput,itcannotbeusedastheASI3WCLKoutputatthesametime) (3) S(4):TheGPIO1,GPIO2,GPIO3,orGPIO6pinscouldbechosentodrivethePLL,ADCClock,andDACClockinputssimultaneously (4) D:DefaultFunction Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table9.MultifunctionPinAssignmentsforPinsWCLK3,BCLK3,DIN3,DOUT3,GPIO1,GPIO2,GPO1, I2C_ADDR_SCL,GPIO6,GPIO3,andGPIO4(continued) 11 12 13 14 15 16 17 18 19 20 21 PinFunction WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/ I2C_ADD GPIO6 GPIO3 GPIO4 MISO(1) R_SCL GG ADCWCLKInputfor E E E E E ASI1 HH ADCBCLKOutputfor E E ASI1 II ADCWCLKOutput E E forASI1 JJ ADCBCLKInputfor E E E E E ASI2 KK ADCWCLKInputfor E E E E E ASI2 LL ADCBCLKOutputfor E E ASI2 MM ADCWCLKOutput E E forASI2 NN ADCBCLKInputfor E E E E E ASI3 OO ADCWCLKInputfor E E E E E ASI3 PP ADCBCLKOutputfor E E ASI3 QQ ADCWCLKOutput E E forASI3 RR BitBangInput E E E E E SS BitBangOutput E E E E E 38 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Analog Audio I/O P1_R45_D1=Power -P112_, R-62,3 0_dDB[4:3] P1_R48_D[6:4]=GainSPKP IN1L-B MAL P1_R45_D7 Class-D LOL P1_R46_D[6:0] Speaker Amp L IN1L 10/20/40KP1_R52_D[7:6] 20K IN1L -78dB to 0dB RIGPH1_TR_C45H__DIN2 6d,B 12, 18, 24, 30 SPKM P1_R46_D[6:0] IN2L 10/20/40KP1_R52_D[5:4] IN1L P1_R17_D3=Power P-71_8RdB4 7t_oD 0[d6B:0] IN3L 10/20/40KP1_R52_D[3:2] P1_R17_D5 P1_R18_D[5:0] MixeLre fAtmp MAL LOR P1_R47_D[6:0] IN4L 20K P1_R53_D5 -3P61d_BR 1to8 _0DdB[5:0] MAR P1_R45_D6 0 to +47.5 dB IN1R10/20/40KP1_R52_D[1:0] P P1_R59 IINN32RR1100//2200//4400KKPP11__RR5544__DD[[35::24]] M MiLce PftGA Left ADC Left DAC PM MLDAALCP PP11__RR2277__DD75 AHmeaPPpd11lipf__iheRRor23 nL71ee__fDDt1[5=:P0]o=wGeari nHPL Left Channel Input Options: LOL-B1P1_R28_D[6:0] -6dB to14dB IN4R 20K P1_R53_D4 Single Ended: IN1L or IN2L or IN3L or IN1R or IN4L -78dB to 0dB P1_R28_D[6:0] 10/20/40KP1_R54_D[7:6] Differential: IN2L(P)and IN2R(M) or IN3L(P)and IN3R(M) or IN4L(P)and IN4R(M) MAL P1_R23_D7 P1_R22_D1=Power 10/20/40KP1_R54_D[1:0] IN1L-BP1_R23_D[4:3] Lineout LOL CCMM21LL NPPGGotAAe (IInnFppouur ttA ==ll +0In 6dp BduB tsfo ftroo rS MDiniigcff leePrdGe nEAtni)a:dl eIdnp Iunpt uwti twh itRhI NR=I N1=0K 10K RLDDAACCMP PP11__RR2222__DD57 ALemftplifier 10/20/40CCKMMP121RR_R57_D[1:0] CM PPPPGGGGAAAA IIIInnnnppppuuuutttt ==== ---0616 d 2 ddB BdB Bf off oorfr orD rSD iSfiinffeifgnerlgereelndent ditEai aEln lI dnnInedppdeuu dtI t nw Iwpniuptihttuh twR RwiINtIhNi=t= h R2 4RI0N0KI=NK =2 04K0K P-718_dRB3 t8o_ 0Dd[6B:0] LOL-BP-7218_dPRB13 _6toR_ D306d[6B_:D0][6:0] PP11__RR4400__DD[75=:P0]o=wGeari nR RERCEECPCP P IN1L P1_R38_D[6:0] LDACP P1_R42_D6 1Receiver 10/20/40KP1_R57_D[7:6] Right Channel Input Options: LDACM P1_R42_D5 A-6mdbp litfoie +r29dB RECM IN1R P1_R39_D[6:0] Single Ended: IN1R or IN2R or IN3R or IN2L or IN4R LOR-B2P1_R37_D[6:0] 2 IN4L 20K P1_R56_D4 Differential: IN1R (P) and IN1L(M) or IN3R(P)and IN3L (M) P-17_8Rd3B9 t_oD 0[6d:B0] -78dB to 0dB PP11__RR4410__DD[65=:P0]o=wGeari nR RECECMM IN3L10/20/40KP1_R57_D[3:2] or IN4R(P)and IN4L (M) P1_R37_D[6:0] IN1L10/20/40KP1_R57_D[5:4] M 0 toP 1+_4R76.50 dB LOLP1_R22_D2 P1_R22_D0=Power IN2L10/20/40KP1_R55_D[1:0] MRiicg hPtGA RightADC RightDAC M RMDAARCM P1P_1R_2R32_2D_6D6 ALimnepoliufiter LOR P P Right IN4R 20K P1_R56_D5 IN1R-BP1_R23_D[1:0] IN3R 10/20/40KP1_R55_D[3:2] -3P61d_ Rto1 09d_BDP[51:_0R]19_D[5:0] P1_R17_D2=Power P-718_dRB2t9o_ D0d[6B:0] IN2R 10/20/40KP1_R55_D[5:4] P1_R17_D4 IN1R MixReirg Ahtmp MAR LLDOARC-BM1P1_PR12_9R_2D7[_6D:02] HeaPPd11p__hRRon23e72__DD0[5=:0P]o=wGeari nHPR IN1R 10/20/40KP1_R55_D[7:6] 20K RDACP P1_R27_D4 A-6mdBpl itfoie +r 1R4igdhBt MAR P1_R27_D6 IN1R -12, -6, 0dB P1_R23_D[1:0] IN1R-B Figure25. AnalogRoutingDiagram FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuideSLAU475. Analog Low Power Bypass The TLV320AIC3263 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation; this supports low-power operation during analog-bypass mode. In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog inputstotheamplifier,whichoutputsonRECPandRECM. ADC Bypass Using Mixer Amplifiers Inadditiontothelow-powerbypassmode,thereisabypassmodethatusestheprogrammablegainamplifiersof the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified and routed to the line, speaker, or headphone outputs, fully bypassing the ADC and DAC. To enable this mode, themixeramplifiersarepoweredonviasoftwarecommand. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Headphone Outputs The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single- ended DC-coupled headphone configurations. An integral charge pump generates the negative supply required to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is made equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in dc- coupled(groundcenteredmode)eliminatestheneedforlargedc-blockingcapacitors. HPL HPR HPVSS_SENSE Figure26. TLV320AIC3263Ground-CenteredHeadphoneOutput Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking capacitors. Stereo Line Outputs The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output common mode of line level drivers can be configured to equal the analog input common-mode setting, either 0.75V or 0.9V. The line-level drivers can drive out a mixed combination of DACsignalandattenuatedADCPGAsignal,andsignalmixingisregister-programmable. Differential Receiver Output The differential receiver amplifier output spans the RECP and RECM pins and can drive a 32Ω receiver driver. With output common-mode setting of 1.65V and RECVDD_33 supply at 3.3V, the receiver driver can drive up to a 1Vrms output signal. With the RECVDD_33 supply at 3.3V, the receiver driver can deliver greater than 128mW into a 32Ω BTL load. If desired, the RECVDD_33 supply can be set to 1.8V, at which the driver can deliver about 40mWintothe32Ω BTLload. Class-D Speaker Output The integrated Class-D speaker driver (SPKP/SPKN) is capable of driving an 8Ω differential load. The speaker driver can be powered directly from the power supply (2.7V to 5.5V) on the SVDD pin, however the voltage (includingspikevoltage)mustbelimitedbelowtheAbsoluteMaximumVoltageof6.0V. The speaker driver is capable of supplying 720 mW at 10% THD+N with a 3.6-V power supply and 1.40W at 10% THD+N with a 5.0V power supply. Separate left and right channels can be sent to the Class-D driver through the Lineout signal path, or from the mixer amplifiers in the ADC bypass. Additionally, the analog mixer beforetheSpeakeramplifiercansumtheleftandrightaudiosignalsformonophonicplayback. ADC / Digital Microphone Interface The TLV320AIC3263 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter and a programmable miniDSP. The ADC supports sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo recording path can be powered up one channel at a time, to support the case where only mono record capability isrequired. 40 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 The ADC path of the TLV320AIC3263 features a large set of options for signal conditioning as well as signal routing: • 2ADCs • 8analoginputswhichcanbemixedand/ormultiplexedinsingle-endedand/ordifferentialconfiguration • 2programmablegainamplifiers(PGA)witharangeof0to+47.5dB • 2mixeramplifiersforanalogbypass • 2lowpoweranalogbypasschannels • Finegainadjustofdigitalchannelswith0.1dBstepsize • Digitalvolumecontrolwitharangeof-12to+20dB • Mutefunction • Automaticgaincontrol(AGC) InadditiontothestandardsetofADCfeaturestheTLV320AIC3263alsooffersthefollowingspecialfunctions: • Builtinmicrophonebiases • Four-channeldigitalmicrophoneinterface – Allows4totalmicrophones – Upto4digitalmicrophones – Upto2analogmicrophones • Channel-to-channelphaseadjustment • Fastchargeofac-couplingcapacitors • Antithump • Adaptivefiltermode ADCProcessingBlocks—Overview The TLV320AIC3263 ADC channel includes a built-in digital decimation filter to process the oversampled data from the to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay and sampling rate. ADC Processing Blocks The TLV320AIC3263 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signalprocessingtheymayuseandwhichdecimationfilterisapplied. The choice between these processing blocks is part of the PowerTune strategy to balance power conservation and signal-processing flexibility. Decreasing the use of signal-processing capabilities reduces the power consumed by the device. Table 10 gives an overview of the available processing blocks of the ADC channel and theirproperties.TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption. Thesignalprocessingblocksavailableare: • First-orderIIR • Scalablenumberofbiquadfilters • Variable-tapFIRfilter • AGC Theprocessingblocksaretunedforcommoncasesandcanachievehighanti-aliasfilteringorlow-groupdelayin combination with various signal processing effects such as audio effects and frequency shaping. The available firstorderIIR,BiQuadandFIRfiltershavefullyuserprogrammablecoefficients. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table10.ADCProcessingBlocks Processing Channel Decimation 1stOrder Number FIR RequiredAOSR Resource Blocks Filter IIRAvailable BiQuads Value Class PRB_R1(1) Stereo A Yes 0 No 128,64,32,16,8,4 7 PRB_R2 Stereo A Yes 2 No 128,64,32,16,8,4 8 PRB_R3 Stereo A Yes 0 17-Tap 128,64,32,16,8,4 8 PRB_R4 Left A Yes 0 No 128,64,32,16,8,4 4 PRB_R5 Left A Yes 5 No 128,64,32,16,8,4 5 PRB_R6 Left A Yes 0 25-Tap 128,64,32,16,8,4 5 PRB_R7 Stereo B Yes 0 No 64,32,16,8,4,2 4 PRB_R8 Stereo B Yes 3 No 64,32,16,8,4,2 5 PRB_R9 Stereo B Yes 0 17-Tap 64,32,16,8,4,2 5 PRB_R10 Left B Yes 0 No 64,32,16,8,4,2 2 PRB_R11 Left B Yes 3 No 64,32,16,8,4,2 3 PRB_R12 Left B Yes 0 17-Tap 64,32,16,8,4,2 3 PRB_R13 Stereo C Yes 0 No 32,16,8,4,2,1 4 PRB_R14 Stereo C Yes 5 No 32,16,8,4,2,1 5 PRB_R15 Stereo C Yes 0 25-Tap 32,16,8,4,2,1 5 PRB_R16 Left C Yes 0 No 32,16,8,4,2,1 2 PRB_R17 Left C Yes 5 No 32,16,8,4,2,1 3 PRB_R18 Left C Yes 0 25-Tap 32,16,8,4,2,1 3 PRB_R19 Stereo A Yes 5 No 128,64,32,16,8,4 9 PRB_R20 Stereo A Yes 0 25-Tap 128,64,32,16,8,4 9 (1) Default FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. 42 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 DAC The TLV320AIC3263 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3263 allows the system designer to program the oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and loweroversamplingratiosforhigherinputdatarates. The TLV320AIC3263 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on requiredfrequencyresponse,groupdelayandsamplingrate. TheDACpathoftheTLV320AIC3263featuresmanyoptionsforsignalconditioningandsignalrouting: • 2headphoneamplifiers – Usableinsingle-endedstereoordifferentialmonomode – Analogvolumesettingwitharangeof-6to+14dB • 2line-outamplifiers – Usableinsingle-endedstereoordifferentialmonomode • Class-Dspeakeramplifier – Usablewithleft,right,ormonophonicmixmodes – Analogvolumecontrolwithasettingsof+6,+12,+18,+24,and+30dB • 1Receiveramplifier – Usableinmonodifferentialmode – Analogvolumesettingwitharangeof-6to+29dB • Digitalvolumecontrolwitharangeof-63.5to+24dB • Mutefunction • Dynamicrangecompression(DRC) InadditiontothestandardsetofDACfeaturestheTLV320AIC3263alsooffersthefollowingspecialfeatures: • Builtinsinewavegeneration(beepgenerator) • Digitalautomute • Adaptivefiltermode • AsynchronousSampleRateConversion DACProcessingBlocks—Overview The TLV320AIC3263 implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may useandwhichinterpolationfilterisapplied. The choice between these processing blocks is part of the PowerTune strategy balancing power conservation and signal processing flexibility. Less signal processing capability will result in less power consumed by the device. The Table 11 gives an overview over all available processing blocks of the DAC channel and their properties.TheResourceClassColumn(RC)givesanapproximateindicationofpowerconsumption. Thesignalprocessingblocksavailableare: • First-orderIIR • Scalablenumberofbiquadfilters • 3D– Effect • BeepGenerator The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-orderIIRandbiquadfiltershavefullyuser-programmablecoefficients. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table11.Overview– DACPredefinedProcessingBlocks Processing Interpolation Channel 1stOrder Num.of DRC 3D Beep RCClass BlockNo. Filter IIRAvailable Biquads Generator PRB_P1(1) A Stereo No 2 No No No 8 PRB_P2 A Stereo Yes 6 Yes No No 12 PRB_P3 A Stereo Yes 6 No No No 10 PRB_P4 A Left No 2 No No No 4 PRB_P5 A Left Yes 6 Yes No No 6 PRB_P6 A Left Yes 6 No No No 5 PRB_P7 B Stereo Yes 0 No No No 6 PRB_P8 B Stereo No 4 Yes No No 8 PRB_P9 B Stereo No 4 No No No 7 PRB_P10 B Stereo Yes 6 Yes No No 10 PRB_P11 B Stereo Yes 6 No No No 8 PRB_P12 B Left Yes 0 No No No 3 PRB_P13 B Left No 4 Yes No No 5 PRB_P14 B Left No 4 No No No 4 PRB_P15 B Left Yes 6 Yes No No 5 PRB_P16 B Left Yes 6 No No No 4 PRB_P17 C Stereo Yes 0 No No No 3 PRB_P18 C Stereo Yes 4 Yes No No 7 PRB_P19 C Stereo Yes 4 No No No 5 PRB_P20 C Left Yes 0 No No No 2 PRB_P21 C Left Yes 4 Yes No No 4 PRB_P22 C Left Yes 4 No No No 3 PRB_P23 A Stereo No 1 No Yes No 8 PRB_P24 A Stereo Yes 3 Yes Yes No 12 PRB_P25 A Stereo Yes 1 Yes Yes Yes 12 PRB_P26 D Stereo No 0 No No No 1 PRB_P27 A Stereo Yes 3 Yes Yes Yes 13 (1) Default FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. PowerTune The TLV320AIC3263 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance, ortoanoperatingpointbetweenthetwoextremestobestfittheapplication. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. Clock Generation and PLL To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required internal clock signals at very low power consumption. For cases where such master clocks are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL isusedtogeneratesomeotherclockthatisonlyusedoutsidetheTLV320AIC3263. 44 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 The TLV320AIC3263 supports a wide range of options for generating clocks for the ADC and DAC sections as well as interface and other control blocks. The clocks for ADC and DAC require source reference clocks, and these clocks can be from a single source or from two separate sources. They can be provided on a variety of device pins such as MCLK, BCLK1, BCLK2, BCLK3, or GPIOx pins. The clocks, ADC_CLKIN and DAC_CLKIN, can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference clocks on MCLK, BCLK1, BCLK2, BCLK3, or GPIOx, the codec also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocksrequiredforADC,DACandtheminiDSPsections. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Interfaces ControlInterfaces The TLV320AIC3263 control interface supports SPI or I2C communication protocols. For SPI, the SPI_SELECT pin should be tied high; for I2C, SPI_SELECT should be tied low. It is not recommended to change the state of SPI_SELECTduringdeviceoperation. I2CControl The TLV320AIC3263 supports the I2C control protocol, and will respond by default (I2C_ADDR_SCLK grounded) to the 7-bit I2C address of 0011000. With the one I2C address pin, I2C_ADDR_SCLK, the device can be configured to respond to one of two 7-bit I2C addresses, 0011000 or 0011001. The full 8-bit I2C address can be calculatedas: 8-BitI2CAddress="001100"+I2C_ADDR_SCLK+R/W Example: to write to the TLV320AIC3263 with I2C_ADDR_SCLK = 1 the 8-Bit I2C Address is "001100" + I2C_ADDR_SCLK+R/W="00110010"=0x32 I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. SPIControl In the SPI control mode, the TLV320AIC3263 uses the pins SCL as SS, I2C_ADDR_SCLK as SCLK, GPO1 as MISO, SDA as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3263) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). AsthebyteshiftsinontheMOSIpin,abyteshiftsoutontheMISOpintothemastershiftregister. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. DigitalAudioInterfaces The TLV320AIC3263 features three digital audio data serial interfaces, or audio buses. These three interfaces can be run simultaneously, thereby enabling reception and transmission of digital audio from/to three separate devices. A common example of this scenario would be individual connections to an application processor, a communication baseband processor, and a Bluetooth chipset. By utilizing the TLV320AIC3263 as the center of the audio processing in a portable audio system, mixing of voice and music audio is greatly simplified. In addition, the miniDSP can be utilized to greatly enhance the portable device experience by providing advanced audio processing to both communication and media audio streams simultaneously. In addition to the three simultaneousdigitalaudiointerfaces,afourthsetofdigitalaudiopinscanbemuxedintoAudioSerialInterface1. In other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3263, with up to threeofthese4-wirebusesreceivingandsendingdigitalaudiodata. 46 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Audio Serial Interfaces AUDIO SERIALINTERFACE 1 AUDIO SERIALINTERFACE 2 AUDIO SERIALINTERFACE 3 WCLK BCLK DIN DOUT WCLK BCLK DIN DOUT WCLK BCLK DIN DOUT WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2 WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPIO6 GPIO5 Figure27. TypicalMultipleConnectionstoThreeAudioSerialInterfaces Each audio bus on the TLV320AIC3263 is very flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a systemdirectly. Each of the three audio buses of the TLV320AIC3263 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-wire mode, the ADC and DAC pathscanoperatebasedonseparatewordclocks. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TLV320AIC3263s may share the same audio bus. When configuring an audio interface forsix-wiremode,theADCandDACpathscanoperatebasedonseparatebitclocks. The TLV320AIC3263 also includes a feature to offset the position of start of data transfer with respect to the word-clock.Thisoffsetcanbecontrolledintermsofnumberofbit-clocks. The TLV320AIC3263 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audiointerfacechosen. The TLV320AIC3263 further includes programmability to 3-state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode,thepinsassociatedwiththeinterfaceareputintoa3-stateoutputcondition. By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3263, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However,italsosupportsafeaturewhenboththewordclocksandbit-clockscanbeactiveevenwhenthecodec ispowereddown.ThisisusefulwhenusingtheTDMmodewithmultiplecodecsonthesamebus,orwhenword- clockorbit-clocksareusedinthesystemasgeneral-purposeclocks. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com miniDSP The TLV320AIC3263 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each miniDSP can run up to 1145 instructions on every audio sample at a 48kHz sample rate. The two cores can run fully synchronized and can exchange data. The TLV320AIC3263 features the ability to process a multitude of algorithms simultaneously. For example, the miniDSPs enable simultaneous noise cancellation, acoustic echo cancellation, sidetone, equalization filtering, dynamic range compression, conversation recording, user-interface sound mixing, and other voice enhancement processing at voice-band sampling rates (such as 8kHz) and high- defintion voice sampling rates (such as 16kHz). The TLV320AIC3263 miniDSPs also enable advanced DSP soundenhancementalgorithmsforanenhancedmediaexperienceonaportableaudiodevice. Software Software development for the TLV320AIC3263 is supported through TI's comprehensive PurePath Studio Development Environment. A powerful, easy-to-use tool designed specifically to simplify software development on the TLV320AIC3xxx miniDSP audio platform. The Graphical Development Environment consists of a library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected together.TheDSPcodecanthenbeassembledfromthegraphicalsignalflowwiththeclickofamouse. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. AsynchronousSampleRateConversion(ASRC) For playing back audio/speech signals at various sampling rates, AIC3263 provides an efficient asynchronous sampling rate conversion with the combination of a dedicated ASRC coefficient calculator and the DAC miniDSP engine. The coefficient calculator estimates the audio/speech data input rate versus the DAC playback rate and feeds the calculated coefficients to the miniDSP, with which it converts the audio/speech data to the DAC playback rate. The whole process can be configured automatically without the need of any input sampling rate related information. The input sampling rates as well as the DAC playback rate are not limited to the typical audio/speechsamplingrates.Areliableandefficienthandshakingisinvolvedbetweenthe. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. Power Supply The TLV320AIC3263 integrates a large amount of digital and analog functionality, and each of these blocks can be powered separately to enable the system to select appropriate power supplies for desired performance and power consumption. The device has separate power domains for digital IO (including three separate digital IO supplies for three separate IOVDD domains), digital core, analog core, analog input, receiver driver, charge- pump input, headphone driver, and speaker driver. If desired, all of the supplies (except for the battery-direct supply for speaker driver and microphone bias) can be connected together and be supplied from one source in the range of 1.65 to 1.95V. Individually, each of the three IOVDD voltages can be supplied in the range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V to 1.95V. The analog core voltages (AVDD1_18, AVDD2_18, AVDD4_18, and AVDD_18) can range from 1.5V to 1.95V. The receiver driver supply (RECVDD_33) voltages can range from 1.65V to 3.6V. The charge-pump input voltage (CPVDD_18) can range from 1.26V to 1.95V, and the headphone driver supply (HVDD_18) voltage can range from 1.5V to 1.95V. The speaker driver voltage (SVDD and SPK_V) and microphone bias voltage (MICBIAS_VDD,whichistheninternallyfilteredforoptimalperformance)canrangefrom2.7Vto5.5V. FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. Device Special Functions Thefollowingspecialfunctionsareavailabletosupportadvancedsystemrequirements: • SARADC • Headsetdetection • Interruptgeneration • Flexiblepinmultiplexing FormoredetailedinformationseetheTLV320AIC3263ApplicationReferenceGuide. 48 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Register Map Summary Table12.SummaryofRegisterMap Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 0 0 0x00 0x00 0x00 PageSelectRegister 0 0 1 0x00 0x00 0x01 SoftwareResetRegister 0 0 2-3 0x00 0x00 0x02- ReservedRegisters 0x03 0 0 4 0x00 0x00 0x04 ClockControlRegister1,ClockInputMultiplexers 0 0 5 0x00 0x00 0x05 ClockControlRegister2,PLLInputMultiplexer 0 0 6 0x00 0x00 0x06 ClockControlRegister3,PLLPandRValues 0 0 7 0x00 0x00 0x07 ClockControlRegister4,PLLJValue 0 0 8 0x00 0x00 0x08 ClockControlRegister5,PLLDValues(MSB) 0 0 9 0x00 0x00 0x09 ClockControlRegister6,PLLDValues(LSB) 0 0 10 0x00 0x00 0x0A ClockControlRegister7,PLL_CLKINDivider 0 0 11 0x00 0x00 0x0B ClockControlRegister8,NDACDividerValues 0 0 12 0x00 0x00 0x0C ClockControlRegister9,MDACDividerValues 0 0 13 0x00 0x00 0x0D DACOSRControlRegister1,MSBValue 0 0 14 0x00 0x00 0x0E DACOSRControlRegister2,LSBValue 0 0 15-17 0x00 0x00 0x0F- ReservedRegisters 0x11 0 0 18 0x00 0x00 0x12 ClockControlRegister10,NADCValues 0 0 19 0x00 0x00 0x13 ClockControlRegister11,MADCValues 0 0 20 0x00 0x00 0x14 ADCOversampling(AOSR)Register 0 0 21 0x00 0x00 0x15 CLKOUTMUX 0 0 22 0x00 0x00 0x16 ClockControlRegister12,CLKOUTMDividerValue 0 0 23 0x00 0x00 0x17 Timerclock 0 0 24 0x00 0x00 0x18 LowFrequencyClockGenerationControl 0 0 25 0x00 0x00 0x19 HighFrequencyClockGenerationControl1 0 0 26 0x00 0x00 0x1A HighFrequencyClockGenerationControl2 0 0 27 0x00 0x00 0x1B HighFrequencyClockGenerationControl3 0 0 28 0x00 0x00 0x1C HighFrequencyClockGenerationControl4 0 0 29 0x00 0x00 0x1D HighFrequencyClockTrimControl1 0 0 30 0x00 0x00 0x1E HighFrequencyClockTrimControl2 0 0 31 0x00 0x00 0x1F HighFrequencyClockTrimControl3 0 0 32 0x00 0x00 0x20 HighFrequencyClockTrimControl4 0 0 33-35 0x00 0x00 0x21- ReservedRegisters 0x23 0 0 36 0x00 0x00 0x24 ADCFlagRegister 0 0 37 0x00 0x00 0x25 DACFlagRegister 0 0 38 0x00 0x00 0x26 DACFlagRegister 0 0 39-41 0x00 0x00 0x27- ReservedRegisters 0x29 0 0 42 0x00 0x00 0x2A StickyFlagRegister1 0 0 43 0x00 0x00 0x2B InterruptFlagRegister1 0 0 44 0x00 0x00 0x2C StickyFlagRegister2 0 0 45 0x00 0x00 0x2D StickyFlagRegister3 0 0 46 0x00 0x00 0x2E InterruptFlagRegister2 0 0 47 0x00 0x00 0x2F InterruptFlagRegister3 Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 0 48 0x00 0x00 0x30 INT1InterruptControl 0 0 49 0x00 0x00 0x31 INT2InterruptControl 0 0 50 0x00 0x00 0x32 SARControl1 0 0 51 0x00 0x00 0x33 InterruptFormatControlRegister 0 0 52-59 0x00 0x00 0x34- ReservedRegisters 0x3B 0 0 60 0x00 0x00 0x3C DACProcessingBlockandminiDSPPowerControl 0 0 61 0x00 0x00 0x3D ADCProcessingBlockControl 0 0 62 0x00 0x00 0x3E ReservedRegister 0 0 63 0x00 0x00 0x3F PrimaryDACPowerandSoft-SteppingControl 0 0 64 0x00 0x00 0x40 PrimaryDACMasterVolumeConfiguration 0 0 65 0x00 0x00 0x41 PrimaryDACLeftVolumeControlSetting 0 0 66 0x00 0x00 0x42 PrimaryDACRightVolumeControlSetting 0 0 67 0x00 0x00 0x43 HeadsetDetection 0 0 68 0x00 0x00 0x44 DRCControlRegister1 0 0 69 0x00 0x00 0x45 DRCControlRegister2 0 0 70 0x00 0x00 0x46 DRCControlRegister3 0 0 71 0x00 0x00 0x47 BeepGeneratorRegister1 0 0 72 0x00 0x00 0x48 BeepGeneratorRegister2 0 0 73 0x00 0x00 0x49 BeepGeneratorRegister3 0 0 74 0x00 0x00 0x4A BeepGeneratorRegister4 0 0 75 0x00 0x00 0x4B BeepGeneratorRegister5 0 0 76 0x00 0x00 0x4C BeepSin(x)MSB 0 0 77 0x00 0x00 0x4D BeepSin(x)LSB 0 0 78 0x00 0x00 0x4E BeepCos(x)MSB 0 0 79 0x00 0x00 0x4F BeepCos(x)LSB 0 0 80 0x00 0x00 0x50 ReservedRegister 0 0 81 0x00 0x00 0x51 ADCChannelPowerControl 0 0 82 0x00 0x00 0x52 ADCFineGainVolumeControl 0 0 83 0x00 0x00 0x53 LeftADCVolumeControl 0 0 84 0x00 0x00 0x54 RightADCVolumeControl 0 0 85 0x00 0x00 0x55 ADCPhaseControl 0 0 86 0x00 0x00 0x56 LeftAGCControl1 0 0 87 0x00 0x00 0x57 LeftAGCControl2 0 0 88 0x00 0x00 0x58 LeftAGCControl3 0 0 89 0x00 0x00 0x59 LeftAGCAttackTime 0 0 90 0x00 0x00 0x5A LeftAGCDecayTime 0 0 91 0x00 0x00 0x5B LeftAGCNoiseDebounce 0 0 92 0x00 0x00 0x5C LeftAGCSignalDebounce 0 0 93 0x00 0x00 0x5D LeftAGCGain 0 0 94 0x00 0x00 0x5E RightAGCControl1 0 0 95 0x00 0x00 0x5F RightAGCControl2 0 0 96 0x00 0x00 0x60 RightAGCControl3 0 0 97 0x00 0x00 0x61 RightAGCAttackTime 0 0 98 0x00 0x00 0x62 RightAGCDecayTime 0 0 99 0x00 0x00 0x63 RightAGCNoiseDebounce 50 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 0 100 0x00 0x00 0x64 RightAGCSignalDebounce 0 0 101 0x00 0x00 0x65 RightAGCGain 0 0 102 0x00 0x00 0x66 ADCDCMeasurementControlRegister1 0 0 103 0x00 0x00 0x67 ADCDCMeasurementControlRegister2 0 0 104 0x00 0x00 0x68 LeftChannelDCMeasurementOutputRegister1(MSBByte) 0 0 105 0x00 0x00 0x69 LeftChannelDCMeasurementOutputRegister2(MiddleByte) 0 0 106 0x00 0x00 0x6A LeftChannelDCMeasurementOutputRegister3(LSBByte) 0 0 107 0x00 0x00 0x6B RightChannelDCMeasurementOutputRegister1(MSBByte) 0 0 108 0x00 0x00 0x6C RightChannelDCMeasurementOutputRegister2(MiddleByte) 0 0 109 0x00 0x00 0x6D RightChannelDCMeasurementOutputRegister3(LSBByte) 0 0 110-111 0x00 0x00 0x6E- ReservedRegisters 0x6F 0 0 112 0x00 0x00 0x70 DigitalMicrophone2Control 0 0 113-114 0x00 0x00 0x71- ReservedRegisters 0x72 0 0 115 0x00 0x00 0x73 I2CInterfaceMiscellaneousControl 0 0 116-118 0x00 0x00 0x74- ReservedRegisters 0x76 0 0 119 0x00 0x00 0x77 miniDSPControlRegister1,RegisterAccessControl 0 0 120 0x00 0x00 0x78 miniDSPControlRegister2,RegisterAccessControl 0 0 121 0x00 0x00 0x79 miniDSPControlRegister3,RegisterAccessControl 0 0 122-126 0x00 0x00 0x7A- ReservedRegisters 0x7E 0 0 127 0x00 0x00 0x7F BookSelectionRegister 0 1 0 0x00 0x01 0x00 PageSelectRegister 0 1 1 0x00 0x01 0x01 PowerConfigurationRegister 0 1 2 0x00 0x01 0x02 ReservedRegister 0 1 3 0x00 0x01 0x03 LeftDACPowerTuneConfigurationRegister 0 1 4 0x00 0x01 0x04 RightDACPowerTuneConfigurationRegister 0 1 5-7 0x00 0x01 0x05- ReservedRegisters 0x07 0 1 8 0x00 0x01 0x08 CommonModeRegister 0 1 9 0x00 0x01 0x09 HeadphoneOutputDriverControl 0 1 10 0x00 0x01 0x0A ReceiverOutputDriverControl 0 1 11 0x00 0x01 0x0B HeadphoneOutputDriverDe-popControl 0 1 12 0x00 0x01 0x0C ReceiverOutputDriverDe-PopControl 0 1 13-16 0x00 0x01 0x0D- ReservedRegisters 0x10 0 1 17 0x00 0x01 0x11 MixerAmplifierControl 0 1 18 0x00 0x01 0x12 LeftADCPGAtoLeftMixerAmplifier(MAL)VolumeControl 0 1 19 0x00 0x01 0x13 RightADCPGAtoRightMixerAmplifier(MAR)VolumeControl 0 1 20-21 0x00 0x01 0x14- ReservedRegisters 0x15 0 1 22 0x00 0x01 0x16 LineoutAmplifierControl1 0 1 23 0x00 0x01 0x17 LineoutAmplifierControl2 0 1 24-26 0x00 0x01 0x18- Reserved 0x1A 0 1 27 0x00 0x01 0x1B HeadphoneAmplifierControl1 Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 1 28 0x00 0x01 0x1C HeadphoneAmplifierControl2 0 1 29 0x00 0x01 0x1D HeadphoneAmplifierControl3 0 1 30 0x00 0x01 0x1E ReservedRegister 0 1 31 0x00 0x01 0x1F HPLDriverVolumeControl 0 1 32 0x00 0x01 0x20 HPRDriverVolumeControl 0 1 33 0x00 0x01 0x21 ChargePumpControl1 0 1 34 0x00 0x01 0x22 ChargePumpControl2 0 1 35 0x00 0x01 0x23 ChargePumpControl3 0 1 36 0x00 0x01 0x24 ReceiverAmplifierControl1 0 1 37 0x00 0x01 0x25 ReceiverAmplifierControl2 0 1 38 0x00 0x01 0x26 ReceiverAmplifierControl3 0 1 39 0x00 0x01 0x27 ReceiverAmplifierControl4 0 1 40 0x00 0x01 0x28 ReceiverAmplifierControl5 0 1 41 0x00 0x01 0x29 ReceiverAmplifierControl6 0 1 42 0x00 0x01 0x2A ReceiverAmplifierControl7 0 1 43-44 0x00 0x01 0x2B- ReservedRegisters 0x2C 0 1 45 0x00 0x01 0x2D SpeakerAmplifierControl1 0 1 46 0x00 0x01 0x2E SpeakerAmplifierControl2 0 1 47 0x00 0x01 0x2F SpeakerAmplifierControl3 0 1 48 0x00 0x01 0x30 SpeakerAmplifierVolumeControls 0 1 49-50 0x00 0x01 0x31- ReservedRegisters 0x32 0 1 51 0x00 0x01 0x33 MicrophoneBiasControl 0 1 52 0x00 0x01 0x34 InputSelect1forLeftMicrophonePGAP-Terminal 0 1 53 0x00 0x01 0x35 InputSelect2forLeftMicrophonePGAP-Terminal 0 1 54 0x00 0x01 0x36 InputSelectforLeftMicrophonePGAM-Terminal 0 1 55 0x00 0x01 0x37 InputSelect1forRightMicrophonePGAP-Terminal 0 1 56 0x00 0x01 0x38 InputSelect2forRightMicrophonePGAP-Terminal 0 1 57 0x00 0x01 0x39 InputSelectforRightMicrophonePGAM-Terminal 0 1 58 0x00 0x01 0x3A InputCommonModeControl 0 1 59 0x00 0x01 0x3B LeftMicrophonePGAControl 0 1 60 0x00 0x01 0x3C RightMicrophonePGAControl 0 1 61 0x00 0x01 0x3D ADCPowerTuneConfigurationRegister 0 1 62 0x00 0x01 0x3E ADCAnalogPGAGainFlagRegister 0 1 63 0x00 0x01 0x3F DACAnalogGainFlagsRegister1 0 1 64 0x00 0x01 0x40 DACAnalogGainFlagsRegister2 0 1 65 0x00 0x01 0x41 AnalogBypassGainFlagsRegister 0 1 66 0x00 0x01 0x42 DriverPower-UpFlagsRegister 0 1 67-118 0x00 0x01 0x43- ReservedRegisters 0x76 0 1 119 0x00 0x01 0x77 HeadsetDetectionTuningRegister1 0 1 120 0x00 0x01 0x78 HeadsetDetectionTuningRegister2 0 1 121 0x00 0x01 0x79 MicrophonePGAPower-UpControlRegister 0 1 122 0x00 0x01 0x7A ReferencePowerupDelayRegister 0 1 123-127 0x00 0x01 0x7B- ReservedRegisters 0x7F 52 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 3 0 0x00 0x03 0x00 PageSelectRegister 0 3 1 0x00 0x03 0x01 ReservedRegister 0 3 2 0x00 0x03 0x02 PrimarySARADCControl 0 3 3 0x00 0x03 0x03 PrimarySARADCConversionMode 0 3 4-5 0x00 0x03 0x04- ReservedRegisters 0x05 0 3 6 0x00 0x03 0x06 SARReferenceControl 0 3 7-8 0x00 0x03 0x07- ReservedRegisters 0x08 0 3 9 0x00 0x03 0x09 SARADCFlagsRegister1 0 3 10 0x00 0x03 0x0A SARADCFlagsRegister2 0 3 11-12 0x00 0x03 0x0B- ReservedRegisters 0x0C 0 3 13 0x00 0x03 0x0D SARADCBufferModeControl 0 3 14 0x00 0x03 0x0E ReservedRegister 0 3 15 0x00 0x03 0x0F ScanModeTimerControl 0 3 16 0x00 0x03 0x10 ReservedRegister 0 3 17 0x00 0x03 0x11 SARADCClockControl 0 3 18 0x00 0x03 0x12 SARADCBufferModeDataReadControl 0 3 19 0x00 0x03 0x13 SARADCMeasurementControl 0 3 20 0x00 0x03 0x14 ReservedRegister 0 3 21 0x00 0x03 0x15 SARADCMeasurementThresholdFlags 0 3 22 0x00 0x03 0x16 IN1LMaxThresholdCheckControl1 0 3 23 0x00 0x03 0x17 IN1LMaxThresholdCheckControl2 0 3 24 0x00 0x03 0x18 IN1LMinThresholdCheckControl1 0 3 25 0x00 0x03 0x19 IN1LMinThresholdCheckControl2 0 3 26 0x00 0x03 0x1A IN1RMaxThresholdCheckControl1 0 3 27 0x00 0x03 0x1B IN1RMaxThresholdCheckControl2 0 3 28 0x00 0x03 0x1C IN1RMinThresholdCheckControl1 0 3 29 0x00 0x03 0x1D IN1RMinThresholdCheckControl2 0 3 30 0x00 0x03 0x1E TEMPMaxThresholdCheckControl1 0 3 31 0x00 0x03 0x1F TEMPMaxThresholdCheckControl2 0 3 32 0x00 0x03 0x20 TEMPMinThresholdCheckControl1 0 3 33 0x00 0x03 0x21 TEMPMinThresholdCheckControl2 0 3 34-53 0x00 0x03 0x22- ReservedRegisters 0x35 0 3 54 0x00 0x03 0x36 IN1LMeasurementData(MSB) 0 3 55 0x00 0x03 0x37 IN1LMeasurementData(LSB) 0 3 56 0x00 0x03 0x38 IN1RMeasurementData(MSB) 0 3 57 0x00 0x03 0x39 IN1RMeasurementData(LSB) 0 3 58 0x00 0x03 0x3A VBATMeasurementData(MSB) 0 3 59 0x00 0x03 0x3B VBATMeasurementData(LSB) 0 3 60-65 0x00 0x03 0x3C- ReservedRegisters 0x41 0 3 66 0x00 0x03 0x42 TEMP1MeasurementData(MSB) 0 3 67 0x00 0x03 0x43 TEMP1MeasurementData(LSB) 0 3 68 0x00 0x03 0x44 TEMP2MeasurementData(MSB) Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 3 69 0x00 0x03 0x45 TEMP2MeasurementData(LSB) 0 3 70-127 0x00 0x03 0x46- ReservedRegisters 0x7F 0 4 0 0x00 0x04 0x00 PageSelectRegister 0 4 1 0x00 0x04 0x01 AudioSerialInterface1,AudioBusFormatControlRegister 0 4 2 0x00 0x04 0x02 AudioSerialInterface1,LeftCh_Offset_1ControlRegister 0 4 3 0x00 0x04 0x03 AudioSerialInterface1,RightCh_Offset_2ControlRegister 0 4 4 0x00 0x04 0x04 AudioSerialInterface1,ChannelSetupRegister 0 4 5 0x00 0x04 0x05 AudioSerialInterface1,ADCAudioBusFormatControlRegister 0 4 6 0x00 0x04 0x06 AudioSerialInterface1,Multi-ChannelSetupRegister2 0 4 7 0x00 0x04 0x07 AudioSerialInterface1,ADCInputControl 0 4 8 0x00 0x04 0x08 AudioSerialInterface1,DACOutputControl 0 4 9 0x00 0x04 0x09 AudioSerialInterface1,ControlRegister9,ADCSlotTristateControl 0 4 10 0x00 0x04 0x0A AudioSerialInterface1,WCLKandBCLKControlRegister 0 4 11 0x00 0x04 0x0B AudioSerialInterface1,BitClockNDividerInputControl 0 4 12 0x00 0x04 0x0C AudioSerialInterface1,BitClockNDivider 0 4 13 0x00 0x04 0x0D AudioSerialInterface1,WordClockNDivider 0 4 14 0x00 0x04 0x0E AudioSerialInterface1,BCLKandWCLKOutput 0 4 15 0x00 0x04 0x0F AudioSerialInterface1,DataOutput 0 4 16 0x00 0x04 0x10 AudioSerialInterface1,ADCWCLKandBCLKControl 0 4 17 0x00 0x04 0x11 AudioSerialInterface2,AudioBusFormatControlRegister 0 4 18 0x00 0x04 0x12 AudioSerialInterface2,DataOffsetControlRegister 0 4 19-20 0x00 0x04 0x13- ReservedRegisters 0x14 0 4 21 0x00 0x04 0x15 AudioSerialInterface2,ADCAudioBusFormatControlRegister 0 4 22 0x00 0x04 0x16 ReservedRegister 0 4 23 0x00 0x04 0x17 AudioSerialInterface2,ADCInputControl 0 4 24 0x00 0x04 0x18 AudioSerialInterface2,DACOutputControl 0 4 25 0x00 0x04 0x19 ReservedRegister 0 4 26 0x00 0x04 0x1A AudioSerialInterface2,WCLKandBCLKControlRegister 0 4 27 0x00 0x04 0x1B AudioSerialInterface2,BitClockNDividerInputControl 0 4 28 0x00 0x04 0x1C AudioSerialInterface2,BitClockNDivider 0 4 29 0x00 0x04 0x1D AudioSerialInterface2,WordClockNDivider 0 4 30 0x00 0x04 0x1E AudioSerialInterface2,BCLKandWCLKOutput 0 4 31 0x00 0x04 0x1F AudioSerialInterface2,DataOutput 0 4 32 0x00 0x04 0x20 AudioSerialInterface2,ADCWCLKandBCLKControl 0 4 33 0x00 0x04 0x21 AudioSerialInterface3,AudioBusFormatControlRegister 0 4 34 0x00 0x04 0x22 AudioSerialInterface3,DataOffsetControlRegister 0 4 35-36 0x00 0x04 0x23- ReservedRegisters 0x24 0 4 37 0x00 0x04 0x25 AudioSerialInterface3,ADCAudioBusFormatControlRegister 0 4 38 0x00 0x04 0x26 ReservedRegister 0 4 39 0x00 0x04 0x27 AudioSerialInterface3,ADCInputControl 0 4 40 0x00 0x04 0x28 AudioSerialInterface3,DACOutputControl 0 4 41 0x00 0x04 0x29 ReservedRegister 0 4 42 0x00 0x04 0x2A AudioSerialInterface3,WCLKandBCLKControlRegister 54 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 4 43 0x00 0x04 0x2B AudioSerialInterface3,BitClockNDividerInputControl 0 4 44 0x00 0x04 0x2C AudioSerialInterface3,BitClockNDivider 0 4 45 0x00 0x04 0x2D AudioSerialInterface3,WordClockNDivider 0 4 46 0x00 0x04 0x2E AudioSerialInterface3,BCLKandWCLKOutput 0 4 47 0x00 0x04 0x2F AudioSerialInterface3,DataOutput 0 4 48 0x00 0x04 0x30 AudioSerialInterface3,ADCWCLKandBCLKControl 0 4 49 0x00 0x04 0x31 AudioSerialInterface1,L1/R1InputControl 0 4 50 0x00 0x04 0x32 AudioSerialInterface1,L2/R2InputControl 0 4 51 0x00 0x04 0x33 AudioSerialInterface1,L3/R3InputControl 0 4 52 0x00 0x04 0x34 AudioSerialInterface1,L4/R4InputControl 0 4 53 0x00 0x04 0x35 AudioSerialInterface2,WCLKandBCLKInputMultiplexersControl 0 4 54 0x00 0x04 0x36 AudioSerialInterface2,DINInputMultiplexerControl 0 4 55 0x00 0x04 0x37 AudioSerialInterface3,WCLKandBCLKInputMultiplexersControl 0 4 56 0x00 0x04 0x38 AudioSerialInterface3,DINInputMultiplexerControl 0 4 57-64 0x00 0x04 0x39- ReservedRegisters 0x40 0 4 65 0x00 0x04 0x41 WCLK1(Input/Output)PinControl 0 4 66 0x00 0x04 0x42 ReservedRegister 0 4 67 0x00 0x04 0x43 DOUT1(Output)PinControl 0 4 68 0x00 0x04 0x44 DIN1(Input)PinControl 0 4 69 0x00 0x04 0x45 WCLK2(Input/Output)PinControl 0 4 70 0x00 0x04 0x46 BCLK2(Input/Output)PinControl 0 4 71 0x00 0x04 0x47 DOUT2(Output)PinControl 0 4 72 0x00 0x04 0x48 DIN2(Input)PinControl 0 4 73 0x00 0x04 0x49 WCLK3(Input/Output)PinControl 0 4 74 0x00 0x04 0x4A BCLK3(Input/Output)PinControl 0 4 75 0x00 0x04 0x4B DOUT3(Output)PinControl 0 4 76 0x00 0x04 0x4C DIN3(Input)PinControl 0 4 77-85 0x00 0x04 0x4D- ReservedRegisters 0x55 0 4 86 0x00 0x04 0x56 GPIO1(Input/Output)PinControl 0 4 87 0x00 0x04 0x57 GPIO2(Input/Output)PinControl 0 4 88 0x00 0x04 0x58 GPIO3(Input/Output)PinControl 0 4 89 0x00 0x04 0x59 GPIO4(Input/Output)PinControl 0 4 90 0x00 0x04 0x5A GPIO5(Input/Output)PinControl 0 4 91 0x00 0x04 0x5B GPIO6(Input/Output)PinControl 0 4 92-95 0x00 0x04 0x5C- ReservedRegisters 0x5F 0 4 96 0x00 0x04 0x60 GPO1(Output)PinControl 0 4 97-99 0x00 0x04 0x61- ReservedRegisters 0x63 0 4 100 0x00 0x04 0x64 DigitalMicrophoneClockControl 0 4 101 0x00 0x04 0x65 DigitalMicrophone1InputPinControl 0 4 102 0x00 0x04 0x66 DigitalMicrophone2InputPinControl 0 4 103 0x00 0x04 0x67 ReservedRegister 0 4 104 0x00 0x04 0x68 Bit-BangOutput Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 0 4 105-106 0x00 0x04 0x69- ReservedRegisters 0x6A 0 4 107 0x00 0x04 0x6B Bit-BangInput 0 4 108-112 0x00 0x04 0x6C- ReservedRegisters 0x70 0 4 113 0x00 0x04 0x71 Bit-BangminiDSPOutputControl 0 4 114 0x00 0x04 0x72 ReservedRegister 0 4 115 0x00 0x04 0x73 AudioSerialInterface1,ADCBCLKandADCWCLKOutput 0 4 116 0x00 0x04 0x74 AudioSerialInterface2,ADCBCLKandADCWCLKOutput 0 4 117 0x00 0x04 0x75 AudioSerialInterface3,ADCBCLKandADCWCLKOutput 0 4 118 0x00 0x04 0x76 miniDSPDataPortControl 0 4 119 0x00 0x04 0x77 DigitalAudioEngineSynchronizationControl 0 4 120-127 0x00 0x04 0x78- ReservedRegisters 0x7F 0 252 0 0x00 0xFC 0x00 PageSelectRegister 0 252 1 0x00 0xFC 0x01 SARBufferModeData(MSB)andBufferFlags 0 252 2 0x00 0xFC 0x02 SARBufferModeData(LSB) 0 252 3-127 0x00 0xFC 0x03- ReservedRegisters 0x7F 20 0 0 0x14 0x00 0x00 PageSelectRegister 20 0 1-126 0x14 0x00 0x01- ReservedRegisters 0x7E 20 0 127 0x14 0x00 0x7F BookSelectionRegister 20 1-26 0 0x14 0x01- 0x00 PageSelectRegister 0x1A 20 1-26 1-7 0x14 0x01- 0x01- ReservedRegisters 0x1A 0x07 20 1-26 8-127 0x14 0x01- 0x08- ADCFixedCoefficientsC(0:767) 0x1A 0x7F 40 0 0 0x28 0x00 0x00 PageSelectRegister 40 0 1 0x28 0x00 0x01 ADCAdaptiveCRAMConfigurationRegister 40 0 2-126 0x28 0x00 0x02- ReservedRegisters 0x7E 40 0 127 0x28 0x00 0x7F BookSelectionRegister 40 1-17 0 0x28 0x01- 0x00 PageSelectRegister 0x11 40 1-17 1-7 0x28 0x01- 0x01- ReservedRegisters 0x11 0x07 40 1-17 8-127 0x28 0x01- 0x08- ADCAdaptiveCoefficientsC(0:509) 0x11 0x7F 40 18 0 0x28 0x12 0x00 PageSelectRegister 40 18 1-7 0x28 0x12 0x01- ReservedRegisters 0x07 40 18 8-15 0x28 0x12 0x08- ADCAdaptiveCoefficientsC(510:511) 0x0F 40 18 16-127 0x28 0x12 0x10- ReservedRegisters 0x7F 60 0 0 0x3C 0x00 0x00 PageSelectRegister 60 0 1-126 0x3C 0x00 0x01- ReservedRegisters 0x7E 60 0 127 0x3C 0x00 0x7F BookSelectionRegister 56 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 www.ti.com SLAS923–JUNE2013 Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 60 1-35 0 0x3C 0x01- 0x00 PageSelectRegister 0x23 60 1-35 1-7 0x3C 0x01- 0x01- ReservedRegisters 0x23 0x07 60 1-35 8-127 0x3C 0x01- 0x08- DACFixedCoefficientsC(0:1023) 0x23 0x7F 80 0 0 0x50 0x00 0x00 PageSelectRegister 80 0 1 0x50 0x00 0x01 DACAdaptiveCoefficientBank#1ConfigurationRegister 80 0 2-126 0x50 0x00 0x02- ReservedRegisters 0x7E 80 0 127 0x50 0x00 0x7F BookSelectionRegister 80 1-17 0 0x50 0x01- 0x00 PageSelectRegister 0x11 80 1-17 1-7 0x50 0x01- 0x01- ReservedRegisters 0x11 0x07 80 1-17 8-127 0x50 0x01- 0x08- DACAdaptiveCoefficientBank#1C(0:509) 0x11 0x7F 80 18 0 0x50 0x12 0x00 PageSelectRegister 80 18 1-7 0x50 0x12 0x01- ReservedRegisters 0x07 80 18 8-15 0x50 0x12 0x08- DACAdaptiveCoefficientBank#1C(510:511) 0x0F 80 18 16-127 0x50 0x12 0x10- ReservedRegisters 0x7F 82 0 0 0x52 0x00 0x00 PageSelectRegister 82 0 1 0x52 0x00 0x01 DACAdaptiveCoefficientBank#2ConfigurationRegister 82 0 2-126 0x52 0x00 0x02- ReservedRegisters 0x7E 82 0 127 0x52 0x00 0x7F BookSelectionRegister 82 1-17 0 0x52 0x01- 0x00 PageSelectRegister 0x11 82 1-17 1-7 0x52 0x01- 0x01- ReservedRegisters 0x11 0x07 82 1-17 8-127 0x52 0x01- 0x08- DACAdaptiveCoefficientBank#2C(0:509) 0x11 0x7F 82 18 0 0x52 0x12 0x00 PageSelectRegister 82 18 1-7 0x52 0x12 0x01- ReservedRegisters 0x07 82 18 8-15 0x52 0x12 0x08- DACAdaptiveCoefficientBank#2C(510:511) 0x0F 82 18 16-127 0x52 0x12 0x10- ReservedRegisters 0x7F 100 0 0 0x64 0x00 0x00 PageSelectRegister 100 0 1-46 0x64 0x00 0x01- ReservedRegisters 0x2E 100 0 47 0x64 0x00 0x2F Non-ProgrammableOverrideOptions 100 0 48 0x64 0x00 0x30 ADCminiDSP_AInstructionControlRegister1 100 0 49 0x64 0x00 0x31 ADCminiDSP_AInstructionControlRegister2 100 0 50 0x64 0x00 0x32 ADCminiDSP_ACICInputandDecimationRatioControlRegister 100 0 51-56 0x64 0x00 0x33- ReservedRegisters 0x38 100 0 57 0x64 0x00 0x39 ADCminiDSP_AInstructionControlRegister3 Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLinks:TLV320AIC3263

TLV320AIC3263 SLAS923–JUNE2013 www.ti.com Table12.SummaryofRegisterMap(continued) Decimal Hex DESCRIPTION BOOK PAGE REG. BOOK PAGE REG. NO. NO. NO. NO. NO. NO. 100 0 58 0x64 0x00 0x3A ADCminiDSP_AISRInterruptControl 100 0 59 0x64 0x00 0x3B ReservedRegisters 100 0 60 0x64 0x00 0x3C ADCminiDSP_ASecondaryCICInputControl 100 0 61 0x64 0x00 0x3D miniDSP_AtoAudioSerialInterfaceHandoffControl 100 0 62-126 0x64 0x00 0x3E- ReservedRegisters 0x7E 100 0 127 0x64 0x00 0x7F BookSelectionRegister 100 1-52 0 0x64 0x01- 0x00 PageSelectRegister 0x34 100 1-52 1-7 0x64 0x01- 0x01- ReservedRegisters 0x34 0x07 100 1-52 8-127 0x64 0x01- 0x08- miniDSP_AInstructions 0x34 0x7F 120 0 0 0x78 0x00 0x00 PageSelectRegister 120 0 1-46 0x78 0x00 0x01- ReservedRegisters 0x2E 120 0 47 0x78 0x00 0x2F Non-ProgrammableOverrideOptions 120 0 48 0x78 0x00 0x30 DACminiDSP_DInstructionControlRegister1 120 0 49 0x78 0x00 0x31 DACminiDSP_DInstructionControlRegister2 120 0 50 0x78 0x00 0x32 DACminiDSP_DInterpolationFactorControlRegister 120 0 51-56 0x78 0x00 0x33- ReservedRegisters 0x38 120 0 57 0x78 0x00 0x39 DACminiDSP_DInstructionControlRegister3 120 0 58 0x78 0x00 0x3A DACminiDSP_DISRInterruptControl 120 0 59-126 0x78 0x00 0x3B- ReservedRegisters 0x7E 120 0 127 0x78 0x00 0x7F BookSelectionRegister 120 1-103 0 0x78 0x01- 0x00 PageSelectRegister 0x67 120 1-103 1-7 0x78 0x01- 0x01- ReservedRegisters 0x67 0x07 120 1-103 8-127 0x78 0x01- 0x08- miniDSP_DInstructions 0x67 0x7F 58 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:TLV320AIC3263

PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (3) (4/5) TLV320AIC3263IYZFR ACTIVE DSBGA YZF 81 2500 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 AIC32AA & no Sb/Br) TLV320AIC3263IYZFT ACTIVE DSBGA YZF 81 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 AIC32AA & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV320AIC3263IYZFR DSBGA YZF 81 2500 330.0 12.4 5.04 5.07 0.75 8.0 12.0 Q1 TLV320AIC3263IYZFT DSBGA YZF 81 250 330.0 12.4 5.04 5.07 0.75 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV320AIC3263IYZFR DSBGA YZF 81 2500 335.0 335.0 25.0 TLV320AIC3263IYZFT DSBGA YZF 81 250 335.0 335.0 25.0 PackMaterials-Page2

D: Max = 4.84 mm, Min = 4.78 mm E: Max = 4.84 mm, Min = 4.78 mm

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