(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 (cid:1) Supply Voltage Range...1.8 V to 3.6 V Operational Amplifier (cid:1) Rail-to-Rail Input/Output (cid:1) + High Bandwidth...8 MHz − (cid:1) High Slew Rate...4.8 V/µs (cid:1) V Exceeds Rails...−0.2 V to V + 0.2 ICR DD (cid:1) Supply Current...650 µA/Channel DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE (cid:1) Input Noise Voltage...9 nV/√Hz at 10 kHz vs (cid:1) FREQUENCY Specified Temperature Range: B 80 240 0−°4C0° tCo t7o0 1°C25.°.C. .C.o.m Inmdeursctiraial lG Graraddee ation − d 7600 VRCDLL= D= 2 =1 k0 1Ω p.8F V & 2.7 V 211800 d e(cid:1)(cid:1)scrUUipnlttriivoaesnrmsaall lO Ppaecrkaatigoinnagl Amplifier EVM ntial Voltage Amplific 24531000000 Phase TA = 25° CGain 1196305200000 °Phase Margin − The TLV278x single supply operational amplifiers ere −10 −30 Diff −20 −60 provide rail-to-rail input and output capability. The − −30 −90 TLV278x takes the minimum operating supply AVD −401 k 10 k 100 k 1 M 10 M−120 voltage down to 1.8 V over the extended industrial temperature range (−40°C to 125°C) while adding f − Frequency − Hz the rail-to-rail output swing feature. The TLV278x also provides 8 MHz bandwidth from only 650 µA of supply current. The maximum recommended supply voltage is 3.6 V, which allows the devices to be operated from (±1.8 V supplies down to ±0.9 V) two rechargeable cells. The combination of wide bandwidth, low noise, and low distortion makes it ideal for high speed and high resolution data converter applications. All members are available in PDIP, SOIC, and the newer, smaller SOT-23 (singles), MSOP (duals), and TSSOP (quads). FAMILY PACKAGE TABLE VDD VIO IDD/ch IIB GBW SLEW RATE Vn, 1 kHz IO RAIL-TO- DEVICE SHUTDOWN [V] [µV] [µA] [pA] [MHz] [V/µs] [nV/√Hz] [mA] RAIL TLV278x(A) 1.8−3.6 250 650 2.5 8 5 18 10 Y I/O TLV276x(A) 1.8−3.6 550 20 3 0.5 0.23 95 5 Y I/O TLV246x(A) 2.7−6 150 550 1300 6.4 1.6 11 25 Y I/O TLV247x(A) 2.7−6 250 600 2.5 2.8 1.5 15 20 Y I/O TLV244x(A) 2.7−10 300 750 1 1.81 1.4 16 2 — O TLV277x(A) 2.5−5.5 360 1000 2 5.1 10.5 17 6 Y O Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:25)(cid:28)(cid:19)(cid:27)(cid:30)"(cid:1)(cid:17)(cid:19)(cid:29) (cid:27)(cid:14)(cid:1)(cid:14) #$%&’()*#&$ #+ ,-’’.$* )+ &% /-01#,)*#&$ 2)*.(cid:20) Copyright  2000−2005, Texas Instruments Incorporated (cid:25)’&2-,*+ ,&$%&’( *& +/.,#%#,)*#&$+ /.’ *3. *.’(+ &% (cid:1).(cid:13))+ (cid:17)$+*’-(.$*+ +*)$2)’2 4)’’)$*5(cid:20) (cid:25)’&2-,*#&$ /’&,.++#$6 2&.+ $&* $.,.++)’#15 #$,1-2. *.+*#$6 &% )11 /)’)(.*.’+(cid:20) WWW.TI.COM 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TLV2780 and TLV2781 AVAILABLE OPTIONS(1) PACKAGED DEVICES TTAA AAVVTTIIOO 22mm55aa°°CCxx SSMMAALLLL OOUUTTLLIINNEE SOT-23 PPLLAASSTTIICC DDIIPP (D)†† (DBV)‡ SYMBOL (P) TLV2780CD TLV2780CDBV VASC — 0°C to 70°C 3000 µV TLV2781CD TLV2781CDBV VATC — TLV2780ID TLV2780IDBV VASI TLV2780IP 3000 µV TLV2781ID TLV2781IDBV VATI TLV2781IP --4400°°CC ttoo 112255°°CC TLV2780AID — — — 2000 µV TLV2781AID — — — †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2780CDR). ‡This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2780CDBVR). For smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g. TLV2780CDBVT). TLV2782 and TLV2783 AVAILABLE OPTIONS(1) PACKAGED DEVICES TTAA AAVTTIIOO 22m55a°°CCx OOSUUMTTLLAIILNNLEE†† MSOP PLADDSIIPPTIC PLADDSIIPPTIC (D) (DGK)† SYMBOL (DGS)† SYMBOL (N) (P) TLV2782CD TLV2782CDGK xxTIADL — — — — 0°C to 70°C 3000 µV TLV2783CD — — TLV2783CDGS xxTIADN — — TLV2782ID TLV2782IDGK xxTIADM — — — TLV2782IP 3000 µV TLV2783ID — — TLV2783IDGS xxTIADO TLV2783IN — −−4400°°CC ttoo 112255°°CC TLV2782AID — — — — — — 2000 µV TLV2783AID — — — — — — †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2782CDR). TLV2784 and TLV2785 AVAILABLE OPTIONS(1) PACKAGED DEVICES TA AVVTIIOO 2mm5aa°Cxx SMALL OUTLINE PLASTIC DIP TSSOP† (D) (N) (PW) TLV2784CD — TLV2784CPW 0°C to 70°C 3000 µV TLV2785CD — TLV2785CPW TLV2784ID TLV2784IN TLV2784IPW 3000 µV TLV2785ID TLV2785IN TLV2785IPW −−4400°°CC ttoo 112255°°CC TLV2784AID — TLV2784AIPW 2000 µV TLV2785AID — TLV2785AIPW †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2784CDR). 1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TLV278x PACKAGE PINOUTS TLV2780 TLV2780 TLV2781 DBV PACKAGE D OR P PACKAGE DBV PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OUT 1 6 VDD NC 1 8 SHDN OUT 1 5 VDD IN− 2 7 VDD GND 2 5 SHDN IN+ 3 6 OUT GND 2 GND 4 5 NC IN+ 3 4 IN− IN+ 3 4 IN− TLV2781 TLV2782 TLV2783 D OR P PACKAGE D, DGK, OR P PACKAGE DGS PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) NC 1 8 NC 1OUT 1 8 VDD 1OUT 1 10 VDD IN− 2 7 VDD 1IN− 2 7 2OUT 1IN− 2 9 2OUT IN+ 3 6 OUT 1IN+ 3 6 2IN− 1IN+ 3 8 2IN− GND 4 7 2IN+ GND 4 5 NC GND 4 5 2IN+ 1SHDN 5 6 2SHDN TLV2783 TLV2784 TLV2785 D OR N PACKAGE D, N, OR PW PACKAGE D, N, OR PW PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) 1OUT 1 14 VDD 1OUT 1 14 4OUT 1OUT 1 16 4OUT 1IN− 2 13 2OUT 1IN− 2 13 4IN− 1IN− 2 15 4IN− 1IN+ 3 12 2IN− 1IN+ 3 12 4IN+ 1IN+ 3 14 4IN+ GND 4 11 2IN+ VDD 4 11 GND VDD 4 13 GND NC 5 10 NC 2IN+ 5 10 3IN+ 2IN+ 5 12 3IN+ 1SHDN 6 9 2SHDN 2IN− 6 9 3IN− 2IN− 6 11 3IN− NC 7 8 NC 2OUT 7 8 3OUT 2OUT 7 10 3OUT 1/2SHDN 8 9 3/4SHDN NC − No internal connection WWW.TI.COM 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V DD Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V ID DD Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA I Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE ΘΘJJCC ΘΘJJAA TTAA ≤≤ 2255°CC TTAA == 112255°CC PPAACCKKAAGGEE (°C/W) (°C/W) POWER RATING POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.3 1022 mW 204.4 mW D (16) 25.7 114.7 1090 mW 218 mW DBV (5) 55 324.1 385 mW 77.1 mW DBV (6) 55 294.3 425 mW 85 mW DGK (8) 54.2 259.9 481 mW 96.2 mW DGS (10) 54.1 257.7 485 mW 97 mW N (14, 16) 32 78 1600 mW 320.5 mW P (8) 41 104 1200 mW 240.4 mW PW (14) 29.3 173.6 720 mW 144 mW PW (16) 28.7 161.4 774 mW 154.9 mW recommended operating conditions MIN MAX UNIT Single supply 1.8 3.6 SSuuppppllyy vvoollttaaggee,, VVDDDD Split supply ±0.9 ±1.8 VV Common-mode input voltage range, VICR −0.2 VDD+0.2 V C-suffix 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA °°CC I-suffix −40 125 VDD < 2.7 V 0.75VDD SShhuuttddoowwnn oonn//ooffff vvoollttaaggee lleevveell‡‡ VVIIHH VDD = 2.7 to 3.6 V 2 VV VIL 0.6 ‡Relative to GND. 4 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 electrical characteristics at specified free-air temperature, V = 1.8 V, 2.7 V (unless otherwise DD noted) dc performance PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 250 3000 TTLLVV227788xx Full range 4500 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == VVDDDD//22,, 25°C 250 2000 µVV RRLL == 22 kkΩΩ,, TTLLVV227788xxAA RRSS == 5500 ΩΩ Full range 3000 TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt ooffffsseett αVVIIOO voltage 88 µVV//°°CC 25°C 50 76 VVDDDD == 11..88 VV VVIICC == 00 ttoo VVDDDD,, Full range 50 RRSS == 5500Ω 25°C 55 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVDDDD == 22..77 VV// 33..66 VV ddBB Full range 50 VVRIISCC = == 5 110..22Ω VV ttoo VVDDDD,, VVDDDD == 22..77 VV// 33..66 VV Fu2ll 5r°aCnge 7700 100 25°C 200 600 VVDDDD == 11..88 VV LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee RRLL == 22 kkΩΩ,, Full range 50 AAVVDD aammpplliiffiiccaattiioonn VVOO((PPPP)) == 11 VV 25°C 200 1000 VV//mmVV VVDDDD == 22..77 VV// 33..66 VV Full range 70 †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. input characteristics PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 2.5 15 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt TLV278xC Full range 100 ppAA VVO == VVDD//22,, TLV278xI Full range 300 RRRRLLSS ==== 2255 00kk ΩΩΩΩ,, 25°C 2.5 15 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt TLV278xC Full range 100 ppAA TLV278xI Full range 300 ri(d) Differential input resistance 25°C 1000 GΩ Ci(c) Common-mode input capacitance f = 1 kHz 25°C 19 pF †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. WWW.TI.COM 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 electrical characteristics at specified free-air temperature, V = 1.8 V, 2.7 V (unless otherwise DD noted) (continued) output characteristics PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 1.7 1.77 VVDDDD == 11..88 VV Full range 1.63 IIOOHH == −−11 mmAA 25°C 2.6 2.68 VVDDDD == 22..77 VV Full range 2.6 VDD = 3.6 V 25°C 3.58 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee 25°C 1.5 1.55 VV VVDDDD == 11..88 VV Full range 1.46 IIOOHH == −−55 mmAA 25°C 2.5 2.55 VVDDDD == 22..77 VV Full range 2.45 VDD = 3.6 V 25°C 3.55 25°C 70 IIOOLL == 11 mmAA Full range 80 25°C 180 240 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVDDDD == 11..88 VV mmVV Full range 290 IIOOLL == 55 mmAA 25°C 120 170 VVDDDD == 22..77 VV Full range 200 VVDDDD == 11..88 VV,, Positive rail 10 VO = 0.5 V from Negative rail 15 IIOO OOuuttppuutt ccuurrrreenntt 2255°°CC mmAA VVDDDD == 22..77 VV,, Positive rail 17 VO = 0.5 V from Negative rail 23 VDD = 1.8 V 13 SSoouurrcciinngg VDD = 2.7 V 35 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 2255°°CC mmAA VDD = 1.8 V 21 SSiinnkkiinngg VDD = 2.7 V 45 †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. power supply PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 650 770 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == VVDDDD//22,, SSHHDDNN == VVDDDD µAA Full range 820 VVDDDD == 11..88 VV ttoo 22..77 VV,, NNoo llooaadd,, 25°C 60 75 VIC = VDD/2 Full range 58 SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo VVDDDD == 22..77 VV ttoo 33..66 VV,, NNoo llooaadd,, 25°C 75 90 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VIC = VDD/2 Full range 70 ddBB VVDDDD == 11..88 VV ttoo 33..66 VV,, NNoo llooaadd,, 25°C 65 80 VIC = VDD/2 Full range 60 †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. 6 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 electrical characteristics at specified free-air temperature, V = 1.8 V, 2.7 V (unless otherwise DD noted) (continued) dynamic performance PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT UGBW Unity gain bandwidth RL = 2 kΩ, CL = 25 pF 25°C 8 MHz 25°C 3.3 4.3 VVDDDD == 11..88 VV Full range 3.1 VVOO((PPPP)) == 11 VV,, 25°C 3.8 4.8 SSRR++ PPoossiittiivvee sslleeww rraattee aatt uunniittyy ggaaiinn RRLL == 22 kkΩΩ, VVDDDD == 22..77 VV Full range 3.5 CCLL == 5500 ppFF 25°C 4 5 VVDDDD == 33..66 VV Full range 3.6 VV//µss 25°C 2.1 2.8 VVDDDD == 11..88 VV Full range 1.89 VVOO((PPPP)) == 11 VV,, 25°C 2.2 2.8 SSRR−− NNeeggaattiivvee sslleeww rraattee aatt uunniittyy ggaaiinn RRLL == 22 kkΩΩ, VVDDDD == 22..77 VV Full range 1.97 CCLL == 5500 ppFF 25°C 3.5 4.2 VVDDDD == 33..66 VV Full range 3.4 φm Phase margin 58° RRLL == 22 kkΩΩ,, CCLL == 2255 ppFF 2255°°CC Gain margin 8 dB VDD = 1.8 V, 0.1% 1.7 VV((SSTTEEPP))PPPP == 11 VV,, AV = −1, CL = 10 pF, RL = 2 kΩ 0.01% 2.8 ttss SSeettttlliinngg ttiimmee 2255°°CC µss VDD = 2.7 V, 0.1% 1.7 VV((SSTTEEPP))PPPP == 11 VV,, AV = −1, CL = 10 pF, RL = 2 kΩ 0.01% 2.4 †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. noise/distortion performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VVOO((PPPP)) == VVDDDD//22,, AV = 1 0.055% TTHHDD ++ NN TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss nnooiissee RRLL == 22 kkΩΩ,, AV = 10 0.08% ff == 1100 kkHHzz AV = 100 0.45% 2255°°CC f = 1 kHz 18 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee nnVV//√√HHzz f = 10 kHz 9 In Equivalent input noise current f = 1 kHz 0.9 fA/√Hz shutdown characteristics PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT SSuuppppllyy ccuurrrreenntt,, ppeerr cchhaannnneell iinn sshhuuttddoowwnn mmooddee 25°C 900 1400 IIDDDD((SSHHDDNN)) (TLV2780, TLV2783, TLV2785) SSHHDDNN == 00 VV Full range 1700 nnAA t(on) Amplifier turnon time‡ RL = 2 kΩ 800 2255°°CC nnss t(off) Amplifier turnoff time‡ RL = 2 kΩ 200 †Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C. ‡Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. WWW.TI.COM 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 CMRR Common-mode rejection ratio vs Frequency 3 VOH High-level output voltage vs High-level output current 4, 6 VOL Low-level output voltage vs Low-level output current 5, 7 VO(PP) Maximum peak-to-peak output voltage vs Frequency 8 Zo Output impedance vs Frequency 9 IDD Supply current vs Supply voltage 10 IDD Supply current vs Free-air temperature 11 PSRR Power supply rejection ratio vs Frequency 12 AVD Differential voltage amplification & phase vs Frequency 13 Gain-bandwidth product vs Free-air temperature 14 vs Supply voltage 15 SSRR SSlleeww rraattee vs Free-air temperature 16, 17 φm Phase margin vs Load capacitance 18 Vn Equivalent input noise voltage vs Frequency 19 Voltage-follower large-signal pulse response vs Time 20 Voltage-follower small-signal pulse response vs Time 21 Inverting large-signal pulse response vs Time 22 Inverting small-signal pulse response vs Time 23 Crosstalk vs Frequency 24 Shutdown forward & reverse isolation vs Frequency 25 IDD(SHDN) Shutdown supply current vs Free-air temperature 26 IDD(SHDN) Shutdown supply current vs Supply voltage 27 IDD(SHDN) Shutdown supply current/output voltage vs Time 28 8 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE COMMON-MODE REJECTION RATIO vs vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE FREQUENCY µV 240000 VTDAD==215.°8 C V µ−V 105000 V DTDA==225.7 ° VC n Ratio − dB111112340000 VDD = 3.6 V oltage −−2000 Voltage −−10500 Rejectio1089000 VDD = 2.7 V nput Offset V−−640000 Input Offset −−−221505000 mmon-Mode 45670000 VDD = 1.8 V I−VIO−800 −VIO−−335000 RR − Co 123000 −1000 −400 CM 0 −0.2 0 0.2 0.40.60.8 1 1.2 1.4 1.6 1.8 2 −0.2 0.2 0.6 1 1.4 1.8 2.2 2.6 3 0 10 100 1k 10k 100k 1M 10M VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V f − Frequency − Hz Figure 1 Figure 2 Figure 3 HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 1.8 1.8 2.7 VDD=1.8 V VDD = 2.7 V − High-Level Output Voltage − V 0001111.......4680246 TTTTTAAAAA = = == =− 2 1047520°0°5C°°C°CCC VDD=1.8 V − Low-Level Output Voltage − V 0001111.......4680246 TATAT=TA=−TA=24A=500=1°°°7CCC205°°CC − High-Level Output Voltage − V 0011122.......6925814 TTTAATAAT===A=1−7=22405500°°°°°CCCCC H 0.2 L 0.2 H 0.3 O O O V 0.0 V 0.0 V 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10121416182022242628 0 5 10 15 20 25 30 35 40 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA IOH − High-Level Output Current − mA Figure 4 Figure 5 Figure 6 MAXIMUM PEAK-TO-PEAK LOW-LEVEL OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT IMPEDANCE vs vs vs LOW-LEVEL OUTPUT CURRENT − V FREQUENCY FREQUENCY 2.7 ge 2.8 100 w-Level Output Voltage − V 011122......925814 VDTDTTAT=AAAT= =2A==−1. =24772500 05V°°°°°CCCCC m Peak-To-Peak Output Volta 11112222........24680246 VO(PVPO)(=P P1.)8= V2.7 V ΩOutput Impedance − 101 VTADA D=V 2==5 21°. 07C V − LoL 0.6 aximu 01..80 ARVL= =2 −k1Ω0 − Zo AV = 1 VO 00..03 − MPP) 00..46 CTAL == 2150° p CF 0.1 0 5 10 15 20 25 30 35 40 45 50 55 O( 100 1 k 10 k 100 k 1 M 10 M 100 1k 10k 100k 1M 10M IOL − Low-Level Output Current − mA V f − Frequency − Hz f − Frequency − Hz Figure 7 Figure 8 Figure 9 WWW.TI.COM 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT POWER SUPPLY REJECTION RATIO vs vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE FREQUENCY 700 1.4 B 120 µISupply Current − −ADD 123456000000000000 TA = 125°C AVTVICA=T ==A1 V 2=5D °−DC4/02° CV I− Supply Current − mADD 1111....1110123...5555123 AVVVIDC D= = 1 =V 2D.D7 /V2 VDVDD =D 1=.8 3 V.6 V − Power Supply Rejection Ratio − dRR 10246800000 VTAD=D2=52°.C7 V S 0 1 P 0 0 0.6 1.2 1.8 2.4 3 3.6 −40−25−10 5 20 35 50 65 80 95 110125 10 100 1 k 10 k 100 k 1 M 10 M VDD − Supply Voltage − V TA − Free-Air Temperature − °C f − Frequency − Hz Figure 10 Figure 11 Figure 12 DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE GAIN-BANDWIDTH PRODUCT vs vs FREQUENCY FREE-AIR TEMPERATURE B 80 240 9 d ation − 7600 VRCDLL= D= 2 =1 k0 1Ω p.8F V & 2.7 V 211800 MHz 78 VDD = 1.8 V Differential Voltage Amplific −−245311200000000 Phase TA = 25° CGain 119630−−52000360000 °Phase Margin − Gain-Bandwidth Product − 23456 RCLL == 21 0k ΩpF VDD = 2.7 V − −30 −90 1 f = 10 kHz D AV −401 k 10 k 100 k 1 M 10 M−120 0−40−25−10 5 20 35 50 65 80 95 110125 f − Frequency − Hz TA − Free-Air Temperature − °C Figure 13 Figure 14 SLEW RATE SLEW RATE SLEW RATE vs vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 8 6 6 7 5 SR+ 5 SR+ s 6 SR− µSR − Slew Rate − V/ 12345 SR+ ARCVVVOILLC === == 1 12 10V k VDpΩPFDP/2 µSR − Slew Rate − V/s 1234 SR− VARCVDLL ==D=21 1= 0k Ω1p.F8 V µSR − Slew Rate − V/s 1234 SR−AVRCVDVOLL= D === 2 =111 k0 2VΩ p.P7F PV TA = 25° C VIC = VDD/2 VIC = VDD/2 0 0 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 −40−25−10 5 20 35 50 65 80 95 110125 −40−25−10 5 20 35 50 65 80 95 110125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 15 Figure 16 Figure 17 10 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS PHASE MARGIN EQUIVALENT INPUT NOISE VOLTAGE vs vs LOAD CAPACITANCE FREQUENCY 100 Hz 140 TA = 25°C 90 V/ 120 °argin − 678000 Rnull=50 Ω nVoltage − 10800 VDD = 2.7 V − Phase M 4500 Rnull=20 Ω put Noise 60 φm 30 VDD = 2.7 V nt In 40 1200 RATAVL === 221 5k°ΩC Rnull=0 Ω quivale 20 VDD = 1.8 V E 0 − 0 10 100 1 k 10 k n 10 100 1 k 10 k 100 k V CL − Load Capacitance − pF f − Frequency − Hz Figure 18 Figure 19 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE vs vs TIME TIME 2.5 V 1.45 − V − Output Voltage − VO 012...12555 VOVI VRCATAVDLL D==== 2 121=5 0k ° 2ΩpC.F7 V 0112..55 − Input Voltage VI − Output Voltage − VO111...334050 VVOIRCVATAVDLL D==== 2 121=5 0k ° 2ΩpC.F7 V 1111....23345050− Input Voltage − VI V 0 V1.25 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 t − Time − µs t − Time − µs Figure 20 Figure 21 INVERTING LARGE-SIGNAL PULSE RESPONSE INVERTING SMALL-SIGNAL PULSE RESPONSE vs vs TIME TIME Output Voltage − V 012...12555 VOVI VRCATAVDLL D==== 2− 21=51 0k ° 2ΩpC.F7 V −−001.105.5− Input Voltage − VVI Output Voltage − V 111...334050 VVIO VRCATAVDLL D==== 2− 21=51 0k ° 2ΩpC.F7 V −000..001.5005 − Input Voltage − VVI − − VO 0 0 0.30.60.91.21.51.82.12.42.7 3 3.3 VO1.25 0 0.3 0.60.9 1.21.5 1.8 2.1 2.4 2.7 3 t − Time − µs t − Time − µs Figure 22 Figure 23 WWW.TI.COM 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS SHUTDOWN FORWARD CROSSTALK AND REVERSE ISOLATION SHUTDOWN SUPPLY CURRENT vs vs vs FREQUENCY FREQUENCY FREE-AIR TEMPERATURE 3 0 140 Shutdown = 0V −20 Crosstalk in Shutdown n - dB 120 Forward and Reverse Isolation µnt −A 2.5 VA VIC == 1VDD/2 Crosstalk − dB −−−−−112086400000 VVART AADIVLCll= D == C = 2 =h21 6ak5 10Ωn°.%Cn8e Vols f& V 2D.D7 V Shutdown Forward Isolatio 10246800000 VVRCAVDILLC =D = = = 1 =2 10V k 1DpΩ.F8D & /2 2.7 V Shutdown Supply Curre−D 012...1550 VDDV=D D3. 6= V2.7 V Crosstalk/No Shutdown TA = 25°C D VDD = 1.8 V −14010 100 1 k 10 k 100 k 010 100 1 k 10 k 100 k 1 M 10 M I 0−40−25−10 5 20 35 50 65 80 95 110125 f − Frequency − Hz f − Frequency − Hz TA − Free-Air Temperature − °C Figure 24 Figure 25 Figure 26 SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE vs TIME 3.0 V − 2.5 e uls 2.0 SHUTDOWN SUPPLY CURRENT n P 1.5 vs w o 1.0 2.6 SUPPLY VOLTAGE Shutd 0.5 SD 2.4 Shutdown = 0 V D − 0.0 2.2 VIC = VDD/2 S AV = 1 A 2 µ 1.5 − 1.8 V upply Current 111...1246 TA = 125°C TA = −40°C ut Voltage − m 00011.....35803 VO − S 0.8 utp 0.0 DD 0.6 − O I 00..24 TA = 25°C VO 00 0.4 V0.D8DF 1−i. 2gSuup1p.r6ley V 22ol7ta2g.e4 − 2V.8 3.2 3.6 µCurrent − A 10111.....58038 VCVARVIDLLC D=== = =111 V 002D .kp7DΩF V/2 own 0.5 IDD(SD) TA = 25°C d 0.3 ut Sh 0.0 − D) S D( −1 0 1 2 3 4 5 6 7 8 9 10 D I t − Time − µsec Figure 28 12 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 PARAMETER MEASUREMENT INFORMATION _ RNULL + RL CL Figure 29 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (R ) with the output of the amplifier, as NULL shown in Figure 30. RF RF RG RG Input − RNULL Input − RNULL Output Output + + RL CL Snubber RL CL C (a) (b) Figure 30. Driving a Capacitive Load offset voltage The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB− RG + − VI VO + RS (cid:2) IIB+(cid:4) (cid:2) (cid:4) (cid:2) (cid:4) (cid:2) (cid:4) R R VOO(cid:1)VIO 1(cid:3) RF (cid:5)IIB(cid:3)RS 1(cid:3) RF (cid:5)IIB–RF G G Figure 31. Output Offset Voltage Model WWW.TI.COM 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 32). RG RF − + VO VI R1 C1 f (cid:1) 1 –3dB 2(cid:1)R1C1 (cid:2) (cid:4) V R (cid:2) (cid:4) O (cid:1) 1(cid:3) F 1 V R 1(cid:3)2(cid:1)fR1C1 I G Figure 32. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) VI + R1 R2 _ f (cid:1) 1 –3dB 2(cid:1)RC C2 RF RG = RF (2 − 1 ) RG Q Figure 33. 2-Pole Low-Pass Sallen-Key Filter 14 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high performance of the TLV278x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. shutdown function Three members of the TLV278x family (TLV2780/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 900 nA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. WWW.TI.COM 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 APPLICATION INFORMATION general power dissipation considerations For a given θ , the maximum power dissipation is shown in Figure 34 and is calculated by the following formula: JA (cid:2) (cid:4) T –T P (cid:1) MAX A D (cid:1) JA Where: P = Maximum power dissipation of TLV278x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A θJA = θJC + θCA θ = Thermal coefficient from junction to case JC θ = Thermal coefficient from case to ambient air (°C/W) CA MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 PDIP Package TJ = 150°C 1.75 Low-K Test PCB θJA = 104°C/W W n − 1.5 MSOP Package o pati 1.25 SOIC Package LθJoAw -=K 2 T6e0s°tC P/WCB si Low-K Test PCB Dis θJA = 176°C/W r 1 e w o m P 0.75 u m xi 0.5 a M 0.25 SOT-23 Package Low-K Test PCB 0 θJA = 324°C/W −55−40−25 −10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 34. Maximum Power Dissipation vs Free-Air Temperature 16 WWW.TI.COM

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:13)(cid:14) (cid:15)(cid:14)(cid:16)(cid:17)(cid:2)(cid:18) (cid:19)(cid:15) (cid:9)(cid:20)(cid:6) (cid:3) (cid:21)(cid:17)(cid:22)(cid:21)(cid:23)(cid:24)(cid:25)(cid:26)(cid:26)(cid:27) (cid:28)(cid:14)(cid:17)(cid:2)(cid:23)(cid:1)(cid:19)(cid:23)(cid:28)(cid:14)(cid:17)(cid:2) (cid:17)(cid:29)(cid:25)(cid:30)(cid:1)(cid:31)(cid:19)(cid:30)(cid:1)(cid:25)(cid:30)(cid:1) (cid:19)(cid:25)(cid:26)(cid:28)(cid:14)(cid:1)(cid:17)(cid:19)(cid:29)(cid:14)(cid:2) (cid:14)(cid:16)(cid:25)(cid:2)(cid:17)(cid:15)(cid:17)(cid:26)(cid:28)(cid:24) !(cid:17)(cid:1)(cid:21) (cid:24)(cid:21)(cid:30)(cid:1)(cid:27)(cid:19)!(cid:29) SLOS245E − MARCH 2000 − REVISED JANUARY 2005 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 35 are generated using TLV278x typical electrical and operating characteristics at T = 25°C. Using this information, A output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (cid:1) (cid:1) Maximum positive output voltage swing Unity-gain frequency (cid:1) (cid:1) Maximum negative output voltage swing Common-mode rejection ratio (cid:1) (cid:1) Slew rate Phase margin (cid:1) (cid:1) Quiescent power dissipation DC output resistance (cid:1) (cid:1) Input bias current AC output resistance (cid:1) (cid:1) Open-loop voltage amplification Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VDD + rp rd1 rd2 rss css egnd fb ro2 c1 − 7 11 12 + c2 1 vlim IN+ + 9 r2 6 − vc D D + 8 − 2 vb ga G G IN− 53 − gcm ioff ro1 S S OUT dp dlp dln 5 10 91 90 92 iss dc + + − vlp hlim vln GND − − + 4 − ve + 54 de * TLV2782_HVDD operational amplifier ”macromodel” subcircuit ga 6 0 11 12 544.75E−6 * created using Model Editor release 9.1 on 03/3/00 at 9:47 gcm 0 6 10 99 1.1538E−9 * Model Editor is an OrCAD product. iss 10 4 dc 56.957E−6 * hlim 90 0 vlim 1K * connections: non−inverting input j1 11 2 10 jx1 * | inverting input J2 12 1 10 jx2 * | | positive power supply r2 6 9 100.00E3 * | | | negative power supply rd1 3 11 1.8357E3 * | | | | output rd2 3 12 1.8357E3 * | | | | | ro1 8 5 10 .subckt TLV2782_HVDD 1 2 3 4 5 ro2 7 99 10 * rp 3 4 2.1845E3 c1 11 12 49.58E−15 rss 10 99 3.5114E6 c2 6 7 10.200E−12 vb 9 0 dc 0 css 10 99 1.0000E−30 vc 3 53 dc .81911 dc 5 53 dy ve 54 4 dc .81911 de 54 5 dy vlim 7 8 dc 0 dlp 90 91 dx vlp 91 0 dc 45.400 dln 92 90 dx vln 0 92 dc 45.400 dp 4 3 dx .model dx D(Is=800.00E−18) egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 .model dy D(Is=800.00E−18 Rs=1m Cjo=10p) fb 7 99 poly(5) vb vc ve vlp vln 0 .model jx1 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1) 41.096E6 −1E3 1E3 41E6 .model jx2 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1) −41E6 .ends Figure 35. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. WWW.TI.COM 17

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2780CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VASC & no Sb/Br) TLV2780CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VASC & no Sb/Br) TLV2780IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VASI & no Sb/Br) TLV2780IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VASI & no Sb/Br) TLV2780IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 T2780I & no Sb/Br) TLV2781CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VATC & no Sb/Br) TLV2781CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VATC & no Sb/Br) TLV2781ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 T2781I & no Sb/Br) TLV2781IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VATI & no Sb/Br) TLV2781IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VATI & no Sb/Br) TLV2781IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 T2781I & no Sb/Br) TLV2782AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2782AI & no Sb/Br) TLV2782CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2782C & no Sb/Br) TLV2782CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2782C & no Sb/Br) TLV2782CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADL & no Sb/Br) TLV2782CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 ADL & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2782CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ADL & no Sb/Br) TLV2782CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2782C & no Sb/Br) TLV2782ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2782I & no Sb/Br) TLV2782IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 ADM & no Sb/Br) TLV2782IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 ADM & no Sb/Br) TLV2782IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2782I & no Sb/Br) TLV2782IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2782IP & no Sb/Br) TLV2783IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ADO & no Sb/Br) TLV2783IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ADO & no Sb/Br) TLV2783IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2783I & no Sb/Br) TLV2784AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2784AI & no Sb/Br) TLV2784AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2784AI & no Sb/Br) TLV2784CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2784C & no Sb/Br) TLV2784ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2784I & no Sb/Br) TLV2784IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2784I & no Sb/Br) TLV2784IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2784I & no Sb/Br) TLV2784IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2784I & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2785AID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2785AI & no Sb/Br) TLV2785CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2785C & no Sb/Br) TLV2785IN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2785I & no Sb/Br) TLV2785IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2785I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2780CDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2780CDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2780IDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2780IDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2780IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2781CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2781CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2781IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2781IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2781IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2782CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2782CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2782CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2782IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2782IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2782IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2783IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2784AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2784CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2784IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2784IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2785CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2785IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2780CDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TLV2780CDBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TLV2780IDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TLV2780IDBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TLV2780IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2781CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2781CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2781IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2781IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2781IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2782CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2782CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2782CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2782IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2782IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2782IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2783IDGSR VSSOP DGS 10 2500 358.0 335.0 35.0 TLV2784AIDR SOIC D 14 2500 350.0 350.0 43.0 TLV2784CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2784IDR SOIC D 14 2500 350.0 350.0 43.0 TLV2784IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2785CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV2785IPWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page3

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 4.75 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 8X 0.5 10 1 3.1 2X 2.9 NOTE 3 2 5 6 0.27 10X 0.17 B 3.1 0.1 C A B 1.1 MAX 2.9 NOTE 4 0.23 TYP SEE DETAIL A 0.13 0.25 GAGE PLANE 0.15 0.7 0 - 8 0.05 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com

EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM (R0.05) TYP 1 10 SYMM 8X (0.5) 5 6 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) SYMM (R0.05) TYP 10X (0.3) 1 10 SYMM 8X (0.5) 5 6 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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