(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 (cid:1) Qualified for Automotive Applications TLV2471 (cid:1) D PACKAGE ESD Protection Exceeds 2000 V Per (TOP VIEW) MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) NC 1 8 NC (cid:1) CMOS Rail-To-Rail Input/Output IN− 2 7 VDD (cid:1) Input Bias Current...2.5 pA IN+ 3 6 OUT (cid:1) Low Supply Current...600 µA/Channel GND 4 5 NC (cid:1) Gain-Bandwidth Product...2.8 MHz (cid:1) High Output Drive Capability − ±10 mA at 180 mV − ±35 mA at 500 mV (cid:1) Input Offset Voltage...250 µV (typ) (cid:1) Supply Voltage Range...2.7 V to 6 V description The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new performance point for supply current versus ac performance. These devices consume just 600 µA/channel while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications, the TLV247x can supply ±35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor interface, portable medical equipment, and other data acquisition circuits. The family is fully specified at 3 V and 5 V across the automotive temperature range (−40°C to 125°C). FAMILY TABLE NNUUMMBBEERR OOFF UUNNIIVVEERRSSAALL EEVVMM DDEEVVIICCEE CHANNELS BOARD TLV2471 1 SSeeee tthhee EEVVMM TLV2472 2 sseelleeccttiioonn gguuiiddee ((SSLLOOUU006600)) TLV2474 4 A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS‡ DEVICE V(DVD) (VµIVO) (MBHWz) SLE(VW/µ RsA)TE IDD (pe(µr Ach)annel) ODURTIPVUET RAIL-TO-RAIL TLV247X 2.7 − 6 250 2.8 1.5 600 ±35 mA I/O TLV245X 2.7 − 6 20 0.22 0.11 23 ±10 mA I/O TLV246X 2.7 − 6 150 6.4 1.6 550 ±90 mA I/O TLV277X 2.5 − 6 360 5.1 10.5 1000 ±10 mA O ‡All specifications measured at 5 V. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:29)(cid:27)(cid:17)!(cid:30)(cid:21)(cid:1)(cid:15)(cid:17)(cid:28) !(cid:12)(cid:1)(cid:12) $%&’()*+$’% $, -.((/%+ *, ’& 0.12$-*+$’% 3*+/(cid:23) Copyright  2008 Texas Instruments Incorporated (cid:29)(’3.-+, -’%&’() +’ ,0/-$&$-*+$’%, 0/( +(cid:22)/ +/(), ’& (cid:1)/(cid:7)*, (cid:15)%,+(.)/%+, ,+*%3*(3 4*((*%+5(cid:23) (cid:29)(’3.-+$’% 0(’-/,,$%6 3’/, %’+ %/-/,,*($25 $%-2.3/ +/,+$%6 ’& *22 0*(*)/+/(,(cid:23) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 ORDERING INFORMATION† (cid:1) ORDERABLE TOP-SIDE TA PACKAGE PART NUMBER MARKING SOP − D Tape and reel TLV2471QDRQ1 2471Q1 −−4400°CC ttoo 112255°CC SOP − D Tape and reel TLV2471AQDRQ1 2471AQ SOT23 − DBV Tape and reel TLV2471QDBVRQ1 471Q SOP − D Tape and reel TLV2472QDRQ1 2472Q1 −−4400°CC ttoo 112255°CC SOP − D Tape and reel TLV2472AQDRQ1 2472AQ MSOP − DGN Tape and reel TLV2472QDGNRQ1§ SOP − D Tape and reel TLV2474QDRQ1 2474Q1 SOP − D Tape and reel TLV2474AQDRQ1 2474AQ1 −−4400°°CC ttoo 112255°°CC TSSOP − PWP Tape and reel TLV2474QPWPRQ1 2474Q1 TSSOP − PWP Tape and reel TLV2474APWPRQ1 2474AQ1 †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. §Product Preview. TLV247x PACKAGE PINOUTS TLV2471 TLV2472 TLV2474 DBV PACKAGE D OR DGN PACKAGE D OR PWP PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OUT 1 5 VDD 1OUT 1 8 VDD 1OUT 1 14 4OUT 1IN− 2 7 2OUT GND 2 1IN+ 3 6 2IN− 1IN− 2 13 4IN− 1IN+ 3 12 4IN+ GND 4 5 2IN+ IN+ 3 4 IN− VDD 4 11 GND 2IN+ 5 10 3IN+ 2IN− 6 9 3IN− 2OUT 7 8 3OUT NC − No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V ID DD Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE θJC θJA TA ≤ 25°C PACKAGE (°C/W) (°C/W) POWER RATING D (8) 38.3 176 710 mW D (14) 26.9 122.3 1022 mW DBV (3) 55 324.1 385 mW DGN (8) 4.7 52.7 2370 mW PWP (14) 2.07 30.7 4070 mW recommended operating conditions MIN MAX UNIT Single supply 2.7 6 SSuuppppllyy vvoollttaaggee,, VVDDDD Split supply ±1.35 ±3 VV Common-mode input voltage range, VICR 0 VDD V Operating free-air temperature, TA −40 125 °C †Relative to GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 electrical characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 250 2200 TTLLVV224477xx VVIICC == VVDDDD//22,, Full range 2400 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVRROOSS ==== 55VV00DD ΩΩDD//22,, TTLLVV224477xxAA 25°C 250 1600 µVV Full range 1800 TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt VIICC = VDDDD/2, αVVIIOO offset voltage VVOO == VVDDDD//22,, 00..44 µVV//°°CC RS = 50 Ω VIICC = VDDDD/2, 25°C 1.5 50 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVOO == VVDDDD//22,, RS = 50 Ω Full range 300 ppAA VIICC = VDDDD/2, 25°C 2 50 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VVOO == VVDDDD//22,, RS = 50 Ω Full range 300 25°C 2.85 2.94 IIOOHH == −−22..55 mmAA Full range 2.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIICC == VVDDDD//22 25°C 2.6 2.74 VV IIOOHH == −−1100 mmAA Full range 2.5 25°C 0.07 0.15 IIOOLL == 22..55 mmAA Full range 0.2 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIICC == VVDDDD//22 25°C 0.2 0.35 VV IIOOLL == 1100 mmAA Full range 0.5 25°C 30 SSoouurrcciinngg Full range 20 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 25°C 30 mmAA SSiinnkkiinngg Full range 20 IO Output current VO = 0.5 V from rail 25°C ±22 mA LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee 25°C 90 116 AAVVDD amplification VVOO((PPPP)) == 11 VV,, RRLL == 1100 kkΩΩ Full range 88 ddBB ri(d) Differential input resistance 25°C 1012 Ω Common-mode input CIC capacitance f = 10 kHz 25°C 19.3 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 2 Ω VVIICC == 00 ttoo 33 VV,, 25°C 58 78 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo RS = 50Ω Full range 56 ddBB VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 68 90 SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 60 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 70 92 ddBB No load Full range 60 25°C 550 750 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == 11..55 VV,, NNoo llooaadd µµAA Full range 800 †Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 operating characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn VVROOL ((=PP 1PP0)) ==kΩ 00..88 VV,, CCLL == 115500 ppFF,, Fu2ll 5r°aCnge 10..16 1.4 VV//µss f = 100 Hz 25°C 28 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 15 nnVV//√√HHzz In Equivalent input noise current f = 1 kHz 25°C 0.405 pA/√Hz VVOO((PPPP)) == 22 VV,, AV = 1 0.02% TTHHDD ++ NN TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss nnooiissee RRLL == 1100 kkΩΩ,, AV = 10 2255°CC 0.1% ff == 11 kkHHzz AV = 100 0.5% Gain-bandwidth product f = 10 kHz, RL = 600 Ω 25°C 2.8 MHz V(STEP)PP = 2 V, 0.1% 1.5 AAVV == −−11,, CL = 10 pF, RL = 10 kΩ 0.01% 3.9 ttss SSeettttlliinngg ttiimmee 2255°°CC µss V(STEP)PP = 2 V, 0.1% 1.6 AAVV == −−11,, CL = 56 pF, RL = 10 kΩ 0.01% 4 φm Phase margin RL = 10 kΩ, CL = 1000 pF 25°C 61° Gain margin RL = 10 kΩ, CL = 1000 pF 25°C 15 dB †Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C. ‡Depending on package dissipation rating POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 250 2200 TTLLVV224477xx VVIICC == VVDDDD//22,, Full range 2400 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVRROOSS ==== 55VV00DD ΩΩDD//22,, TTLLVV224477xxAA 25°C 250 1600 µVV Full range 2000 TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt VIICC = VDDDD/2, αVVIIOO offset voltage VVOO == VVDDDD//22,, 00..44 µVV//°°CC RS = 50 Ω VIICC = VDDDD/2, 25°C 1.7 50 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVOO == VVDDDD//22,, RS = 50 Ω Full range 300 ppAA VIICC = VDDDD/2, 25°C 2.5 50 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VVOO == VVDDDD//22,, RS = 50 Ω Full range 300 25°C 4.85 4.96 IIOOHH == −−22..55 mmAA Full range 4.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIICC == VVDDDD//22 25°C 4.72 4.82 VV IIOOHH == −−1100 mmAA Full range 4.65 25°C 0.07 0.15 IIOOLL == 22..55 mmAA Full range 0.2 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIICC == VVDDDD//22 25°C 0.178 0.28 VV IIOOLL == 1100 mmAA Full range 0.35 25°C 110 SSoouurrcciinngg Full range 60 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 25°C 90 mmAA SSiinnkkiinngg Full range 60 IO Output current VO = 0.5 V from rail 25°C ±35 mA LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee 25°C 92 120 AAVVDD amplification VVOO((PPPP)) == 33 VV,, RRLL == 1100 kkΩΩ Full range 91 ddBB ri(d) Differential input resistance 25°C 1012 Ω Common-mode input CIC capacitance f = 10 kHz 25°C 18.9 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 1.8 Ω VVIICC == 00 ttoo 55 VV,, 25°C 62 84 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo RS = 50Ω Full range 58 ddBB VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 68 90 SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 60 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 70 92 ddBB No load Full range 60 25°C 600 900 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == 22..55 VV,, NNoo llooaadd µµAA Full range 1000 †Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 operating characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn VVROOL ((=PP 1PP0)) ==kΩ 22 VV,, CCLL == 115500 ppFF,, Fu2ll 5r°aCnge 10..17 1.5 VV//µss f = 100 Hz 25°C 28 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 15 nnVV//√√HHzz In Equivalent input noise current f = 1 kHz 25°C 0.39 pA/√Hz VVOO((PPPP)) == 44 VV,, AV = 1 0.01% TTHHDD ++ NN TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss nnooiissee RRLL == 1100 kkΩΩ,, AV = 10 2255°CC 0.05% ff == 11 kkHHzz AV = 100 0.3% Gain-bandwidth product f = 10 kHz, RL = 600 Ω 25°C 2.8 MHz V(STEP)PP = 2 V, 0.1% 1.8 AAVV == −−11,, CL = 10 pF, RL = 10 kΩ 0.01% 3.3 ttss SSeettttlliinngg ttiimmee 2255°°CC µss V(STEP)PP = 2 V, 0.1% 1.7 AAVV == −−11,, CL = 56 pF, RL = 10 kΩ 0.01% 3 φm Phase margin RL = 10 kΩ, CL = 1000 pF 25°C 68° Gain margin RL = 10 kΩ, CL = 1000 pF 25°C 23 dB †Full range is −40°C to 125°C for Q suffix. If not specified, full range is −40°C to 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIB Input bias current vvss FFrreeee--aaiirr tteemmppeerraattuurree 33,, 44 IIO Input offset current VOH High-level output voltage vs High-level output current 5, 7 VOL Low-level output voltage vs Low-level output current 6, 8 Zo Output impedance vs Frequency 9 IDD Supply current vs Supply voltage 10 PSRR Power supply rejection ratio vs Frequency 11 CMRR Common-mode rejection ratio vs Frequency 12 Vn Equivalent input noise voltage vs Frequency 13 VO(PP) Maximum peak-to-peak output voltage vs Frequency 14, 15 AVD Differential voltage gain and phase vs Frequency 16, 17 φm Phase margin vs Load capacitance 18, 19 Gain margin vs Load capacitance 20, 21 Gain-bandwidth product vs Supply voltage 22 vs Supply voltage 23 SSRR SSlleeww rraattee vs Free-air temperature 24, 25 Crosstalk vs Frequency 26 THD+N Total harmonic distortion + noise vs Frequency 27, 28 VO Large and small signal follower vs Time 29 − 32 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS INPUT BIAS AND INPUT OFFSET INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE CURRENTS vs vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE 600 600 50 µInput Offset Voltage −−V −−2442000000000 VTDAD=2=53° V C µInput Offset Voltage −−V−−2442000000000 V TDAD==255 V°C − Input Bias Current − pA − Input Offset Current − pA 12340000 VDD=3 V IIB VIO−600 VIO−600 IIB IIO 0 IIO −800 −800 −10 −0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 −0.5 0.5 1.5 2.5 3.5 4.5 5.5 −55 −35 −15 5 25 45 65 85 105 125 VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V TA − Free-Air Temperature − °C Figure 1 Figure 2 Figure 3 INPUT BIAS AND INPUT OFFSET CURRENTS HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 50 3.5 3.0 I− Input Bias Current − pAIB I− Input Offset Current − pAIO 123400000 VDD=5 V IIBIIO − High-Level Output Voltage − VOH 011223......505050 TTTTAAAA====−128245550°°°°CCCC VDD=3 V V− Low-Level Output Voltage − VOL 01122.....50505 TTTTVAAAAD====−1D2824=55503°°°°CC CCV V −10 0.0 0.0 −55 −35 −15 5 25 45 65 85 105 125 0 10 20 30 40 50 60 0 10 20 30 40 50 TA − Free-Air Temperature − °C IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 4 Figure 5 Figure 6 HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE OUTPUT IMPEDANCE vs vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT FREQUENCY 5.5 5.0 1000 − High-Level Output Voltage − V 112233445.........050505050 TTTAAA===1282555°°°CCC VDD=5 V − Low-Level Output Voltage − VL 11223344........05050505 TTTTAAAA====−128245550°°°°CCCC Ω− Output Impedance −Zo1001.0011 AVTVAD=A=1DV20==531° 0C&0 5 V AV=1 H O O 0.5 TA=−40°C V 0.5 V VDD=5 V 0.0 0.0 0.01 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA f − Frequency − Hz Figure 7 Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS SUPPLY CURRENT POWER SUPPLY REJECTION RATIO COMMON-MODE REJECTION RATIO vs vs vs SUPPLY VOLTAGE FREQUENCY FREQUENCY upply Current − mA 0000001.......4567890 TA=85°C TATT=AA−==42105°2C°5C°C Supply Rejection Ratio − dB 10678900000 PSRR−PSRR+ VRRTADFI===D525=05 3 Ω°k CΩ& 5 V n-Mode Rejection Ratio − dB1111012389000000 VVDICD==25.5 V V I− SDD 0000....0123 APSeHVr=D C N1h=a nVnDeDl − Power PSRR 345000 CMRR − Commo 567000 VVDICD==13.5 V V 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M VDD − Supply Voltage − V f − Frequency − Hz f − Frequency − Hz Figure 10 Figure 11 Figure 12 MAXIMUM PEAK-TO-PEAK MAXIMUM PEAK-TO-PEAK EQUIVALENT NOISE VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs vs FREQUENCY V FREQUENCY V FREQUENCY nV/Hz− Equivalent Input Noise Voltage −Vn 1234567800000000010 100 VAVTADVIN1==Dk=2 =1 5V30°D C&D 5/2 V10k 100k − Maximum Peak-To-Peak Output Voltage − O(PP) 001122334455............05050505050510k VOVO(P(PP)P=)3= 5V V 100k TRTHAL==D21+50N °k C≤Ω2.0% 1M − Maximum Peak-To-Peak Output Voltage − O(PP) 001122334455............05050505050510k VVOO((PPPP))==53 VV 100kTRTHAL==D62+05N0° C ≤Ω2.0% 1M f − Frequency − Hz V f − Frequency − Hz V f − Frequency − Hz Figure 13 Figure 14 Figure 15 DIFFERENTIAL VOLTAGE GAIN AND PHASE DIFFERENTIAL VOLTAGE GAIN AND PHASE vs vs FREQUENCY FREQUENCY 100 45 100 45 Gain − dB 6800 VRCTADLL===D602=05±0°3C Ω −045 Gain − dB 6800 VRCTADLL===D602=05±0°5C Ω −045 e e ntial Voltag 2400 −−19305 °Phase − ntial Voltag 2400 −−19305 °Phase − e e er er Diff 0 −180 Diff 0 −180 − − D−20 −225 D−20 −225 V V A A −40 −270 −40 −270 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M Frequency − Hz Frequency − Hz Figure 16 Figure 17 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS PHASE MARGIN PHASE MARGIN GAIN MARGIN vs vs vs LOAD CAPACITANCE LOAD CAPACITANCE LOAD CAPACITANCE 90 100 0 °− Phase Margin − m 345678000000 VRTSAeDLe==DR 12F=n05i3ug °k CluVlΩ=r e1 0402 Rnull=50Rnull=20 °− Phase Margin − m 34567890000000 VRTSAeDLRe==D n12F=u05i5gl °lkV=CuΩ1re0 042 RRnnuullll==2500 Gain Margin − dB 1120505 VRTADL==D12=05R3 °nkVCΩull=20 Rnull=100 Rnull=0 φ 20 φ 20 25 10 Rnull=0 10 Rnull=0 Rnull=50 0 0 30 100 1k 10k 100k 100 1k 10k 100k 100 1k 10k 100k CL − Load Capacitance − pF CL − Load Capacitance − pF CL − Load Capacitance − pF Figure 18 Figure 19 Figure 20 GAIN MARGIN GAIN-BANDWIDTH PRODUCT SLEW RATE vs vs vs LOAD CAPACITANCE SUPPLY VOLTAGE SUPPLY VOLTAGE 2.0 0 4.0 1.8 SR− 5 Hz 3.5 RL=10 kΩ 1.6 Rnull=0 M s Gain Margin − dB 1232150050 RnullR=5n0ull=20 Rnull=1VR0DL0=D1=05 kVΩ Gain-Bandwidth Product − 011223......505050 CfT=AL1==012 k15H °pCzF RL=600 Ω µSR − Slew Rate − V/ 0000111.......2468024 VAROVL==(P1−0P1 )k=Ω1.5 V SR+ TA=25°C CL=150 pF 0.0 35 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 100 1k 10k 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 CL − Load Capacitance − pF VDD − Supply Voltage − V VDD −F Sigupuprley V2o3ltage − V Figure 21 Figure 22 SLEW RATE SLEW RATE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 2.00 2.00 1.75 1.75 SR− 1.50 SR+ 1.50 µw Rate − V/s11..0205 SR− µw Rate − V/s11..0205 SR+ SR − Sle000...257505 VRCDLL==D11=053 0k ΩVpF SR − Sle000...257505 VRCDLL==D11=055 0k ΩVpF AV=−1 AV=−1 0.00 0.00 −55 −35 −15 5 25 45 65 85 105 125 −55 −35 −15 5 25 45 65 85 105 125 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 24 Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS TOTAL HARMONIC TOTAL HARMONIC CROSSTALK DISTORTION PLUS NOISE DISTORTION PLUS NOISE vs vs vs FREQUENCY FREQUENCY FREQUENCY −200 VARDVL=D = 6 =10 30 VΩ & 5V on + Noise 1 AV = 100 on + Noise 1 AV = 100 Crosstalk − dB−−−−−−111246840000000 V AI(lPl CPh)=a2nVnels THD+N−Total Harmonic Distorti 0.00.11 AAVRVTVVAD0L D===== 11 =1220 05 3V ° kCVPΩP THD+N−Total Harmonic Distorti 0.00.11 AARVVTVVAD0L ==D=== 11 =124005 5V °k CVPΩP −160 0.001 0.001 10 100 1 k 10 k 100 k 10 100 1k 10k 100k 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 26 Figure 27 Figure 28 LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER PULSE RESPONSE PULSE RESPONSE PULSE RESPONSE vs vs vs TIME TIME TIME VI (2 V/DIV) VI (50 mV/DIV) VI (2 V/DIV) VDD = 3 V RL = 10 kΩ e e e CL = 8 pF ag ag ag f = 1 MHz Volt VO (1 V/DIV) Volt Volt TA = 25°C ut ut ut utp utp VO (1 V/DIV) utp O O O − VO VRDL D= 1=0 3k ΩV − VO VRDL D= 1=0 5k ΩV − VO CL = 8 pF CL = 8 pF VO (50 mV/DIV) f = 85 kHz f = 85 kHz TA = 25°C TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 t − Time − µs t − Time − µs t − Time − µs Figure 29 Figure 30 Figure 31 SMALL SIGNAL FOLLOWER PULSE RESPONSE vs TIME VI (50 mV/DIV) VDD = 5 V ge RCLL == 180 p kFΩ a ut Volt fT A= 1= M25H°zC p ut O − O V VO (50 mV/DIV) 0 100 200 300 400 500 t − Time − µs Figure 32 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION _ Rnull + RL CL Figure 33 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (R ) with the output of the amplifier, as shown NULL in Figure 34. A minimum value of 20 Ω should work well for most applications. RF RG Input _ RNULL Output + CLOAD Figure 34. Driving a Capacitive Load offset voltage The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage. RF IIB− RG + − VI VO + RS (cid:2) IIB+(cid:4) (cid:2) (cid:4) (cid:2) (cid:4) (cid:2) (cid:4) R R VOO(cid:1)VIO 1(cid:3) RF (cid:5)IIB(cid:3)RS 1(cid:3) RF (cid:5)IIB–RF G G Figure 35. Output Offset Voltage Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 36). RG RF − + VO VI R1 C1 f (cid:1) 1 –3dB 2(cid:1)R1C1 (cid:2) (cid:4) V R (cid:2) (cid:4) O (cid:1) 1(cid:3) F 1 V R 1(cid:3)sR1C1 I G Figure 36. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) VI + R1 R2 _ f (cid:1) 1 –3dB 2(cid:1)RC C2 RF RG = RF (2 − 1 ) RG Q Figure 37. 2-Pole Low-Pass Sallen-Key Filter 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general PowerPAD design considerations The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 38(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 38. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. Thermal Pad Area Quad Single or Dual 68 mils x 70 mils) with 5 vias 78 mils x 94 mils) with 9 vias (Via diameter = 13 mils (Via diameter = 13 mils) Figure 39. PowerPAD PCB Etch and Via Pattern PowerPAD is a trademark of Texas Instruments Incorporated. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general PowerPAD design considerations (continued) 1. Prepare the PCB with a top side etch pattern as shown in Figure 39. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θ , the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: JA (cid:2) (cid:4) T –T P (cid:1) MAX A D (cid:1) JA Where: P = Maximum power dissipation of TLV247x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A θJA = θJC + θCA θ = Thermal coefficient from junction to case JC θ = Thermal coefficient from case to ambient air (°C/W) CA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general PowerPAD design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 7 PWP Package TJ = 150°C Low-K Test PCB 6 θJA = 29.7°C/W W SOT-23 Package on − 5 LθJoAw -=K 3 T2e4s°tC P/WCB ati DGN Package p Low-K Test PCB ssi 4 θJA = 52.3°C/W Di SOIC Package er Low-K Test PCB ow 3 θJA = 176°C/W P m u m 2 xi a M 1 0 −55 −40−25−10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 40. The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 41 to Figure 46 show this effect, along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using V = 3 V, there DD is generally not a heat problem with an ambient air temperature of 70°C. But, when using V = 5 V, the DD packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases and the heat dissipation JA capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general PowerPAD design considerations (continued) TLV2471† TLV2471† MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 180 Maximum Output Maximum Output A Current Limit Line A Current Limit Line m 160 m 160 − − nt 140 nt 140 rre B Packages With rre B u u C 120 θJA ≤ 110°C/W C 120 put at TA = 125°C put ut 100 or ut 100 S O θJA ≤ 355°C/W S O A RM 80 A at TA = 70°C RM 80 m m Packages With u 60 u 60 m Safe Operating Area m θJA ≤ 210°C/W axi axi at TA = 70°C M 40 M 40 I− ||O 200 VTTAJD D == =112 5±50 °3°C CV I− ||O 200 VTTAJD D == =112 5±50 °5°C CV Safe Operating Area 0 0.25 0.5 0.75 1 1.25 1.5 0 0.5 1 1.5 2 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 41 Figure 42 TLV2472† TLV2472† MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 180 Maximum Output Maximum Output A Current Limit Line A Current Limit Line m 160 m 160 − − nt 140 nt 140 e e rr B rr u u C 120 Packages With C 120 put C θJA ≤ 55°C/W put Out 100 at TA = 125°C Out 100 S or S C RM 80 θJA ≤ 178°C/W RM 80 m at TA = 70°C m B u 60 u 60 m m Packages With axi axi θJA ≤ 105°C/W I− M||O 42000 VTTAJD D == =112 5±50 °3°C CV Safe Operating Area I− M||O 42000 VTTAJD D == =112 5±50 °5°C CV Safe Opate rTaAti n= g7 0A°rCea 0 0.25 0.5 0.75 1 1.25 1.5 0 0.5 1 1.5 2 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 43 Figure 44 †A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION general PowerPAD design considerations (continued) TLV2474† TLV2474† MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 180 Maximum Output Maximum Output A Current Limit Line A Current Limit Line m 160 m 160 − − nt 140 nt 140 e D e r r r r D u u C 120 C 120 ut ut p p ut 100 ut 100 O O S S M 80 Packages With M 80 um R 60 C θaJtA T A≤ 8=8 7°0C°/CW um R 60 VTJD D = =1 5±0 5° CV C xim xim TA = 125°C a a M 40 M 40 − | VDD = ±3 V − | Packages With IO 20 TJ = 150°C IO 20 θJA ≤ 52°C/W | TA = 125°C Safe Operating Area | Safe Operating Area at TA = 70°C 0 0 0 0.25 0.5 0.75 1 1.25 1.5 0 0.5 1 1.5 2 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 45 Figure 46 †A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14) 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:12)(cid:8)(cid:9)(cid:10) (cid:13)(cid:12)(cid:14)(cid:15)(cid:2)(cid:16) (cid:17)(cid:13) (cid:18)(cid:19)(cid:19)(cid:8)µ(cid:12)(cid:20)(cid:21)(cid:22) (cid:4)(cid:23)(cid:24)(cid:8)(cid:14)(cid:25)(cid:26) (cid:27)(cid:12)(cid:15)(cid:2)(cid:8)(cid:1)(cid:17)(cid:8)(cid:27)(cid:12)(cid:15)(cid:2) (cid:15)(cid:28)(cid:29)(cid:30)(cid:1)(cid:20)(cid:17)(cid:30)(cid:1)(cid:29)(cid:30)(cid:1) (cid:25)(cid:15)(cid:31)(cid:25)(cid:8)!(cid:27)(cid:15)(cid:3)" (cid:17)(cid:29)"(cid:27)(cid:12)(cid:1)(cid:15)(cid:17)(cid:28)(cid:12)(cid:2) (cid:12)(cid:14)(cid:29)(cid:2)(cid:15)(cid:13)(cid:15)"(cid:27)# SGLS180B − AUGUST 2003 − REVISED APRIL 2008 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 47 are generated using the TLV247x typical electrical and operating characteristics at T = 25°C. Using this information, output A simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (cid:1) (cid:1) Maximum positive output voltage swing Unity-gain frequency (cid:1) (cid:1) Maximum negative output voltage swing Common-mode rejection ratio (cid:1) (cid:1) Slew rate Phase margin (cid:1) (cid:1) Quiescent power dissipation DC output resistance (cid:1) (cid:1) Input bias current AC output resistance (cid:1) (cid:1) Open-loop voltage amplification Short-circuit output current limit NOTE 1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VDD + rp rd1 rd2 rss css egnd fb ro2 c1 − 7 11 12 + c2 1 vlim IN+ + 9 r2 6 − vc D D + 8 − 2 vb ga G G IN− 53 − gcm ioff ro1 S S OUT dp dlp dln 5 10 91 90 92 iss dc + + − vlp hlim vln GND − − + 4 − ve + 54 de * TLV247x operational amplifier ”macromodel” subcircuit iss 10 4 dc 10.714E−6 * created using Parts release 8.0 on 4/27/99 at 14:31 hlim 90 0 vlim 1K * Parts is a MicroSim product. ioff 0 6 dc 75E−9 * j1 11 2 10 jx1 * connections: non−inverting input j2 12 1 10 jx2 * | inverting input r2 6 9 100.00E3 * | | positive power supply rd1 3 11 12.527E3 * | | | negative power supply rd2 3 12 12.527E3 * | | | | output ro1 8 5 10 * | | | | | ro2 7 99 10 .subckt TLV247x 1 2 3 4 5 rp 3 4 3.8023E3 * rss 10 99 18.667E6 c1 11 12 1.1094E−12 vb 9 0 dc 0 c2 6 7 5.5000E−12 vc 3 53 dc .842 css 10 99 556.53E−15 ve 54 4 dc .842 dc 5 53 dy vlim 7 8 dc 0 de 54 5 dy vlp 91 0 dc 110 dlp 90 91 dx vln 0 92 dc 110 dln 92 90 dx .model dx D(Is=800.00E−18) dp 4 3 dx .model dy D(Is=800.00E−18 Rs=1m Cjo=10p) egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 .model jx1 NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1) fb 7 99 poly(5) vb vc ve vlp vln 0 .model jx2 NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1) + 39.614E6 −1E3 1E3 40E6 −40E6 .ends ga 6 0 11 12 79.828E−6 *$ gcm 0 6 10 99 32.483E−9 Figure 47. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2471AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2471AQ & no Sb/Br) TLV2471QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 471Q & no Sb/Br) TLV2472AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472AQ & no Sb/Br) TLV2472QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472Q1 & no Sb/Br) TLV2472QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472Q1 & no Sb/Br) TLV2474APWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474AQ1 & no Sb/Br) TLV2474AQDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474AQ1 & no Sb/Br) TLV2474QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474Q1 & no Sb/Br) TLV2474QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474Q1 & no Sb/Br) TLV2474QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2471-Q1, TLV2471A-Q1, TLV2472-Q1, TLV2472A-Q1, TLV2474-Q1, TLV2474A-Q1 : •Catalog: TLV2471, TLV2471A, TLV2472, TLV2472A, TLV2474, TLV2474A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2471QDBVRQ1 SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2471QDBVRQ1 SOT-23 DBV 5 3000 182.0 182.0 20.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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