TLV2470,, TLV2471 ® TLV2472, TLV2473 ® TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 FAMILY OF 600μA/Ch 2.8MHz RAIL-TO-RAIL INPUT/OUTPUT HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN FEATURES DESCRIPTION • CMOSRail-To-RailInput/Output The TLV247x is a family of CMOS rail-to-rail input/ • InputBiasCurrent:2.5pA output operational amplifiers that establishes a new • LowSupplyCurrent:600μA/Channel performance point for supply current versus ac performance. These devices consume just • Ultra-LowPowerShutdownMode: 600μA/channel while offering 2.8MHz of IDD(SHDN):350nA/chat3V gain-bandwidth product. Along with increased ac IDD(SHDN):1000nA/chat5V performance, the amplifier provides high output drive • Gain-BandwidthProduct:2.8MHz capability, solving a major shortcoming of older micropower operational amplifiers. The TLV247x can • HighOutputDriveCapability: swing to within 180mV of each supply rail while – – 10mAat180mV driving a 10mA load. For non-RRO applications, the – – 35mAat500mV TLV247x can supply – 35mA at 500mV off the rail. • InputOffsetVoltage:250μV(typ) Both the inputs and outputs swing rail-to-rail for increased dynamic range in low-voltage applications. • SupplyVoltageRange:2.7Vto6V This performance makes the TLV247x family ideal • Ultra-SmallPackaging for sensor interface, portable medical equipment, andotherdataacquisitioncircuits. – SOT23-5or-6(TLV2470/1) – MSOP-8or-10(TLV2472/3) FAMILYPACKAGETABLE NUMBEROF PACKAGETYPES DEVICE SHUTDOWN UNIVERSALEVMBOARD CHANNELS PDIP SOIC SOT23 TSSOP MSOP TLV2470 1 8 8 6 — — Yes TLV2471 1 8 8 5 — — — TLV2472 2 8 8 — — 8 — RefertotheEVMSelection TLV2473 2 14 14 — — 10 Yes Guide(SLOU060) TLV2474 4 14 14 — 14 — — TLV2475 4 16 16 — 16 — Yes ASELECTIONOFSINGLE-SUPPLYOPERATIONALAMPLIFIERPRODUCTS(1) V V BW SLEWRATE I (perchannel) DEVICE DD IO DD OUTPUTDRIVE RAIL-TO-RAIL (V) (μV) (MHz) (V/μs) (μA) TLV247X 2.7–6.0 250 2.8 1.5 600 – 35mA I/O TLV245X 2.7–6.0 20 0.22 0.11 23 – 10mA I/O TLV246X 2.7–6.0 150 6.4 1.6 550 – 90mA I/O TLV277X 2.5–6.0 360 5.1 10.5 1000 – 10mA O (1) Allspecificationsmeasuredat5V. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstruments. MicrosimPARTSisatrademarkofMicroSimCorporation. MicrosimPSpiceisaregisteredtrademarkofMicroSimCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1999–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TLV2470andTLV2471AVAILABLEOPTIONS(1) PACKAGEDDEVICES T SOT23 A SMALLOUTLINE(D)(2) PLASTICDIP(P) (DBV)(2) SYMBOL 0(cid:176) Cto+70(cid:176) C TLV2470CD TLV2470CDBV VAUC TLV2470CP TLV2471CD TLV2471CDBV VAVC TLV2471CP TLV2470ID TLV2470IDBV VAUI TLV2470IP TLV2471ID TLV2471IDBV VAVI TLV2471IP –40(cid:176) Cto+125(cid:176) C TLV2470AID TLV2470AIP —— —— TLV2471AID TLV2471AIP (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Thispackageisavailabletapedandreeled.Toorderthispackagingoption,addanRsuffixtothepartnumber(forexample, TLV2470CDR). TLV2472ANDTLV2473AVAILABLEOPTIONS(1) PACKAGEDDEVICES TA SMALL MSOP MSOP PLASTICDIP PLASTICDIP OUTLINE (D)(2) (DGN)(2) SYMBOL(3) (DGQ)(2) SYMBOL(3) (N) (P) 0(cid:176) Cto+70(cid:176) C TLV2472CD TLV2472CDGN xxTIABU — — — TLV2472CP TLV2473CD — — TLV2473CDGQ xxTIABW TLV2473CN — TLV2472ID TLV2472IDGN xxTIABV — — — TLV2472IP TLV2473ID — — TLV2473IDGQ xxTIABX TLV2473IN — –40(cid:176) Cto+125(cid:176) C TLV2472AID — TLV2472AIP —— —— —— —— TLV2473AID TLV2473AIN — (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Thispackageisavailabletapedandreeled.Toorderthispackagingoption,addanRsuffixtothepartnumber(forexample, TLV2472CDR). (3) xxrepresentsthedevicedatecode. TLV2474andTLV2475AVAILABLEOPTIONS(1) PACKAGEDDEVICES T A SMALLOUTLINE(D)(2) PLASTICDIP(N) TSSOP(PWP)(2) 0(cid:176) Cto+70(cid:176) C TLV2474CD TLV2474CN TLV2474CPWP TLV2475CD TLV2475CN TLV2475CPWP TLV2474ID TLV2474IN TLV2474IPWP TLV2475ID TLV2475IN TLV2475IPWP –40(cid:176) Cto+125(cid:176) C TLV2474AID TLV2474AIN TLV2474AIPWP TLV2475AID TLV2475AIN TLV2475AIPWP (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Thispackageisavailabletapedandreeled.Toorderthispackagingoption,addanRsuffixtothepartnumber(forexample, TLV2474CDR). 2 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TLV247X PACKAGE PINOUTS TLV2470 TLV2470 TLV2471 DBV PACKAGE D OR P PACKAGE DBV PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OUT 1 6 VDD NC 1 8 SHDN OUT 1 5 VDD IN− 2 7 VDD GND 2 5 SHDN IN+ 3 6 OUT GND 2 GND 4 5 NC IN+ 3 4 IN− IN+ 3 4 IN− TLV2471 TLV2472 TLV2473 D OR P PACKAGE D, DGN, OR P PACKAGE DGQ PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) NC 1 8 NC 1OUT 1 8 VDD 1OUT 1 10 VDD IN− 2 7 VDD 1IN− 2 7 2OUT 1IN− 2 9 2OUT IN+ 3 6 OUT 1IN+ 3 6 2IN− 1IN+ 3 8 2IN− GND 4 5 NC GND 4 5 2IN+ GND 4 7 2IN+ 1SHDN 5 6 2SHDN TLV2473 TLV2474 TLV2475 D OR N PACKAGE D, N, OR PWP PACKAGE D, N, OR PWP PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) 1OUT 1 14 VDD 1OUT 1 14 4OUT 1OUT 1 16 4OUT 1IN− 2 13 2OUT 1IN− 2 13 4IN− 1IN− 2 15 4IN− 1IN+ 3 12 2IN− 1IN+ 3 12 4IN+ 1IN+ 3 14 4IN+ GND 4 11 2IN+ VDD 4 11 GND VDD 4 13 GND NC 5 10 NC 2IN+ 5 10 3IN+ 2IN+ 5 12 3IN+ 1SHDN 6 9 2SHDN 2IN− 6 9 3IN− 2IN− 6 11 3IN− NC 7 8 NC 2OUT 7 8 3OUT 2OUT 7 10 3OUT 1/2SHDN 8 9 3/4SHDN NC − No internal connection TYPICALPIN1INDICATORS Pin 1 Printed or Pin 1 Pin 1 Pin 1 Molded Dot Stripe Beveled Edges Molded U Shape SubmitDocumentationFeedback 3

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 DESCRIPTION (CONTINUED) Three members of the family (TLV2470/3/5) offer a shutdown terminal for conserving battery life in portable applications. During shutdown, the outputs are placed in a high-impedance state and the amplifier consumes only 350nA/channel. The family is fully specified at 3V and 5V across an expanded industrial temperature range (–40(cid:176) Cto +125(cid:176) C). The singles and duals are available in the SOT23 and MSOP packages, while the quads are available in TSSOP. The TLV2470 offers an amplifier with shutdown functionality all in a SOT23-6 package, makingitperfectforhigh-densitypower-sensitivecircuits. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. UNIT Supplyvoltage,V (2) 7V DD Differentialinputvoltage,V – V ID DD Continuoustotalpowerdissipation SeeDissipationRatingtable C-suffix 0(cid:176) Cto+70(cid:176) C Operatingfree-airtemperaturerange,T A I-suffix –40(cid:176) Cto+125(cid:176) C Maximumjunctiontemperature,T +150(cid:176) C J Storagetemperaturerange,T –65(cid:176) Cto+150(cid:176) C stg Leadtemperature1,6mm(1/16inch)fromcasefor10seconds +260(cid:176) C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialvoltages,arewithrespecttoGND. DISSIPATION RATING TABLE θ θ T £ +25(cid:176) C PACKAGE ((cid:176) CJ/CW) ((cid:176) CJ/AW) POWAERRATING D(8) 38.3 176 710mW D(14) 26.9 122.3 1022mW D(16) 25.7 114.7 1090mW DBV(5) 55 324.1 385mW DBV(6) 55 294.3 425mW DGN(8) 4.7 52.7 2.37W DGQ(10) 4.7 52.3 2.39W N(14,16) 32 78 1600mW P(8) 41 104 1200mW PWP(14) 2.07 30.7 4.07W PWP(16) 2.07 29.7 4.21W RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Singlesupply 2.7 6 Supplyvoltage,V V DD Splitsupply – 1.35 – 3 Common-modeinputvoltagerange,V 0 V V ICR DD C-suffix 0 +70 Operatingfree-airtemperature,T (cid:176) C A I-suffix –40 +125 V 2 Shutdownon/offvoltagelevel(1) IH V V 0.8 IL (1) RelativetoGND. 4 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS Atspecifiedfree-airtemperature,V =3V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 250 2200 TLV247x Fullrange 2400 V Inputoffsetvoltage μV IO +25(cid:176) C 250 1600 TLV247xA Fullrange 1800 αVIO Tinepmutpoefrfasteutrevocltoaegfeficientof VIC=VDD/2, 0.4 μV/(cid:176) C V =V /2,R =50W O DD S 25(cid:176) C 1.5 50 I Inputoffsetcurrent TLV247xC Fullrange 100 IO TLV247xI Fullrange 300 pA +25(cid:176) C 2 50 I Inputbiascurrent TLV247xC Fullrange 100 IB TLV247xI Fullrange 300 +25(cid:176) C 2.85 2.94 I =–2.5mA OH Fullrange 2.8 V High-leveloutputvoltage V =V /2 V OH IC DD +25(cid:176) C 2.6 2.74 I =–10mA OH Fullrange 2.5 +25(cid:176) C 0.07 0.15 I =2.5mA OL Fullrange 0.2 V Low-leveloutputvoltage V =V /2 V OL IC DD +25(cid:176) C 0.2 0.35 I =10mA OL Fullrange 0.5 +25(cid:176) C 30 Sourcing Fullrange 20 I Short-circuitoutputcurrent mA OS +25(cid:176) C 30 Sinking Fullrange 20 I Outputcurrent V =0.5Vfromrail +25(cid:176) C – 22 mA O O A Large-signaldifferential V =1V,R =10kW +25(cid:176) C 90 116 dB VD voltageamplification O(PP) L Fullrange 88 r Differentialinputresistance +25(cid:176) C 1012 W i(d) C Common-modeinput f=10kHz +25(cid:176) C 19.3 pF IC capacitance z Closed-loopoutput f=10kHz,A =10 +25(cid:176) C 2 W o impedance V +25(cid:176) C 61 78 CMRR Common-moderejectionratio V =0Vto3V, TLV247xC Fullrange 59 dB IC RS=50W TLV247xI Fullrange 58 (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforC-suffixand–40(cid:176) Cto+125(cid:176) CforI-suffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. SubmitDocumentationFeedback 5

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) Atspecifiedfree-airtemperature,V =3V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 74 90 V =2.7Vto6V,V =V /2,Noload DD IC DD Supplyvoltagerejectionratio Fullrange 66 k dB SVR (ΔVDD/ΔVIO) +25(cid:176) C 77 92 V =3Vto5V,V =V /2,Noload DD IC DD Fullrange 68 +25(cid:176) C 550 750 I Supplycurrent(perchannel) V =1.5V,Noload μA DD O Fullrange 800 +25(cid:176) C 350 1500 Supplycurrentinshutdown I mode(TLV2470,TLV2473, TLV247xC Fullrange 2000 nA DD(SHDN) TLV2475)(perchannel) SHDN=0V TLV247xI Fullrange 4000 (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforC-suffixand–40(cid:176) Cto+125(cid:176) CforI-suffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. OPERATING CHARACTERISTICS Atspecifiedfree-airtemperature,V =3V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 1.1 1.4 SR Slewrateatunitygain V =0.8V,C =150pF,R =10kW V/μs O(PP) L L Fullrange 0.6 V Equivalentinputnoise f=100Hz +25(cid:176) C 28 nV/(cid:214) Hz n voltage f=1kHz +25(cid:176) C 15 I Equivalentinputnoise f=1kHz +25(cid:176) C 0.405 pA/(cid:214) Hz n current A =1 0.02% V =2V, V THD+N Totalharmonic RO=(PP1)0kW , A =10 +25(cid:176) C 0.1% distortionplusnoise L V f=1kHz A =100 0.5% V t Amplifierturn-ontime +25(cid:176) C 5 μs (on) R =OPEN(2) t Amplifierturn-offtime L +25(cid:176) C 250 ns (off) Gain-bandwidth f=10kHz,R =600W +25(cid:176) C 2.8 MHz product L V =2V, 0.1% 1.5 (STEP)PP A =–1,C =10pF, V L R =10kW 0.01% 3.9 t Settlingtime L +25(cid:176) C μs s V =2V, 0.1% 1.6 (STEP)PP A =–1,C =56pF, V L R =10kW 0.01% 4 L Φ Phasemargin R =10kW ,C =1000pF +25(cid:176) C 61 (cid:176) m L L Gainmargin R =10kW ,C =1000pF +25(cid:176) C 15 dB L L (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforC-suffixand–40(cid:176) Cto+125(cid:176) CforI-suffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. (2) DisableandenabletimearedefinedastheintervalbetweenapplicationoflogicsignaltoSHDNandthepointatwhichthesupply currenthasreachedhalfitsfinalvalue. 6 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS Atspecifiedfree-airtemperature,V =5V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 250 2200 TLV247x Fullrange 2400 V Inputoffsetvoltage μV IO +25(cid:176) C 250 1600 TLV247xA Fullrange 2000 αVIO Tofefsmeptevroalttuargeecoefficientofinput VVIC==VVDD//22,, 0.4 μV/(cid:176) C O DD RS=50W +25(cid:176) C 1.7 50 I Inputoffsetcurrent TLV247xC Fullrange 100 IO TLV247xI Fullrange 300 pA +25(cid:176) C 2.5 50 I Inputbiascurrent TLV247xC Fullrange 100 IB TLV247xI Fullrange 300 +25(cid:176) C 4.85 4.96 I =–2.5mA OH Fullrange 4.8 V High-leveloutputvoltage V =V /2 V OH IC DD +25(cid:176) C 4.72 4.82 I =–10mA OH Fullrange 4.65 +25(cid:176) C 0.07 0.15 I =2.5mA OL Fullrange 0.2 V Low-leveloutputvoltage V =V /2 V OL IC DD +25(cid:176) C 0.178 0.28 I =10mA OL Fullrange 0.35 +25(cid:176) C 110 Sourcing Fullrange 60 I Short-circuitoutputcurrent mA OS +25(cid:176) C 90 Sinking Fullrange 60 I Outputcurrent V =0.5Vfromrail +25(cid:176) C – 35 mA O O A Large-signaldifferentialvoltage V =3V,R =10kW +25(cid:176) C 92 120 dB VD amplification O(PP) L Fullrange 91 r Differentialinputresistance +25(cid:176) C 1012 W i(d) C Common-modeinputcapacitance f=10kHz +25(cid:176) C 18.9 pF IC z Closed-loopoutputimpedance f=10kHz,A =10 +25(cid:176) C 1.8 W o V +25(cid:176) C 64 84 CMRR Common-moderejectionratio V =0Vto5V, TLV247xC Fullrange 63 dB IC RS=50W TLV247xI Fullrange 58 V =2.7Vto6V,V =V /2, +25(cid:176) C 74 90 DD IC DD Supplyvoltagerejectionratio Noload Fullrange 66 k dB SVR (ΔVDD/ΔVIO) V =3Vto5V,V =V /2, +25(cid:176) C 77 92 DD IC DD Noload Fullrange 66 +25(cid:176) C 600 900 I Supplycurrent(perchannel) V =2.5V,Noload μA DD O Fullrange 1000 (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforC-suffixand–40(cid:176) Cto+125(cid:176) CforI-suffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. SubmitDocumentationFeedback 7

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) Atspecifiedfree-airtemperature,V =5V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 1000 2500 Supplycurrentinshutdownmode nA I (TLV2470,TLV2473,TLV2475) SHDN=0V TLV247xC Fullrange 3000 DD(SHDN) (perchannel) TLV247xI Fullrange 6000 nA (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforC-suffixand–40(cid:176) Cto+125(cid:176) CforI-suffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. OPERATING CHARACTERISTICS Atspecifiedfree-airtemperature,V =5V,unlessotherwisenoted. DD PARAMETER TESTCONDITIONS T (1) MIN TYP MAX UNIT A +25(cid:176) C 1.1 1.5 SR Slewrateatunitygain V =2V,C =150pF,R =10kW V/μs O(PP) L L Fullrange 0.7 V Equivalentinputnoise f=100Hz +25(cid:176) C 28 nV/(cid:214) Hz n voltage f=1kHz +25(cid:176) C 15 I Equivalentinputnoise f=1kHz +25(cid:176) C 0.39 pA/(cid:214) Hz n current A =1 0.01% V =4V, V THD+N Totalharmonic RO=(PP1)0kW , A =10 +25(cid:176) C 0.05% distortionplusnoise L V f=1kHz A =100 0.3% V t Amplifierturn-ontime +25(cid:176) C 5 μs (on) R =OPEN(2) t Amplifierturn-offtime L +25(cid:176) C 250 ns (off) Gain-bandwidth f=10kHz,R =600W +25(cid:176) C 2.8 MHz product L V =2V, 0.1% 1.8 (STEP)PP A =–1,C =10pF, V L R =10kW 0.01% 3.3 t Settlingtime L +25(cid:176) C μs s V =2V, 0.1% 1.7 (STEP)PP A =–1,C =56pF, V L R =10kW 0.01% 3 L Φ Phasemargin R =10kW ,C =1000pF +25(cid:176) C 68 (cid:176) C m L L Gainmargin R =10kW ,C =1000pF +25(cid:176) C 23 dB L L (1) Fullrangeis0(cid:176) Cto+70(cid:176) CforCsuffixand–40(cid:176) Cto+125(cid:176) CforIsuffix.Ifnotspecified,fullrangeis–40(cid:176) Cto+125(cid:176) C. (2) DisableandenabletimearedefinedastheintervalbetweenapplicationoflogicsignaltoSHDNandthepointatwhichthesupply currenthasreachedhalfitsfinalvalue. 8 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE V Inputoffsetvoltage vsCommon-modeinputvoltage Figure1,Figure2 IO I Inputbiascurrent IB vsFree-airtemperature Figure3,Figure4 I Inputoffsetcurrent IO V High-leveloutputvoltage vsHigh-leveloutputcurrent Figure5,Figure7 OH V Low-leveloutputvoltage vsLow-leveloutputcurrent Figure6,Figure8 OL Z Outputimpedance vsFrequency Figure9 o I Supplycurrent vsSupplyvoltage Figure10 DD PSRR Power-supplyrejectionratio vsFrequency Figure11 CMRR Common-moderejectionratio vsFrequency Figure12 V Equivalentinputnoisevoltage vsFrequency Figure13 n V Maximumpeak-to-peakoutputvoltage vsFrequency Figure14,Figure15 O(PP) A Differentialvoltagegainandphase vsFrequency Figure16,Figure17 VD Φ Phasemargin vsLoadcapacitance Figure18,Figure19 m Gainmargin vsLoadcapacitance Figure20,Figure21 Gain-bandwidthproduct vsSupplyvoltage Figure22 vsSupplyvoltage Figure23 SR Slewrate vsFree-airtemperature Figure24,Figure25 Crosstalk vsFrequency Figure26 THD+N Totalharmonicdistortion+noise vsFrequency Figure27,Figure28 V Largeandsmallsignalfollower vsTime Figure29–Figure32 O Shutdownpulseresponse vsTime Figure33,Figure34 Shutdownforwardandreverseisolation vsFrequency Figure35,Figure36 I Shutdownsupplycurrent vsSupplyvoltage Figure37 DD(SHDN) I Shutdownsupplycurrent vsFree-airtemperature Figure38 DD(SHDN) I Shutdownpulsecurrent vsTime Figure39,Figure40 DD(SHDN) SubmitDocumentationFeedback 9

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS INPUTBIASANDINPUTOFFSET INPUTOFFSETVOLTAGE INPUTOFFSETVOLTAGE CURRENTS vs vs vs COMMON-MODEINPUTVOLTAGE COMMON-MODEINPUTVOLTAGE FREE-AIRTEMPERATURE 600 600 50 VDD = 3V VDD = 3V mInput Offset Voltage −−VVIO−−−2464200000000000 TA = +25° C mInput Offset Voltage −−VVIO−−−2464200000000000 TVAD D= =+ 255V °C I− Input Bias Current − pAIB I− Input Offset Current − pAIO 123400000 IIBIIO −800 −800 −10 −0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 −0.5 0.5 1.5 2.5 3.5 4.5 5.5 −55−35 −15 5 25 45 65 85 105 125 VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V TA − Free-Air Temperature − °C Figure1. Figure2. Figure3. INPUTBIASANDINPUTOFFSET CURRENTS HIGH-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE vs vs vs FREE-AIRTEMPERATURE HIGH-LEVELOUTPUTCURRENT LOW-LEVELOUTPUTCURRENT 50 3.5 3.0 − Input Bias Current − pA − Input Offset Current − pA 12340000 VDD = 5V IIB High-Level Output Voltage − V 11223.....05050 TTAA = = ++18255°°CC VDD = 3V Low-Level Output Voltage − V 1122....0505 TTTTAAVAA =D== = D −+ + +4=2108 523°5°5VCC°°CC IIB IIO 0 IIO V− OH 0.5 TTAA == −+4205°°CC V− OL 0.5 −10 0.0 0.0 −55−35 −15 5 25 45 65 85 105 125 0 10 20 30 40 50 60 0 10 20 30 40 50 TA − Free-Air Temperature − °C IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure4. Figure5. Figure6. HIGH-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE OUTPUTIMPEDANCE vs vs vs HIGH-LEVELOUTPUTCURRENT LOW-LEVELOUTPUTCURRENT FREQUENCY 5.5 5.0 1000 − High-Level Output Voltage − VH 112233445.........050505050 TTTAAA = == + ++1822555°°°CCC VDD = 5V − Low-Level Output Voltage − VOL 11223344........05050505 TTTTAAA A= = == + +−+184225055°°°°CCCC W− Output Impedance −Zo1001.0101 VTAADV D= =A =+ V 123 0=5V °1,C 050V AV = 1 VO 0.5 TA = −40°C V 0.5 VDD = 5V 0.0 0.0 0.01 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA f − Frequency − Hz Figure7. Figure8. Figure9. 10 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) POWER-SUPPLYREJECTION SUPPLYCURRENT RATIO COMMON-MODEREJECTIONRATIO vs vs vs SUPPLYVOLTAGE FREQUENCY FREQUENCY I− Supply Current − mADD 00000000001...........01234567890 ASPTHeVAr D= =C N1 h+ =a8n 5Vn°DCeDl TATT AA= ==− 4++021°52C°5C°C − Power Supply Rejection Ratio − dBPSRR 10345678900000000 PSRR−PSRR+ VRRTADFI = D== 5=+50 2k3WW5V°,C 5V CMRR − Common-Mode Rejection Ratio − dB1111012356789000000000 VVDICD = = 1 3.5VV VVDICD = = 2 5.5VV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M VDD − Supply Voltage − V f − Frequency − Hz f − Frequency − Hz Figure10. Figure11. Figure12. MAXIMUMPEAK-TO-PEAK MAXIMUMPEAK-TO-PEAK EQUIVALENTNOISEVOLTAGE OUTPUTVOLTAGE OUTPUTVOLTAGE vs vs vs FREQUENCY FREQUENCY FREQUENCY V V nV/HzVoltage − 56780000 VAVTADVIN D== = =+ 1V 203D5VD°,C /52V k Output Voltage − 34455.....50505 VO(PP) = 5V TRTAHL D== ++1N20 5k≤W° C2.0% k Output Voltage − 34455.....50505 VO(PP) = 5V TTRAHL D== ++6N02 05≤W° C2.0% ut Noise 40 k-To-Pea 23..50 VO(PP) = 3V k-To-Pea 23..50 − Equivalent Inpn 1230000 − Maximum PeaP) 00112.....05050 − Maximum PeaP) 00112.....05050 VO(PP) = 3V V 10 100 1k 10k 100k O(P 10k 100k 1M O(P 10k 100k 1M f − Frequency − Hz V f − Frequency − Hz V f − Frequency − Hz Figure13. Figure14. Figure15. DIFFERENTIALVOLTAGEGAIN DIFFERENTIALVOLTAGEGAIN ANDPHASE ANDPHASE vs vs FREQUENCY FREQUENCY 100 45 100 45 Gain − dB 6800 VRCTADLL D=== =+06 02±053W°C −045 Gain − dB 6800 VRCTADLL D=== =+06 02±055W°C −045 − Differential Voltage 24000 −−−11938050°Phase − − Differential Voltage 24000 −−−11938050°Phase − AVD−20 −225 AVD−20 −225 −40 −270 −40 −270 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M Frequency − Hz Frequency − Hz Figure16. Figure17. SubmitDocumentationFeedback 11

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) PHASEMARGIN PHASEMARGIN GAINMARGIN vs vs vs LOADCAPACITANCE LOADCAPACITANCE LOADCAPACITANCE 90 100 0 80 VRTADL D== =+1 2035kV W° C RNULL = 50 90 VRTADL D== =+1 2055kVW°C RNULL = 50 5 VRTADL D== =+1 2035kVW°C °− Phase Margin − m 3456700000 SeeR FNUigLuL r=e 14020 RNULL = 20 °− Phase Margin − m 345678000000 SeReN UFLiLg =ur 1e0 402 RNULL = 20 Gain Margin − dB 121500 RNULL = 20 RNULL = 100RNULL = 0 f 20 f 20 25 10 RNULL = 0 10 RNULL = 0 RNULL = 50 0 0 30 100 1k 10k 100k 100 1k 10k 100k 100 1k 10k 100k CL − Load Capacitance − pF CL − Load Capacitance − pF CL − Load Capacitance − pF Figure18. Figure19. Figure20. GAINMARGIN GAIN-BANDWIDTHPRODUCT SLEWRATE vs vs vs LOADCAPACITANCE SUPPLYVOLTAGE SUPPLYVOLTAGE 0 4.0 2.0 5 Hz 3.5 RL = 10kW 1.8 SR− Gain Margin − dB 1232150050 RNULLR =N U5L0L = 20RRNNUULLL L= = 0 1VR0D0L D= =1 05kVW Gain-Bandwidth Product − M 011223......505050 CfT =AL ==1 0+1k12Hp5zF°C RL = 600W mSR − Slew Rate − V/s 00001111........24680246 VAROVL (==P P−1)01 =k W1.5V SR+ TA = +25°C CL = 150pF 35 0.0 0.0 100 1k 10k 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 CL − Load Capacitance − pF VDD − Supply Voltage − V VDD − Supply Voltage − V Figure21. Figure22. Figure23. SLEWRATE SLEWRATE vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 2.00 2.00 1.75 1.75 SR− s1.50 SR+ s1.50 SR+ mSR − Slew Rate − V/00011.....2570250505 VRCADVLL D=== =1−1 50130kVWpF SR− mSR − Slew Rate − V/00011.....2570250505 VRCADVLL D=== =1−1 50150kVWpF 0.00 0.00 −55−35 −15 5 25 45 65 85 105 125 −55−35 −15 5 25 45 65 85 105 125 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure24. Figure25. 12 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) TOTALHARMONIC TOTALHARMONIC CROSSTALK DISTORTIONPLUSNOISE DISTORTIONPLUSNOISE vs vs vs FREQUENCY FREQUENCY FREQUENCY Crosstalk − dB−−−−−−−−111124668420000000000 VARV ADVIL(l Pl D= =PC = )1h 6 =3a0 Vn02n,WV e5lVs THD+N−Total Harmonic Distortion + Noise0.00.000.1111 VRVTAAAAD0LVVV D=== === = +1 2 111203V005kVP0W°PC THD+N−Total Harmonic Distortion + Noise0.00.000.1111 AAAVRVTVVVAD0L D====== =111 +14 00205V05kVPW°PC 10 100 1 k 10 k 100 k 10 100 1k 10k 100k 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure26. Figure27. Figure28. LARGE-SIGNALFOLLOWER LARGE-SIGNALFOLLOWER SMALL-SIGNALFOLLOWER PULSERESPONSE PULSERESPONSE PULSERESPONSE vs vs vs TIME TIME TIME VI (2V/DIV) VI (50mV/DIV) VI (2V/DIV) VDD = 3V RL = 10kW e e e CL = 8pF ag ag ag f = 1MHz Volt VO (1V/DIV) Volt Volt TA = +25°C ut ut ut utp utp VO (1V/DIV) utp O O O − VO VRDL D= =1 03kVW − VO VRDL D= 1=0 5kVW − VO CL = 8pF CL = 8pF VO (50mV/DIV) f = 85kHz f = 85kHz TA = +25°C TA = +25°C 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 t − Time − m s t − Time − m s t − Time − m s Figure29. Figure30. Figure31. SMALL-SIGNALFOLLOWER SHUTDOWN(ONANDOFF) SHUTDOWN(ONANDOFF) PULSERESPONSE PULSERESPONSE PULSERESPONSE vs vs vs TIME TIME TIME VI (50mV/DIV) VSHDN (2V/DIV) VDD = 5V VSHDN (2V/DIV) − Output Voltage VO VRCfT OA=LL (=1==5 M 0+81m2Hp05FVkz°W/CDIV) − Output Voltage VO VDD = 3V VO (50R0Lm R=VL 6 /=D0 0I1VW0)kW − Output Voltage VO VDD = 5V VOR L(1 R=VL /6 D=0I 0V1W0)kW CTAL == +82p5F°C CTAL == +82p5F°C 0 100 200 300 400 500 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 18 t − Time − m s t − Time − m s t − Time − m s Figure32. Figure33. Figure34. SubmitDocumentationFeedback 13

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) SHUTDOWNFORWARD ISOLATION SHUTDOWNREVERSEISOLATION SHUTDOWNSUPPLYCURRENT vs vs vs FREQUENCY FREQUENCY SUPPLYVOLTAGE 120 120 A 2.0 VDD = 3V, 5V m on - dB100 CAVVIL( P ==P 0)1 =p F0.1V, 1.5V, 3V on - dB100 urrent − 11..68 own Forward Isolati 648000 RL = 10kW RL = 600W own Forward Isolati 648000 VRDL D= =1 03kVW, 5V RL = 600W Shutdown Supply C 00111.....68024 TTTTAAAA = === ++−+124825055°°°C°CCC Shutd 200 Shutd 200 RCAVVILLN == == 0 110p0.Fk1WVPP, 1.5VPP, 3VPP − DD(SHDN) 000...024 SRVhIL = u= t VdOoDPwDEn/2N On 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M I 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f − Frequency − Hz f − Frequency − Hz VDD − Supply Voltage − V Figure35. Figure36. Figure37. SHUTDOWNSUPPLYCURRENT SHUTDOWNPULSECURRENT SHUTDOWNPULSECURRENT vs vs vs FREE-AIRTEMPERATURE TIME TIME 1.6 2.00 4 2.00 6 SD MODE Channel 1 and 2 Shutdown Pulse mShutdown Supply Current −−AD 0000111.......2468024 VDD = 5V ARVVILN = == O 1VPDEDN/2VDD = 3V I− Supply Current − mADD−10011100........27557022550050505 IDIDDVCT DRADL RL D== L= =+ 8 = 12p3 056FVk°0CW0W −−−−2130−−−1243756Shutdown Pulse − V I− Supply Current − mADD−10011100........27557022550050505 ShuIIDDVCTtdDDADLo DR=R=w L Ln=+8 = =2p5P 5 F6V1u°00Cls0keWW −−20−−4−248610Shutdown Pulse − V ID 0.0 −0.50 0 4 8 12 16 20 24 2830−8 −0.50 0 4 8 12 16 20 24 2830−12 −55−35 −15 5 25 45 65 85 105 125 t − Time − m s t − Time − m s TA − Free-Air Temperature − °C Figure38. Figure39. Figure40. 14 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 PARAMETER MEASUREMENT INFORMATION _ RNULL + RL CL Figure41. APPLICATION INFORMATION DRIVING A CAPACITIVE LOAD When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10pF, it is recommended that a resistor (R ) be placed in series with the output of the amplifier, as NULL showninFigure42.Aminimumvalueof20W shouldworkwellformostapplications. RF RG Input _ RNULL Output + CLOAD Figure42.DrivingaCapacitiveLoad OFFSET VOLTAGE Theoutputoffset voltage (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB thecorrespondinggains.Thefollowingschematicandformulacanbeusedtocalculatetheoutputoffsetvoltage: RF IIB− RG + − VI VO + RS IIB+ VOO(cid:4)VIO(cid:5)1(cid:2)(cid:5)RRF(cid:6)(cid:6)(cid:1)IIB(cid:2)RS(cid:5)1(cid:2)(cid:5)RRF(cid:6)(cid:6)(cid:1)IIB(cid:3)RF G G Figure43.OutputOffsetVoltageModel SubmitDocumentationFeedback 15

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) GENERAL CONFIGURATIONS When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (seeFigure44). RG RF – + VO VI R1 C1 1 f–3dB (cid:2) 2(cid:1)R1C1 VVOI (cid:2) (cid:3)1(cid:1)RRGF(cid:4)(cid:3)1(cid:1)s1R1C1(cid:4) Figure44.Single-PoleLow-PassFilter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency bandwidth.Failuretodothiscanresultinphaseshiftoftheamplifier. C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) VI + R1 R2 _ f–3dB (cid:1) 2(cid:1)1RC C2 RF RG = (2 –RF1 ) RG Q Figure45.2-PoleLow-PassSallen-KeyFilter SHUTDOWN FUNCTION Three members of the TLV247x family (TLV2470/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 350nA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2. DD Therefore, when operating the device with split supply voltages (e.g., – 2.5V), the shutdown terminal needs to be pulledtoV –(notGND)todisabletheoperationalamplifier. DD The amplifier output with a shutdown pulse is shown in Figure 33and Figure 34. The amplifier is powered with a single 5V supply and configured as a noninverting configuration with a gain of 5. The amplifier turn-on and turn-off times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. Thetimesforthesingle,dual,andquadversionsarelistedinthedatatables. 16 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) Figure 35 and Figure 36 show the amplifier forward and reverse isolation in shutdown. The operational amplifier ispoweredby– 1.35Vsuppliesandconfiguredasavoltagefollower(A =1).Theisolation performance is plotted V across frequency using 0.1V , 1.5V , and 2.5V input signals. During normal operation, the amplifier would PP PP PP not be able to handle a 2.5V input signal with a supply voltage of – 1.35V since it exceeds the common-mode PP input voltage range (V ). However, this curve illustrates that the amplifier remains in shutdown even under a ICR worstcasescenario. CIRCUIT LAYOUT CONSIDERATIONS To achieve the levels of high performance of the TLV247x, follow proper printed circuit board (PCB) design techniques.Ageneralsetofguidelinesisgivenbelow: • Ground planes—It is highly recommended that a ground plane be used on the board to provide all componentswithalowinductivegroundconnection.However, in the areas of the amplifier inputs and output, thegroundplanecanberemovedtominimizethestraycapacitance. • Proper power supply decoupling—Use a 6.8μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor oneachsupplyterminal.Itmaybepossibletosharethetantalumamongseveralamplifiersdepending on the application,buta0.1μFceramiccapacitorshouldalwaysbeusedonthesupplyterminalofeveryamplifier.In addition, the 0.1μF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strivefordistancesoflessthan0.1inchesbetweenthedevicepowerterminalsandtheceramiccapacitors. • Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is thebestimplementation. • Short trace runs/compact part placements—Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the inputoftheamplifier. • Surface-mount passive components—Using surface-mount passive components is recommended for high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance ofsurface-mountcomponents,theproblemwithstrayseriesinductanceisgreatlyreduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductanceandcapacitance.Ifleadedcomponentsareused,itisrecommendedthatthelead lengths be kept asshortaspossible. GENERAL PowerPAD™ DESIGN CONSIDERATIONS The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted (see Figure 46a and Figure 46b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see Figure 46c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance canbeachievedbyprovidingagoodthermalpathawayfromthethermalpad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heatcanbeconductedawayfromthepackageintoeitheragroundplaneorotherheatdissipatingdevice. Soldering the PowerPAD to the PCB is always recommended, even with applications that have low power dissipation. It provides the necessary mechanical and thermal connection between the lead frame die pad and thePCB. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surfacemountwithpreviouslyawkwardmechanicalmethodsofheatsinking. SubmitDocumentationFeedback 17

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Thethermalpadiselectricallyisolatedfromallterminalsinthepackage. Figure46.ViewsofThermallyEnhancedDGNPackage Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommendedapproach. 1. Thethermalpadmustbeconnectedtothemostnegativesupplyvoltageonthedevice(GNDpin). 2. PreparethePCBwithatopsideetchpatternasillustrated in the thermal land pattern mechanical drawing attheendofthisdocument.Thereshouldbeetchfortheleadsaswellasetchforthethermalpad. 3. Place holes in the area of the thermal pad as illustrated in the land pattern mechanical drawing at the end of this document. These holes should be 13mils (0.013 inches or 0.3302mm) in diameter. Keep them smallsothatsolderwickingthroughtheholesisnotaproblemduringreflow. 4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helpsdissipatetheheatgeneratedbytheTLV247xIC.Theseadditionalviasmaybelargerthan the 13mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad areatobesolderedsothatwickingisnotaproblem. 5. ConnectallholestotheinternalgroundplanethatisatthesamevoltagepotentialasthedeviceGNDpin. 6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal groundplanewithacompleteconnectionaroundtheentirecircumferenceoftheplated-throughhole. 7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This preventssolderfrombeingpulledawayfromthethermalpadareaduringthereflowprocess. 8. ApplysolderpastetotheexposedthermalpadareaandalloftheICterminals. 9. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. Foragivenθ ,themaximumpowerdissipationisshowninFigure47andiscalculatedbyEquation1: JA PD(cid:2)(cid:3)TMAX(cid:1)(cid:1)TA(cid:4) JA (1) Where: • P =MaximumpowerdissipationofTLV247xIC(watts) D • T =Absolutemaximumjunctiontemperature(+150(cid:176) C) MAX • T =Free-ambientairtemperature((cid:176) C) A • θ =θ +θ JA JC CA – θ =Thermalcoefficientfromjunctiontocase JC – θ =Thermalcoefficientfromcasetoambientair((cid:176) C/W) CA 18 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 7 PWP Package TJ = +150°C Low-K Test PCB 6 q JA = 29.7°C/W W SOT-23 Package − Low-K Test PCB pation 5 DLoGwN- KP aTceksat gPeCB q JA = 324°C/W ssi 4 q JA = 52.3°C/W Di SOIC Package er Low-K Test PCB ow 3 q JA = 176°C/W P PDIP Package m Low-K Test PCB mu 2 q JA = 104°C/W xi a M 1 0 −55 −40−25−10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C ResultsareobtainedwithnoairflowandusingJEDECStandardLow-KtestPCB. Figure47.MaximumPowerDissipationvsFree-AirTemperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 48 to Figure 53 show this effect, along with the quiescent heat, with an ambient air temperature of +70(cid:176) C and +125(cid:176) C. When using V = 3V, DD there is generally not a heat problem with an ambient air temperature of +70(cid:176) C. But, when using V = 5V, the DD package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device,θ decreases and the heat dissipation JA capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quadamplifierpackages,thesumoftheRMSoutput currents and voltages should be used to choose the proper package. SubmitDocumentationFeedback 19

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) TLV2470,TLV2471(1) TLV2470,TLV2471(1) MAXIMUMRMSOUTPUTCURRENT MAXIMUMRMSOUTPUTCURRENT vs vs RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS 180 180 Maximum Output Maximum Output A 160 Current Limit Line A 160 Current Limit Line m m − − nt 140 nt 140 e e put Curr 120 C Paq atJ AcT kA≤a =1g 1e+0s1° 2CW5/°iWtCh put Curr 120 G C B S Out 100 B q JA ≤ 3o5r5°C/W S Out 100 A RM 80 A at TA = +70°C RM 80 m m Packages With u 60 u 60 Maxim 40 Safe Operating Area Maxim 40 qaJtA T ≤A 2=1 +07°C0°/CW I− ||O 200 VTTAJD D == = ++ 1±12355V0°°CC I− ||O 200 VTTAJD D == = ++ 1±12 5550V°°CC Safe Operating Area 0 0.25 0.50 0.75 1.00 1.25 1.50 0 0.5 1.0 1.5 2.0 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure48. Figure49. TLV2472,TLV2473(1) TLV2472,TLV2473(1) MAXIMUMRMSOUTPUTCURRENT MAXIMUMRMSOUTPUTCURRENT vs vs RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS 180 180 Maximum Output Maximum Output A 160 Current Limit Line A 160 Current Limit Line m m − − nt 140 G nt 140 urre H C urre F C 120 Packages With C 120 put D q JA ≤ 55°C/W put G Out 100 at TA = +125°C Out 100 H S or S D RM 80 q JA ≤ 178°C/W RM 80 um 60 at TA = +70°C um 60 C m m Packages With axi axi q JA ≤ 105°C/W I− M||O 42000 VTTAJD D == = ++ 1±12 5350V°°CC Safe Operating Area I− M||O 42000 VTTAJD D == = ++ 1±12 5550V°°CC Safe Oapte TrAa t=in +g7 A0°rCea 0 0.25 0.50 0.75 1.00 1.25 1.50 0 0.5 1.0 1.5 2.0 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure50. Figure51. Note:(1)A- SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP (8);H-PDIP(14):I-PDIP(16);J-TSSOPPP(14/16) 20 SubmitDocumentationFeedback

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) TLV2474,TLV2475(1) TLV2474,TLV2475(1) MAXIMUMRMSOUTPUTCURRENT MAXIMUMRMSOUTPUTCURRENT vs vs RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS 180 180 Maximum Output Maximum Output A 160 Current Limit Line A 160 Current Limit Line m m − − ent 140 J ent 140 urr urr J C 120 C 120 ut H and I ut p p ut 100 ut 100 O E O S S H and I M 80 Packages With M 80 ximum R 60 D aq tJ AT A≤ =8 8+°7C0/°WC ximum R 60 VTTAJD D == = ++ 1±12555V0°°CC E D a a M 40 M 40 I− ||O 20 VTTAJD D == = ++ 1±12355V0°°CC Safe Operating Area I− ||O 20 Safe Operating Area PaqatJc ATk A≤a g=5e 2+s°7 CW0/°WiCth 0 0 0 0.25 0.50 0.75 1.00 1.25 1.50 0 0.5 1.0 1.5 2.0 2.5 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure52. Figure53. NOTE: (1) A - SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP(8);H-PDIP(14):I-PDIP(16);J-TSSOPPP(14/16) SubmitDocumentationFeedback 21

TLV2470,, TLV2471 TLV2472, TLV2473 TLV2474, TLV2475, TLV247xA www.ti.com SLOS232E–JUNE1999–REVISEDJULY2007 APPLICATION INFORMATION (continued) MACROMODEL INFORMATION Macromodel information provided was derived using Microsim PARTS™, the model generation software used with Microsim PSpice®. The Boyle macromodel and subcircuit in Figure 54 are generated using the TLV247x typical electrical and operating characteristics at T = 25(cid:176) C. Using this information, output simulations of the A followingkeyparameterscanbegeneratedtoatoleranceof20%(inmostcases): • Maximumpositiveoutputvoltageswing • Unity-gainfrequency • Maximumnegativeoutputvoltageswing • Common-moderejectionratio • Slewrate • Phasemargin • Quiescentpowerdissipation • DCoutputresistance • Inputbiascurrent • ACoutputresistance • Open-loopvoltageamplification • Short-circuitoutputcurrentlimit 3 99 VDD + rp rd1 rd2 rss css egnd fb ro2 c1 – 7 11 12 + c2 1 vlim IN+ + 9 r2 6 – vc D D + 8 – 2 vb ga G G IN– 53 – gcm ioff ro1 S S OUT dp dlp dln 5 10 91 90 92 iss dc + + – vlp hlim vln GND – – + 4 – ve + 54 de * TLV247x operational amplifier ”macromodel” subcircuit iss 10 4 dc 10.714E–6 * created using Parts release 8.0 on 4/27/99 at 14:31 hlim 90 0 vlim 1K * Parts is a MicroSim product. ioff 0 6 dc 75E–9 * j1 11 2 10 jx1 * connections: non–inverting input j2 12 1 10 jx2 * | inverting input r2 6 9 100.00E3 * | | positive power supply rd1 3 11 12.527E3 * | | | negative power supply rd2 3 12 12.527E3 * | | | | output ro1 8 5 10 * | | | | | ro2 7 99 10 .subckt TLV247x 1 2 3 4 5 rp 3 4 3.8023E3 * rss 10 99 18.667E6 c1 11 12 1.1094E–12 vb 9 0 dc 0 c2 6 7 5.5000E–12 vc 3 53 dc .842 css 10 99 556.53E–15 ve 54 4 dc .842 dc 5 53 dy vlim 7 8 dc 0 de 54 5 dy vlp 91 0 dc 110 dlp 90 91 dx vln 0 92 dc 110 dln 92 90 dx .model dx D(Is=800.00E–18) dp 4 3 dx .model dy D(Is=800.00E–18 Rs=1m Cjo=10p) egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 .model jx1 NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1) fb 7 99 poly(5) vb vc ve vlp vln 0 .model jx2 NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1) + 39.614E6 –1E3 1E3 40E6 –40E6 .ends ga 6 0 11 12 79.828E–6 *$ gcm 0 6 10 99 32.483E–9 G.R.Boyle,B.M.Cohn,D.O.Pederson,andJ.E.Solomon,"MacromodelingofIntegratedCircuitOperational Amplifiers,”IEEEJournalofSolid-StateCircuits,SC-9,353(1974). Figure54.BoyleMacromodelandSubcircuit 22 SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2470AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2470AI & no Sb/Br) TLV2470AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2470AI & no Sb/Br) TLV2470CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2470C & no Sb/Br) TLV2470CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAUC & no Sb/Br) TLV2470CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAUC & no Sb/Br) TLV2470CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2470C & no Sb/Br) TLV2470CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2470C & no Sb/Br) TLV2470CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2470C & no Sb/Br) TLV2470ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2470I & no Sb/Br) TLV2470IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAUI & no Sb/Br) TLV2470IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAUI & no Sb/Br) TLV2470IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2470I & no Sb/Br) TLV2471AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2471AI & no Sb/Br) TLV2471AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2471AI & no Sb/Br) TLV2471AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2471AI & no Sb/Br) TLV2471CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2471C & no Sb/Br) TLV2471CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAVC & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2471CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAVC & no Sb/Br) TLV2471CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAVC & no Sb/Br) TLV2471CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAVC & no Sb/Br) TLV2471CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2471C & no Sb/Br) TLV2471CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2471C & no Sb/Br) TLV2471ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2471I & no Sb/Br) TLV2471IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAVI & no Sb/Br) TLV2471IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAVI & no Sb/Br) TLV2471IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAVI & no Sb/Br) TLV2471IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAVI & no Sb/Br) TLV2471IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2471I & no Sb/Br) TLV2471IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2471I & no Sb/Br) TLV2472AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472AI & no Sb/Br) TLV2472AIDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472AI & no Sb/Br) TLV2472AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472AI & no Sb/Br) TLV2472AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2472AI & no Sb/Br) TLV2472CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2472C & no Sb/Br) TLV2472CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABU & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2472CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABU & no Sb/Br) TLV2472CDGNRG4 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABU & no Sb/Br) TLV2472CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2472C & no Sb/Br) TLV2472CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2472CP & no Sb/Br) TLV2472ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472I & no Sb/Br) TLV2472IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ABV & no Sb/Br) TLV2472IDGNG4 ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ABV & no Sb/Br) TLV2472IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ABV & no Sb/Br) TLV2472IDGNRG4 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ABV & no Sb/Br) TLV2472IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2472I & no Sb/Br) TLV2472IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2472IP & no Sb/Br) TLV2473AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2473AI & no Sb/Br) TLV2473AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2473AI & no Sb/Br) TLV2473AIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2473AIN & no Sb/Br) TLV2473CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2473C & no Sb/Br) TLV2473CDGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 ABW & no Sb/Br) TLV2473CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2473C & no Sb/Br) TLV2473IDGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 ABX & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2473IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2473IN & no Sb/Br) TLV2474AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474AI & no Sb/Br) TLV2474AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474AI & no Sb/Br) TLV2474AIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2474AI & no Sb/Br) TLV2474AINE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2474AI & no Sb/Br) TLV2474AIPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474AI & no Sb/Br) TLV2474AIPWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474AI & no Sb/Br) TLV2474AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474AI & no Sb/Br) TLV2474CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2474C & no Sb/Br) TLV2474CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2474C & no Sb/Br) TLV2474CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2474C & no Sb/Br) TLV2474CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2474C & no Sb/Br) TLV2474CPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 2474C & no Sb/Br) TLV2474CPWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 2474C & no Sb/Br) TLV2474ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474I & no Sb/Br) TLV2474IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2474I & no Sb/Br) TLV2474IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2474I & no Sb/Br) TLV2474IPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474I & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2474IPWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2474I & no Sb/Br) TLV2475AIDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2475AI & no Sb/Br) TLV2475AIN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2475AI & no Sb/Br) TLV2475AIPWP ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2475AI & no Sb/Br) TLV2475AIPWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2475AI & no Sb/Br) TLV2475CD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2475C & no Sb/Br) TLV2475CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2475C & no Sb/Br) TLV2475CN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2475C & no Sb/Br) TLV2475CPWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 2475C & no Sb/Br) TLV2475IPWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2475I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2471, TLV2471A, TLV2472, TLV2472A, TLV2474, TLV2474A : •Automotive: TLV2471-Q1, TLV2471A-Q1, TLV2472-Q1, TLV2472A-Q1, TLV2474-Q1, TLV2474A-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 6

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2470CDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2470CDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2470CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2470IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2470IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2470IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2471AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2471CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2471CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2471CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2471IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2471IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2471IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2472AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2472CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2472CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2472IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2472IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2473AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2473CDGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2473CDGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2473CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2473IDGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2474AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2474AIPWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2474AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2474CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2474CPWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2474IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2474IPWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2475AIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2475AIPWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2475CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2475CPWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2475IPWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 *Alldimensionsarenominal PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2470CDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2470CDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2470CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2470IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2470IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2470IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2471AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2471CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2471CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2471CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2471IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2471IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2471IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2472AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2472CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 TLV2472CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2472IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 TLV2472IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2473AIDR SOIC D 14 2500 350.0 350.0 43.0 TLV2473CDGQR HVSSOP DGQ 10 2500 358.0 335.0 35.0 TLV2473CDGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0 TLV2473CDR SOIC D 14 2500 350.0 350.0 43.0 TLV2473IDGQR HVSSOP DGQ 10 2500 358.0 335.0 35.0 TLV2474AIDR SOIC D 14 2500 350.0 350.0 43.0 TLV2474AIPWPR HTSSOP PWP 14 2000 350.0 350.0 43.0 TLV2474AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2474CDR SOIC D 14 2500 350.0 350.0 43.0 TLV2474CPWPR HTSSOP PWP 14 2000 350.0 350.0 43.0 TLV2474IDR SOIC D 14 2500 350.0 350.0 43.0 TLV2474IPWPR HTSSOP PWP 14 2000 350.0 350.0 43.0 TLV2475AIDR SOIC D 16 2500 350.0 350.0 43.0 TLV2475AIPWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TLV2475CDR SOIC D 16 2500 350.0 350.0 43.0 TLV2475CPWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TLV2475IPWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 PackMaterials-Page3

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE 6.6 TYP C A 6.2 PIN 1 INDEX 0.1 C AREA 14X 0.65 SEATING 16 PLANE 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 4.5 16X B 0.19 4.3 0.1 C A B SEE DETAIL A (0.15) TYP 2X 0.95 MAX NOTE 5 4X (0.3) 8 9 2X 0.23 MAX NOTE 5 2.31 17 0.25 1.75 GAGE PLANE 1.2 MAX 0.75 0.15 1 16 0 -8 0.50 0.05 DETA 20AIL A THERMAL 2.46 TYPICAL PAD 1.75 4224559/B 01/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. www.ti.com

EXAMPLE BOARD LAYOUT PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (3.4) NOTE 9 (2.46) 16X (1.5) SYMM METAL COVERED BY SOLDER MASK 1 16X (0.45) 16 (1.2) TYP (R0.05) TYP SYMM 17 (2.31) (5) (0.6) NOTE 9 14X (0.65) ( 0.2) TYP VIA 8 9 SOLDER MASK (1) TYP DEFINED PAD SEE DETAILS (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDE15.000R MASK DETAILS 4224559/B 01/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (2.46) BASED ON 16X (1.5) 0.125 THICK METAL COVERED STENCIL BY SOLDER MASK 1 16X (0.45) 16 (R0.05) TYP (2.31) SYMM 17 BASED ON 0.125 THICK STENCIL 14X (0.65) 8 9 SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.8) THICKNESSES SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.75 X 2.58 0.125 2.46 X 2.31 (SHOWN) 0.15 2.25 X 2.11 0.175 2.08 X 1.95 4224559/B 01/2019 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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