ICGOO在线商城 > 集成电路（IC） > 线性 - 放大器 - 仪表，运算放大器，缓冲器放大器 > TLV2464ID
Datasheet下载- 型号： TLV2464ID
- 制造商： Texas Instruments
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TLV2464ID产品简介：
ICGOO电子元器件商城为您提供TLV2464ID由Texas Instruments设计生产，在icgoo商城现货销售，并且可以通过原厂、代理商等渠道进行代购。 TLV2464ID价格参考￥10.70-￥21.81。Texas InstrumentsTLV2464ID封装/规格：线性 - 放大器 - 仪表，运算放大器，缓冲器放大器， 通用 放大器 4 电路 满摆幅 14-SOIC。您可以下载TLV2464ID参考资料、Datasheet数据手册功能说明书，资料中有TLV2464ID 详细功能的应用电路图电压和使用方法及教程。
| 参数 | 数值 |
| -3db带宽 | - |
| 产品目录 | 集成电路 (IC)半导体 |
| 描述 | IC OPAMP GP 6.4MHZ RRO 14SOIC运算放大器 - 运放 Quad Rail-Rail |
| 产品分类 | Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps集成电路 - IC |
| 品牌 | Texas Instruments |
| 产品手册 | |
| 产品图片 |
|
| rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
| 产品系列 | 放大器 IC,运算放大器 - 运放,Texas Instruments TLV2464ID- |
| 数据手册 | |
| 产品型号 | TLV2464ID |
| 产品目录页面 | |
| 产品种类 | 运算放大器 - 运放 |
| 供应商器件封装 | 14-SOIC |
| 共模抑制比—最小值 | 60 dB |
| 关闭 | No Shutdown |
| 其它名称 | 296-10608-5 |
| 包装 | 管件 |
| 单位重量 | 122.400 mg |
| 压摆率 | 1.6 V/µs |
| 双重电源电压 | +/- 3 V |
| 商标 | Texas Instruments |
| 增益带宽生成 | 6.4 MHz |
| 增益带宽积 | 6.4MHz |
| 安装类型 | 表面贴装 |
| 安装风格 | SMD/SMT |
| 封装 | Tube |
| 封装/外壳 | 14-SOIC（0.154"，3.90mm 宽） |
| 封装/箱体 | SOIC-14 |
| 工作温度 | -40°C ~ 125°C |
| 工作电源电压 | 2.7 V to 6 V |
| 工厂包装数量 | 50 |
| 放大器类型 | 通用 |
| 最大双重电源电压 | 3 V |
| 最大工作温度 | + 125 C |
| 最小双重电源电压 | 1.35 V |
| 最小工作温度 | - 40 C |
| 标准包装 | 50 |
| 电压-电源，单/双 (±) | 2.7 V ~ 6 V， ±1.35 V ~ 3 V |
| 电压-输入失调 | 500µV |
| 电流-电源 | 550µA |
| 电流-输入偏置 | 1.3nA |
| 电流-输出/通道 | 80mA |
| 电源电流 | 0.5 mA |
| 电路数 | 4 |
| 系列 | TLV2464 |
| 转换速度 | 1.6 V/us |
| 输入偏压电流—最大 | 14 nA |
| 输入参考电压噪声 | 14 nV |
| 输入补偿电压 | 500 uV |
| 输出电流 | 80 mA |
| 输出类型 | 满摆幅 |
| 通道数量 | 4 Channel |
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PDF Datasheet 数据手册内容提取
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 (cid:1) Rail-to-Rail Output Swing TLV2460 (cid:1) DBV PACKAGE Gain Bandwidth Product...6.4 MHz (TOP VIEW) (cid:1) ±80 mA Output Drive Capability (cid:1) Supply Current...500 µA/channel OUT 1 6 VDD+ (cid:1) Input Offset Voltage...100 µV GND 2 5 SHDN (cid:1) Input Noise Voltage...11 nV/√Hz (cid:1) Slew Rate...1.6 V/µs IN+ 3 4 IN− (cid:1) Micropower Shutdown Mode (TLV2460/3/5)...0.3 µA/Channel (cid:1) Universal Operational Amplifier EVM (cid:1) Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control/Print Support Qualification to Automotive Standards description The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for portable applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters. The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current, providing good ac performance with low power consumption. Three members of the family offer a shutdown terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown, the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV. This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for high-density circuits. The family is specified over an expanded temperature range (T = −40°C to 125°C) for A use in industrial control and automotive systems, and over the military temperature range (T = −55°C to 125°C) for use in military systems. A SELECTION GUIDE VDD VIO IDD/ch IIB GBW SLEW RATE Vn, 1 kHz IO DEVICE SHUTDOWN RAIL-RAIL [V] [µV] [µA] [pA] [MHz] [V/µs] [nV/√Hz] [mA] TLV246x(A) 2.7−6 150 550 1300 6.4 1.6 11 25 Y I/O TLV277x(A) 2.5−5.5 360 1000 2 5.1 10.5 17 6 Y O TLV247x(A) 2.7−6 250 600 2.5 2.8 1.5 15 20 Y I/O TLV245x(A) 2.7−6 20 23 500 0.22 0.11 52 10 Y I/O TLV225x(A) 2.7−8 200 35 1 0.2 0.12 19 3 — — TLV226x(A) 2.7−8 300 200 1 0.71 0.55 12 3 — — Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:21)(cid:23)(cid:18)(cid:29)(cid:25)(cid:30)(cid:1)(cid:16)(cid:18)(cid:24) (cid:29)(cid:13)(cid:1)(cid:13) (cid:31)!"#$%&’(cid:31)#! (cid:31)( )*$$+!’ &( #" ,*-.(cid:31))&’(cid:31)#! /&’+0 Copyright 1998−2004, Texas Instruments Incorporated (cid:21)$#/*)’( )#!"#$% ’# (,+)(cid:31)"(cid:31))&’(cid:31)#!( ,+$ ’1+ ’+$%( #" (cid:1)+(cid:12)&( (cid:16)!(’$*%+!’( (cid:18)! ,$#/*)’( )#%,.(cid:31)&!’ ’# (cid:15)(cid:16)(cid:2)(cid:20)(cid:21)(cid:23)(cid:14)(cid:20)(cid:10)5(cid:11)(cid:10)(cid:11)(cid:8) &.. ,&$&%+’+$( &$+ ’+(’+/ (’&!/&$/ 2&$$&!’30 (cid:21)$#/*)’(cid:31)#! ,$#)+(((cid:31)!4 /#+( !#’ !+)+((&$(cid:31).3 (cid:31)!).*/+ *!.+(( #’1+$2(cid:31)(+ !#’+/0 (cid:18)! &.. #’1+$ ,$#/*)’((cid:8) ,$#/*)’(cid:31)#! ’+(’(cid:31)!4 #" &.. ,&$&%+’+$(0 ,$#)+(((cid:31)!4 /#+( !#’ !+)+((&$(cid:31).3 (cid:31)!).*/+ ’+(’(cid:31)!4 #" &.. ,&$&%+’+$(0 WWW.TI.COM 1
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TLV2460C/I/AI and TLV2461C/I/AI AVAILABLE OPTIONS PACKAGED DEVICES TA AVVTIIOO 2mm5aa°Cxx SMALL OUTLINE SOT-23† SYMBOL PLASTIC DIP (D) (DBV) (P) TLV2460CD TLV2460CDBV VAOC TLV2460CP 0°C to 70°C 2000 µV TLV2461CD TLV2461CDBV VAPC TLV2461CP TLV2460ID TLV2460IDBV VAOI TLV2460IP 2000 µV TLV2461ID TLV2461IDBV VAPI TLV2461IP −−4400°°CC ttoo 112255°°CC TLV2460AID — — TLV2460AIP 1500 µV TLV2461AID — — TLV2461AIP †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460CDR). ‡Chip forms are tested at TA = 25°C only. TLV2460M/AM/Q/AQ and TLV2461M/AM/Q/AQ AVAILABLE OPTIONS PACKAGED DEVICES TA AVTIO 2m5a°Cx OSUMTLAILNLE† OSUMTLAILNLE† CERAMIC DIP FCLEARTAPAMCICK CHIP CARRIER (JG) (FK) (D) (PW) (U) TLV2460QD TLV2460QPW — — — 2000 µV TLV2461QD TLV2461QPW — — — −−4400°°CC ttoo 112255°°CC TLV2460AQD TLV2460AQPW — — — 1500 µV TLV2461AQD TLV2461AQPW — — — — — TLV2460MJG TLV2460MU TLV2460MFK 2000 µV — — TLV2461MJG TLV2461MU TLV2461MFK −−5555°°CC ttoo 112255°°CC — — TLV2460AMJG TLV2460AMU TLV2460AMFK 1500 µV — — TLV2461AMJG TLV2461AMU TLV2461AMFK †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460QDR). TLV2462C/I/AI and TLV2463C/I/AI AVAILABLE OPTIONS PACKAGED DEVICES TA AVTIO 2m5a°Cx OSUMTALILNLE † MSOP SYMBOL MSOP† SYMBOL PLASTIC DIP PLASTIC DIP (DGK) (DGS) (N) (P) (D) TLV2462CD TLV2462CDGK xxTIAAI — — — TLV2462CP 0°C to 70°C 2000 µV TLV2463CD — TLV2463CDGS xxTIAAK TLV2463CN — TLV2462ID TLV2462IDGK xxTIAAJ — — — TLV2462IP 2000 µV −−4400°CC ttoo TLV2463ID — TLV2463IDGS xxTIAAL TLV2463IN — 125°C TLV2462AID — — — — — TLV2462AIP 1500 µV TLV2463AID — — — — TLV2463AIN — †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462CDR). ‡Chip forms are tested at TA = 25°C only. 2 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TLV2462M/AM/Q/AQ and TLV2463M/AM/Q/AQ AVAILABLE OPTIONS PACKAGED DEVICES TA AVTIO 2m5a°Cx OSUMTLAILNLE† OSUMTLAILNLE† CERAMIC DIP CERDAIPMIC FCLEARTAPAMCICK CHRIPI ECRAR- (JG) (D) (PW) (J) (U) (FK) TLV2462QD TLV2462QPW — — — — 2000 µV TLV2463QD TLV2463QPW — — — — −−4400°°CC ttoo 112255°°CC TLV2462AQD TLV2462AQPW — — — — 1500 µV TLV2463AQD TLV2463AQPW — — — — — — TLV2462MJG — TLV2462MU TLV2462MFK 2000 µV — — — TLV2463MJ TLV2463MFK −−5555°°CC ttoo 112255°°CC — — TLV2462AMJG — TLV2462AMU TLV2462AMFK 1500 µV — — — TLV2463AMJ TLV2463AMFK †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462QDR). TLV2464C/I/AI and TLV2465C/I/AI AVAILABLE OPTIONS PACKAGED DEVICES TA AVVTIIOO 2mm5aa°Cxx SMALL OUTLINE PLASTIC DIP TSSOP (D) (N) (PW) TLV2464CD TLV2464CN TLV2464CPW 0°C to 70°C 2000 µV TLV2465CD TLV2465CN TLV2465CPW TLV2464ID TLV2464IN TLV2464IPW 2000 µV TLV2465ID TLV2465IN TLV2465IPW −−4400°°CC ttoo 112255°°CC TLV2464AID TLV2464AIN TLV2464AIPW 1500 µV TLV2465AID TLV2465AIN TLV2465AIPW †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number(e.g., TLV2464CDR). ‡Chip forms are tested at TA = 25°C only. TLV2464M/AM/Q/AQ and TLV2465M/AM/Q/AQ AVAILABLE OPTIONS PACKAGED DEVICES TA AVTIO 2m5a°Cx OSUMTLAILNLE† OSUMTLAILNLE† CERAMIC DIP CHIP CARRIER (J) (FK) (D) (PW) TLV2464QD TLV2464QPW — — 2000 µV TLV2465QD TLV2465QPW — — --4400°°CC ttoo 112255°°CC TLV2464AQD TLV2464AQPW — — 1500 µV TLV2465AQD TLV2465AQPW — — — — TLV2464MJ TLV2464MFK 2000 µV — — TLV2465MJ TLV2465MFK −−5555°°CC ttoo 112255°°CC — — TLV2464AMJ TLV2464AMFK 1500 µV — — TLV2465AMJ TLV2465AMFK †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2464QDR). WWW.TI.COM 3
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TLV246x PACKAGE PINOUTS(1) TLV2460 TLV2461 TLV2460 DBV PACKAGE DBV PACKAGE D, P, JG, OR PW PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OUT 1 6 VDD+ OUT 1 5 VDD+ NC 1 8 SHDN IN− 2 7 VDD+ GND 2 5 SHDN GND 2 IN+ 3 6 OUT GND 4 5 NC IN+ 3 4 IN− IN+ 3 4 IN− TLV2461 TLV2462 TLV2463 D, P, JG, OR PW PACKAGE D, DGK, P, JG, OR PW PACKAGE DGS PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) NC 1 8 NC 1OUT 1 8 VDD+ 1OUT 1 10 VDD+ IN− 2 7 VDD+ 1IN− 2 7 2OUT 1IN− 2 9 2OUT IN+ 3 6 OUT 1IN+ 3 6 2IN− 1IN+ 3 8 2IN− GND 4 5 NC GND 4 5 2IN+ GND 4 7 2IN+ 1SHDN 5 6 2SHDN TLV2463 TLV2464 TLV2465 D, N, J, OR PW PACKAGE D, N, PWP, J, OR PW PACKAGE D, N, PWP, J, OR PW PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) 1OUT 1 14 VDD+ 1OUT 1 14 4OUT 1OUT 1 16 4OUT 1IN− 2 13 2OUT 1IN− 2 15 4IN− 1IN− 2 13 4IN− 1IN+ 3 12 2IN− 1IN+ 3 14 4IN+ 1IN+ 3 12 4IN+ GND 4 11 2IN+ VDD+ 4 11 GND VDD+ 4 13 GND NC 5 10 NC 2IN+ 5 12 3IN+ 2IN+ 5 10 3IN+ 1SHDN 6 9 2SHDN 2IN− 6 11 3IN− 2IN− 6 9 3IN− NC 7 8 NC 2OUT 7 10 3OUT 2OUT 7 8 3OUT 1/2SHDN 8 9 3/4SHDN NC − No internal connection (1) SOT−23 may or may not be indicated TYPICAL PIN 1 INDICATORS Pin 1 Printed or Pin 1 Pin 1 Pin 1 Molded Dot Stripe Bevel Edges Molded ”U” Shape 4 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TLV246x PACKAGE PINOUTS (continued)(1) TLV2460 TLV2461 TLV2462 U PACKAGE U PACKAGE U PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) NC 1 10 NC NC 1 10 NC NC 1 10 NC NC 2 9 SHDN NC 2 9 NC 1OUT 2 9 VDD+ IN− 3 8 VDD IN− 3 8 VDD 1IN− 3 8 2OUT IN+ 4 7 OUTPUT IN+ 4 7 OUTPUT 1IN+ 4 7 2IN− GND 5 6 NC GND 5 6 NC GND 5 6 2IN+ TLV2460 TLV2461 TLV2462 FK PACKAGE FK PACKAGE FK PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) N D T T NC NC NC SH NC NC NC NC NC NC 1IN− 1OU NC VDD2OU 3 2 1 20 19 3 2 1 20 19 3 2 1 20 19 NC 4 18 NC NC 4 18 NC 1IN+ 4 18 2IN− IN− 5 17 VDD IN− 5 17 VDD NC 5 17 NC NC 6 16 NC NC 6 16 NC GND 6 16 2IN+ IN+ 7 15 OUT IN+ 7 15 OUT NC 7 15 NC NC 8 14 NC NC 8 14 NC NC 8 14 NC 9 10 11 12 13 9 10 11 12 13 9 10 11 12 13 C D C C C N N N N N C D C C C C C C C C G N N N N N N N N N N G TLV2463 TLV2464 TLV2465 FK PACKAGE FK PACKAGE FK PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) 1IN− 1OUT NC VDD2OUT 1IN− 1OUT NC 4OUT 4IN− 1IN− 1OUT NC 4OUT 4IN− 3 2 1 20 19 3 2 1 20 19 3 2 1 20 19 1IN+ 4 18 2IN− 1IN+ 4 18 4IN+ 1IN+ 4 18 4IN+ NC 5 17 NC NC 5 17 NC VDD+ 5 17 GND GND 6 16 2IN+ VDD+ 6 16 GND NC 6 16 NC NC 7 15 NC NC 7 15 NC 2IN+ 7 15 3IN+ NC 8 14 NC 2IN+ 8 14 3IN+ 2IN− 8 14 3IN− 9 10 11 12 13 9 10 11 12 13 9 10 11 12 13 N C C C N − T C T − T N C N T D N N N D N U N U N U D N D U H H 2I O O 3I O H H O S S 2 3 2 S S 3 1 2 1/2 3/4 NC − No internal connection (1) SOT−23 may or may not be indicated WWW.TI.COM 5
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V DD Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to V + 0.2 V ID DD Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA I Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 175 mA O Total input current, I (into V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA I DD+ Total output current, I (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I and Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE FOR C and I SUFFIX θθJJCC θθJJAA TTAA ≤≤ 2255°CC TTAA << 112255°CC PPAACCKKAAGGEE (°C/W) (°C/W) POWER RATING POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.6 1022 mW 204.4 mW D (16) 25.7 114.7 1090 mW 218 mW DBV (5) 55 324.1 385 mW 77.1 mW DBV (6) 55 294.3 425 mW 84.9 mW DGK 54.2 259.9 481 mW 96.2 mW DGS 54.1 257.7 485 mW 97 mW N (14, 16) 32 78 1600 mW 320.5 mW P (8) 41 104 1200 mW 240.4 mW PW (14) 29.3 173.6 720 mW 144 mW PW (16) 28.7 161.4 774 mW 154.9 mW NOTE: Thermal resistances are not production tested and are for informational purposes only. DISSIPATION RATING TABLE FOR Q and M SUFFIX TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C‡‡ POWER RATING POWER RATING POWER RATING FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW U 675 mW 5.4 mW/°C 432 mW 350 mW 135 mW ‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for informational purposes only. 6 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 recommended operating conditions MIN MAX UNIT Single supply 2.7 6 SSuuppppllyy vvoollttaaggee,, VVDDDD Split supply ±1.35 ±3 VV Common-mode input voltage range, VICR 0 VDD V C-suffix 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA I-suffix and Q-suffix −40 125 °CC M-suffix −55 125 SShhuuttddoowwnn oonn//ooffff vvoollttaaggee lleevveell‡‡ VIH 2 VV VIL 0.7 ‡Relative to voltage on the GND terminal of the device. electrical characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 500 2000 VVDDDD == 33 VV,, Full range 2200 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVIICC == 11..55 VV,, 25°C 500 1500 µVV VVOO == 11..55 VV,, TTLLVV224466xxAA RRSS == 5500 ΩΩ Full range 1700 αVIO Temperature coefficient of input offset voltage 2 µV/°C 25°C 2.8 7 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVDDDD == 33 VV,, TLV246xC Full range 20 nnAA VVIICC == 11..55 VV,, TLV246xI/Q/M Full range 75 VVOO == 11..55 VV,, 25°C 4.4 14 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt RRS == 5500 Ω TLV246xC Full range 25 nnAA TLV246xI/Q/M Full range 75 25°C 2.9 IIOOHH == −−22..55 mmAA Full range 2.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee 25°C 2.7 VV IIOOHH == −−1100 mmAA Full range 2.5 25°C 0.1 VVIICC == 11..55 VV,, IIOOLL == 22..55 mmAA Full range 0.2 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee 25°C 0.3 VV VVIICC == 11..55 VV,, IIOOLL == 1100 mmAA Full range 0.5 25°C 50 SSoouurrcciinngg Full range 20 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 25°C 40 mmAA SSiinnkkiinngg Full range 20 IO Output current Measured 1 V from rail 25°C ±40 mA LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee 25°C 90 105 AAVVDD amplification RRLL == 1100 kkΩΩ, VVOO((PPPP)) == 11 VV Full range 89 ddBB ri(d) Differential input resistance 25°C 109 Ω †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. WWW.TI.COM 7
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD (continued) PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT Common-mode input ci(c) capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 33 Ω 25°C 66 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VRRVIISSCC ==RR 55==00 00ΩΩ ttoo 33 VV,, TLV246xC Full range 64 ddBB TLV246xI/Q/M Full range 60 VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 80 85 SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 75 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 85 95 ddBB No load Full range 80 25°C 0.5 0.575 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneellss)) VVOO == 11..55 VV,, NNoo llooaadd mmAA Full range 0.9 SSuuppppllyy ccuurrrreenntt iinn sshhuuttddoowwnn SSHHDDNN << 00..77 VV,, 25°C 0.3 IIDDDD((SSHHDDNN)) (TLV2460, TLV2463, TLV2465) Per channel in shutdown Full range 2.5 µAA †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. operating characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 0.9 1.6 SR Slew rate at unity gain VVROOL ((=PP 1PP0)) ==kΩ 00..88 VV,, CCLL == 116600 ppFF,, Full 0.8 V/µs range f = 100 Hz 25°C 16 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 11 nnVV//√√HHzz In Equivalent input noise current f = 1 kHz 25°C 0.13 pA/√Hz AV = 1 0.006% TTHHDD ++ NN TTnnoooottiiaasseell hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss VVRROOLL ((==PP 11PP00)) ==kkΩΩ 22,, VVff ,,== 11 kkHHzz AV = 10 2255°CC 0.02% AV = 100 0.08% Both channels 7.6 t(on) Amplifier turnon time AV = 1, RL = 10 kΩ Channel 1 only, 25°C µs 7.65 Channel 2 on Both channels 333 Channel 1 only, 328 tt((ooffff)) AAmmpplliiffiieerr ttuurrnnooffff ttiimmee AAVV == 11,, RRLL == 1100 kkΩΩ Channel 2 on 2255°CC nnss Channel 2 only, 329 Channel 1 on Gain-bandwidth product f = 10 kHz, CL = 160 pF RL = 10 kΩ, 25°C 5.2 MHz V((SSTTEEPP))PPPP = 2 V, 0.1% 1.47 AAVV == −−11,, CCLL == 1100 ppFF,, RL = 10 kΩ 0.01% 1.78 ttss SSeettttlliinngg ttiimmee 2255°°CC µss V((SSTTEEPP))PPPP = 2 V, 0.1% 1.77 AAVV == −−11,, CCLL == 5566 ppFF,, RL = 10 kΩ 0.01% 1.98 φm Phase margin at unity gain 25°C 44° Gain margin RRLL == 1100 kkΩΩ,, CCLL == 116600 ppFF 25°C 7 dB †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. 8 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 500 2000 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVVVDDIICCDD == == 22 55..55 VV,, ,, Fu2ll 5r°aCnge 500 21250000 µVV TTLLVV224466xxAA VOO = 2.5 V, Full range 1700 RRSS == 5500 ΩΩ TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt ooffff-- αVVIIOO set voltage 2255°°CC 22 µVV//°°CC 25°C 0.3 7 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVDDDD == 55 VV,, TLV246xC Full range 15 nnAA VVIICC == 22..55 VV,, TLV246xI/Q/M Full range 60 VVOO == 22..55 VV,, 25°C 1.3 14 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt RRS == 5500 Ω TLV246xC Full range 30 nnAA TLV246xI/Q/M Full range 60 25°C 4.9 IIOOHH == −−22..55 mmAA Full range 4.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee 25°C 4.8 VV IIOOHH == −−1100 mmAA Full range 4.7 25°C 0.1 VVIICC == 22..55 VV,, IIOOLL == 22..55 mmAA Full range 0.2 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee 25°C 0.2 VV VVIICC == 22..55 VV,, IIOOLL == 1100 mmAA Full range 0.3 25°C 145 SSoouurrcciinngg Full range 60 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 25°C 100 mmAA SSiinnkkiinngg Full range 60 IO Output current Measured at 1 V from rail 25°C ±80 mA AAVVDD LLaaamrrpggleeif--issciiaggtnnioaanll ddiiffffeerreennttiiaall vvoollttaaggee VVVIIOCC === 122 ..V55 tVVo,, 4 V RRLL == 1100 kkΩΩ,, Fu2ll 5r°aCnge 9920 109 ddBB ri(d) Differential input resistance 25°C 109 Ω ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 29 Ω 25°C 71 85 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VRRVIISSCC ==RR 55==00 00ΩΩ VV ttoo 55 VV,, TLV246xC Full range 69 ddBB TLV246xI/Q/M Full range 60 VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 80 85 ddBB SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 75 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 85 95 ddBB No load Full range 80 25°C 0.55 0.65 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == 22..55 VV,, NNoo llooaadd,, mmAA Full range 1 SSuuppppllyy ccuurrrreenntt iinn sshhuuttddoowwnn SSHHDDNN << 00..77 VV,, PPeerr cchhaannnneellss iinn 25°C 1 IIDDDD((SSHHDDNN)) (TLV2460, TLV2463, TLV2465) shutdown Full range 3 µAA †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. WWW.TI.COM 9
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 operating characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 0.9 1.6 SR Slew rate at unity gain VRVOOL ((=PP 1PP0)) ==kΩ 22 VV,, CCLL == 116600 ppFF,, Full 0.8 V/µs range f = 100 Hz 25°C 14 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 11 nnVV//√√HHzz In Equivalent input noise current f = 100 Hz 25°C 0.13 pA/√Hz VVOO((PPPP)) == 44 VV,, AV = 1 0.004% TTHHDD ++ NN TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss nnooiissee RRLL == 1100 kkΩΩ,, AV = 10 2255°CC 0.01% ff == 1100 kkHHzz AV = 100 0.04% Both channels 7.6 Channel 1 only, 7.65 tt((oonn)) AAmmpplliiffiieerr ttuurrnnoonn ttiimmee AAVV == 11,, RRLL == 1100 kkΩΩ Channel 2 on 2255°CC µµss Channel 2 only, 7.25 Channel 1 on Both channels 333 Channel 1 only, 328 tt((ooffff)) AAmmpplliiffiieerr ttuurrnnooffff ttiimmee AAVV == 11,, RRLL == 1100 kkΩΩ Channel 2 on 2255°CC nnss Channel 2 only, 329 Channel 1 on Gain-bandwidth product f = 10 kHz, RL = 10 kΩ, 25°C 6.4 MHz CL = 160 pF V(STEP)PP = 2 V, 0.1% 1.53 AAVV == −−11,, CL = 10 pF, RL = 10 kΩ 0.01% 1.83 ttss SSeettttlliinngg ttiimmee 2255°°CC µss V(STEP)PP = 2 V, 0.1% 3.13 AAVV == −−11,, CL = 56 pF, RL = 10 kΩ 0.01% 3.33 φm Phase margin at unity gain 25°C 45° Gain margin RRLL == 1100 kkΩΩ,, CCLL == 116600 ppFF 25°C 7 dB †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. 10 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIB Input bias current vs Free-air temperature 3, 4 IIO Input offset current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 6 VOL Low-level output voltage vs Low-level output current 7, 8 VO(PP) Peak-to-peak output voltage vs Frequency 9, 10 Open-loop gain vs Frequency 11, 12 Phase vs Frequency 11, 12 AVD Differential voltage amplification vs Load resistance 13 Capacitive load vs Load resistance 14 Zo Output impedance vs Frequency 15, 16 CMRR Common-mode rejection ratio vs Frequency 17 kSVR Supply-voltage rejection ratio vs Frequency 18, 19 vs Supply voltage 20 IIDDDD SSuuppppllyy ccuurrrreenntt vs Free-air temperature 21 Amplifier turnon characteristics 22 Amplifier turnoff characteristics 23 Supply current turnon 24 Supply current turnoff 25 Shutdown supply current vs Free-air temperature 26 SR Slew rate vs Supply voltage 27 vs Frequency 28, 29 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee vs Common-mode input voltage 30, 31 THD Total harmonic distortion vs Frequency 32, 33 THD+N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35 vs Frequency 11, 12 φφmm PPhhaassee mmaarrggiinn vs Load capacitance 36 vs Free-air temperature 37 vs Supply voltage 38 GGaaiinn bbaannddwwiiddtthh pprroodduucctt vs Free-air temperature 39 Large signal follower 40, 41 Small signal follower 42, 43 Inverting large signal 44, 45 Inverting small signal 46, 47 WWW.TI.COM 11
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 1 1 VDD = 3 V VDD = 5 V 0.8 TA = 25°C 0.8 TA = 25°C V 0.6 V 0.6 m m Voltage − 00..42 Voltage − 00..42 Offset 0 Offset 0 − Input −−00..24 − Input −−00..24 O O VI −0.6 VI −0.6 −0.8 −0.8 −1 −1 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V Figure 1 Figure 2 INPUT BIAS AND INPUT OFFSET CURRENT INPUT BIAS AND INPUT OFFSET CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Current − nA 4.455 IIB VVDI =D 1 =.5 3 V V Current − nA 65 VVDI =D 2 =.5 5 V V Bias and Input Offset 213...32555 Bias and Input Offset 432 IIB − Input O 0.15 − Input O 1 IIO andIBI −0.05 IIO andIBI −01 II −55 −35 −15 5 25 45 65 85 105 125 II −55 −35 −15 5 25 45 65 85 105 125 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 3 Figure 4 12 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 3 5 VDD = 3 VDC VDD = 5 VDC 4.5 Voltage − V 2.25 TA = −55°C Voltage − V 3.45 TA = −55°C High-Level Output 1.15 TATTAA = = =1 822555°°°CCC High-Level Output 21..2355 TATTAA = = =1 822555°°°CCC − H TA = −40°C − H 1 TA = −40°C O 0.5 O V V 0.5 0 0 0 10 20 30 40 50 60 70 80 0 20 40 60 80 100 120 140 160 180 200 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 5 Figure 6 LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 3 4.5 VDD = 3 VDC VDD = 5 VDC 4 V 2.5 V e − TA = −40°C e − 3.5 TA = −40°C g g a a ut Volt 2 TA = 25°C ut Volt 3 TA = 25°C el Outp 1.5 TATA = = 1 8255°°CC el Outp 2.25 TATA = = 1 8255°°CC v v e e L L w- 1 w- 1.5 o o L L − − L L 1 O 0.5 O V TA = −55°C V 0.5 TA = −55°C 0 0 0 10 20 30 40 50 60 70 0 20 40 60 80 100 120 140 160 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 7 Figure 8 WWW.TI.COM 13
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS PEAK-TO-PEAK OUTPUT VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE vs vs FREQUENCY FREQUENCY 3 5.5 VDD = 3 V VDD = 5 V V AV = −10 V 5 AV = −10 Output Voltage − 2.25 TRHLD = =1 01 %kΩ Output Voltage − 34..4355 TRHLD = =1 01 %kΩ Peak 1.5 Peak 2.5 Peak-to- 1 Peak-to- 1.25 − − P) 0.5 P) 1 P P O( O( V V 0.5 0 0 10k 100k 1M 10M 10k 100k 1M 10M f − Frequency − Hz f − Frequency − Hz Figure 9 Figure 10 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 100 40° VDD = ±1.5 V 90 RL = 10 kΩ 20° 80 CL = 0 0° TA = 25°C 70 −20° B − d 60 −40° ain 50 AVD −60° G e p 40 −80° as o h o P L 30 −100° en- Phase p 20 −120° O 10 −140° 0 −160° −10 −180° −20 −200° 10 100 1k 10k 100k 1M 10M f − Frequency − Hz Figure 11 14 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS OPEN-LOOP GAIN AND PHASE vs FREQUENCY 100 40° VDD = ±2.5 V 90 RL = 10 kΩ 20° 80 CL = 0 0° TA = 25°C 70 −20° B − d 60 −40° ain 50 AVD −60° G e p 40 −80° as o h o P L 30 −100° en- Phase p 20 −120° O 10 −140° 0 −160° −10 −180° −20 −200° 10 100 1k 10k 100k 1M 10M f − Frequency − Hz Figure 12 DIFFERENTIAL VOLTAGE AMPLIFICATION CAPACITIVE LOAD vs vs LOAD RESISTANCE LOAD RESISTANCE 180 10000 V TA = 25°C m 160 V/ − n 140 o ati F Phase Margin < 30° c 120 p plifi VDD = ±2.5 V d − m a A 100 Lo ge VDD = ±1.5 V ve 1000 olta 80 citi V a ntial 60 − Cap Phase Margin > 30° ere 40 CL Diff VDD = 5 V − 20 Phase Margin = 30° VD TA = 25°C A 0 100 100 1k 10k 100k 1M 10 100 1k 10k RL − Load Resistance − Ω RL − Load Resistance − Ω Figure 13 Figure 14 WWW.TI.COM 15
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY 1000 1000 VDD = ±1.5 V VDD = ±2.5 V TA = 25°C TA = 25°C 100 100 Ω Ω mpedance − 10 AV = 100 mpedance − 10 AV = 100 Output I 1 AV = 10 Output I 1 AV = 10 − − Zo 0.1 AV = 1 Zo 0.1 AV = 1 0.01 0.01 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M f − Frequency − Hz f − Frequency − Hz Figure 15 Figure 16 COMMON-MODE REJECTION RATIO vs FREQUENCY 90 B d − o 85 ati R n o 80 cti e VDD = 5 V Rej VIC = 2.5 V e 75 d o on-M VVDICD = = 1 3.5 V V m 70 m o C − R 65 R M C 60 10 100 1k 10k 100k 1M 10M f − Frequency − Hz Figure 17 16 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS SUPPLY-VOLTAGE REJECTION RATIO SUPPLY-VOLTAGE REJECTION RATIO vs vs FREQUENCY FREQUENCY 110 90 Rejection Ratio − dB 1890000 −kS+VkRSVR VTAD D= =25 ±°1C.5 V Rejection Ratio − dB 8700 −kSVR +kSVR VTAD D= =25 ±°2C.5 V Voltage 70 Voltage 60 − Supply 60 +kSVR − Supply 50 +kSVR R 50 R kSV −kSVR kSV −kSVR 40 40 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M f − Frequency − Hz f − Frequency − Hz Figure 18 Figure 19 SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 0.8 0.80 IDD = 125°C 0.7 IDD = 85°C 0.75 mA A 0.70 VDD = 5 V ent − 0.6 nt − m 0.65 VI = 2.5 V urr 0.5 rre 0.60 C u pply ply C 0.55 u 0.40 p VDD = 3 V S u 0.50 − D IDD = 25°C − S VI = 1.5 V ID 0.30 IDD = −55°C DD 0.45 I IDD = −40°C 0.40 0.20 0.35 0.10 0.30 2.5 3 3.5 4 4.5 5 5.5 6 −55 −35 −15 5 25 45 65 85 105 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 20 Figure 21 WWW.TI.COM 17
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS AMPLIFIER WITH A SHUTDOWN PULSE AMPLIFIER WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS TURNOFF CHARACTERISTICS 5 5 VDD = 5 V 4 Shutdown Pin 4 Shutdown Pin RL = 10 kΩ AV = 1 V 3 3 TA = 25°C age − 2 e − V 2 olt ag own V 1 n Volt 1 d 0 w 0 − Shut 3 Amplifier Output Shutdo 3 Amplifier Output SD VDD = 5 V − V 2 RL = 10 kΩ SD 2 AV = 1 V 1 TA = 25°C 1 0 0 −5 −3 −1 1 3 5 7 9 11 −5 −3 −1 1 3 5 7 t − Time − µs t − Time − µs Figure 22 Figure 23 SUPPLY CURRENT WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS 1 5.5 Shutdown Pin 0.8 4.5 V − mA 0.6 3.5 ge − ent olta r V ur Supply Current n C 0.4 2.5 w y o ppl utd u h S S − 0.2 1.5 − D D D S I VDD = 5 V V 0 VI = 2.5 V 0.5 AV = 1 TA = 25°C −0.2 −0.5 −0.4 −0.2 0 0.2 0.4 0.6 t − Time − µs Figure 24 18 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS TURNOFF SUPPLY CURRENT WITH A SHUTDOWN PULSE 1 5.5 VDD = 5 V VI = 2.5 V 0.8 Shutdown Pin AV = 1 4.5 TA = 25°C V − mA 0.6 3.5 ge − ent olta r V ur n C 0.4 Supply Current 2.5 w y o ppl utd u h S S − 0.2 1.5 − D D D S I V 0 0.5 −0.2 −0.5 −0.4 −0.2 0 0.2 0.4 0.6 t − Time − µs Figure 25 SHUTDOWN SUPPLY CURRENT SLEW RATE vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 3 1.8 A 2.5 1.75 µ − nt 2 VDD = 5 V 1.7 urre VI = 2.5 V µs 1.65 SR+ pply C 1.5 e − V/ 1.6 utdown Su 0.15 VVID =D 1 =.5 3 V V − Slew Rat 11.5.55 SR− h R S S 1.45 VO(PP) = 2 V 0 − CL = 160 pF D 1.4 D AV = 1 I −0.5 RL = 10 kΩ 1.35 TA = 25°C −1 1.3 −55 −35 −15 5 25 45 65 85 105 125 2.5 3 3.5 4 4.5 5 5.5 6 TA − Free-Air Temperature − °C VDD − Supply Voltage − V Figure 26 Figure 27 WWW.TI.COM 19
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS EQUIVALENT INPUT NOISE VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE vs vs FREQUENCY FREQUENCY 18 18 Hz 17 VAVD D= =1 03 V Hz 17 VAVD D= =1 05 V V/ VI = 1.5 V V/ VI = 2.5 V nVoltage − 1156 TA = 25°C nVoltage − 1156 TA = 25°C Noise 14 Noise 14 − Equivalent Input 111123 − Equivalent Input 111123 Vn Vn 10 10 100 1k 10k 100k 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz Figure 28 Figure 29 EQUIVALENT INPUT NOISE VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 20 20 Hz VDD = 3 V Hz VDD = 5 V AV = 10 AV = 10 nV/Noise Voltage − 111543 fT A= 1= k2H5°zC nV/Noise Voltage − 111435 fT A= 1= k2H5°zC − Equivalent Input 1112 − Equivalent Input 1112 Vn Vn 10 10 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V Figure 30 Figure 31 20 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY 0.5 1 VDD = ±1.5 V VDD = ±2.5 V VO(PP) = 2 V VO(PP) = 4 V % RL = 10 kΩ % RL = 10 kΩ Distortion − 0.1 AV = 100 Distortion − 0.1 AV = 100 monic AV = 10 monic D − Total Har 0.010 AV = 1 D − Total Har 0.010 AV = 10 H H AV = 1 T T 0.001 0.001 10 100 1k 10k 100k 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz Figure 32 Figure 33 TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs PEAK-TO-PEAK SIGNAL AMPLITUDE PEAK-TO-PEAK SIGNAL AMPLITUDE 1 1 % VDD = 3 V % RL = 250 Ω Distortion + Noise − 0.1 ATAV == 215°C RRLL R= = L1 20= kk2ΩΩ50 Ω Distortion + Noise − 0.1 RL = R1L0 k=Ω 2 kΩ monic monic Har 0.010 Har 0.010 N − Total RL = 100 kΩ N − Total VDD = 5 V RL = 100 kΩ D+ D+ AV = 1 TH TH TA = 25°C 0.001 0.001 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 Peak-to-Peak Signal Amplitude − V Peak-to-Peak Signal Amplitude − V Figure 34 Figure 35 WWW.TI.COM 21
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS PHASE MARGIN PHASE MARGIN vs vs LOAD CAPACITANCE FREE-AIR TEMPERATURE 90 60 VDD = ±2.5 V RL = 10 kΩ 80 TA = 25°C CL = 160 pF RL = 10 kΩ 55 es 70 s e e gr Rnull = 50 Ω re de 60 eg 50 rgin − 50 gin − d VDD = ±2.5 V Ma ar 45 − Phase 4300 Rnull = 20 Ω − Phase M 40 VDD = ±1.5 V m φ 20 Rnull = 0 Ω φm 35 10 0 30 10 100 1k 10k 100k −55 −35 −15 5 25 45 65 85 105 125 CL − Load Capacitance − pF TA − Free-Air Temperature − °C Figure 36 Figure 37 GAIN BANDWIDTH PRODUCT GAIN BANDWIDTH PRODUCT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 5 5 CL = 160 pF RL = 10 kΩ RL = 10 kΩ 4.75 CL = 160 pF 4.75 f = 10 kHz MHz TA = 25°C MHz 4.5 VDD = ±2.5 V − − ct 4.5 ct du du 4.25 o o Pr Pr h 4.25 h 4 dt dt wi wi and 4 and 3.75 ain B ain B 3.5 VDD = ±1.5 V G G 3.75 3.25 3.5 3 2.5 3 3.5 4 4.5 5 5.5 6 −55 −35 −15 5 25 45 65 85 105 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 38 Figure 39 22 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER 2.2 3.7 2 3.3 Input Input 1.8 2.9 V V − Output − Output e 1.6 e g g a a 2.5 olt olt − VO 1.4 VDD = 3 V Input − VO VVDI(PDP =) =5 2V V Input V VI(PP) = 1 V V 2.1 VI = 2.5 V 1.2 VRIL = = 1 1.50 VkΩ Output RCLL == 1106 0k pΩF Output 1 CATAVL === 21156°0C pF 1.7 ATAV == 215°C 0.8 1.3 −2 0 2 4 6 8 10 12 14 16 18 −2 0 2 4 6 8 10 12 14 16 18 t − Time − µs t − Time − µs Figure 40 Figure 41 SMALL SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER 1.6 2.6 1.55 2.55 V V − Input − Input e e g g a 1.5 a 2.5 olt olt V V − Output − Output O O V V 1.45 2.45 VDD = 3 V VDD = 5 V VI(PP) = 100 mV CL = 160 pF VI(PP) = 100 mV CL = 160 pF VI = 1.5 V AV = 1 VI = 2.5 V AV = 1 RL = 10 kΩ TA = 25°C RL = 10 kΩ TA = 25°C 1.4 2.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t − Time − µs t − Time − µs Figure 42 Figure 43 WWW.TI.COM 23
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS INVERTING LARGE SIGNAL INVERTING LARGE SIGNAL 2.3 4 2.1 Input Input 3.5 1.9 VDD = 3 V VDD = 5 V 1.7 VI(PP) = 1 V 3 VI(PP) = 2 V e − V 1.5 VRIL = = 1 1.50 VkΩ e − V VRIL = = 2 1.50 VkΩ ag CL = 160 pF ag 2.5 CL = 160 pF − Volt 1.3 ATAV == 2−51°C − Volt ATAV == 2−51°C O O V 1.1 V 2 0.9 Output Output 1.5 0.7 0.5 1 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t − Time − µs t − Time − µs Figure 44 Figure 45 INVERTING SMALL SIGNAL INVERTING SMALL SIGNAL 1.6 2.6 Input Input 1.55 2.55 VDD = 3 V VDD = 5 V − V VI(PP) = 100 mV − V VI(PP) = 100 mV Voltage 1.5 VRCILL = == 1 11.506 0Vk pΩF Voltage 2.5 VRCILL = == 2 11.506 0Vk pΩF − AV = −1 − AV = −1 VO TA = 25°C VO TA = 25°C 1.45 2.45 Output Output 1.4 2.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t − Time − µs t − Time − µs Figure 46 Figure 47 24 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION _ Rnull + RL CL Figure 48 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (R ) with the output of the amplifier, as NULL shown in Figure 49. A minimum value of 20 Ω should work well for most applications. RF RG Input _ RNULL Output + CLOAD Figure 49. Driving a Capacitive Load offset voltage The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB− RG + − VI VO + RS (cid:2) IIB+(cid:4) (cid:2) (cid:4) (cid:2) (cid:4) (cid:2) (cid:4) R R VOO(cid:1)VIO 1(cid:3) RF (cid:5)IIB(cid:3)RS 1(cid:3) RF (cid:5)IIB–RF G G Figure 50. Output Offset Voltage Model WWW.TI.COM 25
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 51). RG RF − + VO VI R1 C1 f (cid:1) 1 –3dB 2(cid:1)R1C1 (cid:2) (cid:4) V R (cid:2) (cid:4) O (cid:1) 1(cid:3) F 1 V R 1(cid:3)sR1C1 I G Figure 51. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) VI + R1 R2 _ f (cid:1) 1 –3dB 2(cid:1)RC C2 RF RG = RF (2 − 1 ) RG Q Figure 52. 2-Pole Low-Pass Sallen-Key Filter 26 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 APPLICATION INFORMATION shutdown function Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2. DD Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to V − (not GND) to disable the operational amplifier. DD The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. circuit layout considerations To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. WWW.TI.COM 27
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 APPLICATION INFORMATION general power dissipation considerations For a given θ , the maximum power dissipation is shown in Figure 53 and is calculated by the following formula: JA (cid:2) (cid:4) T –T P (cid:1) MAX A D (cid:1) JA Where: P = Maximum power dissipation of THS246x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A θJA = θJC + θCA θ = Thermal coefficient from junction to case JC θ = Thermal coefficient from case to ambient air (°C/W) CA MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 PDIP Package TJ = 150°C 1.75 Low-K Test PCB θJA = 104°C/W W n − 1.5 MSOP Package o pati 1.25 SOIC Package LθJoAw -=K 2 T6e0s°tC P/WCB si Low-K Test PCB Dis θJA = 176°C/W r 1 e w o m P 0.75 u m xi 0.5 a M 0.25 SOT-23 Package Low-K Test PCB 0 θJA = 324°C/W −55−40−25 −10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 53. Maximum Power Dissipation vs Free-Air Temperature 28 WWW.TI.COM
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are generated using the TLV246x typical electrical and operating characteristics at T = 25°C. Using this A information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (cid:1) (cid:1) Maximum positive output voltage swing Unity-gain frequency (cid:1) (cid:1) Maximum negative output voltage swing Common-mode rejection ratio (cid:1) (cid:1) Slew rate Phase margin (cid:1) (cid:1) Quiescent power dissipation DC output resistance (cid:1) (cid:1) Input bias current AC output resistance (cid:1) (cid:1) Open-loop voltage amplification Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 EGND + FB RO2 − C2 3 R2 6 7 VDD+ + + ISS RSS CSS VD 9 + VLIM RP − VB GCM GA 8 − 2 10 53 − IN− DC RO1 J1 J2 IN+ OUT 1 11 12 DE DLN 5 92 C1 54 DP 90 91 RD1 RD2 + + + − DLP VE HLIM VLP VLN 4 − − − + GND .SUBCKT TLV246X 1 2 3 4 5 RD1 3 11 2.8964E3 C1 11 12 2.46034E−12 RD2 3 12 2.8964E3 C2 6 7 10.0000E−12 R01 8 5 5.6000 CSS 10 99 443.21E−15 R02 7 99 6.2000 DC 5 53 DY RP 3 4 8.9127 DE 54 5 DY RSS 10 99 10.610E6 DLP 90 91 DX VB 9 0 DC 0 DLN 92 90 DX VC 3 53 DC .7836 DP 4 3 DX VE 54 4 DC .7436 EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 VLIM 7 8 DC 0 FB 7 99 POLY (5) VB VC VE VLP VLP 91 0 DC 117 + VLN 0 21.600E6 −1E3 1E3 22E6 −22E6 VLN 0 92 DC 117 GA 6 0 11 12 345.26E−6 .MODEL DX D (IS=800.00E−18) GCM 0 6 10 99 15.4226E−9 .MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p) ISS 10 4 DC 18.850E−6 .MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3 HLIM 90 0 VLIM 1K + VTO=−1) J1 11 2 10 JX1 .MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3 J2 12 1 10 JX2 + VTO=−1) R2 6 9 100.00E3 .ENDS Figure 54. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. WWW.TI.COM 29
Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 macromodel information (continued) .subckt TLV_246Y 1 2 3 4 5 6 rp 3 71 8.9127 c1 11 12 2.4603E−12 rss 10 99 10.610E6 c2 72 7 10.000E−12 rs1 6 4 1G css 10 99 443.21E−15 rs2 6 4 1G dc 70 53 dy rs3 6 4 1G de 54 70 dy rs4 6 4 1G dlp 90 91 dx s1 71 4 6 4 s1x dln 92 90 dx s2 70 5 6 4 s1x dp 4 3 dx s3 10 74 6 4 s1x egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 s4 74 4 6 4 s2x fb 7 99 poly(5) vb vc ve vlp vln 0 vb 9 0 dc 0 21.600E6 −1E3 1E3 22E6 −22E6 vc 3 53 dc .7836 ga 72 0 11 12 345.26E−6 ve 54 4 dc .7436 gcm 0 72 10 99 15.422E−9 vlim 7 8 dc 0 iss 74 4 dc 18.850E−6 vlp 91 0 dc 117 hlim 90 0 vlim 1K vln 0 92 dc 117 j1 11 2 10 jx1 .model dx D(Is=800.00E−18) j2 12 1 10 jx2 .model dy D(Is=800.00E−18 Rs=1m Cjo=10p) r2 72 9 100.00E3 .model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1) rd1 3 11 2.8964E3 .model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1) rd2 3 12 2.8964E3 .model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0) ro1 8 70 5.6000 .model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5) ro2 7 99 6.2000 .ends Figure 54. Boyle Macromodels and Subcircuit (Continued) 30 WWW.TI.COM
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-0051201QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051201QHA TLV2460M 5962-0051203QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051203QHA TLV2461M 5962-0051205QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051205QHA TLV2462M 5962-0051206Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 0051206Q2A TLV2462A MFKB 5962-0051206QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051206QHA TLV2462AM 5962-0051206QPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 0051206QPA TLV2462AM TLV2460AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2460AI & no Sb/Br) TLV2460AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2460AI & no Sb/Br) TLV2460CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2460C & no Sb/Br) TLV2460ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2460I & no Sb/Br) Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2460IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAOI & no Sb/Br) TLV2460IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAOI & no Sb/Br) TLV2460IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAOI & no Sb/Br) TLV2460IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2460I & no Sb/Br) TLV2460IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2460I & no Sb/Br) TLV2460MUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051201QHA TLV2460M TLV2461AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2461AI & no Sb/Br) TLV2461AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2461AI & no Sb/Br) TLV2461AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2461AI & no Sb/Br) TLV2461CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2461C & no Sb/Br) TLV2461CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAPC & no Sb/Br) TLV2461CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAPC & no Sb/Br) TLV2461CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAPC & no Sb/Br) TLV2461CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2461C & no Sb/Br) TLV2461CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2461C & no Sb/Br) TLV2461ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2461I & no Sb/Br) TLV2461IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAPI & no Sb/Br) Addendum-Page 2
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2461IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAPI & no Sb/Br) TLV2461IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAPI & no Sb/Br) TLV2461IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2461I & no Sb/Br) TLV2461IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2461I & no Sb/Br) TLV2461MUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051203QHA TLV2461M TLV2462AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462AI & no Sb/Br) TLV2462AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462AI & no Sb/Br) TLV2462AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462AI & no Sb/Br) TLV2462AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2462AI & no Sb/Br) TLV2462AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 0051206Q2A TLV2462A MFKB TLV2462AMJG ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 TLV2462AMJG TLV2462AMJGB ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 0051206QPA TLV2462AM TLV2462AMUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051206QHA TLV2462AM TLV2462AQD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V2462A & no Sb/Br) TLV2462AQDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM V2462A & no Sb/Br) TLV2462AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM V2462A & no Sb/Br) TLV2462AQPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V2462A & no Sb/Br) Addendum-Page 3
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2462AQPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM V2462A & no Sb/Br) TLV2462CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2462C & no Sb/Br) TLV2462CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2462C & no Sb/Br) TLV2462CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AAI & no Sb/Br) TLV2462CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAI & no Sb/Br) TLV2462CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AAI & no Sb/Br) TLV2462CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAI & no Sb/Br) TLV2462CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2462C & no Sb/Br) TLV2462CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2462C & no Sb/Br) TLV2462CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2462CP & no Sb/Br) TLV2462CPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2462CP & no Sb/Br) TLV2462ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462I & no Sb/Br) TLV2462IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462I & no Sb/Br) TLV2462IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AAJ & no Sb/Br) TLV2462IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAJ & no Sb/Br) TLV2462IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AAJ & no Sb/Br) TLV2462IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAJ & no Sb/Br) Addendum-Page 4
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2462IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2462I & no Sb/Br) TLV2462IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2462IP & no Sb/Br) TLV2462MUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051205QHA TLV2462M TLV2462QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V2462Q & no Sb/Br) TLV2462QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM V2462Q & no Sb/Br) TLV2463AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2463AI & no Sb/Br) TLV2463AMJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 TLV2463AMJ TLV2463CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2463C & no Sb/Br) TLV2463CDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2463C & no Sb/Br) TLV2463CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2463CN & no Sb/Br) TLV2463ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2463I & no Sb/Br) TLV2463IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAL & no Sb/Br) TLV2463IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAL & no Sb/Br) TLV2463IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2463IN & no Sb/Br) TLV2464AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) Addendum-Page 5
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2464AIDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) TLV2464AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) TLV2464AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) TLV2464AIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2464AIN & no Sb/Br) TLV2464AIPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TY2464A & no Sb/Br) TLV2464AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TY2464A & no Sb/Br) TLV2464CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2464C & no Sb/Br) TLV2464CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2464C & no Sb/Br) TLV2464CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2464CN & no Sb/Br) TLV2464CNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2464CN & no Sb/Br) TLV2464CPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV2464 & no Sb/Br) TLV2464CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TV2464 & no Sb/Br) TLV2464ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2464I & no Sb/Br) TLV2464IDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2464I & no Sb/Br) TLV2464IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2464I & no Sb/Br) TLV2464IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2464IN & no Sb/Br) TLV2464IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TY2464 & no Sb/Br) Addendum-Page 6
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLV2464IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TY2464 & no Sb/Br) TLV2464IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TY2464 & no Sb/Br) TLV2465CD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2465C & no Sb/Br) TLV2465CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2465C & no Sb/Br) TLV2465CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2465C & no Sb/Br) TLV2465ID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2465I & no Sb/Br) TLV2465IDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2465I & no Sb/Br) TLV2465IN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2465IN & no Sb/Br) TLV2465IPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) TLV2465IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) TLV2465IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 7
PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2460, TLV2460A, TLV2460M, TLV2461, TLV2461A, TLV2461M, TLV2462, TLV2462A, TLV2462AM, TLV2462M, TLV2463, TLV2463A, TLV2463AM, TLV2464A : •Catalog: TLV2460, TLV2461, TLV2462A, TLV2462, TLV2463A •Automotive: TLV2460-Q1, TLV2460A-Q1, TLV2460-Q1, TLV2461-Q1, TLV2461A-Q1, TLV2461-Q1, TLV2462-Q1, TLV2462A-Q1, TLV2462A-Q1, TLV2462-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2463A-Q1, TLV2464A-Q1 •Enhanced Product: TLV2462A-EP, TLV2462A-EP, TLV2464A-EP •Military: TLV2460M, TLV2461M, TLV2462M, TLV2462AM, TLV2463AM NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 8
PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2460AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2460CDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460CDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2460IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461CDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2461CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462AQPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462AQPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2462CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462QPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2463AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2463CDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2463CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2463IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2464AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2464CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2464IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2465CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2465CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2465IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2465IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page2
PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2460AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2460CDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2460CDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2460CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2460IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2460IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2460IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV2461CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV2461CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV2461IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV2461IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462AQPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462AQPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2462CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2462CDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page3
PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2462IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2462IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2462IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462QPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462QPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 TLV2463AIDR SOIC D 14 2500 350.0 350.0 43.0 TLV2463CDGSR VSSOP DGS 10 2500 358.0 335.0 35.0 TLV2463CDR SOIC D 14 2500 350.0 350.0 43.0 TLV2463IDGSR VSSOP DGS 10 2500 358.0 335.0 35.0 TLV2464AIDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2464CDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2464IDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2465CDR SOIC D 16 2500 350.0 350.0 43.0 TLV2465CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV2465IDR SOIC D 16 2500 350.0 350.0 43.0 TLV2465IPWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page4
PACKAGE OUTLINE U0010A CFP - 2.03 mm max height SCALE 1.400 CERAMIC FLATPACK .27 MAX .045 MAX .010 .002 PIN 1 ID GLASS .005 MIN TYP TYP 1 10 8X .050 .005 .27 MAX GLASS 10X .017 .002 5 6 +.019 5X .32 .01 .241 5X .32 .01 -.003 .005 .001 +.013 .067 -.012 .045 .026 4225582/A 01/2020 NOTES: 1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com
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PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com
EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com
EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com
EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com
PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 4.75 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 8X 0.5 10 1 3.1 2X 2.9 NOTE 3 2 5 6 0.27 10X 0.17 B 3.1 0.1 C A B 1.1 MAX 2.9 NOTE 4 0.23 TYP SEE DETAIL A 0.13 0.25 GAGE PLANE 0.15 0.7 0 - 8 0.05 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com
EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM (R0.05) TYP 1 10 SYMM 8X (0.5) 5 6 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) SYMM (R0.05) TYP 10X (0.3) 1 10 SYMM 8X (0.5) 5 6 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com
EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com
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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com
EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com
EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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