【线性 - 放大器 - 仪表，运算放大器，缓冲器放大器_TLV2462AQPWR】封装/厂家_TLV2462AQPWR中文资料_价格

ICGOO在线商城 > 集成电路（IC） > 线性 - 放大器 - 仪表，运算放大器，缓冲器放大器 > TLV2462AQPWR

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型号： TLV2462AQPWR
制造商： Texas Instruments
库位|库存： xxxx|xxxx
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TLV2462AQPWR产品简介：

ICGOO电子元器件商城为您提供TLV2462AQPWR由Texas Instruments设计生产，在icgoo商城现货销售，并且可以通过原厂、代理商等渠道进行代购。 TLV2462AQPWR价格参考￥11.83-￥12.84。Texas InstrumentsTLV2462AQPWR封装/规格：线性 - 放大器 - 仪表，运算放大器，缓冲器放大器，通用放大器 2 电路满摆幅 8-TSSOP。您可以下载TLV2462AQPWR参考资料、Datasheet数据手册功能说明书，资料中有TLV2462AQPWR 详细功能的应用电路图电压和使用方法及教程。

产品参数图文手册常见问题

参数	数值
-3db带宽	-
产品目录	集成电路 (IC)
描述	IC OPAMP GP 6.4MHZ RRO 8TSSOP
产品分类	Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps
品牌	Texas Instruments
数据手册	点击此处下载产品Datasheet
产品图片
产品型号	TLV2462AQPWR
rohs	无铅 / 符合限制有害物质指令(RoHS)规范要求
产品系列	-
产品目录页面	点击此处下载产品Datasheet
供应商器件封装	8-TSSOP
其它名称	296-12067-2
包装	带卷（TR）
压摆率	1.6 V/µs
增益带宽积	6.4MHz
安装类型	表面贴装
封装/外壳	8-TSSOP（0.173"，4.40mm 宽）
工作温度	-40°C ~ 125°C
放大器类型	通用
标准包装	2,000
电压-电源，单/双 (±)	2.7 V ~ 6 V， ±1.35 V ~ 3 V
电压-输入失调	500µV
电流-电源	550µA
电流-输入偏置	1.3nA
电流-输出/通道	80mA
电路数	2
输出类型	满摆幅

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Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 (cid:1) Rail-to-Rail Output Swing TLV2460 (cid:1) DBV PACKAGE Gain Bandwidth Product...6.4 MHz (TOP VIEW) (cid:1) ±80 mA Output Drive Capability (cid:1) Supply Current...500 µA/channel OUT 1 6 VDD+ (cid:1) Input Offset Voltage...100 µV GND 2 5 SHDN (cid:1) Input Noise Voltage...11 nV/√Hz (cid:1) Slew Rate...1.6 V/µs IN+ 3 4 IN− (cid:1) Micropower Shutdown Mode (TLV2460/3/5)...0.3 µA/Channel (cid:1) Universal Operational Amplifier EVM (cid:1) Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control/Print Support Qualification to Automotive Standards description The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for portable applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters. The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current, providing good ac performance with low power consumption. Three members of the family offer a shutdown terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown, the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV. This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for high-density circuits. The family is specified over an expanded temperature range (T = −40°C to 125°C) for A use in industrial control and automotive systems, and over the military temperature range (T = −55°C to 125°C) for use in military systems. A SELECTION GUIDE VDD VIO IDD/ch IIB GBW SLEW RATE Vn, 1 kHz IO DEVICE SHUTDOWN RAIL-RAIL [V] [µV] [µA] [pA] [MHz] [V/µs] [nV/√Hz] [mA] TLV246x(A) 2.7−6 150 550 1300 6.4 1.6 11 25 Y I/O TLV277x(A) 2.5−5.5 360 1000 2 5.1 10.5 17 6 Y O TLV247x(A) 2.7−6 250 600 2.5 2.8 1.5 15 20 Y I/O TLV245x(A) 2.7−6 20 23 500 0.22 0.11 52 10 Y I/O TLV225x(A) 2.7−8 200 35 1 0.2 0.12 19 3 — — TLV226x(A) 2.7−8 300 200 1 0.71 0.55 12 3 — — Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:21)(cid:23)(cid:18)(cid:29)(cid:25)(cid:30)(cid:1)(cid:16)(cid:18)(cid:24) (cid:29)(cid:13)(cid:1)(cid:13) (cid:31)!"#$%&’(cid:31)#! (cid:31)( )*$$+!’ &( #" ,*-.(cid:31))&’(cid:31)#! /&’+0 Copyright  1998−2004, Texas Instruments Incorporated (cid:21)$#/*)’( )#!"#$% ’# (,+)(cid:31)"(cid:31))&’(cid:31)#!( ,+$ ’1+ ’+$%( #" (cid:1)+(cid:12)&( (cid:16)!(’$*%+!’( (cid:18)! ,$#/*)’( )#%,.(cid:31)&!’ ’# (cid:15)(cid:16)(cid:2)(cid:20)(cid:21)(cid:23)(cid:14)(cid:20)(cid:10)5(cid:11)(cid:10)(cid:11)(cid:8) &.. ,&$&%+’+$( &$+ ’+(’+/ (’&!/&$/ 2&$$&!’30 (cid:21)$#/*)’(cid:31)#! ,$#)+(((cid:31)!4 /#+( !#’ !+)+((&$(cid:31).3 (cid:31)!).*/+ *!.+(( #’1+$2(cid:31)(+ !#’+/0 (cid:18)! &.. #’1+$ ,$#/*)’((cid:8) ,$#/*)’(cid:31)#! ’+(’(cid:31)!4 #" &.. ,&$&%+’+$(0 ,$#)+(((cid:31)!4 /#+( !#’ !+)+((&$(cid:31).3 (cid:31)!).*/+ ’+(’(cid:31)!4 #" &.. ,&$&%+’+$(0 WWW.TI.COM 1

Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V DD Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to V + 0.2 V ID DD Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA I Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 175 mA O Total input current, I (into V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA I DD+ Total output current, I (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I and Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE FOR C and I SUFFIX θθJJCC θθJJAA TTAA ≤≤ 2255°CC TTAA << 112255°CC PPAACCKKAAGGEE (°C/W) (°C/W) POWER RATING POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.6 1022 mW 204.4 mW D (16) 25.7 114.7 1090 mW 218 mW DBV (5) 55 324.1 385 mW 77.1 mW DBV (6) 55 294.3 425 mW 84.9 mW DGK 54.2 259.9 481 mW 96.2 mW DGS 54.1 257.7 485 mW 97 mW N (14, 16) 32 78 1600 mW 320.5 mW P (8) 41 104 1200 mW 240.4 mW PW (14) 29.3 173.6 720 mW 144 mW PW (16) 28.7 161.4 774 mW 154.9 mW NOTE: Thermal resistances are not production tested and are for informational purposes only. DISSIPATION RATING TABLE FOR Q and M SUFFIX TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C‡‡ POWER RATING POWER RATING POWER RATING FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW U 675 mW 5.4 mW/°C 432 mW 350 mW 135 mW ‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for informational purposes only. 6 WWW.TI.COM

Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD (continued) PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT Common-mode input ci(c) capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 33 Ω 25°C 66 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VRRVIISSCC ==RR 55==00 00ΩΩ ttoo 33 VV,, TLV246xC Full range 64 ddBB TLV246xI/Q/M Full range 60 VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 80 85 SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 75 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 85 95 ddBB No load Full range 80 25°C 0.5 0.575 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneellss)) VVOO == 11..55 VV,, NNoo llooaadd mmAA Full range 0.9 SSuuppppllyy ccuurrrreenntt iinn sshhuuttddoowwnn SSHHDDNN << 00..77 VV,, 25°C 0.3 IIDDDD((SSHHDDNN)) (TLV2460, TLV2463, TLV2465) Per channel in shutdown Full range 2.5 µAA †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. operating characteristics at specified free-air temperature, V = 3 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 0.9 1.6 SR Slew rate at unity gain VVROOL ((=PP 1PP0)) ==kΩ 00..88 VV,, CCLL == 116600 ppFF,, Full 0.8 V/µs range f = 100 Hz 25°C 16 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 11 nnVV//√√HHzz In Equivalent input noise current f = 1 kHz 25°C 0.13 pA/√Hz AV = 1 0.006% TTHHDD ++ NN TTnnoooottiiaasseell hhaarrmmoonniicc ddiissttoorrttiioonn pplluuss VVRROOLL ((==PP 11PP00)) ==kkΩΩ 22,, VVff ,,== 11 kkHHzz AV = 10 2255°CC 0.02% AV = 100 0.08% Both channels 7.6 t(on) Amplifier turnon time AV = 1, RL = 10 kΩ Channel 1 only, 25°C µs 7.65 Channel 2 on Both channels 333 Channel 1 only, 328 tt((ooffff)) AAmmpplliiffiieerr ttuurrnnooffff ttiimmee AAVV == 11,, RRLL == 1100 kkΩΩ Channel 2 on 2255°CC nnss Channel 2 only, 329 Channel 1 on Gain-bandwidth product f = 10 kHz, CL = 160 pF RL = 10 kΩ, 25°C 5.2 MHz V((SSTTEEPP))PPPP = 2 V, 0.1% 1.47 AAVV == −−11,, CCLL == 1100 ppFF,, RL = 10 kΩ 0.01% 1.78 ttss SSeettttlliinngg ttiimmee 2255°°CC µss V((SSTTEEPP))PPPP = 2 V, 0.1% 1.77 AAVV == −−11,, CCLL == 5566 ppFF,, RL = 10 kΩ 0.01% 1.98 φm Phase margin at unity gain 25°C 44° Gain margin RRLL == 1100 kkΩΩ,, CCLL == 116600 ppFF 25°C 7 dB †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. 8 WWW.TI.COM

Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 500 2000 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVVVDDIICCDD == == 22 55..55 VV,, ,, Fu2ll 5r°aCnge 500 21250000 µVV TTLLVV224466xxAA VOO = 2.5 V, Full range 1700 RRSS == 5500 ΩΩ TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt ooffff-- αVVIIOO set voltage 2255°°CC 22 µVV//°°CC 25°C 0.3 7 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVDDDD == 55 VV,, TLV246xC Full range 15 nnAA VVIICC == 22..55 VV,, TLV246xI/Q/M Full range 60 VVOO == 22..55 VV,, 25°C 1.3 14 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt RRS == 5500 Ω TLV246xC Full range 30 nnAA TLV246xI/Q/M Full range 60 25°C 4.9 IIOOHH == −−22..55 mmAA Full range 4.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee 25°C 4.8 VV IIOOHH == −−1100 mmAA Full range 4.7 25°C 0.1 VVIICC == 22..55 VV,, IIOOLL == 22..55 mmAA Full range 0.2 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee 25°C 0.2 VV VVIICC == 22..55 VV,, IIOOLL == 1100 mmAA Full range 0.3 25°C 145 SSoouurrcciinngg Full range 60 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt 25°C 100 mmAA SSiinnkkiinngg Full range 60 IO Output current Measured at 1 V from rail 25°C ±80 mA AAVVDD LLaaamrrpggleeif--issciiaggtnnioaanll ddiiffffeerreennttiiaall vvoollttaaggee VVVIIOCC === 122 ..V55 tVVo,, 4 V RRLL == 1100 kkΩΩ,, Fu2ll 5r°aCnge 9920 109 ddBB ri(d) Differential input resistance 25°C 109 Ω ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 29 Ω 25°C 71 85 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VRRVIISSCC ==RR 55==00 00ΩΩ VV ttoo 55 VV,, TLV246xC Full range 69 ddBB TLV246xI/Q/M Full range 60 VVDDDD == 22..77 VV ttoo 66 VV,, VVIICC == VVDDDD//22,, 25°C 80 85 ddBB SSuuppppllyy vvoollttaaggee rreejjeeccttiioonn rraattiioo No load Full range 75 kkSSVVRR ((∆VVDDDD //∆VVIIOO)) VVDDDD == 33 VV ttoo 55 VV,, VVIICC == VVDDDD//22,, 25°C 85 95 ddBB No load Full range 80 25°C 0.55 0.65 IIDDDD SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == 22..55 VV,, NNoo llooaadd,, mmAA Full range 1 SSuuppppllyy ccuurrrreenntt iinn sshhuuttddoowwnn SSHHDDNN << 00..77 VV,, PPeerr cchhaannnneellss iinn 25°C 1 IIDDDD((SSHHDDNN)) (TLV2460, TLV2463, TLV2465) shutdown Full range 3 µAA †Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix. WWW.TI.COM 9

Device TLV2465A is Obsolete (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:11)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:12)(cid:13) (cid:14)(cid:13)(cid:15)(cid:16)(cid:2)(cid:17) (cid:18)(cid:14) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:18)(cid:19)(cid:22)(cid:23) (cid:23)(cid:13)(cid:16)(cid:2)(cid:20)(cid:1)(cid:18)(cid:20)(cid:23)(cid:13)(cid:16)(cid:2) (cid:16)(cid:24)(cid:21)(cid:25)(cid:1)(cid:26)(cid:18)(cid:25)(cid:1)(cid:21)(cid:25)(cid:1) (cid:18)(cid:21)(cid:22)(cid:23)(cid:13)(cid:1)(cid:16)(cid:18)(cid:24)(cid:13)(cid:2) (cid:13)(cid:15)(cid:21)(cid:2)(cid:16)(cid:14)(cid:16)(cid:22)(cid:23)(cid:27) (cid:19)(cid:16)(cid:1)(cid:28) (cid:27)(cid:28)(cid:25)(cid:1)(cid:29)(cid:18)(cid:19)(cid:24) SLOS220J − JULY 1998 − REVISED FEBRUARY 2004 APPLICATION INFORMATION shutdown function Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2. DD Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to V − (not GND) to disable the operational amplifier. DD The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. circuit layout considerations To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. WWW.TI.COM 27

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-0051201QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051201QHA TLV2460M 5962-0051203QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051203QHA TLV2461M 5962-0051205QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051205QHA TLV2462M 5962-0051206Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 0051206Q2A TLV2462A MFKB 5962-0051206QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051206QHA TLV2462AM 5962-0051206QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 0051206QPA TLV2462AM TLV2460AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2460AI & no Sb/Br) TLV2460AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2460AI & no Sb/Br) TLV2460CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAOC & no Sb/Br) TLV2460CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2460C & no Sb/Br) TLV2460CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2460C & no Sb/Br) TLV2460ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2460I & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2462MUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 0051205QHA TLV2462M TLV2462QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 V2462Q & no Sb/Br) TLV2462QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM V2462Q & no Sb/Br) TLV2463AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2463AI & no Sb/Br) TLV2463AMJ ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 TLV2463AMJ TLV2463CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2463C & no Sb/Br) TLV2463CDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AAK & no Sb/Br) TLV2463CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2463C & no Sb/Br) TLV2463CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLV2463CN & no Sb/Br) TLV2463ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2463I & no Sb/Br) TLV2463IDGS ACTIVE VSSOP DGS 10 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAL & no Sb/Br) TLV2463IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AAL & no Sb/Br) TLV2463IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2463IN & no Sb/Br) TLV2464AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) TLV2464AIDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) TLV2464AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2464AI & no Sb/Br) Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2465CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2465C & no Sb/Br) TLV2465CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2465C & no Sb/Br) TLV2465ID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2465I & no Sb/Br) TLV2465IDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2465I & no Sb/Br) TLV2465IN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2465IN & no Sb/Br) TLV2465IPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) TLV2465IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) TLV2465IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2465I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2460, TLV2460A, TLV2460M, TLV2461, TLV2461A, TLV2461M, TLV2462, TLV2462A, TLV2462AM, TLV2462M, TLV2463, TLV2463A, TLV2463AM, TLV2464A : •Catalog: TLV2460, TLV2461, TLV2462A, TLV2462, TLV2463A •Automotive: TLV2460-Q1, TLV2460A-Q1, TLV2460-Q1, TLV2461-Q1, TLV2461A-Q1, TLV2461-Q1, TLV2462-Q1, TLV2462A-Q1, TLV2462A-Q1, TLV2462-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2463A-Q1, TLV2464A-Q1 •Enhanced Product: TLV2462A-EP, TLV2462A-EP, TLV2464A-EP •Military: TLV2460M, TLV2461M, TLV2462M, TLV2462AM, TLV2463AM NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 8

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2460AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2460CDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460CDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2460IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2460IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461CDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV2461CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2461IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TLV2461IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462AQPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462AQPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2019 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2462CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2462IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2462QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2462QPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2463AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2463CDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2463CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2463IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2464AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2464CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2464IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2464IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2465CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2465IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2465IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2460AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2460CDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2460CDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2460CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2460IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TLV2460IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TLV2460IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV2461CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV2461CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2461IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV2461IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV2461IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462AQPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462AQPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2462CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2462CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2462IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2462IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2462QPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2462QPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 TLV2463AIDR SOIC D 14 2500 350.0 350.0 43.0 TLV2463CDGSR VSSOP DGS 10 2500 358.0 335.0 35.0 TLV2463CDR SOIC D 14 2500 350.0 350.0 43.0 TLV2463IDGSR VSSOP DGS 10 2500 358.0 335.0 35.0 TLV2464AIDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2464CDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2464IDR SOIC D 14 2500 333.2 345.9 28.6 TLV2464IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2465CDR SOIC D 16 2500 350.0 350.0 43.0 TLV2465IDR SOIC D 16 2500 350.0 350.0 43.0 TLV2465IPWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page3

PACKAGE OUTLINE U0010A CFP - 2.03 mm max height SCALE 1.400 CERAMIC FLATPACK .27 MAX .045 MAX .010 .002 PIN 1 ID GLASS .005 MIN TYP TYP 1 10 8X .050 .005 .27 MAX GLASS 10X .017 .002 5 6 +.019 5X .32 .01 .241 5X .32 .01 -.003 .005 .001 +.013 .067 -.012 .045 .026 4225582/A 01/2020 NOTES: 1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

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PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 4.75 TYP SEATING PLANE A PIN 1 ID 0.1 C AREA 8X 0.5 10 1 3.1 2X 2.9 NOTE 3 2 5 6 0.27 10X 0.17 B 3.1 0.1 C A B 1.1 MAX 2.9 NOTE 4 0.23 TYP SEE DETAIL A 0.13 0.25 GAGE PLANE 0.15 0.7 0 - 8 0.05 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com

EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM (R0.05) TYP 1 10 SYMM 8X (0.5) 5 6 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) SYMM (R0.05) TYP 10X (0.3) 1 10 SYMM 8X (0.5) 5 6 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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