TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 (cid:0) Micro-Power Operation... < 1 m A/Channel Operational Amplifier (cid:0) Input Common-Mode Range Exceeds the Rails... –0.1 V to V + 5 V CC (cid:0) – Reverse Battery Protection Up To 18 V (cid:0) Rail-to-Rail Input/Output + (cid:0) Gain Bandwidth Product... 5.5 kHz (cid:0) Supply Voltage Range... 2.5 V to 16 V (cid:0) Specified Temperature Range SUPPLY CURRENT – T = 0°C to 70°C... Commercial Grade vs A SUPPLY VOLTAGE – T = –40°C to 125°C... Industrial Grade A (cid:0) 1.4 Ultrasmall Packaging AV = 1 – 5-Pin SOT-23 (TLV2401) A/Ch 1.2 VTAIN = = 2 V5 C°CC / 2 – 8-Pin MSOP (TLV2402) (cid:0) Universal OpAmp EVM (Refer to the EVM mnt – 1.0 e Selection Guide SLOU060) urr 0.8 C ply 0.6 p description u S – 0.4 C The TLV240x family of single-supply operational C I 0.2 amplifiers has the lowest supply current available today at only 880 nA per channel. Reverse battery 0 0 2 4 6 8 10 12 14 16 protection guards the amplifier from an over- VCC – Supply Voltage – V current condition due to improper battery installation. For harsh environments, the inputs can be taken 5 V above the positive supply rail without damage to the device. The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-W resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical offset voltage as low as 390 m V, CMRR of 120 dB and minimum open loop gain of 130 V/mV at 2.7 V. The maximum recommended supply voltage is as high as 16 V and ensured operation down to 2.5 V, with electrical characteristics specified at 2.7 V, 5 V and 15 V. The 2.5-V operation makes it compatible with Li-Ion battery-powered systems and many micro-power microcontrollers available today including TI’s MSP430. All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP, and quads in TSSOP. SELECTION OF SINGLE SUPPLY OPERATIONAL AMPLIFIER PRODUCTS† VCC VIO BW SLEW RATE ICC/ch DEVICE RAIL-TO-RAIL (V) (mV) (MHz) (V/m s) (m A) TLV240x‡ 2.5–16 0.390 0.005 0.002 0.880 I/O TLV224x 2.5–12 0.600 0.005 0.002 1 I/O TLV2211 2.7–10 0.450 0.065 0.025 13 O TLV245x 2.7–6 0.020 0.22 0.110 23 I/O TLV225x 2.7–8 0.200 0.2 0.12 35 O †All specifications are typical values measured at 5 V. ‡This device also offers 18-V reverse battery protection and 5-V over-the-rail operation on the inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TLV2401 AVAILABLE OPTIONS PACKAGED DEVICES TA AVVTIO 2mm5aa°Cxx SMALL OUTLINE† SOT-23† SYMBOLS PLASTIC DIP (D) (DBV) (P) 0°C to 70°C TLV2401CD TLV2401CDBV VAWC — 11550000 mm VV -40°C to 125°C TLV2401ID TLV2401IDBV VAWI TLV2401IP †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2401CDR). TLV2402 AVAILABLE OPTIONS PACKAGED DEVICES TA AVVTIO 2mm5aa°Cxx SMALL OUTLINE† MSOP† SYMBOLS PLASTIC DIP (D) (DGK) (P) 0°C to 70°C TLV2402CD TLV2402CDGK xxTIAIX — 11550000 mm VV –40°C to 125°C TLV2402ID TLV2402IDGK xxTIAIY TLV2402IP †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2402CDR). TLV2404 AVAILABLE OPTIONS PACKAGED DEVICES TA AVVTIO 2mm5aa°Cxx SMALL OUTLINE† PLASTIC DIP TSSOP (D) (N) (PW) 0°C to 70°C TLV2404CD TLV2404CN TLV2404CPW 11550000 mm VV –40°C to 125°C TLV2404ID TLV2404IN TLV2404IPW †This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2404CDR). TLV240x PACKAGE PINOUTS TLV2401 TLV2401 TLV2402 DBV PACKAGE D OR P PACKAGE D, DGK, OR P PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OUT 1 5 VCC NC 1 8 NC 1OUT 1 8 VCC IN– 2 7 VCC 1IN– 2 7 2OUT GND 2 IN+ 3 6 OUT 1IN+ 3 6 2IN– GND 4 5 NC GND 4 5 2IN+ IN+ 3 4 IN– TLV2404 D, N, OR PW PACKAGE (TOP VIEW) 1OUT 1 14 4OUT 1IN– 2 13 4IN– 1IN+ 3 12 4IN+ VCC 4 11 GND 2IN+ 5 10 3IN+ 2IN– 6 9 3IN– 2OUT 7 8 3OUT NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V CC Differential input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V ID Input current range, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA I Output current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND DISSIPATION RATING TABLE PPAACCKKAAGGEE Q JJCC Q JJAA TAA ≤ 25°C TAA = 125°C (°C/W) (°C/W) POWER RATING POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.6 1022 mW 204.4 mW DBV (5) 55 324.1 385 mW 77.1 mW DGK (8) 54.2 259.9 481 mW 96.2 mW N (14) 32 78 1600 mW 320.5 mW P (8) 41 104 1200 mW 240.4 mW PW (14) 29.3 173.6 720 mW 144 mW recommended operating conditions MIN MAX UNIT Single supply 2.5 16 SSuuppppllyy vvoollttaaggee, VVCCCC VV Split supply ±1.25 ±8 Common-mode input voltage range, VICR –0.1 VCC+5 V C-suffix 0 70 OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTAA °°CC I-suffix –40 125 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, V = 2.7, 5 V, and 15 V (unless CC otherwise noted) dc performance PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 390 1200 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == VVCCCC//22 VV,, mm VV VIC = VCC/2 V, Full range 1500 a VIO Offset voltage draft RS = 50 W 25°C 3 m V/°C 25°C 63 120 VVCCCC == 22.77 VV Full range 60 CCMMRRRR CCoommmmoonn-mmooddee rreejjeeccttiioonn rraattiioo VRIISCC = = 5 00 toW VCCCC,, VVCCCC == 55 VV Fu2ll 5ra°Cnge 7603 120 ddBB 25°C 80 120 VVCCCC == 1155 VV Full range 75 25°C 130 400 VVCCCC == 22.77 VV, VVOO((pp)) == 11 VV, RRLL == 550000 kkWW Full range 30 Largge-siggnal differential voltagge 25°C 300 1000 AAVVDD VVCCCC == 55 VV, VVOO((pp)) == 33 VV, RRLL == 550000 kkWW VV//mmVV amplification Full range 100 25°C 1000 1800 VVCCCC == 1155 VV, VVOO((pp)) == 66 VV, RRLL == 550000 kkWW Full range 120 †Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C. input characteristics PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 25 250 IIO Input offset current TLV240xC 300 pA FFuullll rraannggee VO = VCC/2 V, TLV240xI 400 VVRRIISSCC == = 55 VV00CC WWCC//22 VV, 25°C 100 300 IIB Input bias current TLV240xC 350 pA FFuullll rraannggee TLV240xI 900 ri(d) Differential input resistance 25°C 300 MW Ci(c) Common-mode input capacitance f = 100 kHz 25°C 3 pF †Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, V = 2.7, 5 V, and 15 V (unless CC otherwise noted) (continued) output characteristics PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 2.65 2.68 VVCCCC == 22.77 VV Full range 2.63 VIOIICCH == V–2CC CCm A/2,, VVCCCC == 55 VV Fu2ll 5ra°Cnge 44..9953 4.98 25°C 14.95 14.98 VVCCCC == 1155 VV Full range 14.93 VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VV 25°C 2.62 2.65 VVCCCC == 22.77 VV Full range 2.6 VIOIICCH == V–5CC0CC m/2A,, VVCCCC == 55 VV Fu2ll 5ra°Cnge 44.9.92 4.95 25°C 14.92 14.95 VVCCCC == 1155 VV Full range 14.9 25°C 90 150 VVIICC == VVCCCC//22, IIOOLL == 22 mm AA Full range 180 VVOOLL LLooww-lleevveell oouuttppuutt vvoollttaaggee mmVV 25°C 180 230 VVIICC == VVCCCC//22, IIOOLL == 5500 mm AA Full range 260 IO Output current VO = 0.5 V from rail 25°C ±200 m A †Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C. power supply PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT 25°C 880 950 VVCCCC == 22.77 VV oorr 55 VV Full range 1290 IICCCC SSuuppppllyy ccuurrrreenntt ((ppeerr cchhaannnneell)) VVOO == VVCCCC//22 nnAA 25°C 900 990 VVCCCC == 1155 VV Full range 1350 Reverse supply current VCC = –18 V, VIN = 0 V, 25°C 50 nA VO = Open circuit 25°C 100 120 VVCCCC == 22..77 ttoo 55 VV,, ddBB VIC = VCC/2 V, TLV240xC 96 PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo No load, FFuullll rraannggee PSRR ((DD VVCCCC//DD VVIIOO)) TLV240xI 85 dB VCCCC = 5 to 15 V, VIICC = VCCCC/2 V, 25°C 100 120 ddBB No load Full range 100 †Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, V = 2.7, 5 V, and 15 V (unless CC otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT UGBW Unity gain bandwidth RL = 500 kW , CL = 100 pF 25°C 5.5 kHz SR Slew rate at unity gain VO(pp) = 0.8 V, RL = 500 kW , CL = 100 pF 25°C 2.5 V/ms f M Phase margin 60° RRLL == 550000 kkWW , CCLL == 110000 ppFF 2255°°CC Gain margin 15 dB VCC = 2.7 or 5 V, V(STEP)PP = 1 V, CL = 100 pF, 0.1% 1.84 AV = –1, RL = 100 kW tts SSeettttlliinngg ttiimmee 2255°°CC mmss VCC = 15 V, 0.1% 6.1 VV((SSTTEEPP))PPPP == 11 VV, CCLL == 110000 pFF, AV = –1, RL = 100 kW 0.01% 32 noise/distortion performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT f = 10 Hz 800 VVn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee nnVV//√√HHzz f = 100 Hz 25°C 500 In Equivalent input noise current f = 100 Hz 8 fA/√Hz 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input Offset Voltage vs Common-mode input voltage 1, 2, 3 vs Free-air temperature 4, 6, 8 IIIIBB IInnppuutt BBiiaass CCuurrrreenntt vs Common-mode input voltage 5, 7, 9 vs Free-air temperature 4, 6, 8 IIIIOO IInnppuutt OOffffsseett CCuurrrreenntt vs Common-mode input voltage 5, 7, 9 CMRR Common-mode rejection ratio vs Frequency 10 VOH High-level output voltage vs High-level output current 11, 13, 15 VOL Low-level output voltage vs Low-level output current 12, 14, 16 VO(PP) Output voltage peak-to-peak vs Frequency 17 Zo Output impedance vs Frequency 18 ICC Supply current vs Supply voltage 19 PSRR Power supply rejection ratio vs Frequency 20 AVD Differential voltage gain vs Frequency 21 Phase vs Frequency 21 Gain-bandwidth product vs Supply voltage 22 SR Slew rate vs Free-air temperature 23 f m Phase margin vs Capacitive load 24 Gain margin vs Capacitive load 25 Supply current vs Reverse voltage 26 Voltage noise over a 10 Second Period 27 Large signal follower pulse response 28, 29, 30 Small signal follower pulse response 31 Large signal inverting pulse response 32, 33, 34 Small signal inverting pulse response 35 Crosstalk vs Frequency 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE vs vs vs COMMON-MODE INPUT COMMON-MODE INPUT COMMON-MODE INPUT VOLTAGE VOLTAGE VOLTAGE 1400 100 400 m– Input Offset Voltage – V 11022468000000000000 VTAC C= 2=5 2°.C7 V m– Input Offset Voltage – V ––2100000 m– Input Offset Voltage – V––2112300000000000 VTAC C= 2=5 1 °5C V O O–300 O VI 0 VI VCC = 5 V VI–300 TA = 25 °C –200 –400 –400 ––00.2.100.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9 ––00..210.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 ––00..21 2.0 4.2 6.4 8.6 10.8 13.0 15.2 VICR – Common-Mode Input Voltage – V VICR – Common-Mode Input Voltage – V VICR – Common-Mode Input Voltage –V Figure 1 Figure 2 Figure 3 INPUT BIAS / OFFSET CURRENT INPUT BIAS / OFFSET CURRENT vs INPUT BIAS / OFFSET CURRENT vs COMMON MODE INPUT vs FREE-AIR TEMPERATURE VOLTAGE FREE-AIR TEMPERATURE 600 400 600 I/I– Input Bias / Offset Current – pAIBIO––2112345000000000000000–40–2VV5CIC–C1 = 0= 1 2.53.75 VV20 II3IIOB5 50 65 80 95110125 I/I– Input Bias / Offset Current – pAIBIO––11–112233505050505500000000000––00..21 0VTA.C2 C= 2=05 .26 °.7C V1IIII.OB0 1.4 1.8 2.2 2.62.9 I/I– Input Bias / Offset Current – pAIBIO––2112345000000000000000–40–2VV5CIC–C1 = 0= 2 5.55 V V20 II3IIOB5 50 65 80 95110125 TA – Free-Air Temperature – °C VICR – Common Mode Input Voltage – V TA – Free-Air Temperature – °C Figure 4 Figure 5 Figure 6 INPUT BIAS / OFFSET CURRENT INPUT BIAS / OFFSET CURRENT vs INPUT BIAS / OFFSET CURRENT vs COMMON-MODE INPUT vs COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE VOLTAGE 200 700 250 I/I– Input Bias / Offset Current – pAIBIO––11–115050550000000––00..12 0VT.4AC C=1 2=.05 5 ° VC1.6IIIIOB2.2 2.8 3.4 4.0 4.6 5.2 I/I– Input Bias / Offset Current – pAIBIO––2112345600000000000000000–40–2VV5CIC–C1 = 0= 7 1.555 VV20 I3IO5IIB50 65 80 95110125 I/I– Input Bias / Offset Current – pAIBIO––11–112505050500000000––00..21 VT2AC.0 C= 2=5 41 .°52C VI6IO.I4IB 8.6 10.8 13.0 15.2 VICR – Common Mode Input Voltage – V TA – Free-Air Temperature – °C VICR – Common-Mode Input Voltage –V Figure 7 Figure 8 Figure 9 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs vs FREQUENCY HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT B120 2.7 1.50 R – Common-Mode Rejection Ratio – d10246800000 VRRCFI==C11= k02W0.7 k,W 5, 15 V – High-Level Output Voltage – VOH 1122....5814 VCC = 2.7 VTTTTTAAAAA ===== 271––50204 5°0°°C °CC°CC V– Low-Level Output Voltage – VOL 00011.....2570250505 VTTTTTAAACAA C===== 02–=71 54 02°2 0 5C°.°°7 CC°C CV R V CM 0 1.2 0 1 10 100 1k 10k 0 50 100 150 200 0 50 100 150 200 f – Frequency – Hz IOH – High-Level Output Current – m A IOL – Low-Level Output Current – m A Figure 10 Figure 11 Figure 12 HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 5.0 1.50 15.0 – High-Level Output Voltage – V 344...505 VCC = 5 V TTTTTAAAAA ===== 271––50204 5°0°°C CC°°CC – Low-Level Output Voltage – VL 00011.....2570250505 VTTTTTAACAAA C===== =0–271 4502°50 5C °°V° CC°CC – High-Level Output Voltage – V 111344...505 TTTTAAAA ==== 271–5020 5°°°C CC°CTA = –40°C H O H O V O V V VCC = 15 V 3.0 0 13 0 50 100 150 200 0 50 100 150 200 0 50 100 150 200 IOH – High-Level Output Current – m A IOL – Low-Level Output Current – m A IOH – High-Level Output Current – m A Figure 13 Figure 14 Figure 15 OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE PEAK-TO-PEAK OUTPUT IMPEDANCE vs vs vs LOW-LEVEL OUTPUT CURRENT FREQUENCY FREQUENCY 1.50 V 16 10k V– Low-Level Output Voltage – VOL 00011.....2570250505 VTCAC = = – 1450 °VC TTTTAAAA ==== 271–5020 5°°°C CC°C – Output voltage Peak–to–Peak – O(PP) 11102402468 VVCCCC = =5 2V.7V VCC = 15 V RCTALL === 211500°00C kpWF W– Output Impedance –Zo1010k AV = 10 AV =VT AC1 C= =25 2°.C7, 5, & 15 V 0 V –2 10 0 50 100 150 200 10 100 1k 100 1k 10k IOL – Low-Level Output Current – m A f – Frequency – Hz f – Frequency – Hz Figure 16 Figure 17 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT POWER SUPPLY REJECTION RATIO vs vs SUPPLY VOLTAGE FREQUENCY 1.4 B 120 d m– A/Ch 11..02 on Ratio – 110100 VTAC C= 2=5 2°.C7, 5, & 15 V urrent 0.8 Rejecti 90 ISupply C–CC 000...246 AV = 1 TTTTTAAAAA ===== 0721– 0524° 50C°°°°CCCC R – Power Supply 56780000 VIN = VCC / 2 SR 0 P 40 0 2 4 6 8 10 12 14 16 10 100 1k 10k VCC – Supply Voltage – V f – Frequency – Hz Figure 19 Figure 20 DIFFERENTIAL VOLTAGE GAIN AND PHASE GAIN BANDWIDTH PRODUCT vs vs FREQUENCY SUPPLY VOLTAGE 7 60 135 Hz TA = 25°C ential Voltage Gain – dB 1324500000 4950 °Phase – n Bandwidth Product – k 3456 RCf =LL 1== k11H00z00 kpWF er ai 2 – DiffAVD–100 VRCTACLL C=== =521050 20°0.C 7kp,WF 5, & 15 V 0 GBWP –G 1 –20 –45 0 10 100 1k 10k 2.5 4.0 5.5 7.0 8.5 10.011.513.014.516.0 f – Frequency – Hz VCC – Supply Voltage –V Figure 21 Figure 22 SLEW RATE PHASE MARGIN vs vs FREE-AIR TEMPERATURE CAPACITIVE LOAD 3.5 80 3.0 SR+ 70 s m VCC = 5, 15 V 60 w Rate – V/ 22..05 VCC = 2.7 V °Margin – 4500 – Sle 1.5 ase 30 SR 1.0 SR– VCC = 2.7, 5, & 15 V Ph VCC = 2.7, 5, & 15 V 20 RL = 500 kW 0.5 10 TA = 25°C 0 0 –40–25–10 5 20 35 50 65 80 95110125 10 100 1k 10k TA – Free-Air Temperature – °C CL – Capacitive Load – pF Figure 23 Figure 24 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS GAIN MARGIN SUPPLY CURRENT vs vs CAPACITIVE LOAD REVERSE VOLTAGE 25 60 RL= 500 kW 55 20 TA = 25°C 50 TA = 25°C A n 45 n Margin – dB 1105 VCC = 15 V pply Current – 43230550 Gai 5 VCC = 2.7 & 5 V I – SuCC 211050 5 0 0 10 100 1k 10k –18–16 –14 –12–10 –8 –6 –4 –2 0 CL – Capacitive Load – pF VCC – Reverse Voltage – V Figure 25 Figure 26 LARGE SIGNAL FOLLOWER VOLTAGE NOISE PULSE RESPONSE OVER A 10 SECOND PERIOD 5 2 4 VCC = 5 V m– V 3 fT A= 0=. 12 5H°zC to 10 Hz 4 VIN 1 Noise 2 e – V 3 0e – V d Voltage 01 put Voltag 2 VARCVCLL C=== 1=1100 200. 7kp WVF –1put Voltag ut Referre ––12 V– OutO 01 VO TA = 25°C V– InIN p n –3 I –1 –4 –1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 t – Time – s t – Time – ms Figure 27 Figure 28 LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER PULSE RESPONSE PULSE RESPONSE 8 4 30 15 7 VAVC C= 1= 5 V 3 25 VAVC C= 1= 15 V 10 6 VIN RL = 100 kW 2 VIN RL = 100 kW V– Output Voltage – VO 12345 VO CTAL == 2150°0C pF –110 V– Input Voltage – VIN V– Output Voltage – VO 1120505 VO CTAL == 2150°0C pF –550 V– Input Voltage – VIN 0 0 –1 –5 –1 0 1 2 3 4 5 6 –2 0 2 4 6 8 10 12 14 16 t – Time – ms t – Time – ms Figure 29 Figure 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS SMALL SIGNAL FOLLOWER LARGE SIGNAL INVERTING PULSE RESPONSE PULSE RESPONSE 180 300 2.0 3 160 VIN 150 1.5 VIN 2 V 140 0 – Output Voltage – m 110246800000 VO V&AR TCAV CL1L C=5 === V=21 115 020°0.0C7 k,p W5F, –150 – Input Voltage – mV – Output Voltage – V –0001....5050 VARCTAVCLL C==== 2=–115100 2°00.C 7kp WVF – 101 – Input Voltage – V VO 20 VIN VO–1.0 VIN –1.5 VO 0 –20 –2 –50 0 50100150200250300350400450500 –1 0 1 2 3 4 5 6 7 t – Time – m s t – Time – ms Figure 31 Figure 32 LARGE SIGNAL INVERTING LARGE SIGNAL INVERTING PULSE RESPONSE PULSE RESPONSE 2.5 4 12 12 2.0 3 10 9 1.5 VIN 2 8 VIN 6 V– Output Voltage – VO––––2110001.......0505050 VARCTAVCLL C==== 2=–115100 5°00 C VkpWF – 101 V– Input Voltage – VIN V– Output Voltage – VO–––6420246 VAR TCAVCLL C== == 2–= 11510 01°005C k pVWF – 303 V– Input Voltage – VIN –2.5 VO –8 VO –3.0 –10 –3.5 –12 –1 0 1 2 3 4 5 6 7 –5 0 5 10 15 20 25 30 35 t – Time – ms t – Time – ms Figure 33 Figure 34 CROSSTALK SMALL SIGNAL INVERTING vs PULSE RESPONSE FREQUENCY 200 200 0 VIN VCC = 2.7, 150 100 –20 5, & 15 V V All Channels – m 100 VCC = 2.7, 5, 0 mV –40 RL = 100 kW – Output Voltage –55000 &AR TCAV L1L =5= == V2– 115100°00C k pWF –100 – Input Voltage – Crosstalk –dB –1––086000 VCVCILNC = = =1 1 02 0V.7 Pp, FP5 V VCC = 15 V O N V VO VI –100 –120 –150 –140 –200 0 200 400 600 800 1000 1200 10 100 1k 10k t – Time – ms f – Frequency –Hz Figure 35 Figure 36 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION reverse battery protection The TLV2401/2/4 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient temperature increases. When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input ESD structure will turn on—this current should be limited to less than 10 mA. If the inputs or outputs are referred to ground, rather than midrail, no extra precautions need be taken. common-mode input range The TLV2401/2/4 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to V – 0.8 V a PNP CC differential pair will provide the gain. For inputs between V – 0.8 V and V , two NPN emitter followers buffering a second PNP differential pair CC CC provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above the rails, because as the inputs go above V , the NPNs switch from functioning as transistors to functioning CC as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed V . CC The TLV2401/2/4 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion. offset voltage The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB– RG + – VI VO + RS IIB+ (cid:3) (cid:3)RF(cid:4)(cid:4) (cid:3) (cid:3)RF(cid:4)(cid:4) VOO(cid:2)VIO 1(cid:1) RG (cid:0)IIB(cid:1) RS 1(cid:1) RG (cid:0)IIB– RF Figure 37. Output Offset Voltage Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 38). RG RF – + VO VI R1 C1 1 f–3dB (cid:1) 2(cid:0)R1C1 VVOI (cid:1) (cid:2)1(cid:0)RRGF(cid:3)(cid:2)1(cid:0)s1R1C1(cid:3) Figure 38. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) VI + R1 R2 _ f–3dB (cid:1) 2(cid:0)1RC C2 RF RG = RF (2 – 1 ) RG Q Figure 39. 2-Pole Low-Pass Sallen-Key Filter 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high performance of the TLV240x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. (cid:0) Ground planes – It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:0) Proper power supply decoupling – Use a 6.8-m F tantalum capacitor in parallel with a 0.1-m F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-m F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-m F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:0) Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:0) Short trace runs/compact part placements – Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:0) Surface-mount passive components – Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION general power dissipation considerations For a given q , the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: JA (cid:1)TMAX–TA(cid:2) PD(cid:0) (cid:0) JA Where: P = Maximum power dissipation of THS240x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A q JA = q JC + q CA q = Thermal coefficient from junction to case JC q = Thermal coefficient from case to ambient air (°C/W) CA MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 PDIP Package TJ = 150°C 1.75 Low-K Test PCB q JA = 104°C/W W n – 1.5 MSOP Package o pati 1.25 SOIC Package Lq JoAw -=K 2 T6e0s°tC P/WCB si Low-K Test PCB Dis q JA = 176°C/W r 1 e w o P m 0.75 u m xi 0.5 a M 0.25 SOT-23 Package Low-K Test PCB 0 q JA = 324°C/W –55–40–25 –10 5 20 35 50 65 80 95 110 125 TA – Free-Air Temperature – °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 40. Maximum Power Dissipation vs Free-Air Temperature 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 41 are generated using the TLV240x typical electrical and operating characteristics at T = 25°C. Using this A information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (cid:0) (cid:0) Maximum positive output voltage swing Unity-gain frequency (cid:0) (cid:0) Maximum negative output voltage swing Common-mode rejection ratio (cid:0) (cid:0) Slew rate Phase margin (cid:0) (cid:0) Quiescent power dissipation DC output resistance (cid:0) (cid:0) Input bias current AC output resistance (cid:0) (cid:0) Open-loop voltage amplification Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VCC+ + rp rc1 rc2 ree cee egnd fb ro2 – c1 7 11 12 + 1 c2 IN+ + 9 r2 6 vlim – vc 2 + 8 IN– q1 q2 – vb ga 53 – gcm ioff ro1 dp 13 14 re1 re2 VOUT dlp dln 10 91 90 92 5 iee dc + + – vlp hlim vln VCC– – – + 4 – ve + 54 de .subckt 240X_5V–X 1 2 3 4 5 rc1 3 11 978.81E3 * rc2 3 12 978.81E3 c1 11 12 9.8944E–12 re1 13 10 30.364E3 c2 6 7 30.000E–12 re2 14 10 30.364E3 cee 10 99 8.8738E–12 ree 10 99 3.6670E9 dc 5 53 dy ro1 8 5 10 de 54 5 dy ro2 7 99 10 dlp 90 91 dx rp 3 4 1.4183E6 dln 92 90 dx vb 9 0 dc 0 dp 4 3 dx vc 3 53 dc .88315 egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 ve 54 4 dc .88315 fb 7 99 poly(5) vb vc ve vlp vln 0 61.404E6 –1E3 1E3 61E6 –61E6 vlim 7 8 dc 0 ga 6 0 11 12 1.0216E–6 vlp 91 0 dc 540 gcm 0 6 10 99 10.216E–12 vln 0 92 dc 540 iee 10 4 dc 54.540E–9 .model dx D(Is=800.00E–18) ioff 0 6 dc 5e–12 .model dy D(Is=800.00E–18 Rs=1m Cjo=10p) hlim 90 0 vlim 1K .model qx1 NPN(Is=800.00E–18 Bf=27.270E21) q1 11 2 13 qx1 .model qx2 NPN(Is=800.0000E–18 Bf=27.270E21) q2 12 1 14 qx2 .ends r2 6 9 100.00E3 Figure 41. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2401CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2401C & no Sb/Br) TLV2401CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAWC & no Sb/Br) TLV2401CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 VAWC & no Sb/Br) TLV2401CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2401C & no Sb/Br) TLV2401CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2401C & no Sb/Br) TLV2401ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2401I & no Sb/Br) TLV2401IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAWI & no Sb/Br) TLV2401IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAWI & no Sb/Br) TLV2401IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAWI & no Sb/Br) TLV2401IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 VAWI & no Sb/Br) TLV2401IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2401I & no Sb/Br) TLV2401IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2401I & no Sb/Br) TLV2401IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2401I & no Sb/Br) TLV2402CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2402C & no Sb/Br) TLV2402CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2402C & no Sb/Br) TLV2402CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AIX & no Sb/Br) TLV2402CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AIX & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2402CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2402C & no Sb/Br) TLV2402ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2402I & no Sb/Br) TLV2402IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2402I & no Sb/Br) TLV2402IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AIY & no Sb/Br) TLV2402IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AIY & no Sb/Br) TLV2402IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AIY & no Sb/Br) TLV2402IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2402I & no Sb/Br) TLV2402IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2402I & no Sb/Br) TLV2402IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2402I & no Sb/Br) TLV2404CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLV2404C & no Sb/Br) TLV2404CPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2404C & no Sb/Br) TLV2404CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2404C & no Sb/Br) TLV2404CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 2404C & no Sb/Br) TLV2404ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2404I & no Sb/Br) TLV2404IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2404I & no Sb/Br) TLV2404IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2404I & no Sb/Br) TLV2404IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLV2404IN & no Sb/Br) TLV2404IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2404I & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLV2404IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2404I & no Sb/Br) TLV2404IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2404I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2402 : Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Automotive: TLV2402-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 22-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLV2401CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2401CDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV2401CDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV2401CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2401CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2401IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV2401IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2401IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2401IDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV2401IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2402CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2402CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2402IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2402IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2404CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2404IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2404IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLV2401CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2401CDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV2401CDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV2401CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2401CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2401IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV2401IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2401IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2401IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV2401IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2402CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2402CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2402IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2402IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2404CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2404IDR SOIC D 14 2500 350.0 350.0 43.0 TLV2404IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

None

None

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

None

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated