Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver 1 Introduction 1.1 Features 1 • LowPowerConsumption: • Error-Free100Base-TOperationupto150Meters – SingleSupply: <205mWPHY,275mWwith UnderTypicalConditions CenterTap(Typical) • Error-Free10Base-TOperationupto300Meters – DualSupplies: <126mWPHY,200mWwith UnderTypicalConditions CenterTap(Typical) • IEEE802.3uENDEC,10Base-T • ProgrammablePowerBackOfftoreducePHY TransceiversandFilters powerupto20%insystemswithshortercables • IEEE802.3uPCS,100Base-TXTransceivers • LowdeterministiclatencysupportsIEEE1588 • IntegratedANSIX3.263CompliantTP-PMD implementation PhysicalSublayerwithAdaptiveEqualizationand • CableDiagnostics (TLK106) BaselineWanderCompensation • ProgrammableFastLinkDownModes, <10µs • ProgrammableLEDSupportLink,Activity reactiontime • 10/100MbsPacketBIST(BuiltinSelfTest) • VariableI/Ovoltagerange:3.3V,2.5V,1.8V • HBMESDprotectiononRD± andTD± of16kV • MACInterfaceI/Ovoltagerange: • 32-pinQFN(5mm)× (5mm) – MIII/Ovoltagerange:3.3V,2.5V,1.8V – RMIII/Ovoltagerange:3.3V,2.5V • FixedTXClocktoXI,withprogrammablephase shift • Auto-MDIXfor10/100Mbs • EnergyDetectionMode • MIIandRMIICapabilities • SerialManagementInterface • IEEE802.3uMII • IEEE802.3uAuto-NegotiationandParallel Detection 1.2 Applications • IndustrialNetworksandFactoryAutomation • MotorandMotionControl • RealTimeIndustrialEthernetApplicationssuchas • GeneralEmbeddedApplications EtherCAT®,Ethernet/IP™,ProfiNET®,SERCOSIII andVARAN 1.3 Device Overview TLK10x 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com The TLK10x is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The TLK10x supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface(RMII)fordirectconnectiontoaMediaAccessController(MAC). The TLK10x is designed for power-supply flexibility, and can operate with a single 3.3V power supply or withcombinationsof3.3Vand1.55Vpowersuppliesforreducedpoweroperation. The TLK10x uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. This device not only meets the requirements of IEEE802.3,butmaintainshighmarginsintermsofcross-talkandaliennoise. The TLK10x Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100m cable length, or the extended 150m, error-free cable reachoftheTLK10x.Formoredetail,see applicationnoteSLLA328. MII Option RMII Option MII/RMII Interface Cable Diagnostics (TLK106 only) Figure1-1.TLK10xFunctionalBlockDiagram 2 Introduction Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 1.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. Table of Contents 1 Introduction............................................... 1 5.3 10Base-TReceivePath............................. 29 .............................................. ..................................... 1.1 Features 1 5.4 AutoNegotiation 30 ........................................... ............................. 1.2 Applications 1 5.5 LinkDownFunctionality 32 1.3 Device Overview ..................................... 1 6 ResetandPowerDownOperation.................. 33 ...................... ..................................... 1.4 ElectrostaticDischargeCaution 3 6.1 HardwareReset 33 2 PinDescriptions......................................... 4 6.2 SoftwareReset...................................... 33 ............................................ ............................... 2.1 PinLayout 4 6.3 PowerDown/Interrupt 33 .................. ................................. 2.2 SerialManagementInterface(SMI) 5 6.4 PowerSaveModes 34 2.3 MACDataInterface.................................. 5 7 DesignGuidelines...................................... 35 .................. ................................. 2.4 10Mbsand100MbsPMDInterface 6 7.1 TPINetworkCircuit 35 ....................................... ......................... 2.5 ClockInterface 6 7.2 ClockIn(XI)Requirements 35 ......................................... .................... 2.6 LEDInterface 6 7.3 ThermalViasRecommendation 37 2.7 ResetandPowerDown.............................. 6 8 RegisterBlock.......................................... 38 ......................... ................................... 2.8 PowerandBiasConnections 7 8.1 RegisterDefinition 43 3 HardwareConfiguration................................ 7 8.2 CableDiagnosticControlRegister(CDCR)......... 67 .............................. ............ 3.1 Bootstrap Configuration 7 8.3 PHYResetControlRegister(PHYRCR) 68 .......................... ............... 3.2 PowerSupplyConfiguration 8 8.4 ComplianceTestregister(COMPTR) 69 .................... .......... 3.3 IOPinsHi-ZStateDuringReset 10 8.5 TX_CLKPhaseShiftRegister(TXCPSR) 69 .................................... .... 3.4 Auto-Negotiation 10 8.6 PowerBackOffControlRegister(PWRBOCR) 70 ........................................... ........ 3.5 Auto-MDIX 10 8.7 VoltageRegulatorControlRegister(VRCR) 70 .................................... ... 3.6 MIIIsolateMode 11 8.8 CableDiagnosticConfiguration/ResultRegisters 70 3.7 PHYAddress........................................ 11 9 ElectricalSpecifications.............................. 76 ....................................... ........................ 3.8 LEDInterface 12 9.1 AbsoluteMaximumRatings 76 .............................. ........................................ 3.9 LoopbackFunctionality 13 9.2 ESDRatings 76 ................................................. .............. 3.10 BIST 15 9.3 RecommendedOperatingConditions 76 3.11 CableDiagnostics................................... 15 9.5 TLK10532-PinIndustrialDevice(85°C)Thermal ....................................... 4 Interfaces ................................................ 17 Characteristics 77 .................. 9.6 TLK10632-PinExtendedTemperature(105°C) 4.1 MediaIndependentInterface(MII) 17 ..................... DeviceThermalCharacteristics 77 ...... 4.2 ReducedMediaIndependentInterface(RMII) 18 ....................... 9.7 DCCharacteristics,VDD_IO 78 ....................... 4.3 SerialManagementInterface 20 ................................. 9.8 DCCharacteristics 78 5 Architecture............................................. 24 ....................... 9.9 PowerSupplyCharacteristics 79 ......................... 5.1 100Base-TXTransmitPath 24 .................................... 9.10 ACSpecifications 80 ......................... 5.2 100Base-TXReceivePath 27 10 RevisionHistory........................................ 96 Copyright©2012–2016,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 2 Pin Descriptions TheTLK10xpinsfallintothefollowinginterfacecategories(subsequentsectionsdescribeeachinterface): • SerialManagementInterface • ResetandPowerDown • MACDataInterface • BootstrapConfigurationInputs • ClockInterface • 10/100MbsPMDInterface • LEDInterface • SpecialConnectPins • PowerandGroundpins Note:Configurationpinoption.SeeSection3.1 forJumperDefinitions. Thedefinitionsbelowdefinethefunctionalityofeachpin. Type:I Input Type:OD OpenDrain Type:O Output Type:PD,PU InternalPulldown/Pullup Type:I/O Input/Output Type:S ConfigurationPin(Allconfigurationpinshaveweakinternal pullupsorpulldowns.Useanexternal2.2kΩ resistorifyou needadifferentdefaultvalue.SeeSection3.1 fordetails.) 2.1 Pin Layout G F C _ N D E D_2 / PHYAD3 D_1 / PHYAD2 D_0 / PHYAD1 L/ PHYAD0 _ER /AMDIX_E S/CRS_DV / LE _DV / MII_MOD _CLK X X X O X R X X R R R C R C R R 32 31 30 29 28 27 26 25 RXD_3 / PHYAD4 1 24 PFBIN2 TX_CLK 2 23 XI TX_EN 3 22 XO TXD_0 4 21 VDD_IO GND TXD_1 5 20 MDC TXD_2 6 19 MDIO TXD_3 7 18 RESET INT / PWDN 8 17 LED_LINK /AN_0 9 10 11 12 13 14 15 16 – + – + 1 3 T S D D D D N 3 U A R R T T PFBI AVDD PFBO RBI Figure2-1.TLK10xPINDIAGRAM,TOPVIEW This document describes signals that take on different names depending on configuration. In such cases, the different names are placed together and separated by slash (/) characters. For example, "RXD_3 / PHYAD4".Activelowsignalsarerepresentedby overbars. . 4 PinDescriptions Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 2.2 Serial Management Interface (SMI) PIN TYPE DESCRIPTION NAME NO. MANAGEMENTDATACLOCK:Clocksignalforthemanagementdatainput/output(MDIO)interface.The MDC 20 I maximumMDCrateis25MHz;thereisnominimumMDCrate.MDCisnotrequiredtobesynchronoustothe TX_CLKortheRX_CLK. MANAGEMENTDATAI/O:Bidirectionalcommand/datasignalsynchronizedtoMDC.Eitherthelocal MDIO 19 I/O controllerortheTLK10xmaydrivetheMDIOsignal.Thispinrequiresapull-upresistorwithvalue2.2kΩ. 2.3 MAC Data Interface PIN TYPE DESCRIPTION NAME NO. MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock depending on the speed. Note that in MII mode, this clock has constant phase referenced to TX_CLK 2 O,PD REF_CLK.Applicationsrequiringsuchconstantphasemayusethisfeature. Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and receive. TRANSMITENABLE:TX_ENispresentedontherisingedgeoftheTX_CLK.TX_EN TX_EN 3 I,PD indicatesthepresenceofvaliddatainputsonTXD[3:0]inMIImode,andonTXD[1:0]inthe RMIImode.TX_ENisanactivehighsignal. TXD_0 4 TRANSMITDATA:InMIImode,thetransmitdatanibblereceivedfromtheMACis TXD_1 5 I,PD synchronoustotherisingedgeoftheTX_CLKsignal.InRMIImode,TXD[1:0]receivedfrom TXD_2 6 theMACissynchronoustothe50MHzreferenceclockonXI. TXD_3 7 RECEIVECLOCK:InMIImodeitisthereceiveclockthatprovideseithera25MHzor2.5MHz RX_CLK 25 O referenceclock,dependingonthespeed,thatisderivedfromthereceiveddatastream. RECEIVEDATAVALID:ThispinindicatesvaliddataispresentontheRXD[3:0]forMIImode RX_DV/MII_MODE 26 S,O,PD oronRXD[1:0]forRMIImode,independentlyfromCarrierSense. RECEIVEERROR:Thispinindicatesthatanerrorsymbolhasbeendetectedwithinareceived packetinbothMIIandRMIImode.InMIImode,RX_ERisassertedhighsynchronouslyto RX_ER/AMDIX_EN 28 S,O,PU RX_CLKandinRMIImode,synchronouslytoXI(50MHz).Thispinisnotrequiredtobeused bytheMAC,ineitherMIIorRMII,becausethePHYiscorruptingdataonareceiveerror. RECEIVEDATA:Symbolsreceivedonthecablearedecodedandpresentedonthesepins synchronoustoRX_CLK.TheycontainvaliddatawhenRX_DVisasserted.AnibbleRXD[3:0] RXD_0/PHYAD1 30 isreceivedintheMIImodeand2-bitsRXD[1:0]isreceivedintheRMIIMode. RXD_1/PHYAD2 31 S,O,PD RXD_2/PHYAD3 32 PHYaddresspinsPHYAD[4:1]aremultiplexedwithRXD[3:0],andarepulleddown.PHYAD0 RXD_3/PHYAD4 1 (LSBoftheaddress)ismultiplexedwithCOLonpin29,andispulledup. Ifnoexternalpullup/pulldownispresent,thedefaultaddressis0x01. CARRIERSENSE:InMIImodethispinisassertedhighwhenthereceivemediumisnon-idle. CRS/CRS_DV/ 27 S,O,PU LED_CFG CARRIERSENSE/RECEIVEDATA VALID: InRMIImode,thispincombinestheRMIICarrier andReceiveDataValidindications. COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base- COL/PHYAD0 29 S,O,PU T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and receivemediaarenon-idle.ThispinisnotusedinRMIImode. Copyright©2012–2016,TexasInstrumentsIncorporated PinDescriptions 5 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 2.4 10Mbs and 100Mbs PMD Interface PIN TYPE DESCRIPTION NAME NO. Differentialcommondrivertransmitoutput(PMDOutputPair):Thesedifferentialoutputsare automaticallyconfiguredtoeither10Base-Tor100Base-TXsignaling. TD–,TD+ 11,12 I/O InAuto-MDIXmodeofoperation,thispaircanbeusedastheReceiveInputpair.Thesepinsrequire3.3V biasforoperation. Differentialreceiveinput(PMDInputPair):Thesedifferentialinputsareautomaticallyconfiguredto accepteither100Base-TXor10Base-Tsignaling. RD–,RD+ 9,10 I/O In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3Vbiasforoperation. 2.5 Clock Interface PIN TYPE DESCRIPTION NAME NO. CRYSTAL/OSCILLATORINPUT: MIIreferenceclock: Referenceclock.25MHz±50ppm-tolerancecrystalreferenceoroscillatorinput.Thedevicesupportseither anexternalcrystalresonatorconnectedacrosspinsXIandXO,oranexternalCMOS-leveloscillator sourceconnectedtopinXIonly.WhenusinganexternalCMOS-leveloscillator,theoscillatormusthave XI 23 I thesamevoltagereferenceastheVDD_IOsupply. RMIIreferenceclock:PrimaryclockreferenceinputfortheRMIImode.Theinputmustbeconnectedtoa 50MHz±50ppm-toleranceCMOS-leveloscillatorsource.WhenusinganexternalCMOS-leveloscillator, theoscillatormusthavethesamevoltagereferenceastheVDD_IOsupply.RMIIisnotsupportedwitha 1.8Vreferenceclock. CRYSTALOUTPUT:ReferenceClockoutput.XOpinisusedforcrystalonly.Thispinshouldbeleft XO 22 O floatingwhenanoscillatorinputisconnectedtoXI. 2.6 LED Interface (SeeTable3-4forLEDModeSelection) PIN TYPE DESCRIPTION NAME NO. LEDPintoindicatestatus Mode1 LINKIndicationLED:Indicatesthestatusofthelink.Whenthelinkisgood,theLED LED_LINK/ isON. 17 S,O,PU AN_0 Mode2 ACTindicationLED:Indicatestransmitandreceiveactivityinadditiontothestatus oftheLink.TheLEDisONwhenLinkisgood.TheLEDblinkswhenthetransmitter orreceiverisactive. 2.7 Reset and Power Down PIN TYPE DESCRIPTION NAME NO. Thispinisanactive-lowresetinputthatinitializesorre-initializesalltheinternalregistersofthe RESET 18 I,PU TLK10x.Assertingthispinlowforatleast1µswillforcearesetprocesstooccur.Alljumper optionsarereinitializedaswell. Registeraccessisrequiredforthispintobeconfiguredeitheraspowerdownorasaninterrupt. Thedefaultfunctionofthispinispowerdown. Whenthispinisconfiguredforapowerdownfunction,anactivelowsignalonthispinplacesthe INT/PWDN 8 IO,OD,PU deviceinpowerdownmode. Whenthispinisconfiguredasaninterruptpin,thenthispinisassertedlowwhenaninterrupt conditionoccurs.Thepinhasanopen-drainoutputwithaweakinternalpull-up.Some applicationsmayrequireanexternalpull-upresistor. 6 PinDescriptions Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 2.8 Power and Bias Connections PIN TYPE DESCRIPTION NAME NO. RBIAS 16 I BiasResistorConnection:Usea4.87kΩ1%resistorconnectedfromRBIAStoGND. PFBOUT 15 O PowerFeedbackOutput:Place10µfand0.1μFcapacitors(ceramicpreferred)closetoPFBOUT. Insingle-supplyoperation,connectthispintoPFBIN1andPFBIN2(pin13andpin24).SeeFigure3-1 forproperplacement. Inmultiplesupplyoperation,thispinisnotused. PowerFeedbackInput:ThesepinsarefedwithpowerfromPFBOUT(pin15)insinglesupply PFBIN1 13 operation. I Inmultiplesupplyoperation,connecta1.55Vexternalpowersupplytothesepins.Connectasmall PFBIN2 24 capacitorof0.1µFclosetoeachpin.Topowerdowntheinternallinearregulator,writetoregister 0x00d0. VDD_IO 21 P I/O3.3V,2.5V,or1.8VSupply-Fordetails,seeSection3.2.3 AVDD33 14 P Analog3.3Vpowersupply Ground GroundPad GND P Pad 3 Hardware Configuration This section includes information on the various configuration options available with the TLK10x. The configurationoptionsdescribedbelowinclude: • BootstrapConfiguration • PHYAddress • PowerSupplyConfiguration • LEDInterface • IOPinsHi-ZStateDuringReset • LoopbackFunctionality • Auto-Negotiation • BIST • Auto-MDIX • CableDiagnostics • MIIIsolatemode 3.1 Bootstrap Configuration Bootstrap configuration is a convenient way to configure the TLK10x into specific modes of operation. Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. The table below describesbootstrapconfiguration. A 2.2kΩ resistor is used for pull-down or pull-up to change the default configuration. If the default option is desired, then there is no need for external pull-up or pull down resistors. Because these pins may have alternatefunctionsafterresetisdeasserted,theymustnotbeconnecteddirectlytoVCCorGND. Table3-1.StrapOptions PIN TYPE NAME NO. DESCRIPTION PHYAD0(COL) 29 PHYAddress[4:0]:TheTLK10xprovidesfivePHYaddresspins,thestatesofwhichare PHYAD1(RXD_0) 30 latchedintoaninternalregisteratsystemhardwarereset.TheTLK10xsupportsPHY S,O,PD/ PHYAD2(RXD_1) 31 Addressvalues0(<00000>)through31(<11111>).PHYAD[4:1]pinshaveweakinternal PU PHYAD3(RXD_2) 32 pull-downresistors,andPHYAD[0]hasweakinternalpull-upresistor,settingthedefault PHYAD4(RXD_3) 1 PHYADifnoexternalresistorsareconnected. AN_0:FD-HDconfig.FD=pullup. AN_0(LED_LINK) 17 S,O,PU Thedefaultwake-upisautonegotiationenable100BT. Copyright©2012–2016,TexasInstrumentsIncorporated HardwareConfiguration 7 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table3-1.StrapOptions(continued) PIN TYPE NAME NO. DESCRIPTION LEDConfiguration:ThisoptionselectstheoperationmodeoftheLEDLINKpin.Default LED_CFG(CRS) 27 S,O,PU isMode1.Allmodesarealsoconfigurableviaregisteraccess.SeePHYControlRegister (PHYCR),Address0x0019. Auto-MDIXEnable:ThisoptionsetstheAuto-MDIXmode.Bydefault,itenablesAuto- AMDIX_EN(RX_ER) 28 S,O,PU MDIX.Anexternalpull-downresistordisablesAuto-MDIXmode. MIIModeSelect:ThisoptionselectstheoperatingmodeoftheMACdatainterface.This MII_MODE(RX_DV) 26 S,O,PD pinhasaweakinternalpull-down,anditdefaultstonormalMIIoperationmode.An externalpull-upcausesthedevicetooperateinRMIImode. 3.2 Power Supply Configuration TheTLK10xprovidesbest-in-classflexibilityofpowersupplies. 3.2.1 Single Supply Operation If a single 3.3V power supply is desired, the TLK10x internal regulator provides the necessary core supply voltages. Ceramic capacitors of 10µf and 0.1µf should be placed close to the PFBOUT (pin 15) which is the output of the internal regulator. The PFBOUT pin should be connected to the PFBIN1 and PFBIN2 on the board. A small capacitor of 0.1µF should be placed close to the PFBIN1 (pin 13) and PFBIN2 (pin 24). Tooperateinthismode,connecttheTLK10xsupplypinsasshowninFigure3-1. 3.3V Supply 3.3V Supply Pin 14 Pin 9 10mF 10nF 1nF 100pF (AVDD33) (RD–) 3.3V 49.9W Supply 1:1 1mF 0.1mF 49.9W RD– 0.1μF Pin 13 Pin 10 RD+ (PFBIN1) (RD+) 1mF F* m Pin 15 0.1 (PFBOUT) 0.1μF 10μF Pin 11 Pin 24 (TD–) 3.3V TD– (PFBIN2) 49.9W Supply TD+ 0.1μF 1mF RJ45 1mF 0.1mF* 0.1mF* 1:1 T1 49.9W Pin 12 (TD+) 3.3V Supply Pin 21 (VDD_IO) 100pF 1nF 10nF 10mF Copyright © 2016,Texas Instruments Incorporated Figure3-1.PowerConnectionsforSingleSupplyOperation 8 HardwareConfiguration Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 3.2.2 Dual Supply Operation When a 1.55V external power rail is available, the TLK10x can be configured as shown in Figure 3-2. PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2 (pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing‘1’tobit15oftheVRCRregister(0x00d0h). 3.3V Supply 3.3V Supply Pin 14 Pin 9 (AVDD33) (RD–) 10mF 10nF 1nF 100pF 49.9W 3.3V Supply 1:1 1mF 0.1mF RD– 49.9W Floating Pin 15 Pin 10 (PFBOUT) (RD+) RD+ 1.55V 1mF Supply F* m Pin 13 0.1 10mF 10nF 1nF 100pF (PFBIN1) Pin 11 TD– (TD–) 3.3V 49.9W Supply TD+ 1mF RJ45 1mF 0.1mF 0.1mF* 1:1 T1 1.55V Supply 49.9W Pin 12 Pin 24 (TD+) 10mF 10nF 1nF 100pF (PFBIN2) 3.3V Supply Pin 21 (VDD_IO) 100pF 1nF 10nF 10mF Copyright © 2016,Texas Instruments Incorporated Figure3-2.PowerConnectionsforDualSupplyOperation Whenoperatingwithdualsupplies,followtheseguidelines: • Whenpoweringup,rampupthe3.3Vsupplybeforethe1.55Vsupply. • Whenpoweringdown,turnoffthe1.55Vsupplybeforeturningoffthe3.3Vsupply. • UsetheexternalRESETpinafterpoweruptoresetthePHY. • To use the internal power-on reset, PFBIN1 and PFBIN2 must be operational less than 100ms after 3.3VrisestodetecttheinternalRESET. 3.2.3 Variable IO Voltage The TLK10x digital IO pins can operate with a variable supply voltage. While the primary applications will use3.3V,VDD_IOcanalsooperateon2.5V,andforMIImodeonly,VDD_IOof1.8Vcanbeusedaswell. Formoredetails,seeSection9.7. Copyright©2012–2016,TexasInstrumentsIncorporated HardwareConfiguration 9 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 3.3 IO Pins Hi-Z State During Reset ThefollowingIOoroutputpinsareinhi-Zstatewhen RESETisactive(Low). INTERNAL Internal PINNAME TYPE PINNAME TYPE PU/PD PU/PD TXD_3 IO PD COL IO PU TX_EN IO PD RXD_0 IO PD INT/PWDN IO PU RXD_1 IO PD LED_LINK IO PU RXD_2 IO PD MDIO IO RXD_3 IO PD RX_DV IO PD TX_CLK O CRS IO PU RX_CLK O RX_ER IO PU 3.4 Auto-Negotiation The TLK10x device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation enabled, the TLK10x negotiates with the link partner to determine the speed and duplex mode. If the link partner cannot Auto-Negotiate, the TLK10x device enters parallel-detect mode to determine the speed of thelinkpartner.Parallel-detectmodeusesfixedhalf-duplexmode. The TLK10x supports four different Ethernet protocols (10Mbs Half-Duplex, 10Mbs Full-Duplex, 100Mbs Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the highest performance protocol based on the advertised ability of the Link Partner. Control the Auto-Negotiation function within the TLK10x by internalregisteraccessaccordingtotheIEEEspecification. Alternatively, control the HD-FD functionality by configuring the AN_0 pins. The state of AN_0 selects full or half duplex mode, both in Auto-negotiation or force 100/10 mode as given in Table 3-2. The state of AN_0uponpower-up/reset,determinesthestateofbits[8:5]oftheANARregister(0x04h). Auto-Negotiation advertises ANEN, 100BT by default. Full-Duplex or Half-Duplex configuration is available throughtheAN_0bit.Internalregisteraccessconfiguresthedeviceforaspecificmode. Table3-2.Auto-NegotiationModes AN_0 FORCEDMODE 0 10Base-T,Half-Duplex 100Base-TX,Half-Duplex 1 10Base-T,HalforFull-Duplex 100Base-TX,HalforFull-Duplex Internal register access controls the Auto-Negotiation function, as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u specification. 3.5 Auto-MDIX The TLK10x device automatically determines whether or not it needs to cross over between pairs, eliminating the requirement for an external crossover cable. If the TLK10x interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which deviceperformsthecrossover. Auto-MDIX is enabled by default and can be configured via pin strap, control register CR1 (0x09h), bit 14 orviaregisterPHYCR(0x19h),bit15. The crossover can be manually forced through bit 14 of the PHYCR (0x19h) register. Neither Auto- NegotiationnorAuto-MDIXisrequiredtobeenabledinforcingcrossoveroftheMDIpairs. 10 HardwareConfiguration Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Auto-MDIX can be used in the forced 100Base-TX mode. Because in modern networks all the nodes are 100Base-TX, having the Auto-MDIX working in the forced 100Base-TX mode resolves the link faster withouttheneedforthelongAuto-Negotiationperiod. 3.6 MII Isolate Mode TheTLK10xcanbeputintoMII-Isolatemodebywritingbit10oftheBMCRregister. When in the MII-Isolate mode, the TLK10x ignores packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs.Wheninisolatemode,theTLK10xcontinuestorespondtoallmanagementtransactions. When in isolate mode, the PMD output pair does not transmit packet data, but continues to source 100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK10x can auto-negotiate or parallel detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even whentheTLK10xisinIsolatemode. 3.7 PHY Address The5PHYaddressinputspinsaresharedwiththeRXD[3:0]pinsandCOLpinasshowninTable3-3. Table3-3.PHYAddressMapping PINNumber PHYADFUNCTION RXDFUNCTION 29 PHYAD0 COL 30 PHYAD1 RXD_0 31 PHYAD2 RXD_1 32 PHYAD3 RXD_2 1 PHYAD4 RXD_3 Each TLK10x or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK10x can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is00001(0x01h). See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the PHYADconfigurationresultsinaddress00011(0x03h). 3 2 1 0 _ _ _ _ D D D D L X X X X O R R R R C PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1 2.2 kW VCC Copyright © 2016,Texas Instruments Incorporated Figure3-3.IllustrativePHYADConfigurationExample Copyright©2012–2016,TexasInstrumentsIncorporated HardwareConfiguration 11 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 3.8 LED Interface The TLK10x supports one configurable Light Emitting Diode (LED) pin. The device supports 2 LED configurations: Link and Activity. Functions are multiplexed into two modes. The LED can be controlled by configuration pin and internal register bits. Bit 5 of the PHY Control register (PHYCR) selects the LED modeasdescribedinTable3-4. Table3-4.LEDModeSelect LED_CFG[0] MODE LED_LINK (BIT5)or(PIN27) ONforGoodLink 1 1 OFFforNoLink ONforGoodLink 2 0 BLINKforActivity TheLED_LINKpininMode1indicatesthelinkstatusoftheport.TheLEDisOFFwhennolinkispresent. In Mode 2 it is ON to indicate that the link is good; BLINK indicates that activity is present on either transmit or receive channel. Bits 10:9 of the LEDCR register (0x18) control the blink rate. The default blink rate is 5Hz. Enabling Enhanced LED Link via the CR2 register (0x0A) bit 4 overrides the LED blinking functionality of the PHYCR register (0x0019) bit 5. The Link LED will not blink for activity when Enhanced LEDLinkisenabled. See Figure 3-4 for an example of AN_0 connections to external components. In this example, the configurationresultsinFull-Duplexadvertised. K N LI _ D E L AN_O = 1 2.2 kW 470W VCC Copyright © 2016,Texas Instruments Incorporated Figure3-4.ANPinConfigurationandLEDLoadingExample 12 HardwareConfiguration Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 3.9 Loopback Functionality The TLK10x provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK10x digital and analog data path. Generally, the TLK10x may be configured to one of the Near-end loopback modes or to the Far-end (reverse)loopback. 3.9.1 Near-End Loopback Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with severaloptionsbeingprovided.Figure3-5showsthePHYnear-endloopbackfunctionality. PCS Loopback Analog Loopback 1 2 3 M 5 MAC/ Signal PHY 4 4 I PCS XFMR J Switch Process AFE R 5 I 6 7 PHYDigital 8 MII Loopback Digital Loopback External Loopback Copyright © 2016,Texas Instruments Incorporated Figure3-5.BlockDiagram,Near-EndLoopbackMode The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at address0x0000,bit[14]. TheNear-endLoopbackcanbeselectedaccordingtothefollowing: • Reg0x0000,Bit[14]:MIILoopback • Reg0x0016,Bit[0]:PCSinputLoopback • Reg0x0016,Bit[1]:PCSoutputLoopback • Reg0x0016,Bit[2]:DigitalLoopback • Reg0x0016,Bit[3]:AnalogLoopback Table3-5describestheavailableoperationalmodesforeachloopmode: Table3-5.LoopModes LOOPMODE MII PCSINPUT PCS DIGITAL ANALOG(1) EXTERNAL OUTPUT Force10/100ANEG OperationalSetting Force/ANEG100/10 Force100/10 Force100 Force100 Force/ANEG100/10 10 OperationalMACint. MIIOnly MIIorRMII MIIorRMII MIIorRMII MIIorRMII MIIorRMII (1) Requires100Ωtermination Copyright©2012–2016,TexasInstrumentsIncorporated HardwareConfiguration 13 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. For proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This constraint does not apply for external-loopback mode. For selected loopback Delay propagation timing pleaseseeSection9.10.21. 3.9.2 Far-End Loopback Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on theMIIandtransmittedbacktothelinkpartner.Figure3-6showsFar-endloopbackfunctionality. M XFMR MAC/ Signal PHY CAT5Cable I PCS & Link Partner Switch Process AFE I RJ45 PHYDigital Reverse Loopback Copyright © 2016,Texas Instruments Incorporated Figure3-6.BlockDiagram,Far-EndLoopbackMode The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII registeraddress0x0016. While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface andalldatasignalsthatcomefromtheMACareignored. Table3-6describestheoperatingmodesforFar-EndLoopback. Table3-6.Far-EndLoopbackModes OPERATIONALMAC MIIMODE RMIIMODE INT. OperationalSetting Force/ANEG10/100 Force/ANEG10 14 HardwareConfiguration Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 3.10 BIST The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets andInter-PacketGap(IPG)onthelines.TheBISTallowsfullcontrolofthepacketlengthsandoftheIPG. The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker received is stored in the BICSR1 register (0x001Bh). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be read from the BISCR register (0x0016h). While the lock and sync indications are required to identify the beginning of proper data reception, for any link failures or data corruption,thebestindicationisthecontentsofthetheerrorcounterintheBICSR1register(0x001Bh). The PRBS test can be put in a continuous mode or single mode by using bit 14 of the BISCR register (0x0016h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again. In single mode, when the PRBS counter reaches its maximum value, the PRBScheckerstopscounting. ThedeviceallowstheusertocontrolthelengthofthePRBSpacket.ByprogrammingtheBICSR2register (0x001Ch) one can set the length of the PRBS packet. There is also an option to generate a single-packet transmission of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016h). Thesinglegeneratedpacketiscomposedofaconstantdata. 3.11 Cable Diagnostics With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit providesextensiveinformationaboutcableintegrity. TheTLK10xoffersthefollowingcapabilitiesinitsCableDiagnostictoolskit: 1. TimeDomainReflectometry(TDR) 2. ActiveLinkCableDiagnostic(ALCD) 3.11.1 TDR The TLK10x uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, crossfaults,crossshortsandanyotherdiscontinuitiesalongthecable. The TLK10x transmits a test pulse of known amplitude (1V or 2.5V) down each of the two pairs of an attached cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector, and from the end of the cable itself. After the pulse transmission the TLK10x measures the return time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude (impedance) of non-terminated cables (open or short), discontinuities(badconnectors),andimproperly-terminatedcableswith ±1maccuracy. The TLK10x also uses data averaging to reduce noise and improve accuracy. The TLK10x can record up to five reflections within the tested pair. If more than 5 reflections are recorded, the TLK10x saves the first 5 of them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflectionsinthetestedchannel.TheTLK10xTDRcanmeasurecablesupto200minlength. Copyright©2012–2016,TexasInstrumentsIncorporated HardwareConfiguration 15 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category(forexample,CAT5,CAT5e,orCAT6). TDRmeasurementisallowedintheTLK10xinthefollowingscenarios: • WhileLinkpartnerisdisconnected– cableisunpluggedattheotherside • Linkpartnerisconnectedbutremains“quiet”(forexample,inpowerdownmode) • TDR could be automatically activated when the link fails or is dropped by setting bit 8 of register 0x0009 (CR1). The results of the TDR run after the link fails will be saved in the TDR registers. The SW could read these registers at any time to apply post processing on the TDR results. This mode is designedforcasesinwhichthelinkdroppedduetocabledisconnections,inwhichafterlinkfailure,the linewillbequiettoallowaproperfunctionoftheTDR. 3.11.2 ALCD The TLK10x also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. The ALCD uses passive digital signal processing based on adapteddata,thusenablingmeasurementofcablelengthwithanactivelinkpartner. The ALCD Cable length measurement accuracy is ±5m for the pair used in the Rx path (due to the passivenatureofthetest,onlythereceivepathismeasured). 16 HardwareConfiguration Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 4 Interfaces 4.1 Media Independent Interface (MII) The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHYtotheMACin100B-TXand10B-Tmodes.TheMIIisfullycompliantwithIEEE802.3-2002clause22. TheMIIsignalsaresummarizedbelow. Datasignals TXD[3:0] RXD[3:0] Transmitandreceive-validsignals TX_EN RX_DV Line-statussignals CRS(carriersense) COL(collision) Figure4-1showstheMII-modesignals. PHY MAC TX_CLK TX_CLK TX_EN TX_EN TXD [3:0] TXD [3:0] RX_CLK RX_CLK RX_DV RX_DV RX_ER RX_ER RXD [3:0] RXD [3:0] CRS CRS COL COL Figure4-1.MIISignaling The Isolate bit (BMCR register bit 10), defined in IEEE802.3-2002, electrically isolates the PHY from the MII(ifset,alltransactionsontheMIIinterfaceareignoredbythePHY). Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur duringhalf-duplexoperationwhenbothtransmitandreceiveoperationoccursimultaneously. Copyright©2012–2016,TexasInstrumentsIncorporated Interfaces 17 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 4.2 Reduced Media Independent Interface (RMII) TLK10x incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification providesanadditionalreconciliationlayeroneithersideoftheMII,butcanbeimplementedintheabsence ofanMII. TheRMIIspecificationhasthefollowingcharacteristics: • Supports10Mbsand100Mbsdatarates • SingleclockreferencesourcedfromtheMACtoPHY(orfromanexternalsource) • Providesindependent2bitwide(di-bit)transmitandreceivedatapaths • UsesCMOSsignallevels,operatesat3.3Vor2.5VVDD_IOlevels 18 Interfaces Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and receive.RMIImodeusesthefollowingpins: SIGNAL PIN XI(RMIIreferenceclockis50MHz) 23 TXD_0 4 TXD_1 5 TX_EN 3 CRS_DV 27 RX_ER 28 RXD_0 30 RXD_1 31 Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generatedonevery10thclocksothatanattachedMACdevicecansamplethedataevery10clocks. In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though not required by RMII spec (The TLK10x supports optional use of RX_ER and RX_DV in RMII as anextrafeature).RMIImoderequiresa50MHzoscillatorconnectedtothedeviceXIpin. The TLK10x supports a special mode called “RMII receive clock” mode. This mode, which is not part of the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DVandRX_ERsignalstothisclock.Settingregister0x000Abit[0]isrequiredtoactivatethismode. Figure4-2describestheRMIIsignalsconnectivitybetweentheTLK10xandanyMACdevice. PHY MAC TX_EN TX_EN TXD[1:0] TXD[1:0] RX_CLK (optional) RX_CLK RX_DV RX_DV (optional) RX_ER (optional) RX_ER RXD[1:0] RXD[1:0] CRS/RX_DV CRS/RX_DV XI 50MHz Clock Source Copyright © 2016,Texas Instruments Incorporated Figure4-2.TLK10xRMII/MACConnection Copyright©2012–2016,TexasInstrumentsIncorporated Interfaces 19 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagationdelaybasedonexpectedmaximumpacketsizeandclockaccuracy. indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumesthattheRMIIreferenceclockandthefar-endtransmitterclockhavethesameaccuracy. RecommendedRMIIPacketSizes RECOMMENDEDPACKETSIZE RECOMMENDEDPACKETSIZE STARTTHRESHOLDRBR[1:0] LATENCYTOLERANCE AT±50PPM AT±100PPM 1(4-bits) 2bits 2400bytes 1200bytes 2(8-bits) 6bits 7200bytes 3600bytes 3(12-bits) 10bits 12000bytes 6000bytes 0(16-bits) 14bits 16800bytes 8400bytes 4.3 Serial Management Interface The Serial Management Interface (SMI), provides access to the TLK10x internal register space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide additionalvisibilityandcontrollabilityoftheTLK10xdevice. TheSMIincludestheMDCmanagementclockinputandthemanagementMDIOdatapin.TheMDCclock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entitywhenthebusisidle. The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which, duringIDLEandturnaround,pullsMDIOhigh. Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK10x latches the PHYAD[4:0] configuration pins (Pin 29 to Pin 32) to determineitsaddress. The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de- asserted. In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific).Thedatafieldisusedforbothreadingandwriting.TheStartcodeisindicatedbya <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK10x drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO asdriven/receivedbytheStation(STA)andtheTLK10x(PHY)foratypicalregisterreadaccess. For write transactions, the station-management entity writes data to the addressed TLK10x, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The framestructureandgeneralread/writetransactionsareshowninTable4-1,Figure4-3,andFigure4-4. Table4-1.TypicalMDIOFrameFormat MIIMANAGEMENTSERIALPROTOCOL <IDLE><START><OPCODE><DEVICEADDR><REG ADDR><TURNAROUND><DATA><IDLE> ReadOperation <idle><01><10><AAAAA><RRRRR><Z0><xxxxxxxxxxxxxxxx><idle> 20 Interfaces Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table4-1.TypicalMDIOFrameFormat(continued) MIIMANAGEMENTSERIALPROTOCOL <IDLE><START><OPCODE><DEVICEADDR><REG ADDR><TURNAROUND><DATA><IDLE> WriteOperation <idle><01><01><AAAAA><RRRRR><10><xxxxxxxxxxxxxxxx><idle> MDC MDIO Z Z (STA) MDIO Z Z (PHY) Z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Z Opcode PHYAddress RegisterAddress Idle Start TA RegisterData Idle (Read) (PHYAD=0Ch) (00h=BMCR) Figure4-3.TypicalMDC/MDIOReadOperation MDC Z Z MDIO (STA) Z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z Opcode PHYAddress RegisterAddress Idle Start TA RegisterData Idle (Read) (PHYAD=0Ch) (00h=BMCR) Figure4-4.TypicalMDC/MDIOWriteOperation Copyright©2012–2016,TexasInstrumentsIncorporated Interfaces 21 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 4.3.1 Extended Address Space Access The TLK10x SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method definedinIEEE802.3ahDraftforclause22foraccessingtheclause45extendedregisterset. The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the indirect method, except for register REGCR(0x000Dh) and ADDAR(0x000Eh) which is accessed only usingthenormalMDIOtransaction.TheSMIfunctionwillignoreindirectaccessestotheseregisters. REGCR(0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR(0x000Eh) register to the appropriate MMD. Specifically, the TLK10x uses the vendor-specific DEVAD[4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR must use this DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data withpostincrementonreadandwrites(10)anddatawithpostincrementonwritesonly(11). • ADDAR is the address/data MMD register. ADDAR is used in conjunction with REGCR to provide the access to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended register set address register. This address register must always be initialized in order to accessanyoftheregisterswithintheextendedregisterset. • WhenREGCR[15:14]issetto01,accessestoregisterADDARaccesstheregisterwithintheextended registersetselectedbythevalueintheaddressregister. • When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for both reads andwrites,thevalueintheaddressregisterisincremented. • When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the addressregisterremainsunchanged. The following sections describe how to perform operations on the extended register set using register REGCRandADDAR. 4.3.1.1 WriteAddressOperation Tosettheaddressregister: 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. SubsequentwritestoregisterADDAR(step2)continuetowritetheaddressregister. 4.3.1.2 ReadAddressOperation Toreadtheaddressregister: 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. ReadtheregisteraddressfromregisterADDAR. SubsequentreadstoregisterADDAR(step2)continuetoreadtheaddressregister. 22 Interfaces Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 4.3.1.3 Write(nopostincrement)Operation Towritearegisterintheextendedregisterset: 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x401F(data,nopostincrementfunctionfield=01,DEVAD=31)toregisterREGCR. 4. WritethecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the addressregister. Note:steps(1)and(2)canbeskippediftheaddressregisterwaspreviouslyconfigured. 4.3.1.4 Read(nopostincrement)Operation Toreadaregisterintheextendedregisterset: 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x401F(data,nopostincrementfunctionfield=01,DEVAD=31)toregisterREGCR. 4. ReadthecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the addressregister. Note:steps(1)and(2)canbeskippediftheaddressregisterwaspreviouslyconfigured. 4.3.1.5 Write(postincrement)Operation 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. WritetheregisteraddressfromregisterADDAR. 3. Writethevalue0x801F(data,postincrementonreadsandwritesfunctionfield=10,DEVAD=31)or thevalue0xC01F(data,postincrementonwritesfunctionfield=11.DEVAD=31)toregisterREGCR. 4. WritethecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by thevalueoftheaddressregister;theaddressregisterisincrementedaftereachaccess. 4.3.1.6 Read(postincrement)Operation Toreadaregisterintheextendedregistersetandautomaticallyincrementtheaddressregistertothenext highervaluefollowingthewriteoperation: 1. Writethevalue0x001F(addressfunctionfield=00,DEVAD=31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x801F(data,postincrementonreadsandwritesfunctionfield=10,DEVAD=31)to registerREGCR. 4. ReadthecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by thevalueoftheaddressregister;theaddressregisterisincrementedaftereachaccess. Copyright©2012–2016,TexasInstrumentsIncorporated Interfaces 23 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 5 Architecture The TLK10x Fast Ethernet transceiver is a physical layer core for Ethernet 100Base-TX and 10Base-T applications.TheTLK10xcontainsalltheactivecircuitryrequiredtoimplementthephysicallayerfunctions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII), as well as the Reduced Media Independent Interface(RMII),fordirectconnectiontoaMAC/Switchport. The TLK10x uses mixed signal processing to perform equalization, data recovery and error correction to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The TLK10x architecture not only meets the requirements of IEEE802.3, but maintains a high level of margin over the IEEErequirementsforNEXT,AlienandExternalnoise. 4B/5B Scrambler NRZtoNRZI MLT-3 D/A 100BaseTX encoding Convertor encoding Convertor LineDriver Transmit Manchester 10BaseT 10BaseT encoding Filter LineDriver 100BaseTX MII Adv. LinkMonitor 10Base-T Receive 10BaseT Manchester Receive decoding Filter de4cBo/5dBing DeScrambler NCRoZnIvtoerNtoRrZ deMcLoTd-i3ng DCSorPre(cBtioLnW, AADmCpl(iFfieiltrel)r, Adapt.Equal) Copyright © 2016,Texas Instruments Incorporated Figure5-1.PHYArchitecture 5.1 100Base-TX Transmit Path In 100Base-TX, the MAC feeds the 100Mbps transmit data in 4-bit wide nibbles through the MII interface. The data is encoded into 5-bit code groups, encapsulated with control code symbols and serialized. The control-code symbols indicate the start and end of the frame and code other information such as transmit errors. When no data is available from the MAC, IDLE symbols are constantly transmitted. The serialized bit stream is fed into a scrambler. The scrambled data stream passes through an NRZI encoder and then through an MLT3 encoder. Finally, it is fed to the DAC and transmitted through one of the twisted pairs of thecable. 5.1.1 MII Transmit Error Code Forwarding AccordingtoIEEE802.3: “If TX_EN is de-asserted on an odd nibble boundary, PHY should extend TX_EN by one TX_CLK cycleandbehaveasifTX_ERwereassertedduringthatcycle”. The TLK10x supports Error Forwarding in MII transmission from the MAC to the PHY. Error forwarding allows adding information to the frame to be used as an error code between the 2 MACs. The error code informs the receiving MAC on the link partner side of the reason for the error from the transmitting side. If the MAC transmits an odd number of nibbles, an additional error nibble is added to the transmitted frame justbeforetheendofthetransmission. To turn off Transmit Error Forwarding, write to bit 1 of register CR2 (0x000A). If Error Forwarding is disabled,deliveredpacketscontaineitheroddorevennumbersofnibbles. In Figure 5-2, Error Code Forwarding functionality is illustrated. The wave diagram demonstrates MAC’s transmittedsignalsinonesideandMAC’sreceptionsignalsonlinkpartnerside. 24 Architecture Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 TX_CLK TX_EN Data n-2 Data n-2 Data n-1 Data n-1 Data n Data n Error TXD[3:0] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] Code RX_CLK RX_DV RXD[3:0] Da[3ta:0 n]-2 Da[7ta:4 n]-2 Da[3ta:0 n]-1 Da[7ta:4 n]-1 D[a3t:a0 ]n D[a7t:a4 ]n CEorrdoer Don't Care RX_ER Figure5-2.TransmitCodeErrorForwardingDiagram 5.1.2 4-Bit to 5-Bit Encoding The transmit data that is received from the MAC first passes through the 4-Bit to 5-Bit encoder. This block encodes4-bitnibbleinto5-bitcode-groupsaccordingtotheTable5-1.Each4-bitdatanibbleismappedto 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information ortheyareconsideredasnotvalid. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4-bit preamble and data nibbles with corresponding 5-bit code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder adds the T/R code- grouppair(0110100111)indicatingtheendoftheframe. After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data streamuntilthenexttransmitpacketisdetected. Copyright©2012–2016,TexasInstrumentsIncorporated Architecture 25 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table5-1.4-Bitto5-BitCodeTable 4-BITCODE SYMBOL 5-BITCODE RECEIVERINTERPRETATION 0000 0 11110 Data 0001 1 01001 0010 2 10100 0011 3 10101 0100 4 01010 0101 5 01011 0110 6 01110 0111 7 01111 1000 8 10010 1001 9 10011 1010 A 10110 1011 B 10111 1100 C 11010 1101 D 11011 1110 E 11100 1111 F 11101 IDLEANDCONTROLCODES DESCRIPTION Symbol(1) 5-BitCode Inter-PacketIDLE I 11111 IDLE FirstnibbleofSSD J 11000 FirstnibbleofSSD,translatedto"0101"following/I/(IDLE), elseRX_ERassertedhigh SecondnibbleofSSD K 10001 SecondnibbleofSSD,translatedto"0101"following/J/,else RX_ERassertedhigh FirstnibbleofESD T 01101 FirstnibbleofESD,causesde-assertionofCRSiffollowed by/R/,elseassertionofRX_ER SecondnibbleofESD R 00111 SecondnibbleofESD,causesde-assertionofCRSif following/T/,elseassertionofRX_ER TransmitErrorSymbol H 00100 RX_ER InvalidSymbol V 00000 INVALID RX_ERassertedhighIfduringRX_DV V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 (1) Controlcode-groupsI,J,K,TandRindatafieldswillbemappedasinvalidcodes,togetherwithRX_ERasserted. 5.1.3 Scrambler The purpose of the scrambler is to flatten the power spectrum of the transmitted signal, thus reduce EMI. The scrambler seed is generated with reference to the PHY address so that multiple PHYs that reside withinthesystemwillnotusethesamescramblersequence. 5.1.4 NRZI and MLT-3 Encoding To comply with the TP-PMD standard for 100Base-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level representsacodebit'1'andthelogicoutputremainingatthesamelevelrepresentsacodebit'0'. 26 Architecture Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 5.1.5 Digital to Analog Converter The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements andenabletheuseoflow-costtransformers. Digitalpulse-shapefilteringisalsoappliedinordertoconformtothepulsemasksdefinedbystandardand toreduceEMIandhighfrequencysignalharmonics. 5.2 100Base-TX Receive Path In 100B-TX, the ADC sampled data is passed to an adaptive equalizer. The adaptive equalizer drives the received symbols to the MLT3 decoder. The decoded NRZ symbols are transferred to the descrambler blockfordescramblinganddeserialization. 5.2.1 Analog Front End The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. The AFE consists of an AnalogtoDigitalConverter(ADC),receivefiltersandaProgrammableGainAmplifier(PGA). The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input while maintaining high power-supply rejection ratio and low power consumption. There is only one ADC in the TLK10x, which receives the analog input data from the relevant cable pair, according to MDI-MDIX resolution. The PGA, digitally controlled by the adaptive equalizer, fully uses the dynamic range of the ADC by adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and amplifieslong-cableweaksignals. 5.2.2 Adaptive Equalizer The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the channel and analog Tx/Rx filters. The TLK10x includes both Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE). The combination of both adaptive modules with the adaptive gain control results in a powerful equalizer that can eliminate ISI and compensate for cable attenuation for longer-reach cables. In addition, the Equalizer includes a Shift Gear Step mechanism to provide fast convergenceontheonehandandsmallresidual-adaptivenoiseinsteadystateontheotherhand. 5.2.3 Baseline Wander Correction The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because ofthisphenomenon,thereceivercorrectsthebaselinewanderandcanreceivetheANSITP-PMD-defined "killerpacket"withnobiterrors. 5.2.4 NRZI and MLT-3 Decoding TheTLK10xdecodestheMLT-3informationfromtheDigitalAdaptiveEqualizerblocktobinaryNRZIdata. TheNRZI-to-NRZdecoderisusedtopresentNRZ-formatteddatatothedescrambler. Copyright©2012–2016,TexasInstrumentsIncorporated Architecture 27 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 5.2.5 Descrambler The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100B- TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason, synchronizationislost,thedescramblertriestore-acquiresynchronizationusingtheIDLEsymbols. 5.2.6 5B/4B Decoder and Nibble Alignment The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair precededbyIDLEcode-groupsatthestartofapacket.Oncethecodegroupalignmentisdetermined,itis stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble. Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5- bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter (ESD)orwiththereceptionofaminimumoftwoIDLEcode-groups. 5.2.7 Timing Loop and Clock Recovery The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing. The timing loop recovers the far-end clock frequency and offset from the received data samples and tracksinstantaneousphasedriftscausedbytimingjitter. The TLK10x has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the Far- End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an advanced tracking mechanism that when combined with different available phases, always keeps track of the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and Jitter. The TLK10x is capable of dealing with PPM and jitter at levels far higher than those defined by the standard. 5.2.8 Phase-Locked Loops (PLL) In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the received Manchester signal. The DPLL is able to combat clock jitter of up to ±18ns and frequency drifts of ±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a decodedserialbitstream. The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal oscillator,oratXIwithanexternalreferenceclock). 5.2.9 Link Monitor The TLK10x implements the link monitor State Machine (SM) as defined by the IEEE 802.3 100Base-TX Standard. In addition, the TLK10x enables several add-ons to the link monitor SM activated by configurationbits.Thenewadd-onsincludetherecoverystatewhichenablesthePHYtoattemptrecovery in the event of a temporary energy-loss situation before entering the LINK_FAIL state, thus restarting the whole link establishment procedure. This sequence allows significant reduction of the recovery time in scenarioswherethelinklossistemporal. In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time. Theseadd-onsaresupplementarytotheIEEEstandardandarebypassedbydefault. 28 Architecture Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 5.2.10 Signal Detect The signal detect function of the TLK10x is incorporated to meet the specifications mandated by the ANSIFDDITP-PMDStandardaswellastheIEEE802.3100Base-TXStandardforbothvoltagethresholds andtimingparameters. The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is comparedtopredefinedthresholdsinordertodecidethepresenceorabsenceofanincomingsignal. The energy detector also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required. 5.2.11 Bad SSD Detection A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the TLK10x asserts RX_ER, and presents RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the FCSCR register (0x14h) is incrementedbyoneforeveryerrorinthenibble. WhenatleasttwoIDLEcodegroupsaredetected,RX_ERandCRSarede-asserted. 5.3 10Base-T Receive Path In 10B-T, after the far-end clock is recovered, the received Manchester symbols pass to the Manchester decoder. The serial decoded bit stream is aligned to the start of the frame, de-serialized to 4-bit wide nibblesandsenttotheMACthroughtheMII. 5.3.1 10M Receive Input and Squelch The squelch feature determines when valid data is present on the differential receive inputs. The TLK10x implements a squelch to prevent impulse noise on the receive inputs from being mistaken for a valid signal. Squelch operation is independent of the 10Base-T operating mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) todeterminethevalidityofdataonthetwisted-pairinputs. The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checkedbeforeindicatingthatvaliddataispresent.Atthistime,thesquelchcircuitryisreset. 5.3.2 Collision Detection When in Half-Duplex mode, a 10Base-T collision is detected when receive and transmit channels are activesimultaneously.CollisionsarereportedbytheCOLsignalontheMII. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected,itisreportedimmediately(throughtheCOLpin). 5.3.3 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity after valid data is detected via the squelch function. For 10Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.For10Mb/sFullDuplexoperation,CRSisassertedonlyduringreceiveactivity. CRSisde-assertedfollowinganend-of-packet. Copyright©2012–2016,TexasInstrumentsIncorporated Architecture 29 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 5.3.4 Jabber Function Jabberisaconditioninwhichastationtransmitsforaperiodoftimelongerthanthemaximumpermissible packet length, usually due to a fault condition. The jabber function monitors the TLK10x output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors thetransmitteranddisablesthetransmissionifthetransmitterisactiveforapproximately100ms. When disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal must be de-asserted for approximately 500ms (theunjabtime)beforetheJabberfunctionre-enablesthetransmitoutputs. TheJabberfunctionisonlyavailableandactivein10Base-Tmode. 5.3.5 Automatic Link Polarity Detection and Correction Swapping the wires within the twisted pair causes polarity errors. Wrong polarity affects the 10B-T PHYs. The 100B-TX is immune to polarity problems because it uses MLT3 encoding. The 10B-T automatically detects reversed polarity according to the received link pulses or data. Note that the default transmit link pulsepolarityfortheTLK10xisreversed. 5.3.6 10Base-T Transmit and Receive Filtering External 10Base-T filters are not required when using the TLK10x, because the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all theharmonicsinthetransmitsignalareattenuatedbyatleast30dB. 5.3.7 10Base-T Operational Modes TheTLK10xhastwobasic10Base-Toperationalmodes: • Half Duplex mode – In Half Duplex mode the TLK10x functions as a standard IEEE 802.3 10Base-T transceiversupportingtheCSMA/CDprotocol. • Full Duplex mode – In Full Duplex mode the TLK10x is capable of simultaneously transmitting and receiving without asserting the collision signal. The TLK10x 10Mbs ENDEC is designed to encode and decodesimultaneously. 5.4 Auto Negotiation The auto-negotiation function, described in detail in IEEE802.3 chapter 28, provides the means to exchange information between two devices and automatically configure both of them to take maximum advantageoftheirabilities. 5.4.1 Operation Auto negotiation uses the 10B-T link pulses to encapsulate the transmitted data in a sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data sequence. Extraction of the data bits fromtheFLPBurstyieldsaLinkCodeWordthatidentifiestheoperationalmodessupportedbytheremote device,aswellassomeinformationusedfortheautonegotiationfunction’shandshakemechanism. The information exchanged between the devices during the auto-negotiation process consists of the devices' abilities such as duplex support and speed. This information allows higher levels of the network (MAC) to send to the other link partner vendor-specific data (via the Next Page mechanism, see below), andprovidesthemechanismforbothpartiestoagreeonthehighestperformancemodeofoperation. 30 Architecture Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Whenautonegotiationhasstarted,theTLK10xtransmitsFLPononetwistedpairandlistensontheother, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information. If the other link partner is a legacy PHY or does not activate the auto negotiation, then the TLK10x uses the parallel detection function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation modes. 5.4.2 Initialization and Restart TheTLK10xinitiatestheautonegotiationfunctionifoneofthefollowingeventshavehappened: 1. Hardwareresetde-assertion 2. Softwarereset(viaregister) 3. Autonegotiationrestart(viaregisterBMCR(0x0000h)bit9) 4. Power-upsequence(viaregisterBMCR(0x0000h)bit11) The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR (0x0000h)bit12andoneofthefollowingeventshashappened: 1. Softwarerestart 2. Transitioningtolink_failstate,asdescribedinIEEE802.3 To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK10x operation. For the changes to take place,issuearestartcommandthroughregisterBMCR(0x0000h)bit9. 5.4.3 Next Page Support The TLK10x supports the optional feature of the transmission and reception of auto-negotiation additional (vendorspecific)nextpages. Ifnextpagesareneeded,theusermustsetregisterANAR(0x0004h)bit15to'1'.Thenextpagesarethen sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively. The user must poll register ANER(0x0006h) bit 1 to check whether a new page has been received, and then read register ANLNPTR for the received next page's content. Only after register ANLNPTR is read may the userwritetoregisterANNPTRthenextpagetobetransmitted.AfterregisterANNPTRiswritten,newnext pagesoverwritethecontentsofregisterANLNPTR. If register ANAR(0x0004h) bit 15 is set, then the next page sequence is controlled by the user, meaning that the auto-negotiation function always waits for register ANNPTR to be written before transmitting the nextpage. If additional user-defined next pages are transmitted and the link partner has more next pages to send, it is the user's responsibility to keep writing null pages (of value 0x2001) to register ANNPTR until the link partnernotifiesthatithassentitslastpage(bysettingbit15ofitstransmittednextpagetozero). Copyright©2012–2016,TexasInstrumentsIncorporated Architecture 31 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 5.5 Link Down Functionality The TLK10x includes advanced link-down capabilities that support various real-time applications. The link- down mechanism of the TLK10x is configurable and includes enhanced modes that allow extremely fast reactiontimestolink-drops. First Link Failure Occurrence Valid Data LOW Quality Data / Link Loss Signal Link Drop T1 Link Loss Indication (Link LED) Figure5-3.TLK10xLinkLossMechanism As described in Figure 5-3, the TLK10x link loss mechanism is based on a time window search period, in whichthesignalbehaviorismonitored.TheT1windowissetbydefaulttoreducetypicallink-dropstoless than1ms. The TLK10x supports enhanced modes that shorten the window called Fast Link Down mode. In this mode, which can be configured in Control Register 3 (CR3), address 0x000B, bits 3:0, the T1 window is shortened significantly, in most cases less than 10µs. In this period of time there are several criteria allowedtogeneratelinklosseventanddropthelink: 1. CountRXErrorintheMIIinterface:Whenapredefinednumberof32RXErroroccurrencesintime windowof10µsisreachedthelinkwilldrop. 2. CountMLT3Errorsatthesignalprocessingoutput(100BTusesMLT3coding,andwhenaviolationof thiscodingisdetected,anMLT3errorisdeclared).Whenapredefinednumberof20errors occurrencesin10µsisreachedthelinkwilldrop. 3. CountLowSignalQualityThresholdcrossing(Whenthesignalqualityisunderacertainthresholdthat allowsproperlinkconditions).Whenapredefinednumberof20occurrencesin10µsisreached,the linkwilldrop. 4. Signal/Energylossindications.WhenEnergydetectorindicatesEnergyLoss,thelinkwillbedropped. Typicalreactiontimeis10µs. TheFastLinkDownfunctionalityallowstheuseofeachoftheseoptionsseparatelyorinanycombination. Notethatsincethismodeenablesextremelyquickreactiontime,itismoreexposedtotemporarybadlink- qualityscenarios. 32 Architecture Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 6 Reset and Power Down Operation The TLK10x includes an internal power-on-reset (POR) function, and therefore does not need an explicit resetfornormaloperationafterpowerup. At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If requiredduringnormaloperation,thedevicecanberesetbyahardwareorsoftwarereset. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to RESET. This pulse resets the device such that all registers are reinitialized to default values, and the hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally isapproximately200µs. 6.2 Software Reset An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x0000h).ThisbitonlyresetstheIEEE-definedstandardregistersintheaddressspace0x00hto0x07h. A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to ‘1’. This bit resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the extended registers. The global software reset resets the device such that all registers are reset to default valuesandthehardwareconfigurationvaluesaremaintained. A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to ‘1’. This actionresetsallthePHYcircuitsexcepttheregistersintheRegisterFile. The time from the point when the resets/restart bits are set to the point when the software resets/restart has concluded is approximately 200µs. TI recommends that the software driver code must wait 500µs followingsoftwareresetbeforeallowingfurtherserialMIIoperationswiththeTLK10x. 6.3 Power Down/Interrupt The Power Down and Interrupt functions are multiplexed on pin 8 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 0 (INT_OE) to ‘1’ in the PHYSCR (0x0011h) register. The PHYSCR registerisalsousedtoenableandsetthepolarityoftheinterrupt. 6.3.1 Power Down Control Mode The INT/PWDN pin can be asserted low to put the device in a Power Down mode. An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the INT/PWDNpin. 6.3.2 Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. The MISR1 (0x0012) and MISR2 (0x0013) registers provide independent interrupt enable bits for the various interrupts supported by the TLK10x. The INT/PWDN pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the interrupt status registers MISR1 (0x0012h) and MISR2 (0x0013). One or more bits in the MISR registers will be set, indicating all currently-pendinginterrupts.ReadingtheMISRregistersclearsALLpendinginterrupts. Copyright©2012–2016,TexasInstrumentsIncorporated ResetandPowerDownOperation 33 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 6.4 Power Save Modes The TLK10x supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMIfunctionalityisshutdown(Registeraccessisstillavailable). To enable and activate all other power save modes through register access, use register PHYSCR (0x0011h).Settingbit14enablesallpower-savemodes;bits[13:12]selectbetweenthem. Settingbits[13:12]to “01”powersdownthePHY,forcingitintoIEEEpowerdownmode(SimilartoBMCR bit11functionality). Settingbits[13:12]to “10”putsthePHYinLowPowerActiveEnergySavingmode. Settingbits[13:12]to “11”putsthePHYinLowPowerPassiveEnergySavingmode. When these bits are cleared, the PHY powers up and returns to the last state it was in before it was powereddown. 34 ResetandPowerDownOperation Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 7 Design Guidelines 7.1 TPI Network Circuit Figure7-1showstherecommendedcircuitfora10/100Mbstwistedpairinterface.Commonmode chokesonthedevicesideofthetransformerarerequired.VariationswithPCBandcomponent characteristicsrequirethattheapplicationbetestedtoverifythatthecircuitmeetstherequirements oftheintendedapplication. Vdd Common mode chokes on the RD– device side of the transformer Vdd are required. 49.9 : 1:1 0.1 PF RD– 49.9 : RD+ RD+ * 1 PF F P 1 0. TD– TD– Vdd 49.9 : TD+ 1 PF RJ45 1:1 T1 0.1 PF* 0.1 PF 49.9 : Note: Center tap is connected to Vdd TD+ * Place capacitors close to the transformer center taps Place resistors and capacitors close to the device. All values are typical and are r1% Copyright © 2016, Texas Instruments Incorporated Figure7-1.10/100MbsTwistedPairInterface 7.2 Clock In (XI) Requirements The TLK10x supports an external CMOS-level oscillator source or an internal oscillator with an external crystal. 7.2.1 Oscillator If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The oscillator should use the same supply voltage as the VDD_IO supply. When operating in RMII, the oscillatorsupplyvoltagemustbe3.3Vor2.5V. Copyright©2012–2016,TexasInstrumentsIncorporated DesignGuidelines 35 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 7.2.2 Crystal The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystalvendors;checkwiththevendorfortherecommendedloads. The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW. If a crystal is specified for a lower drive level, a current limiting resistor mustbeplacedinseriesbetweenXOandthecrystal. As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for C and C at 33pF, and R should be set at 0Ω. Specifications for a 25MHz crystal are L1 L2 1 listedinTable7-3. XI XO R 1 C C L1 L2 S0340-01 Copyright © 2016,Texas Instruments Incorporated Figure7-2.CrystalOscillatorCircuit Table7-1.25MHzOscillatorSpecification PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Frequency 25 MHz FrequencyTolerance OperationalTemperature ±50 ppm FrequencyStability 1yearaging ±50 ppm Rise/FallTime 10%–90% 8 nsec Jitter(Shortterm) Cycle-to-cycle 50 psec Jitter(Longterm) Accumulativeover10ms 1 nsec Symmetry DutyCycle 40% 60% LoadCapacitance 15 30 pF Table7-2.50MHzOscillatorSpecification PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Frequency 50 MHz FrequencyTolerance OperationalTemperature ±50 ppm FrequencyStability 1yearaging ±50 ppm Rise/FallTime 10%–90% 6 nsec Jitter(Shortterm) Cycle-to-cycle 50 psec Jitter(Longterm) Accumulativeover10ms 1 nsec Symmetry DutyCycle 40% 60% Table7-3.25MHzCrystalSpecification PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Frequency 25 MHz FrequencyTolerance OperationalTemperature ±50 ppm At25°C ±50 ppm FrequencyStability 1yearaging ±5 ppm 36 DesignGuidelines Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table7-3.25MHzCrystalSpecification(continued) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT LoadCapacitance 10 40 pF 7.3 Thermal Vias Recommendation ThefollowingthermalviaguidelinesapplytoDOWN_PAD,pin 33: 1. Thermalviasize=0.2mm 2. Recommend4vias 3. Viashaveacentertocenterseparationof2mm. Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure7-3illustratesanexamplelayout. Figure7-3.ExampleLayout Copyright©2012–2016,TexasInstrumentsIncorporated DesignGuidelines 37 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8 Register Block Table8-1.RegisterMap OFFSETHEX ACCESS TAG DESCRIPTION 00h RW BMCR BasicModeControlRegister 01h RO BMSR BasicModeStatusRegister 02h RO PHYIDR1 PHYIdentifierRegister1 03h RO PHYIDR2 PHYIdentifierRegister2 04h RW ANAR Auto-NegotiationAdvertisementRegister 05h RO ANLPAR Auto-NegotiationLinkPartnerAbilityRegister 06h RO ANER Auto-NegotiationExpansionRegister 07h RW ANNPTR Auto-NegotiationNextPageTX 08h RO ANLNPTR Auto-NegotiationLinkPartnerAbilityNextPageRegister 09h RW CR1 ControlRegister1 0Ah RW CR2 ControlRegister2 0Bh RW CR3 ControlRegister3 0Ch RW RESERVED RESERVED 0Dh RW REGCR Registercontrolregister 0Eh RW ADDAR AddressorDataregister 0Fh RW RESERVED RESERVED 0x0010 RO PHYSTS PHYStatusRegister 0x0011 RW PHYSCR PHYSpecificControlRegister 0x0012 RW MISR1 MIIInterruptStatusRegister1 0x0013 RW MISR2 MIIInterruptStatusRegister2 0x0014 RO FCSCR FalseCarrierSenseCounterRegister 0x0015 RO RECR ReceiveErrorCountRegister 0x0016 RW BISCR BISTControlRegister 0x0017 RO RBR RMIIandStatusRegister 0x0018 RW LEDCR LEDControlRegister 0x0019 RW PHYCR PHYControlRegister 0x001A RW 10BTSCR 10Base-TStatus/ControlRegister 0x001B RW BICSR1 BISTControlandStatusRegister1 0x001C RO BICSR2 BISTControlandStatusRegister2 0x001D RW RESERVED RESERVED 0x001E RW CDCR CableDiagnosticControlRegister 0x001F RW PHYRCR PHYResetControlRegister EXTENDEDREGISTERS 0x0020-0x0026 RW RESERVED RESERVED 0x0027 RW COMPTR ComplianceTestregister 0x0028-0x0041 RW RESERVED RESERVED 0x0042 RO TXCPSR TX_CLKPhaseShiftRegister 0x0043-0x00AD RW RESERVED RESERVED 0x00AE RW PWRBOCR PowerBackOffControlRegister 0x00AF-0x00CF RW RESERVED RESERVED 0x00D0 RW VRCR VoltageRegulatorControlRegister 0x00D1-0x0154 RW RESERVED RESERVED 0x0155 RW ALCDRR1 ALCDControlandResults1 0x0156-0x016F RW RESERVED RESERVED 0x0170 RW CDSCR1 CableDiagnosticSpecificControlRegister1 38 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table8-1.RegisterMap(continued) OFFSETHEX ACCESS TAG DESCRIPTION 0x0171 RW CDSCR2 CableDiagnosticSpecificControlRegister2 0x0172 RW RESERVED RESERVED 0x0173 RW CDSCR3 CableDiagnosticSpecificControlRegister3 0x0174-0x0176 RW RESERVED RESERVED 0x0177 RW CDSCR4 CableDiagnosticSpecificControlRegister4 0x0178-0x017F RW RESERVED RESERVED 0x0180 RO CDLRR1 CableDiagnosticLocationResultRegister1 0x0181 RO CDLRR2 CableDiagnosticLocationResultRegister2 0x0182 RO CDLRR3 CableDiagnosticLocationResultRegister3 0x0183 RO CDLRR4 CableDiagnosticLocationResultRegister4 0x0184 RO CDLRR5 CableDiagnosticLocationResultRegister5 0x0185 RO CDLAR1 CableDiagnosticAmplitudeResultRegister1 0x0186 RO CDLAR2 CableDiagnosticAmplitudeResultRegister2 0x0187 RO CDLAR3 CableDiagnosticAmplitudeResultRegister3 0x0188 RO CDLAR4 CableDiagnosticAmplitudeResultRegister4 0x0189 RO CDLAR5 CableDiagnosticAmplitudeResultRegister5 0x018A RW CDGRR CableDiagnosticGeneralResultRegister 0x018B-0x0214 RW RESERVED RESERVED 0x0215 RW ALCDRR2 ALCDControlandResults2Register Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 39 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-2.RegisterTable RegisterName Addr Tag Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BasicModeControl 00h BMCR Reset Loopback Speed Auto-Neg IEEE Isolate Restart Duplex Collision Reserved Register Selection Enable Power Auto-Neg Mode Test Down BasicModeStatus 01h BMSR 100Base- 100Base- 100Base- 10Base-T 10Base-T Reserved MF Auto-Neg Remote Auto-Neg LinkStatus Jabber Extended Register T4 TXFDX TXHDX FDX HDX Preamble Complete Fault Ability Detect Capability Suppress PHYIdentifier 02h PHYIDR1 OUIMSB Register1 PHYIdentifier 03h PHYIDR2 OUILSB VNDR_MDL MDL_REV Register2 Auto-Negotiation 04h ANAR NextPage Reserved Remote Reserved ASM_DIR PAUSE 100B-T4 100B- 100B-TX 10B-T_FD 10B-T ProtocolSelection[4:0] Advertisement Ind Fault TX_FD Register Auto-NegotiationLink 05h ANLPAR NextPage ACK Remote Reserved ASM_DIR PAUSE 100B-T4 100B- 100B-TX 10B-T_FD 10B-T ProtocolSelection[4:0] PartnerAbility Ind Fault TX_FD Register(BasePage) Auto-Negotiation 06h ANER Reserved PDF LP_NP_ NP_ABLE PAGE_RX LP_AN_AB ExpansionRegister ABLE LE Auto-NegotiationNext 07h ANNPTR NextPage Reserved Message ACK2 TOG_TX CODE PageTXRegister Ind Page Auto-NegotiateLink 08h ANLNPTR NextPage Reserved Message ACK2 Toggle CODE PartnerAbilityPage Ind Page Register ControlRegister1 09h CR1 Reserved RMII TDRAuto LinkLoss FastAuto Robust FastAN FastANSelect FastRXDV Reserved Enhance Run Recovery MDI/X AutoMDI/X Enable Detect Mode ControlRegister2 0Ah CR2 Reserved FastLink- Extended Enhance IsolateMII RXERR OddNibble RMII UpinPD FDAbility LEDLink in100BT During Detect Receive HD IDLE Disable Clock ControlRegister3 0Bh CR3 Reserved Polarity MDI/X Reserved FastLinkDownSel Swap Swap RESERVED 0Ch Reserved Reserved RegisterControl 0Dh REGCR Function Reserved DEVICEADDRESS Register AddressorData 0Eh ADDAR Addr/Data Register RESERVED 0Fh Reserved Reserved False MDI-X ReceiveErr Polarity Signal Descramb Page MII Remote Jabber Auto-Neg Loopback Duplex Speed PHYStatusRegister 10h PHYSTS Reserved CarrierSen LinkStatus Mode Latch Status Detect Lock Receive Interrupt Fault Detect Status Status Status Status Latch Power PHYSpecificControl Disable Scrambler COLFD 11h PHYSCR Save PowerSaveMode Reserved LoopbackFifoDepth Reserved INTPOL TINT INT_EN INT_OE Register PLL Bypass Enable Enable MIIInterruptStatus LinkStatus Duplex Auto-Neg LinkStatus Duplex Auto-Neg 12h MISR1 Reserved SpeedINT FCHFINT REHFINT Reserved SpeedEN FCHFEn REHFEn Register1 INT ModeINT CompINT En ModeEn CompEn Page Loopback MDI Page Loopback MDI MIIInterruptStatus Auto-Neg Sleep Auto-Neg Sleep 13h MISR2 Reserved Received FIFOO/U Crossover PolarityINT JabberINT Reserved Received FIFOO/U Crossover PolarityEN JabberEN Register2 ErrorINT ModeINT ErrorEN ModeEN INT INT INT EN EN EN MIIInterruptControl 14h FCSCR Reserved FCSCount Register 40 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table8-2.RegisterTable (continued) RegisterName Addr Tag Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ReceiveError 15h RECR RXErrCount CounterRegister PRBS Generate PRBS PRBS Transmitin PacketGen PacketGen Power BISTControlRegister 16h BISCR Reserved Count PRBS Checker Checker Reserved MII Reserved LoopbackMode Enable Status Mode Mode Packets Lock SyncLoss Loopback RMIIControl,Status RMII RMIIOVF RMIIUNF 17h RCSR Reserved RMIIMode ELASTBUF Register Revision Status Status LED Activity LEDSpeed LEDLink DriveLED DriveLED DriveLED SpeedLED LinkLED LEDControlRegister 18h LEDCR Reserved BlinkRate Activity LED Polarity Polarity Speed Link Activity ON/OFF ON/OFF Polarity ON/OFF Bypass AutoMDI/X Force PauseRX PauseTX MILink PHYControlRegister 19h PHYCR Reserved LED LEDCFG PHYADDR Enable MDI/X Status Status Status Stretching BISTPacketLength Receiver NLP Polarity Jabber 1Ah 10BTSCR Reserved Squelch Reserved Reserved Reserved register TH Disable Status Disable BISTControl,Status 1Bh BICSR1 BISTErrCount BISTIPGLength Register1 BISTControl,Status 1Ch BICSR2 Reserved PacketLength Register2 CableDiagnostic Diagnostic Diagnostic Diagnostic 1Eh CDCR Reserved LinkQuality LinkQuality Reserved ControlRegister Start Done Fail Software Software PowerDownRegister 1Fh PDR Reserved Reset Restart space Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 41 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-3.RegisterTable,ExtendedRegisters RegisterName Addr Tag Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ComplianceTest TestMode 27h COMPTR Reserved TestConfiguration register Select PhaseShift TX_CLK 42h TXCPSR Reserved PhaseShiftValue En VoltageRegulator D0h VRCR VRPD Reserved ControlRegister ALCDControland 155h ALCDRR1 alcd_start Reserved alcd_done alcd_out1 Reserved alcd_ctrl Results1 PowerBackOff AEh PWRBOCR Reserved PowerBackOff Reserved ControlRegister CableDiagnostic Cross TPTD TPRD SpecificControl 170h CDSCR1 Reserved Reserved AverageCycles Reserved Disable Bypass Bypass Register1 CableDiagnostic SpecificControl 171h CDSCR2 Reserved TDRpulsecontrol Register2 CableDiagnostic SpecificControl 173h CDSCR3 Cablelength Reserved Register3 CableDiagnostic SpecificControl 177h CDSCR4 ShortcablesTH Reserved Register4 CableDiagnostic 180h CDLRR1 LocationResults Register1-5 181h CDLRR2 182h CDLRR3 TPTD/RDPeakLocation 183h CDLRR4 184h CDLRR5 185h CDLAR1 186h CDLAR2 CableDiagnostic AmplitudeResults 187h CDLAR3 Reserved TPTD/RDPeakAmplitude Reserved TPTD/RDPeakAmplitude Register1-5 188h CDLAR4 189h CDLAR5 CableDiagnostic Cross Cross Above5 Above5 TPTDPeak TPTDPeak TPTDPeak TPTDPeak TPTDPeakTPRDPeakTPRDPeakTPRDPeakTPRDPeakTPRDPeak GeneralResults 18Ah CDGRR Detecton Detecton TPTD TPTD Reserved Reserved Polarity5 Polarity4 Polarity3 Polarity2 Polarity1 Polarity5 Polarity4 Polarity3 Polarity2 Polarity1 Register TPTD TPRD Peaks Peaks ALCDControland 215h ALCDRR2 alcd_out2 alcd_out3 Results2Register 42 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1 Register Definition Intheregisterdefinitionsunderthe‘Default’heading,thefollowingdefinitionsholdtrue: • COR=ClearonRead • Pin_Strap=Defaultvalueloadsfromstrappingpinafterreset • LH=LatchedHighandhelduntilread,basedupontheoccurrenceofthecorrespondingevent • LL=LatchedLowandhelduntilread,basedupontheoccurrenceofthecorrespondingevent • RO=ReadOnlyaccess • RO/COR=ReadOnly,ClearonRead • RO/P=ReadOnly,Permanentlysettoadefaultvalue • RW=ReadWriteaccess • RW/SC=ReadWriteAccess/SelfClearingbit • SC=RegistersetsoneventoccurrenceandSelf-Clearswheneventends 8.1.1 Basic Mode Control Register (BMCR) Table8-4.BasicModeControlRegister(BMCR),address0x0000 BIT BITNAME DEFAULT DESCRIPTION 15 Reset 0,RW/SC PHYSoftwareReset: 1= InitiatesoftwareReset/ResetinProcess 0= Normaloperation Writinga1tothisbitresetsthePHY.Whentheresetoperationisdone,thisbitisclearedto 0automatically.Theconfigurationisrelatched. 14 MIILoopback 0,RW MIILoopback: 1= MIILoopbackenabled 0= Normaloperation WhenMIIloopbackmodeisactivated,thetransmitterdatapresentedonMIITXDislooped backtoMIIRXDinternally. 13 SpeedSelection 1,RW SpeedSelect: Whenauto-negotiationisdisabledwritingtothisbitallowstheportspeedtobeselected. 1= 100Mbs 0= 10Mbs 12 Auto-Negotiation 1,RW Auto-NegotiationEnable: Enable 1= Auto-NegotiationEnabled–bits8and13ofthisregisterareignoredwhenthisbitis set. 0= Auto-NegotiationDisabled–bits8and13determinetheportspeedandduplex mode. 11 IEEEPower 0,RW PowerDown: Down 1= EnablesIEEEpowerdownmode 0= Normaloperation SettingthisbitpowersdownthePHY.Onlyminimalregisterfunctionalityisenabledduring thepowerdowncondition.Tocontrolthepowerdownmechanism,thisbitisORedwiththe inputfromtheINT/PWDNpin.WhentheactivelowINT/PWDNisasserted,thisbitisset. 10 Isolate 0,RW Isolate: 1= IsolatesthePortfromtheMIIwiththeexceptionoftheserialmanagement 0= Normaloperation Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 43 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-4.BasicModeControlRegister(BMCR),address0x0000(continued) BIT BITNAME DEFAULT DESCRIPTION 9 RestartAuto- 0,RW/SC RestartAuto-Negotiation: Negotiation 1= RestartAuto-Negotiation.Re-initiatestheAuto-Negotiationprocess.IfAuto- Negotiationisdisabled(bit12=0),thisbitisignored.Thisbitisself-clearingandwill returnavalueof1untilAuto-Negotiationisinitiated,whereuponitwillself-clear. OperationoftheAuto-Negotiationprocessisnotaffectedbythemanagemententity clearingthisbit. 0= Normaloperation Re-initiatestheAuto-Negotiationprocess.IfAuto-Negotiationisdisabled(bit12=0),thisbit isignored.Thisbitisself-clearingandwillreturnavalueof1untilAuto-Negotiationis initiated,whereuponitself-clears.OperationoftheAuto-Negotiationprocessisnotaffected bythemanagemententityclearingthisbit. 8 DuplexMode 1,Pin_Strap DuplexMode: Whenauto-negotiationisdisabledwritingtothisbitallowstheportDuplexcapabilitytobe selected. 1= FullDuplexoperation ledcontrol 0= HalfDuplexoperation 7 CollisionTest 0,RW CollisionTest: 1= Collisiontestenabled 0= Normaloperation Whenset,thisbitcausestheCOLsignaltobeassertedinresponsetotheassertionof TX_ENwithin512bittimes.TheCOLsignalisde-assertedwithin4bittimesinresponseto thede-assertionofTX_EN. 6:0 RESERVED 0,RO RESERVED:Writeignored,readas0. 44 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.2 Basic Mode Status Register (BMSR) Table8-5.BasicModeStatusRegister(BMSR),address0x0001 BIT BITNAME DEFAULT DESCRIPTION 15 100Base-T4 0,RO/P 100Base-T4Capable: Thisprotocolisnotavailable.Always0=Devicedoesnotperform100Base-T4mode. 14 100Base-TX 1,RO/P 100Base-TXFullDuplexCapable: FullDuplex 1= Deviceabletoperform100Base-TXinfullduplexmode 0= Devicenotabletoperform100Base-TXinfullduplexmode 13 100Base-TX 1,RO/P 100Base-TXHalfDuplexCapable: HalfDuplex 1= Deviceabletoperform100Base-TXinhalfduplexmode 0= Devicenotabletoperform100Base-TXinhalfduplexmode 12 10Base-T 1,RO/P 10Base-TFullDuplexCapable: FullDuplex 1= Deviceabletoperform10Base-Tinfullduplexmode 0= Devicenotabletoperform10Base-Tinfullduplexmode 11 10Base-THalf 1,RO/P 10Base-THalfDuplexCapable: Duplex 1= Deviceabletoperform10Base-Tinhalfduplexmode 0= Devicenotabletoperform10Base-Tinhalfduplexmode 10:7 RESERVED 0,RO RESERVED:Writeas0,readas0 6 MFPreamble 1,RO/P PreamblesuppressionCapable: Suppression 1= Deviceabletoperformmanagementtransactionwithpreamblesuppressed,32-bitsof preambleneededonlyonceafterreset,invalidopcodeorinvalidturnaround. 0= Devicewillnotperformmanagementtransactionwithpreamblessuppressed 5 Auto- 0,RO Auto-NegotiationComplete: Negotiation 1= Auto-Negotiationprocesscomplete Complete 0= Auto-Negotiationprocessnotcomplete(eitherstillinprocess,disabled,orreset) 4 RemoteFault 0,RO/LH RemoteFault: 1= RemoteFaultconditiondetected(clearedonreadorbyreset).Faultcriteria:FarEndFault IndicationornotificationfromLinkPartnerofRemoteFault. 0= Noremotefaultconditiondetected 3 Auto- 1,RO/P AutoNegotiationAbility: Negotiation 1= DeviceisabletoperformAuto-Negotiation Ability 0= DeviceisnotabletoperformAuto-Negotiation 2 LinkStatus 0,RO/LL LinkStatus: 1= Validlinkestablished(foreither10or100Mbsoperation) 0= Linknotestablished 1 JabberDetect 0,RO/LH JabberDetect:Thisbitonlyhasmeaningin10Mbsmode. 1= Jabberconditiondetected 0= NoJabber.conditiondetected Thisbitisimplementedwithalatchingfunction,suchthattheoccurrenceofajabbercondition causesittosetuntilitisclearedbyareadtothisregisterbythemanagementinterfaceorbya reset. 0 Extended 1,RO/P ExtendedCapability: Capability 1= Extendedregistercapabilities 0= Basicregistersetcapabilitiesonly Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 45 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.3 PHY Identifier Register 1 (PHYIDR1) The PHY Identifier Registers 1 and 2 together form a unique identifier for the TLK10x. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. The Texas Instruments IEEE-assigned OUI is 080028h, implemented as Reg 0x2 [15:0] = OUI[21:6] = 2000(h) and Reg0x3[15:10]=OUI[5:0]=A(h). Table8-6.PHYIdentifierRegister1(PHYIDR1),address0x0002 BIT BITNAME DEFAULT DESCRIPTION 15:0 OUI_MSB 0010000000000000, OUI[21:6]=2000(h):ThemostsignificanttwobitsoftheOUIareignored(theIEEE RO/P standardreferstotheseasbits1and2). 8.1.4 PHY Identifier Register 2 (PHYIDR2) Table8-7.PHYIdentifierRegister2(PHYIDR2),address0x0003 BIT BITNAME DEFAULT DESCRIPTION 15:10 OUI_LSB 101000,RO/P OUI[5:0]=28(h) 9:4 VNDR_MDL 100001,RO/P VendorModelNumber: Thesixbitsofvendormodelnumberaremappedfrombits9to4(mostsignificantbittobit9). 3:0 MDL_REV 0001,RO/P ModelRevisionNumber: Fourbitsofthevendormodelrevisionnumberaremappedfrombits3to0(mostsignificantbitto bit3).Thisfieldisincrementedforallmajordevicechanges. 46 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.5 Auto-Negotiation Advertisement Register (ANAR) Thisregistercontainstheadvertisedabilitiesofthisdeviceastheyaretransmittedtoitslinkpartnerduring Auto-Negotiation. Table8-8.AutoNegotiationAdvertisementRegister(ANAR),address0x0004 BIT BITNAME DEFAULT DESCRIPTION 15 NP 0,RW NextPageIndication: 0= NextPageTransfernotdesired 1= NextPageTransferdesired 14 RESERVED 0,RO/P RESERVEDbyIEEE:Writesignored,Readas0 13 RF 0,RW RemoteFault: 1= AdvertisesthatthisdevicehasdetectedaRemoteFault 0= NoRemoteFaultdetected 12 RESERVED 0,RW RESERVEDforFutureIEEEuse:Writeas0,Readas0 11 ASM_DIR 0,RW AsymmetricPAUSESupportforFullDuplexLinks:TheASM_DIRbitindicatesthatasymmetric PAUSEissupported. 1= AsymmetricPAUSEimplemented.AdvertisethattheDTE/MAChasimplementedboththe optionalMACcontrolsublayerandthepausefunctionasspecifiedinclause31andannex31B ofIEEE802.3u. 0= AsymmetricPAUSEnotimplemented EncodingandresolutionofPAUSEbitsisdefinedinIEEE802.3Annex28B,Tables28B-2and28B- 3,respectively.PauseresolutionstatusisreportedinPHYCR[13:12]. 10 PAUSE 0,RW PAUSESupportforFullDuplexLinks:ThePAUSEbitindicatesthatthedeviceiscapableof providingthesymmetricPAUSEfunctionsasdefinedinAnnex31B. 1= MACPAUSEimplemented.AdvertisethattheDTE(MAC)hasimplementedboththeoptional MACcontrolsub-layerandthepausefunctionasspecifiedinclause31andannex31Bof 802.3u. 0= MACPAUSEnotimplemented EncodingandresolutionofPAUSEbitsisdefinedinIEEE802.3Annex28B,Tables28B-2and28B- 3,respectively.PauseresolutionstatusisreportedinPHYCR[13:12]. 9 100B-T4 0,RO/P 100Base-T4Support: 1= 100Base-T4issupportedbythelocaldevice 0= 100Base-T4notsupported 8 100B-TX_FD 1,RW 100Base-TXFullDuplexSupport: 1= 100Base-TXFullDuplexissupportedbythelocaldevice 0= 100Base-TXFullDuplexnotsupported 7 100B-TX 1,RW 100Base-TXSupport: 1= 100Base-TXissupportedbythelocaldevice 0= 100Base-TXnotsupported 6 10B-T_FD 1,RW 10Base-TFullDuplexSupport: 1= 10Base-TFullDuplexissupportedbythelocaldevice 0= 10Base-TFullDuplexnotsupported 5 10B-T 1,RW 10Base-TSupport: 1= 10Base-Tissupportedbythelocaldevice 0= 10Base-Tnotsupported 4:0 Selector 00001,RW ProtocolSelectionBits: Thesebitscontainthebinaryencodedprotocolselectorsupportedbythisport.<00001>indicatesthat thisdevicesupportsIEEE802.3u. Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 47 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The contentchangesafterthesuccessfulauto-negotiationifNext-pagesaresupported. Table8-9.Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR)(BASEPage),address0x0005 BIT BITNAME DEFAULT DESCRIPTION 15 NP 0,RO NextPageIndication: 0= LinkPartnerdoesnotdesireNextPageTransfer 1= LinkPartnerdesiresNextPageTransfer 14 ACK 0,RO Acknowledge: 1= LinkPartneracknowledgesreceptionoftheabilitydataword 0= Notacknowledged.TheAuto-Negotiationstatemachinewillautomaticallycontrolthethisbit basedontheincomingFLPbursts. 13 RF 0,RO RemoteFault: 1= RemoteFaultindicatedbyLinkPartner 0= NoRemoteFaultindicatedbyLinkPartner 12 RESERVED 0,RO RESERVEDforFutureIEEEuse:Writeas0,readas0 11 ASM_DIR 0,RO ASYMMETRICPAUSE: 1= AsymmetricpauseissupportedbytheLinkPartner 0= AsymmetricpauseisnotsupportedbytheLinkPartner 10 PAUSE 0,RO PAUSE: 1= PausefunctionissupportedbytheLinkPartner 0= PausefunctionisnotsupportedbytheLinkPartner 9 100B-T4 0,RO 100Base-T4Support: 1= 100Base-T4issupportedbytheLinkPartner 0= 100Base-T4isnotsupportedbytheLinkPartner 8 100B-TX_FD 0,RO 100Base-TXFullDuplexSupport: 1= 100Base-TXFullDuplexissupportedbytheLinkPartner 0= 100Base-TXFullDuplexisnotsupportedbytheLinkPartner 7 100B-TX 0,RO 100Base-TXSupport: 1= 100Base-TXissupportedbytheLinkPartner 0= 100Base-TXisnotsupportedbytheLinkPartner 6 10B-T_FD 0,RO 10Base-TFullDuplexSupport: 1= 10Base-TFullDuplexissupportedbytheLinkPartner 0= 10Base-TFullDuplexisnotsupportedbytheLinkPartner 5 10B-T 0,RO 10Base-TSupport: 1= 10Base-TissupportedbytheLinkPartner 0= 10Base-TisnotsupportedbytheLinkPartner 4:0 Selector 00000,RO ProtocolSelectionBits: LinkPartner’sbinaryencodedprotocolselector. 48 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.7 Auto-Negotiate Expansion Register (ANER) ThisregistercontainsadditionalLocalDeviceandLinkPartnerstatusinformation. Table8-10.Auto-NegotiateExpansionRegister(ANER),address0x0006 BIT BITNAME DEFAULT DESCRIPTION 15:5 RESERVED 0,RO RESERVED:Writesignored,Readas0. 4 PDF 0,RO ParallelDetectionFault: 1= FaultdetectedviatheParallelDetectionfunction 0= Nofaultdetected 3 LP_NP_ABLE 0,RO LinkPartnerNextPageAble: 1= LinkPartnerdoessupportNextPage 0= LinkPartnerdoesnotsupportNextPage 2 NP_ABLE 1,RO/P NextPageAble: 1= IndicateslocaldeviceisabletosendadditionalNextPages 0= IndicateslocaldeviceisnotabletosendadditionalNextPages 1 PAGE_RX 0,RO/COR LinkCodeWordPageReceived: 1= LinkCodeWordhasbeenreceived,clearedonaread 0= LinkCodeWordhasnotbeenreceived 0 LP_AN_ABLE 0,RO LinkPartnerAuto-NegotiationAble: 1= indicatesthattheLinkPartnersupportsAuto-Negotiation 0= indicatesthattheLinkPartnerdoesnotsupportAuto-Negotiation Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 49 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto- Negotiation. Table8-11.Auto-NegotiationNextPageTransmitRegister(ANNPTR),address0x0007 BIT BITNAME DEFAULT DESCRIPTION 15 NP 0,RW NextPageIndication: 0= NootherNextPageTransferdesired 1= AnotherNextPagedesired 14 RESERVED 0,RO RESERVED:Writesignored,readas0 13 MP 1,RW MessagePage: 1= MessagePage 0= UnformattedPage 12 ACK2 0,RW Acknowledge2: 1= Willcomplywithmessage 0= Cannotcomplywithmessage Acknowledge2isusedbythenextpagefunctiontoindicatethatLocalDevicehastheability tocomplywiththemessagereceived. 11 TOG_TX 0,RO Toggle: 1= ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas0 0= ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas1 ToggleisusedbytheArbitrationfunctionwithinAuto-NegotiationtosynchronizewiththeLink PartnerduringNextPageexchange.ThisbitalwaystakestheoppositevalueoftheToggle bitinthepreviouslyexchangedLinkCodeWord. 10:0 CODE 00000000001, Thisfieldrepresentsthecodefieldofthenextpagetransmission.IftheMPbitisset(bit13of RW thisregister),thenthecodeisinterpretedasaMessagePage,asdefinedinannex28Cof IEEE802.3u.Otherwise,thecodeisinterpretedasanUnformattedPage,andthe interpretationisapplicationspecific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. 50 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) This register contains the next page information sent by this device to its Link Partner during Auto- Negotiation. Table8-12.Auto-NegotiationLinkPartnerAbilityRegisterNextPage(ANLNPTR),address0x0008 BIT BITNAME DEFAULT DESCRIPTION 15 NP 0,RO NextPageIndication: 1= NootherNextPageTransferdesired 0= AnotherNextPagedesired 14 ACK 0,RO Acknowledge: 1= LinkPartneracknowledgesreceptionoftheabilitydataword 0= Notacknowledged TheAuto-NegotiationstatemachineautomaticallycontrolsthisbitbasedontheincomingFLP bursts.Softwareshouldnotattempttowritetothisbit. 13 MP 1,RO MessagePage: 1= MessagePage 0= UnformattedPage 12 ACK2 0,RO Acknowledge2: 1= LinkPartnerhastheabilitytocomplytonext-pagemessage 0= LinkPartnercannotcomplytonext-pagemessage Acknowledge2isusedbythenextpagefunctiontoindicatethatLocalDevicehastheabilityto complywiththemessagereceived. 11 Toggle 0,RO Toggle: 1= ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas0 0= ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas1 ToggleisusedbytheArbitrationfunctionwithinAuto-NegotiationtosynchronizewiththeLink PartnerduringNextPageexchange.ThisbitalwaystakestheoppositevalueoftheTogglebit inthepreviouslyexchangedLinkCodeWord. 10:0 CODE 00000000001,RO Code: Thisfieldrepresentsthecodefieldofthenextpagetransmission.IftheMPbitisset(bit13of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretationisapplicationspecific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 51 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.10 Control register 1 (CR1) Table8-13.Controlregister1(CR1),address0x0009 BIT BITNAME DEFAULT DESCRIPTION 15:10 RESERVED 1,RW RESERVED 9 RMII 0,RW RMIIEnhancedMode: Enhanced 1= EnableRMIIEnhancedMode Mode 0= RMIIoperatesinnormalmode Innormalmode,IfthelineisnotidleCRS_DVgoeshigh.AssoonastheFalseCarrieris detected,RX_ERisassertedandRXDissetto“2”.Thissituationremainsfortheduration ofthereceiveevent.Whileinenhancedmode,CRS_DVisdisqualifiedandde-asserted whentheFalseCarrierdetected.Thisstatusalsoremainsforthedurationofthereceive event.Inadditioninnormalmode,thestartofthepacketisintact.Eachsymbolerroris indicatedbysettingRX_ERhigh.ThedataonRXDisreplacedwith“1”startingwiththe firstsymbolerror.Whileinenhancedmode,theCRS_DVisde-assertedwiththefirst symbolerror. 8 TDR 0,RW TDRAutoRunatlinkdown: AUTORUN 1= EnableexecutionofTDRprocedureafterlinkdownevent 0= DisableautomaticexecutionofTDR 7 LinkLoss 0,RW LinkLossRecovery: Recovery 1= EnableLinkLossRecoverymechanism.Thismodeallowrecoveryfromshort interferenceandcontinuetoholdthelinkupforperiodofadditionalfewmSectill theshortinterferencewillgoneandthesignalisOK. 0= NormalLinkLossoperation.Linkstatuswillgodownapproximately250µsfrom signalloss. 6 FastAuto 0,RW FastAutoMDI/MDIX: MDI-X 1= EnableFastAutoMDI/MDIXmode 0= NormalAutoMDI/MDIXmode. IfbothlinkpartnersareconfiguredtoworkinForce100Base-TXmode(Auto-Negotiation isdisabled),thismodeenablesAutomaticMDI/MDIXresolutioninashorttime. 5 RobustAuto 0,RW RobustAutoMDI-X: MDI-X 1= EnableRobustAutoMDI/MDIXresolution 0= NormalAutoMDI/MDIXmode IflinkpartnersareconfiguredtooperationalmodesthatarenotsupportedbynormalAuto MDI/MDIXmode(likeAuto-NegversusForce100Base-TXorForce100Base-TXversus Force100Base-TX),thisRobustAutoMDI/MDIXmodeallowsMDI/MDIXresolutionand preventsdeadlock. 4 FastANEn 0,RW FastANEn: 1= EnableFastAuto-Negotiationmode–ThePHYauto-negotiatesusingTimer settingaccordingtoFastANSelbits(bits3:2thisregister) 0= DisableFastAuto-Negotiationmode–ThePHYauto-negotiatesusingnormal Timersetting AdjustingthesebitsreducesthetimeittakestoAuto-negotiatebetweentwoPHYs.Note: Whenusingthisoptioncaremustbetakentomaintainproperoperationofthesystem. Whileshorteningthesetimerintervalsmaynotcauseproblemsinnormaloperation,there arecertainsituationswherethismayleadtoproblems. 52 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table8-13.Controlregister1(CR1),address0x0009(continued) BIT BITNAME DEFAULT DESCRIPTION 3:2 FastANSel 0,RW FastAuto-NegotiationSelectbits: FastAN Break LinkFail Auto-NegWaitTimer Select Link Inhibit Timer Timer <00> 80 50 35 <01> 120 75 50 <10> 240 150 100 <11> NA NA NA AdjustingthesebitsreducesthetimeittakestoAuto-negotiatebetweentwoPHYs.In FastANmode,bothPHYsshouldbeconfiguredtothesameconfiguration.These2bits definethedurationforeachstateoftheAutoNegotiationprocessaccordingtothetable above.Thenewdurationtimemustbeenabledbysetting“FastANEn”-bit4ofthis register.Note:Usingthismodeincaseswherebothlinkpartnersarenotconfiguredto thesameFastAuto-negotiationconfigurationmightproducescenarioswithunexpected behavior. 1 FastRXDV 0,RW FastRXDVDetection: Detection 1= EnableassertionhighofRX_DVonreceivepacketduetodetectionof/J/symbol only.Ifaconsecutive/K/doesnotappear,RX_ERisgenerated. 0= DisableFastRX_DVdetection.ThePHYoperatesinnormalmode-RX_DV assertionafterdetectionof/J/K/. 0 RESERVED 1,RW RESERVED Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 53 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.11 Control register 2 (CR2) Table8-14. Controlregister2(CR2),address0x000A BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RW RESERVED 14 RESERVED 0,RW RESERVED 13:7 RESERVED 2,RW RESERVED 6 FastLink-Upin 0,RW FastLink-UpinParallelDetectMode: ParallelDetect 1= EnableFastLink-UptimeDuringParallelDetection 0= NormalParallelDetectionlinkestablishment InFastAutoMDI-XandinRobustAutoMDI-Xmodes(bits6and5inregisterCR1),this bitisautomaticallyset. 5 ExtendedFD 0,RW ExtendedFull-DuplexAbility: Ability 1= ForceFull-Duplexwhileworkingwithlinkpartnerinforced100B-TX.Whenthe PHYissettoAuto-NegotiationorForce100B-TXandthelinkpartnerisoperated inForce100B-TX,thelinkisalwaysFullDuplex 0= DisableExtendedFullDuplexAbility.DecisiontoworkinFullDuplexorHalf DuplexmodefollowsIEEEspecification. 4 EnhancedLED 0,RW EnhancedLEDLinkFunctionality: Link 1= LEDLinkisONonlywhenlinkisestablishedin100B-TXFullDuplexmode. 0= LEDLinkisONwhenlinkisestablished. EnablingEnhancedLEDLinkoverridestheLEDblinkingfunctionalityofthePHYCR register(0x0019)bit5.TheLinkLEDwillnotblinkforactivitywhenEnhancedLEDLinkis enabled. 3 IsolateMIIin 0,RW IsolateMIIoutputswhenFDLink@100BTisnotachievable: 100BTHD 1= WhenHDlinkestablishedin100B-TXMIIoutputsareisolated 0= NormalMIIoutputsoperation 2 RXERRDuring 1,RW DetectionofReceiveSymbolErrorDuringIDLEState: IDLE 1= EnabledetectionofReceivesymbolerrorduringIDLEstate 0= DisabledetectionofReceivesymbolerrorduringIDLEstate. 1 Odd-Nibble 0,RW DetectionofTransmitError: Detection 1= Disabledetectionoftransmiterrorinodd-nibbleboundary Disable 0= Enabledetectionofde-assertionofTX_ENonanodd-nibbleboundary.Inthiscase TX_ENisextendedbyoneadditionalTX_CLKcycleandbehavesasifTX_ER wereassertedduringthatadditionalcycle. 0 RMIIReceive 0,RW RMIIReceiveClock: Clock 1= RMIIData(RXD[1:0])issampledandreferencedtoRX_CLK 0= RMIIData(RXD[1:0])issampledandreferencedtoXI 54 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.12 Control Register 3 (CR3) Table8-15. Controlregister3(CR3),address0x000B BIT BITNAME DEFAULT DESCRIPTION 15:7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6 Polarity 0,RW PolaritySwap: Swap 1= Normalpolarity 0= Invertedpolarityonbothpairs:TPTD+↔TPTD-,TPRD+↔TPRD- PortMirrorfunction:ToEnableportmirroring,setbit5andthisbithigh. 5 MDI/MDIX 0,RW MDI/MDIXSwap: Swap 1= SwapMDIpairs(ReceiveonTPTDpair,TransmitonTPRDpair) 0= MDIpairsnormal(ReceiveonTPRDpair,TransmitonTPTDpair) PortMirrorfunction:ToEnableportmirroring,setthisbitandbit6high. 4 RESERVED 0,RW RESERVED 3:0 FastLink 0,RW FastLinkDownModes: DownMode Bit3 DropthelinkbasedonRXErrorcountoftheMIIinterface–Whenapredefinednumber of32RXErroroccurrencesina10µsintervalisreached,thelinkwillbedropped. Bit2 DropthelinkbasedonMLT3Errorscount(ViolationoftheMLT3codingintheDSP output)–Whenapredefinednumberof20MLT3Erroroccurrencesina10µsintervalis reached,thelinkwillbedropped. Bit1 DropthelinkbasedonLowSNRThreshold–Whenapredefinednumberof20 Thresholdcrossingoccurrencesina10µsintervalisreached,thelinkwillbedropped. Bit0 DropthelinkbasedonSignal/Energylossindication–WhentheEnergydetector indicatesEnergyLoss,thelinkwillbedropped.Typicalreactiontimeis10µs. TheFastLinkDownfunctionisanORofallthese4options,sothedesignercanenable combinationsoftheseconditions. Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 55 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.13 Extended Register Addressing REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above0x001F)usingindirectaddressing. • REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set. • REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. The address register contents (pointer) remainunchanged. • REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for both reads andwrites,thevalueintheaddressregisterisincremented. • REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the addressregisterremainsunchanged. 8.1.13.1 RegisterControlRegister(REGCR) This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCRalsocontainsselectionbits(15:14)fortheaddressauto-incrementmodeofADDAR. Table8-16.RegisterControlRegister(REGCR),address0x000D BIT BITNAME DEFAULT DESCRIPTION 15:14 Function 0,RW 00=Address 01=Data,nopostincrement 10=Data,postincrementonreadandwrite 11=Data,postincrementonwriteonly 13:5 RESERVED 0,RO RESERVED:Writesignored,readas0. 4:0 DEVAD 0,RW DeviceAddress:Ingeneral,thesebits[4:0]arethedeviceaddressDEVADthatdirectsany accessesofADDARregister(0x000E)totheappropriateMMD.Specifically,theTLK10xusesthe vendorspecificDEVAD[4:0]=“11111”foraccesses.AllaccessesthroughregistersREGCRand ADDARshouldusethisDEVAD.TransactionswithotherDEVADareignored. 8.1.13.2 AddressorDataRegister(ADDAR) This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D)toprovidetheaccessbyindirectread/writemechanismtotheextendedregisterset. Table8-17.DataRegister(ADDAR),address0x000E BIT BITNAME DEFAULT DESCRIPTION 15:0 Addr/data 0,RW IfREGCRregister15:14=00,holdstheMMDDEVAD'saddressregister,otherwiseholdsthe MMDDEVAD'sdataregister 8.1.14 PHY Status Register (PHYSTS) ThisregisterprovidesquickaccesstocommonlyaccessedPHYcontrolstatusandgeneralinformation. Table8-18.PHYStatusRegister(PHYSTS),address0x0010 BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 56 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 Table8-18.PHYStatusRegister(PHYSTS),address0x0010(continued) BIT NAME DEFAULT DESCRIPTION 14 MDI-XMode 0,RO MDI-XmodeasreportedbytheAuto-Negotiationstatemachine: 1= MDIpairsswapped(ReceiveonTPTDpair,TransmitonTPRDpair) 0= MDIpairsnormal(ReceiveonTRDpair,TransmitonTPTDpair) ThisbitwillbeaffectedbythesettingsoftheAMDIX_ENandFORCE_MDIXbitsinthePHYCR register.WhenMDIXisenabled,butnotforced,thisbitwillupdatedynamicallyastheAuto-MDIX algorithmswapsbetweenMDIandMDI-Xconfigurations. 13 ReceiveError 0,RO/LH ReceiveErrorLatch: Latch 1= ReceiveerroreventhasoccurredsincelastreadofRXERCNTregister(0x0015) 0= Noreceiveerroreventhasoccurred ThisbitwillbecleareduponareadoftheRECRregister 12 PolarityStatus 0,RO PolarityStatus: 1= InvertedPolaritydetected 0= CorrectPolaritydetected Thisbitisaduplicationofbit4inthe10BTSCRregister(0x001A).Thisbitwillbecleareduponaread ofthe10BTSCRregister,butnotuponareadofthePHYSTSregister. 11 FalseCarrier 0,RO/LH FalseCarrierSenseLatch: SenseLatch 1= FalseCarriereventhasoccurredsincelastreadofFCSCRregister(0x0014) 0= NoFalseCarriereventhasoccurred ThisbitwillbecleareduponareadoftheFCSRregister. 10 SignalDetect 0,RO/LL SignalDetect: Activehigh100Base-TXunconditionalSignalDetectindicationfromPMD 9 Descrambler 0,RO/LL DescramblerLock: Lock Activehigh100Base-TXDescramblerLockindicationfromPMD Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 57 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-18.PHYStatusRegister(PHYSTS),address0x0010(continued) BIT NAME DEFAULT DESCRIPTION 8 Page 0,RO LinkCodeWordPageReceived: Received 1= AnewLinkCodeWordPagehasbeenreceived.ThisbitisaduplicateofPageReceived(bit1) intheANERregisteranditisclearedonreadoftheANERregister(0x0006). 0= LinkCodeWordPagehasnotbeenreceived. ThisbitwillnotbecleareduponareadofthePHYSTSregister. 7 MIIInterrupt 0,RO MIIInterruptPending: 1= Indicatesthataninternalinterruptispending.Interruptsourcecanbedeterminedbyreadingthe MISRRegister(0x0012).ReadingtheMISRwillclearthisInterruptbitindication. 0= Nointerruptpending 6 RemoteFault 0,RO RemoteFault: 1= RemoteFaultconditiondetected.Faultcriteria:notificationfromLinkPartnerofRemoteFault viaAuto-Negotiation.ClearedonreadofBMSRregister(0x0001)orbyreset. 0= Noremotefaultconditiondetected 5 JabberDetect 0,RO JabberDetect: 1= Jabberconditiondetected.Thisbithasmeaningonlyin10Mb/smode.Thisbitisaduplicateof theJabberDetectbitintheBMSRregister(0x0001). 0= NoJabber ThisbitwillnotbecleareduponareadofthePHYSTSregister. 4 Auto-Neg 0,RO Auto-NegotiationStatus: Status 1= Auto-Negotiationcomplete 0= Auto-Negotiationnotcomplete 3 MIILoopback 0,RO MIILoopback: Status 1= Loopbackactive(enabled) 0= Normaloperation 2 DuplexStatus 0,RO DuplexStatus: 1= Fullduplexmode 0= Halfduplexmode ThisbitindicatesduplexstatusandisdeterminedfromAuto-NegotiationorForcedModes.Therefore,it isonlyvalidifAuto-NegotiationisenabledandcompleteandthereisavalidlinkorifAuto-Negotiation isdisabledandthereisavalidlink. 1 SpeedStatus 0,RO SpeedStatus: 1= 10Mb/smode 0= 100Mb/smode ThisbitindicatesthestatusofthespeedandisdeterminedfromAuto-NegotiationorForcedModes. SpeedStatusisonlyvalidifAuto-Negotiationisenabledandcompleteandthereisavalidlinkorif Auto-Negotiationisdisabledandthereisavalidlink. 0 LinkStatus 0,RO LinkStatus: 1= Validlinkestablished(foreither10or100Mb/soperation).ThisbitisaduplicateoftheLink StatusbitintheBMSRregister(0x0001). 0= Linknotestablished ThisbitwillnotbecleareduponareadofthePHYSTSregister. 58 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.15 PHY Specific Control Register (PHYSCR) This register implements the PHY Specific Control register. This register allows access to general functionalityinsidethePHYtoenableoperationinreducedpowermodesandcontrolinterruptmechanism. Table8-19.PHYSpecificControlRegister(PHYSCR),address0x0011 BIT NAME DEFAULT DESCRIPTION 15 DisablePLL 0,RW DisablePLL: 1= DisableinternalclocksCircuitries 0= Normalmodeofoperation Note:ClockCircuitrycanbedisabledonlyinIEEEpower-downmode 14 PSEnable 0,RW PowerSaveModesEnable: 1= Enablepowersavemodes 0= Normalmodeofoperation 13:12 PSModes 00,RW PowerSaveModes: PowerMode Name Description <00> Normal Normaloperationmode.PHYisfullyfunctional <01> IEEEpower LowPowermodethatshutdownallinternalcircuitry down besideSMIfunctionality. <10> ActiveSleep LowPowerActiveEnergySavingmode thatshutdownallinternalcircuitrybesideSMIandenergy detectfunctionalities.InthismodethePHYsendsNLP every1.4Sectowakeuplink-partner.Automaticpower- upisdonewhenlinkpartnerisdetected. <11> Passive LowPowerEnergySavingmode Sleep thatshutdownallinternalcircuitrybesideSMIandenergy detectfunctionalities.Automaticpower-upisdonewhen linkpartnerisdetected. 11 Scrambler 0,RW ScramblerBypass: Bypass 1= Scramblerbypassenabled 0= Scramblerbypassdisabled 10 RESERVED 0,RO RESERVED:Writesignored,readas0. 9:8 Loopback 01,RW Far-EndLoopbackFIFODepth: FIFODepth 00= 4nibblesFIFO 01= 5nibblesFIFO 10= 6nibblesFIFO 11= 8nibblesFIFO ThisFIFOisusedtoadjustRX(recovered)clockratetoTXclockrate.FIFOdepthneedtobeset basedonexpectedmaximumpacketsizeandclockaccuracy.Defaultvaluesetsto5nibbles. 7:5 RESERVED 000,RO RESERVED:Writesignored,readas0. 4 COLFD 0,RW CollisioninFull-DuplexMode: Enable 1= EnablegeneratingCollisionsignalinginFullDuplex 0= DisableCollisionindicationinFullDuplexmode.CollisionwillbeactiveinHalfDuplexonly. 3 INTPOL 1,RW InterruptPolarity: 1= Steadystate(normaloperation)is1logicandduringinterruptis0logic. 0= Steadystate(normaloperation)is0logicandduringinterruptis1logic. 2 tint 0,RW TestInterrupt: 1= Generateaninterrupt 0= Donotgenerateinterrupt ForcesthePHYtogenerateaninterrupttofacilitateinterrupttesting.Interruptswillcontinuetobe generatedaslongasthisbitremainsset. Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 59 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-19.PHYSpecificControlRegister(PHYSCR),address0x0011(continued) BIT NAME DEFAULT DESCRIPTION 1 INT_EN 0,RW InterruptEnable: 1= Enableeventbasedinterrupts 0= Disableeventbasedinterrupts EnableinterruptdependentontheeventenablesintheMISRregister(0x0012). 0 INT_OE 0,RW InterruptOutputEnable: 1= INT/PWDNisanInterruptOutput 0= INT/PWDNisaPowerDown EnableactivelowinterrupteventsviatheINT/PWDNpinbyconfiguringtheINT/PWDNpinasan output. 8.1.16 MII Interrupt Status Register 1 (MISR1) This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the registerisset,aninterruptwillbegeneratediftheeventoccurs.ThePHYSCRregister(0x0011)bits1and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt isnotenabled. Table8-20.MIIInterruptStatusRegister1(MISR1),address0x0012 BIT NAME DEFAULT DESCRIPTION 15:14 RESERVED 00,RO RESERVED:Writesignored,readas0. 13 LinkStatusChangedINT 0,RO,COR ChangeofLinkStatusinterrupt: 1=Changeoflinkstatusinterruptispending 0=Nochangeoflinkstatus 12 SpeedChangedINT 0,RO,COR ChangeofSpeedStatusinterrupt: 1=Changeofspeedstatusinterruptispending 0=Nochangeofspeedstatus 11 DuplexModeChangedINT 0,RO,COR Changeofduplexstatusinterrupt: 1=Duplexstatuschangeinterruptispending 0=Nochangeofduplexstatus 10 Auto-NegotiationCompletedINT 0,RO,COR Auto-NegotiationCompleteinterrupt: 1=Auto-negotiationcompleteinterruptispending. 0=NoAuto-negotiationcompleteeventispending 9 FCHFINT 0,RO,COR FalseCarrierCounterhalf-fullinterrupt: 1=Falsecarriercounter(RegisterFCSCR,address0x0014)exceedshalf- fullinterruptispending 0=Falsecarriercounterhalf-fulleventisnotpending 8 REHFINT 0,RO,COR ReceiveErrorCounterhalf-fullinterrupt: 1=Receiveerrorcounter(RegisterRECR,address0x0015)exceedshalf fullinterruptispending 0=NoReceiveerrorcounterhalffulleventpending 7:6 RESERVED 00,RO RESERVED:Writesignored,readas0. 5 LinkStatusChangedEN 0,RW EnableInterruptonchangeoflinkstatus 4 SpeedChangedEN 0,RW EnableInterruptonchangeofspeedstatus 3 DuplexModeChangedEN 0,RW EnableInterruptonchangeofduplexstatus 2 Auto-NegotiationCompletedEN 0,RW EnableInterruptonAuto-negotiationcompleteevent 1 FCHFEN 0,RW EnableInterruptonFalseCarrierCounterRegisterhalf-fullevent 0 REHFEN 0,RW EnableInterruptonReceiveErrorCounterRegisterhalf-fullevent 60 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.17 MII Interrupt Status Register 2 (MISR2) This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the registerisset,aninterruptwillbegeneratediftheeventoccurs.ThePHYSCRregister(0x0011)bits1and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt isnotenabled. Table8-21.MIIInterruptStatusRegister2(MISR2),address0x0013 BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14 ANErrorINT 0,RO,COR Auto-NegotiationErrorInterrupt: 1=Auto-negotiationerrorinterruptispending 0=NoAuto-negotiationerroreventpending 13 PageRecINT 0,RO,COR PageReceiveInterrupt: 1=Pagehasbeenreceived 0=Pagehasnotbeenreceived 12 LoopbackFIFOOF/UFINT 0,RO,COR LoopbackFIFOOverflow/UnderflowEventInterrupt: 1=FIFOOverflow/Underfloweventinterruptpending 0=NoFIFOOverflow/Underfloweventpending 11 MDICrossoverChangedINT 0,RO,COR MDI/MDIXCrossoverStatusChangedInterrupt: 1=MDIcrossoverstatuschangedinterruptispending 0=MDIcrossoverstatushasnotchanged 10 SleepModeINT 0,RO,COR SleepModeEventInterrupt: 1=SleepModeeventinterruptispending 0=Nosleepmodeeventpending 9 PolarityChangedINT 0,RO,COR PolarityChangedInterrupt: 1=Datapolaritychangedinterruptpending 0=NoDatapolarityeventpending 8 JabberDetectINT 0,RO JabberDetectEventInterrupt: 1=Jabberdetecteventinterruptpending 0=NoJabberdetecteventpending 7 RESERVED 0,RW RESERVED:Writesignored,readas0 6 ANErrorEN 0,RW EnableInterruptonAuto-Negotiationerrorevent 5 PageRecEN 0,RW EnableInterruptonpagereceiveevent 4 LoopbackFIFOOF/UFEN 0,RW EnableInterruptonloopbackFIFOoverflow/underflowevent 3 MDICrossoverChangedEN 0,RW EnableInterruptonchangeofMDI/Xstatus 2 SleepModeEventEN 0,RW EnableInterruptsleepmodeevent 1 PolarityChangedEN 0,RW EnableInterruptonchangeofpolaritystatus 0 JabberDetectEN 0,RW EnableInterruptonJabberdetectionevent 8.1.18 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the "False Carriers" attribute within the MAU managedobjectclassofClause30oftheIEEE802.3uspecification. Table8-22.FalseCarrierSenseCounterRegister(FCSCR),address0x0014 BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 00000000,RO RESERVED:Writesignored,readas0 7:0 FCSCNT 0,RO/COR FalseCarrierEventCounter: This8-bitcounterincrementsoneveryfalsecarrierevent.Thiscounterstopswhenit reachesitsmaximumcount(FFh).Whenthecounterexceedshalffull(7Fh),aninterrupt eventisgenerated.Thisregisterisclearedonread. Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 61 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.19 Receiver Error Counter Register (RECR) This counter provides information required to implement the "Symbol Error During Carrier" attribute within thePHYmanagedobjectclassofClause30oftheIEEE802.3uspecification. Table8-23.ReceiverErrorCounterRegister(RECR),address0x0015 BIT BITNAME DEFAULT DESCRIPTION 15:0 RXErrorCount 0,RO,/COR RX_ERCounter: Whenavalidcarrierispresent(onlywhileRXDVisset),andthereisatleastoneoccurrenceof aninvaliddatasymbol,this16-bitcounterincrementsforeachreceiveerrordetected.The RX_ERcounterdoesnotcountinMIIloopbackmode.Thecounterstopswhenitreachesits maximumcountofFFFFh.Whenthecounterexceedshalf-full(7FFFh),aninterruptis generated.Thisregisterisclearedonread. 62 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.20 BIST Control Register (BISCR) This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of theexactloopbackpointinthesignalchainisalsodoneinthisregister. Table8-24.BISTControlRegister(BISCR),address0x0016 BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0 14 PRBSCountMode 0,RW PRBSSingle/ContinuesMode: 1= Continuousmode,thePRBScountersreachesmaxcountvalue,pulseis generatedandcounterstartscountingfromzeroagain. 0= Singlemode,WhenBISTErrorCounterreachesitsmaxvalue,PRBSchecker stopscounting. 13 GeneratePRBSPackets 0,RW GeneratedPRBSPackets: 1= Whenpacketgeneratorisenabled,generatecontinuouspacketswithPRBS data.Whenpacketgeneratorisdisabled,PRBScheckerisstillenabled. 0= Whenpacketgeneratorisenabled,generatesinglepacketwithconstantdata. PRBSgen/checkisdisabled. 12 PacketGenerationEnable 0,RW PacketGenerationEnable: 1= EnablepacketgenerationwithPRBSdata 0= Disablepacketgenerator 11 PRBSCheckerLock 0,RO PRBSCheckerLockIndication: 1= PRBScheckerislockedandsyncedonreceivedbitstream 0= PRBScheckerisnotlocked 10 PRBSCheckerSyncLoss 0,RO,LH PRBSCheckerSyncLossIndication: 1= PRBScheckerlosesynconreceivedbitstream–Thisisanerrorindication 0= PRBScheckerisnotlocked 9 PacketGenStatus 0,RO PacketGeneratorStatusIndication: 1= PacketGeneratorisactiveandgeneratepackets 0= PacketGeneratorisoff 8 PowerMode 0,RO SleepModeIndication: 1= IndicatethatthePHYisinnormalpowermode 0= IndicatethatthePHYisinoneofthesleepmodes,eitheractiveorpassive 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6 TransmitinMIILoopback 0,RW TransmitDatainMIILoop-backMode(validonlyat100BT): 1= EnabletransmissionofthedatafromtheMACreceivedontheTXpinstothe lineinparalleltotheMIIloopbacktoRXpins.ThisbitmaybesetonlyinMII Loopbackmode–settingbit14inBMCRregister(0x0000). 0= DataisnottransmittedtothelineinMIIloopback 5 RESERVED 0,RO RESERVED:Mustbe0 4:0 LoopbackMode 0,RW Loop-backModeSelect: ThePHYprovidesseveraloptionsforLoopbackthattestandverifyvariousfunctional blockswithinthePHY.Enablingloopbackmodeallowsin-circuittestingoftheTLK10x digitalandanalogdatapath Near-endLoopback 00001= PCSInputLoopback 00010= PCSOutputLoopback 00100= DigitalLoopback 01000= AnalogLoopback(requires100Ωtermination) Far-endLoopback: 10000= ReverseLoopback Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 63 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.1.21 RMII Control and Status Register (RCSR) ThisregisterconfigurestheRMIIModeofoperation.WhenRMIImodeisdisabled,theRMIIfunctionalityis bypassed. Table8-25.RMIIControlandStatusRegister(RCSR),address0x0017 BIT NAME DEFAULT DESCRIPTION 15:6 RESERVED 0000000000,RO RESERVED:Writesignored,readas0. 5 RMIIMode 0,RW,Pin_Strap RMIIModeEnable:RMIIModeisoperationalifdevicepoweredupinRMIImode (pin_strap)and50Mhzclockpresent.Pleasenote,thatinordertoswitchfromRMIItoMII andviseversa,thePHYmustinitializeafterpowerupinRMIImode(Strapis'1'and REF_CLKis50MHz).IfthePHYinitializesinMIImode,thisbithasnoeffect. 1= EnableRMII(ReducedMII)modeofoperation 0= EnableMIImodeofoperation 4 RMIIRevision 0,RW RMIIRevisionSelect: Select 1= (RMIIrevision1.0)CRS_DVwillremainasserteduntilfinaldataistransferred. CRS_DVwillnottoggleattheendofapacket. 0= (RMIIrevision1.2)CRS_DVwilltoggleattheendofapackettoindicatede- assertionofCRS. 3 RMIIOVFLStatus 0,COR RXFIFOOverFlowStatus: 1= Normal 0= Overflowdetected 2 RMIIOVFLStatus 0,COR RXFIFOUnderFlowStatus: 1= Normal 0= Underflowdetected 1:0 ELAST_BUF 01,RW ReceiveElasticityBufferSize: ThisfieldcontrolstheReceiveElasticityBufferwhichallowsforfrequencyvariation tolerancebetweenthe50MHzRMIIclockandtherecovereddata.Thefollowingvalues indicatethetoleranceinbitsforasinglepacket.Theminimumsettingallowsforstandard Ethernetframesizesat±50ppmaccuracyforbothRMIIandReceiveclocks.Forgreater frequencytolerancethepacketlengthsmaybescaled(for±100ppm,dividethepacket lengthsby2). 00= 14bittolerance(upto16800bytepackets) 01= 2bittolerance(upto2400bytepackets) 10= 6bittolerance(upto7200bytepackets) 11= 10bittolerance(upto12000bytepackets) 64 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.22 LED Control Register (LEDCR) Thisregisterprovidestheabilitytodirectlymanuallycontrol theLinkLEDoutput. Table8-26.LEDControlRegister(LEDCR),address0x0018 BIT NAME DEFAULT DESCRIPTION 15:11 RESERVED 00000,ro RESERVED:Writesignored,readas0. 10:9 BlinkRate 10,RW LEDBlinkingRate(ON/OFFduration): 00=20Hz(50mSec) 01=10Hz(100mSec) 10=5Hz(200mSec) 11=2Hz(500mSec) 8 RESERVED RO RESERVED 7 LEDLinkPolarity 0,RW, LEDLinkPolaritySetting: Pin_Strap 1=ActiveHighpolaritysetting 0=ActiveLowpolaritysetting TheLinkLEDpolarityisdefinedbythestrapvalueofthispin.Ifthepinis strappedhighviaapull-upresistor,theLEDwillbeactivelow.Ifthepinis strappedlowviaapull-downresistor,theLEDwillbeactivehigh.Thisregister allowsoverrideofthestrappingvalue. 6 RESERVED RO RESERVED 5 RESERVED RO RESERVED 4 DriveLinkLED 0,RW DriveLEDLinktotheforcedOn/Offsettingdefinedinbit1: 1=DrivevalueofOn/OffbitontoLED_LINKoutputpin 0=Normaloperation 3 RESERVED RO RESERVED 2 RESERVED RO RESERVED 1 LinkLEDOn/OffSetting 0,RW ValuetoforceonLinkLEDoutput 0 RESERVED RO RESERVED 8.1.23 PHY Control Register (PHYCR) ThisregisterprovidestheabilitytocontrolandsetgeneralfunctionalityinsidethePHY. Table8-27.PHYControlRegister(PHYCR),address0x0019 BIT NAME DEFAULT DESCRIPTION 15 AutoMDI/X 1,RW, Auto-MDIXEnable: Enable Pin_Strap 1=EnableAuto-negotiationAuto-MDIXcapability 0=DisableAuto-negotiationAuto-MDIXcapability 14 ForceMDI/X 0,RW ForceMDIX: 1=ForceMDIpairstocross.(ReceiveonTPTDpair,TransmitonTPRDpair) 0=Normaloperation.(TransmitonTPTDpair,ReceiveonTPRDpair) 13 PauseRX 0,RO PauseReceiveNegotiatedStatus:IndicatesthatpausereceiveshouldbeenabledintheMAC. Status Basedonbits[11:10]inANARregisterandbits[11:10]inANLPARregistersettings. ThisfunctionshallbeenabledaccordingtoIEEE802.3Annex28BTable28B-3,“Pause Resolution”,onlyiftheAuto-NegotiatedHighestCommonDenominatorisafullduplextechnology. 12 PauseTX 0,RO PauseTransmitNegotiatedStatus: Status IndicatesthatpausetransmitshouldbeenabledintheMAC.Basedonbits[11:10]inANARregister andbits[11:10]inANLPARregistersettings. ThisfunctionshallbeenabledaccordingtoIEEE802.3Annex28BTable28B-3,“Pause Resolution”,onlyiftheAuto-NegotiatedHighestCommonDenominatorisafullduplextechnology. 11 MILink 0,RO MIILinkStatus: Status 1=100BTFull-duplexLinkisactiveanditwasestablishedusingAuto-Negotiation 0=Noactivelinkof100BTFull-duplex,establishedusingAuto-Negotiation 10:8 RESERVED 000,RO RESERVED:Writesignored,readas0. 7 BypassLED 0,RW BypassLEDStretching: Stretching 1=BypassLEDstretching 0=NormalLEDoperation Setthisbitto1tobypasstheLEDstretching;theLEDreflectstheinternalvalue. 6 RESERVED RO RESERVED Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 65 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-27.PHYControlRegister(PHYCR),address0x0019(continued) BIT NAME DEFAULT DESCRIPTION 5 LEDCFG 0,RW, LEDConfigurationModes: Pin_Strap Mode LED_CFG LED_LINK ONforGoodLink 1 1 OFFforNoLink ONforGoodLink 2 0 BLINKforActivity 4:0 PHYADDR 00001,RO PHYAddress: StrappingconfigurationforPHYAddress. 8.1.24 10Base-T Status/Control Register (10BTSCR) ThisregisterprovidestheabilitytocontrolandreadstatusofthePHY’sinternal10Base-Tfunctionality. Table8-28.10Base-TStatus/ControlRegister(10BTSCR),address0x001A BIT NAME DEFAULT DESCRIPTION 15:14 RESERVED 000,RO RESERVED:Writesignored,readas0. 13 ReceiverTH 0,RW LowerReceiverThresholdEnable: 1=Enable10Base-Tlowerreceiverthresholdtoallowoperationwithlongercables 0=Normal10Base-Toperation 12:9 Squelch 0000,RW SquelchConfiguration: UsedtosetthePeakSquelch‘ON’thresholdforthe10Base-Treceiver.Everystepisequalto 50mVandallowraising/loweringtheSquelchthresholdfrom200mVto600mV.Thedefault Squelchthresholdissetto200mV. 8 RESERVED 0,RO RESERVED:Writesignored,readas0. 7 NLPDisable 0,RW NLPTransmissionControl: 1=DisabletransmissionofNLPs 0=EnabletransmissionofNLPs 6:5 RESERVED 00,RO RESERVED:Writesignored,readas0. 4 PolarityStatus 0,RO 10MbPolarityStatus: 1=InvertedPolaritydetected 0=CorrectPolaritydetected Thisbitisaduplicationofbit12inthePHYSTSregister(0x0010).Bothbitswillbecleared uponareadof10BTSCRregister,butnotuponareadofthePHYSTSregister. 3:1 RESERVED 000,RO RESERVED:Writesignored,readas0. 0 JabberDisable 0,RW JabberDisable: 1=Jabberfunctiondisabled 0=Jabberfunctionenabled Note:Thisfunctionisapplicableonlyin10Base-T 66 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.1.25 BIST Control and Status Register 1 (BICSR1) This register provides the total number of error bytes that was received by the PRBS checker and defines theInterpacketGap(IPG)forthepacketgenerator. Table8-29.BISTControlandStatusRegister1(BICSR1),address0x001B BIT BITNAME DEFAULT DESCRIPTION 15:8 BISTError 0,RO BISTErrorCount: Count HoldsnumberoferroneousbytesthatwerereceivedbythePRBSchecker.Valueinthis registerislockedwhenwriteisdonetobit[0]orbit[1](seebelow). WhenPRBSCountModesettozero,countstopson0xFF.SeeBISCRregister(0x0016)for furtherdetails Note:Writing“1”tobit15willlockcounter’svalueforsuccessivereadoperationandclearthe BISTErrorCounter. 7:0 BISTIPG 01111101,RW BISTIPGLength: Length InterPacketGap(IPG)Lengthdefinesthesizeofthegap(inbytes)betweenany2successive packetsgeneratedbytheBIST.Defaultvalueis0x7Dwhichisequalto125bytes 8.1.26 BIST Control and Status Register2 (BICSR2) ThisregisterallowsprogrammingthelengthofthegeneratedpacketsinbytesfortheBISTmechanism. Table8-30.BISTControlandStatusRegister2(BICSR2),address0x001C BIT BITNAME DEFAULT DESCRIPTION 15:11 RESERVED 00000,RO RESERVED:Writesignored,readas0. 10:0 BISTPacket 1011101 BISTPacketLength: Length 1100,RW LengthofthegeneratedBISTpackets.Thevalueofthisregisterdefinesthesize(inbytes)of everypacketthatgeneratedbytheBIST.Defaultvalueis0x5DCwhichisequalto1500bytes 8.2 Cable Diagnostic Control Register (CDCR) CableDiagnosticControlRegister(CDCR),address0x001E BIT BITNAME DEFAULT DESCRIPTION 15 DiagnosticStart 0,RW CableDiagnosticProcessStart: 1=Startexecutecablemeasurement 0=CableDiagnosticisdisabled DiagnosticStartbitisclearedwithraiseofDiagnosticDoneindication. 14:10 RESERVED 00000,RO RESERVED:Writesignored,readas0. 9:8 LinkQuality 00,RO LinkQualityIndication 00=Reserved 01=GoodQualityLinkIndication 10=MidQualityLinkIndication 11=PoorQualityLinkIndication Thevalueofthesebitsarevalidonlywhenlinkisactive–Whilereading“1”from“Link Status”bit0onPHYSTSregister(0x0010). 7:4 RESERVED 0000,RO RESERVED:Writesignored,readas0. 3:2 RESERVED 00,RO RESERVED:Writesignored,readas0. 1 DiagnosticDone 0,RO CableDiagnosticProcessDone: 1=Indicationthatcablemeasurementprocesscompleted 0=Diagnostichasnotcompleted 0 DiagnosticFail 0,RO CableDiagnosticProcessFail: 1=Indicationthatcablemeasurementprocessfailed 0=Diagnostichasnotfailed Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 67 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.3 PHY Reset Control Register (PHYRCR) Table8-31.PHYResetControlRegister(PHYRCR),address0x001F BIT BITNAME DEFAULT DESCRIPTION 15 SoftwareReset 0,RW,SC SoftwareReset: 1=ResetPHY.ThisbitisselfclearedandhassameeffectasHardwareresetpin. 0=NormalOperation 14 Software 0,RW,SC SoftwareRestart: Restart 1=ResetPHY.ThisbitisselfclearedandresetsallPHYcircuitryexcepttheregisters. 0=NormalOperation 13:0 RESERVED 0000000000 Writesignored,readas0 0000,RO 68 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.4 Compliance Test register (COMPTR) Thisregisterallowsgenerationoftestpatternsforcompliancetesting. Table8-32.ComplianceTestregister(COMPTR),address0x0027 BIT BITNAME DEFAULT DESCRIPTION 15:6 RESERVED 0000000000, Writesignored,readas0 RO 5 TestMode 0,RW MSBbitfor100Base-TXtestmode.Note:bit4mustbe'0'for100Base-TXtestmodes. Select 4:0 Test 00000,RW Bit4enables10Base-Ttestmodes. Configuration 1=10Base-Ttestmodes 0=100Base-TXtestmodes For10Base-Ttesting,bits[3:0]selectthe10Base-Tpatternasfollows: 0000=SingleNLP 0000=SingleNLP 0001=SinglePulse1 0010=SinglePulse0 0011=Repetitive1 0100=Repetitive0 0101=Preamble(repetitive'10') 0110=Single1followedbyTP_IDLE 0111=Single0followedbyTP_IDLE 1000=Repetitive'1001'sequence 1001=Random10Base-Tdata 1010=TP_IDLE_00 1011=TP_IDLE_01 1100=TP_IDLE_10 1101=TP_IDLE_11 1001=Random10Base-Tdata For100Base-TXtesting,bits{5,[3:0]}selectthetransmitsequence.Thetestmode transmitsarepetitivesequenceconsistingofa'1'followedbyaconfigurablenumberof'0' bits. Bits{5,[3:0]}definethenumberof'0'bitsthatfollowthe'1'.1to31'1'bitsmaybe selected. 0,0001-1,1111:single'0'to31zeroes 0,0000:Cleartheregister Note1:Bit4mustbe'0'for100Base-TXtestmodes. Note2:100Base-Ttestmodesmustbeclearedbeforeapplyinganewvalue.Bits{5,[3:0]} mustbewrittento0x0beforeconfiguringanewvalue. Note3:Whenperforming100Base-TXor10Base-Ttests,thespeedmustbeforcedusing theBasicModeControlRegister(BMCR),address0x0000. 8.5 TX_CLK Phase Shift Register (TXCPSR) This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems, therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value greaterthan10iswritten,theupdatevaluewillbethewrittenvaluemodulo10. Table8-33.TX_CLKPhaseShiftRegister(TXCPSR),address0x0042 BIT BITNAME DEFAULT DESCRIPTION 15:5 RESERVED 00000000 RESERVED:Writesignored,readas0 000,RO 4 PhaseShift 0,RW,SC TXClockPhaseShiftEnable: Enable 1=PerformPhaseShifttotheTX_CLKaccordingtothevaluewrittentoPhaseShiftValueinbits [4:0]. 0=NochangeinTXClockphase Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 69 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com Table8-33.TX_CLKPhaseShiftRegister(TXCPSR),address0x0042(continued) BIT BITNAME DEFAULT DESCRIPTION 3:0 PhaseShift 0000,RW TXClockPhaseShiftValue: Value ThevalueofthisregisterrepresentsthecurrentphaseshiftbetweenReferenceclockatXIandMII TransmitClockatTX_CLK.AnydifferentvaluethatwillbewrittentothesebitswillshiftTX_CLKby4 timesthedifference(innSec). Forexample,ifthevalueofthisregisteris0x2,Writing0x9tothisregistershiftsTX_CLKby28nS(4 times7).However,sincethemaximumdifferencebetweenXIandTX_CLKcouldbe40nSec(valueof 10)incaseofwritingvaluebiggerthan10,theupdatedvalueisthewrittenvaluemodulo10. 8.6 Power Back Off Control Register (PWRBOCR) Table8-34.PowerBackOffControlRegister(PWRBOCR),address0x00AE BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 1,RO RESERVED 14 RESERVED 0,RO RESERVED 13:9 RESERVED 00000,RO RESERVED 8:6 PowerBack 0,RW PowerBackOffLevel:SeeApplicationNoteSLLA328 Off 000=NormalOperation 001=Level1(upto140mcablebetweenTLKlinkpartners) 010=Level2(upto100mcablebetweenTLKlinkpartners) 011=Level3(upto80mcablebetweenTLKlinkpartners) Others=Reserved 5:0 RESERVED 100000,RO RESERVED 8.7 Voltage Regulator Control Register (VRCR) This register gives the host processor the ability to power down the voltage-regulator block of the PHY via register access. This power-down operation is available in systems operating with an external power supply. Table8-35.VoltageRegulatorControlRegister(VRCR),address0x00D0 BIT BITNAME DEFAULT DESCRIPTION 15 VRPD 0,RW,SC VoltageRegulatorPowerDown: 1=PowerDown.AllowthesystemtopowerdownthevoltageregulatorblockofthePHY usingregisteraccess. 0=NormalOperation.VoltageRegulatorispoweredandoutputsvoltageonthePFBOUT pin. 14:0 RESERVED 00000000000,RW RESERVED:Mustbewrittenas0. 8.8 Cable Diagnostic Configuration/Result Registers 8.8.1 ALCD Control and Results 1 (ALCDRR1) Table8-36.ALCDControlandResults1(ALCDRR1),address0x0155 BIT BITNAME DEFAULT DESCRIPTION 15 alcd_start 0,SC 1=StartALCD 14:13 00,RO RESERVED:Writesignored,readas0. 12 alcd_done 0,RO TPTDDiagnosticBypass 1=BypassTPTDdiagnostic.TDRonTPTDpairisnotexecuted. 0=TDRisexecutedonTPTDpair 11:4 alcd_out1 00000000, alcd_out1 RO 3 RESERVED 0,RO RESERVED:Writesignored,readas0 2:0 alcd_ctrl 001,RW ControlofALCDAveragefactor 70 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.8.2 Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4) Use CDSCR1 to select the channel for the cable diagnostics test. CDSCR1 contains the enable and bypass bits for the diagnostic tests, and defines the number of executed and averaged TDR sequences. CDSCR2-CDSCR4configureotherparametersforcablediagnostics. Table8-37.CableDiagnosticSpecificControlRegister(CDSCR),address0x0170 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14 DiagnosticCross 0,RW CrossTDRDiagnosticmode Disable 1=DisableTDRCrossmode–TDRwillbeexecutedinregularmodeonly 0=DiagnosticofcrossingpairsisenabledInCrossDiagnosticmode,theTDRmechanism islookingforreflectionontheotherpairtocheckshortbetweenpairs. 13 DiagnosticTPTD 0,RW TPTDDiagnosticBypass Bypass 1=BypassTPTDdiagnostic.TDRonTPTDpairwillnotbeexecuted. 0=TDRisexecutedonTPTDpair InbypassTPTD,resultsareavailableinTPRDslots. 12 DiagnosticTPRD 0,RO TPRDDiagnosticBypass Bypass 1=BypassTPRDdiagnostic.TDRonTPRDpairwillnotbeexecuted. 0=TDRisexecutedonTPRDpair 11 RESERVED 1,RW RESERVED:MustbeSetto1. 10:8 DiagnosticsAverage 110,RW NumberOfTDRCyclestoAverage: Cycles <000>:1TDRcycle <001>:2TDRcycles <010>:4TDRcycles <011>:8TDRcycles <100>:16TDRcycles <101>:32TDRcycles <110>:64TDRcycles(default) <111>:Reserved 7:0 RESERVED 0,RO RESERVED:Writesignored,readas0. Table8-38.CableDiagnosticSpecificControlRegister2(CDSCR2),address0x0171 BIT BITNAME DEFAULT DESCRIPTION 15:4 RESERVED 11001000 RESERVED:Ignoreonread 0101,RW 3:0 TDRpulsecontrol 1100,RW ConfigureexpectedselfreflectioninTDR Table8-39.CableDiagnosticSpecificControlRegister3(CDSCR3),address0x0173 BIT BITNAME DEFAULT DESCRIPTION 15:8 Cablelengthcfg 11111111, Configuredurationoflisteningtodetectlongcablereflections RW 7:0 RESERVED 11111111, RESERVED:Ignoreonread RW Table8-40.CableDiagnosticSpecificControlRegister4(CDSCR4),address0x0177 BIT BITNAME DEFAULT DESCRIPTION 15:13 RESERVED 000,RW RESERVED:Ignoreonread 12:8 ShortcablesTH 11000,RW THtocompensateforstrongreflectionsinshortcables 7:0 RESERVED 10010110, RESERVED:Ignoreonread RW Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 71 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.8.3 Cable Diagnostic Location Results Register 1 (CDLRR1) This register provides the peaks locations after execution of the TDR. The values of this register are valid afterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-41.CableDiagnosticLocationResultsRegister1(CDLRR1),address0x0180 BIT BITNAME DEFAULT DESCRIPTION 15:8 TPTDPeak 00000000,RO LocationoftheSecondpeakdiscoveredbytheTDRmechanismonTransmitChannel Location2 (TPTD).ThevalueofthesebitsistranslatedintodistancefromthePHY 7:0 TPTDPeak 00000000,RO LocationoftheFirstpeakdiscoveredbytheTDRmechanismonTransmitChannel Location1 (TPTD).ThevalueofthesebitsistranslatedintodistancefromthePHY 8.8.4 Cable Diagnostic Location Results Register 2 (CDLRR2) This register provides the peaks locations after execution of the TDR. The values of this register are valid afterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-42.CableDiagnosticLocationResultsRegister2(CDLRR2),address0x0181 BIT BITNAME DEFAULT DESCRIPTION 15:8 TPTDPeak 00000000,RO LocationoftheFourthpeakdiscoveredbytheTDRmechanismonTransmitChannel Location4 (TPTD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 7:0 TPTDPeak 00000000,RO LocationoftheThirdpeakdiscoveredbytheTDRmechanismonTransmitChannel Location3 (TPTD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 8.8.5 Cable Diagnostic Location Results Register 3 (DDLRR3) This register provides the peaks locations after execution of the TDR. The values of this register are valid afterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-43.CableDiagnosticLocationResultsRegister3(DDLRR3),address0x0182 BIT BITNAME DEFAULT DESCRIPTION 15:8 TPRDPeak 00000000,RO LocationoftheFirstpeakdiscoveredbytheTDRmechanismonReceiveChannel Location1 (TPRD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 7:0 TPTDPeak 00000000,RO LocationoftheFifthpeakdiscoveredbytheTDRmechanismonTransmitChannel Location5 (TPTD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 8.8.6 Cable Diagnostic Location Results Register 4 (CDLRR4) This register provides the peaks locations after execution of the TDR. The values of this register are valid afterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-44.CableDiagnosticLocationResultsRegister4(CDLRR4),address0x0183 BIT BITNAME DEFAULT DESCRIPTION 15:8 TPRDPeak 00000000,RO LocationoftheThirdpeakdiscoveredbytheTDRmechanismonReceiveChannel Location3 (TPRD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 7:0 TPRDPeak 00000000,RO LocationoftheSecondpeakdiscoveredbytheTDRmechanismonReceiveChannel Location2 (TPRD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 72 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.8.7 Cable Diagnostic Location Results Register 5 (CDLRR5) This register provides the peaks locations after execution of the TDR. The values of this register are valid afterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-45.CableDiagnosticLocationResultsRegister5(CDLRR5),address0x0184 BIT BITNAME DEFAULT DESCRIPTION 15:8 TPRDPeak 00000000,RO LocationoftheFifthpeakdiscoveredbytheTDRmechanismonReceiveChannel Location5 (TPRD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 7:0 TPRDPeak 00000000,RO LocationoftheFourthpeakdiscoveredbytheTDRmechanismonReceiveChannel Location4 (TPRD).ThevalueofthesebitsistranslatedintodistancefromthePHY. 8.8.8 Cable Diagnostic Amplitude Results Register 1 (CDARR1) This register provides the peaks amplitude measurement after the execution of the TDR. The values of thisregisterarevalidafterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-46.CableDiagnosticAmplitudeResultsRegister1(CDARR1),address0x0185 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14:8 TPTDPeak 0000000,RO AmplitudeoftheSecondpeakdiscoveredbytheTDRmechanismonTransmitChannel Amplitude2 (TPTD).Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[15:8]inregisterCDLRR1(0x180) 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6:0 TPTDPeak 0000000,RO AmplitudeoftheFirstpeakdiscoveredbytheTDRmechanismonTransmitChannel(TPTD). Amplitude1 Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[7:0]inregisterCDLRR1(0x180) 8.8.9 Cable Diagnostic Amplitude Results Register 2 (CDARR2) This register provides the peaks amplitude measurement after the execution of the TDR. The values of thisregisterarevalidafterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-47.CableDiagnosticAmplitudeResultsRegister2(CDARR2),address0x0186 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14:8 TPTDPeak 0000000,RO AmplitudeoftheFourthpeakdiscoveredbytheTDRmechanismonTransmitChannel Amplitude4 (TPTD).Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[15:8]inregisterCDLRR2(0x181) 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6:0 TPTDPeak 0000000,RO AmplitudeoftheThirdpeakdiscoveredbytheTDRmechanismonTransmitChannel Amplitude3 (TPTD).Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[7:0]inregisterCDLRR2(0x181) Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 73 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 8.8.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3) This register provides the peaks amplitude measurement after the execution of the TDR. The values of thisregisterarevalidafterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-48.CableDiagnosticAmplitudeResultsRegister3(CDARR3),address0x0187 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14:8 TPRDPeak 0000000,RO AmplitudeoftheFirstpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD). Amplitude1 Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[15:8]inregisterCDLRR3(0x182) 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6:0 TPTDPeak 0000000,RO AmplitudeoftheFifthpeakdiscoveredbytheTDRmechanismonTransmitChannel(TPTD). Amplitude5 Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[7:0]inregisterCDLRR3(0x182) 8.8.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4) This register provides the peaks amplitude measurement after the execution of the TDR. The values of thisregisterarevalidafterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-49.CableDiagnosticAmplitudeResultsRegister4(CDARR4),address0x0188 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14:8 TPRDPeak 0000000,RO AmplitudeoftheThirdpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD). Amplitude3 Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[15:8]inregisterCDLRR4(0x183) 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6:0 TPRDPeak 0000000,RO AmplitudeoftheSecondpeakdiscoveredbytheTDRmechanismonReceiveChannel Amplitude2 (TPRD).Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[7:0]inregisterCDLRR4(0x183) 8.8.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5) This register provides the peaks amplitude measurement after the execution of the TDR. The values of thisregisterarevalidafterreading1inDiagnosticDonebit1inregisterCDCR(0x1E). Table8-50.CableDiagnosticAmplitudeResultsRegister5(CDARR5),address0x0189 BIT BITNAME DEFAULT DESCRIPTION 15 RESERVED 0,RO RESERVED:Writesignored,readas0. 14:8 TPRDPeak 0000000,RO AmplitudeoftheFifthpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD). Amplitude5 Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[15:8]inregisterCDLRR4(0x184) 7 RESERVED 0,RO RESERVED:Writesignored,readas0. 6:0 TPRDPeak 0000000,RO AmplitudeoftheFourthpeakdiscoveredbytheTDRmechanismonReceiveChannel Amplitude4 (TPRD).Thevalueofthesebitsistranslatedintotypeofcablefaultand-orinterference. Thisamplitudevaluereferstopeaklocationstoredinbits[7:0]inregisterCDLRR4(0x184) 74 RegisterBlock Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 8.8.13 Cable Diagnostic General Results Register (CDGRR) This register provides general measurement results after the execution of the TDR. The Cable Diagnostic softwareshouldpostprocessthisresulttogetherwithotherPeaks’locationandamplituderesults. Table8-51.CableDiagnosticGeneralResultsRegister(CDGRR),address0x018A BIT BITNAME DEFAULT DESCRIPTION 15 TPTDPeakPolarity5 0,RO PolarityoftheFifthpeakdiscoveredbytheTDRmechanismonTransmitChannel(TPTD) 14 TPTDPeakPolarity4 0,RO PolarityoftheFourthpeakdiscoveredbytheTDRmechanismonTransmitChannel (TPTD) 13 TPTDPeakPolarity3 0,RO PolarityoftheThirdpeakdiscoveredbytheTDRmechanismonTransmitChannel(TPTD) 12 TPTDPeakPolarity2 0,RO PolarityoftheSecondpeakdiscoveredbytheTDRmechanismonTransmitChannel (TPTD) 11 TPTDPeakPolarity1 0,RO PolarityoftheFirstpeakdiscoveredbytheTDRmechanismonTransmitChannel(TPTD) 10 TPRDPeakPolarity5 0,RO PolarityoftheFifthpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD) 9 TPRDPeakPolarity4 0,RO PolarityoftheFourthpeakdiscoveredbytheTDRmechanismonReceiveChannel (TPRD) 8 TPRDPeakPolarity3 0,RO PolarityoftheThirdpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD) 7 TPRDPeakPolarity2 0,RO PolarityoftheSecondpeakdiscoveredbytheTDRmechanismonReceiveChannel (TPRD) 6 TPRDPeakPolarity1 0,RO PolarityoftheFirstpeakdiscoveredbytheTDRmechanismonReceiveChannel(TPRD) 5 CrossDetectonTPTD 0,RO CrossReflectionweredetectedonTPTD.IndicateonShortbetweenTPTDandTPRD 4 CrossDetectonTPRD 0,RO CrossReflectionweredetectedonTPRD.IndicateonShortbetweenTPTDandTPRD 3 Above5TPTDPeaks 0,RO Morethan5reflectionsweredetectedonTPTD 2 Above5TPRDPeaks 0,RO Morethan5reflectionsweredetectedonTPRD 1:0 RESERVED 00,RO RESERVED:Writesignored,readas0 8.8.14 ALCD Control and Results 2 (ALCDRR2) Table8-52.ALCDControlandResults2(ALCDRR2),address0x0215 BIT BITNAME DEFAULT DESCRIPTION 15:12 alcd_out2 0011,SC 11:0 alcd_out3 01100000 alcd_out3 0000,RW Copyright©2012–2016,TexasInstrumentsIncorporated RegisterBlock 75 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9 Electrical Specifications Allparametersarederivedbytest,statisticalanalysis,ordesign. 9.1 Absolute Maximum Ratings(1) MIN MAX UNIT VDD_IO,AVDD33 Supplyvoltage –0.3 3.8 V PFBIN1,PFBIN2 –0.3 1.8 XI DCInputvoltage –0.3 3.8 V TD-,TD+,RD-,RD+ –0.3 6 OtherInputs –0.3 3.8 XO DCOutputvoltage –0.3 3.8 V Otheroutputs –0.3 3.8 T Maximumdietemperature 125 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 9.2 ESD Ratings VALUE UNIT Allpins(2) ±4000 HumanBodyModel(HBM),per V Electrostaticdischarge ANSI/ESDA/JEDECJS001(1) ETDth–e,rnReDt+n,eRtwDo–r)k(3p)ins(TD+, ±16000 V ESD (ESD)performance: CpehraJrgEeSdDD22e-vCic1e0M1(o4d)el(CDM), Allpins(5) ±750 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) TestedinaccordancetoJEDECStandard22,TestMethodA114. (3) TestmethodbaseduponJEDECStandard22TestMethodA114,Ethernetnetworkpins(TD+,TD–,RD+,RD–)pinsstressedwith respecttoGND. (4) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. (5) TestedinaccordancetoJEDECStandard22,TestMethodC101. 9.3 Recommended Operating Conditions MIN NOM MAX UNIT DUALSUPPLYOPERATION CoreSupplyvoltage(PFBIN1,PFBIN2) 1.48 1.55 1.68 V P Powerdissipation(1) 200 mW D SINGLESUPPLYOPERATION (PFBOUTconnectedtoPFBIN1,PFBIN2SeeFigure3-1) P Powerdissipation(2) 270 mW D AVDD33 Analog3.3-VSupply 3.0 3.3 3.6 V 3.3-VOption 3.0 3.3 3.6 VDD_IO 2.5-VOption 2.25 2.5 2.75 V 1.8-VOption(MIIModeonly) 1.62 1.8 1.98 T Ambienttemperature(3) TLK105 –40 85 A °C TLK106 –40 105 (1) For100Base-TX (2) For100Base-TX,Wheninternal1.55Visused.Deviceisoperatedfromsingle3.3-Vsupplyonly. (3) ProvidedthatDOWN_PAD,pin33,issoldereddown.SeeThermalViasRecommendationformoredetail. 76 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.5 TLK105 32-Pin Industrial Device (85°C) Thermal Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) overoperatingfree-airtemperaturerange(unlessotherwisenoted) TLK105L, TLK106L THERMALMETRIC(1) UNIT RHB(VQFN) 32PINS R Junction-to-ambientthermalresistance 36.4 °C/W θJA R Junction-to-boardthermalresistance 9.3 °C/W θJB R Junction-to-case(top)thermalresistance 26.8 °C/W θJC(top) R Junction-to-case(bottom)thermalresistance 1.7 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 9.6 TLK106 32-Pin Extended Temperature (105°C) Device Thermal Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) TLK105L, TLK106L THERMALMETRIC(1) UNIT RHB(VQFN) 32PINS R Junction-to-ambientthermalresistance(noairflow),JEDEChigh-Kmodel 36.4 °C/W θJA R Junction-to-boardthermalresistance 9.3 °C/W θJB R Junction-to-case(top)thermalresistance 26.8 °C/W θJC(top) R Junction-to-case(bottom)thermalresistance 1.7 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.7 DC Characteristics, VDD_IO overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 3.3VVDD_IO V Inputhighvoltage NominalVCC=3.3V VDD_IO=3.3V±10% 2.0 V IH V Inputlowvoltage VDD_IO=3.3V±10% 0.8 V IL V Outputlowvoltage I =4mA VDD_IO=3.3V±10% 0.4 V OL OL V Outputhighvoltage I =–4mA VDD_IO=3.3V±10% VDD_IO–0.5 V OH OH 2.5VVDD_IO V Inputhighvoltage VDD_IO=2.5V±10% 1.5 V IH V Inputlowvoltage VDD_IO=2.5V±10% 0.5 V IL V Outputlowvoltage I =2mA VDD_IO=2.5V±10% 0.4 V OL OL V Outputhighvoltage I =–2mA VDD_IO=2.5V±10% VDD_IO–0.4 V OH OH 1.8VVDD_IO V Inputhighvoltage VDD_IO=1.8V±10% 1.3 V IH V Inputlowvoltage VDD_IO=1.8V±10% 0.45 V IL V Outputlowvoltage I =2mA VDD_IO=1.8V±10% 0.4 V OL OL V Outputhighvoltage I =–2mA VDD_IO=1.8V±10% VDD_IO–0.4 V OH OH 9.8 DC Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I Inputhighcurrent V =V 10 μA IH IN CC I Inputlowcurrent V =GND 10 μA IL IN I 3-Stateleakage V =V ,V =GND ±10 μA OZ OUT CC OUT R IntegratedPullupResistance 14.7 23.7 49.7 kΩ PULLUP R IntegratedPulldownResistance 14.5 24.9 48.1 kΩ PULLDOWN V 100Mtransmitvoltage 0.95 1 1.05 V TPTD_100 V 100Mtransmitvoltagesymmetry ±2% TPTDsym V 10Mtransmitvoltage 2.2 2.5 2.8 V TPTD_10 C CMOSinputcapacitance 5 pF IN1 C CMOSoutputcapacitance 5 pF OUT1 V 10Base-TReceivethreshold 200 mV TH1 78 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.9 Power Supply Characteristics The data was measured using a TLK10x evaluation board. The current from each of the power supplies is measured and the power dissipation is computed. For the single 3.3-V external supply case the power dissipation across the internal linear regulator is also included. All the power dissipation numbers are measured at the nominal power supply and typical temperature of 25°C. The power needed is given both for the device only, and including the center tap of the transformer for a total system power requirement. The center tap of the transformer is normally connected to the 3.3-V supply, thus the current needed may alsobeeasilycalculated. 9.9.1 Active Power, Single Supply Operation FROM PARAMETER TESTCONDITIONS FROMPOWERPINS TRANSFORMER UNIT CENTERTAP 100Base-TX/WTraffic(fullpacket1518B 203 73 rate) Single3.3-Vexternalsupply mW 10Base-T/WTraffic(fullpacket1518Brate) 96 211 9.9.2 Active Power, Dual Supply Operation PARAMETER TESTCONDITIONS FROM3.3-V FROM1.55V FROM UNIT POWER PFBIN1,PFBIN2 TRANSFORMER CENTERTAP 100Base-TX/WTraffic(fullpacket 53 73 73 1518Brate) Dualexternalsupplies, mW 10Base-T/WTraffic(fullpacket 3.3Vand1.55V 23 35 212 1518Brate) 9.9.3 Power-Down Power FROM PARAMETER TESTCONDITIONS(1) FROM3.3-VPOWER FROM1.55V TRANSFORMER UNIT PFBIN1,PFBIN2 CENTERTAP IEEEPWDN Single3.3-Vexternalsupply 12 – 5 PassiveSleepMode 71 – 5 ActiveSleepMode 71 – 5 mW IEEEPWDN Dualexternalsupplies, 12 0 5 3.3Vand1.55V PassiveSleepMode 21 23 5 ActiveSleepMode 21 23 5 (1) Measuredundertypicalconditions. Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10 AC Specifications 9.10.1 Power Up Timing Table9-1.PowerUpTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Timefrompoweruptohardware-configurationpin t transitiontooutput-driverfunction,usinginternal 100 270 ms 1 POR(RESETpintiedhigh) XIClockmustbestableforminimumof1µs t XIClockinitialization 1 µs 2 priortoconfiguration. VDD Hardware RESET t 1 Dual function pins t 2 Become enabled As outputs XI Clock Figure9-1.PowerUpTiming NOTE It is important to choose pullup and-or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch in the proper value priortothepintransitioningtoanoutputdriver. 9.10.2 Reset Timing Table9-2.ResetTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT XIClockmustbestableforminimumof1µs t RESETpulsewidth 1 µs 1 duringRESETpulselowtime. 80 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 V CC XI Clock t 1 Hardware RESET T0339-01 Figure9-2.ResetTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.3 MII Serial Management Timing Table9-3.MIISerialManagementTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t MDCFrequency 2.5 25 MHz 1 t MDCtoMDIO(Output)DelayTime 0 30 ns 2 t MDIO(Input)toMDCHoldTime 10 ns 3 t MDIO(Input)toMDCSetupTime 10 ns 4 MDC t 1 t 2 MDIO(Output) MDC t 3 t 4 MDIO(Input) ValidData T0340-01 Figure9-3.MIISerialManagementTiming 9.10.4 100Mb/s MII Transmit Timing Table9-4.100Mb/sMIITransmitTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TX_CLKHighTime 1 100MbsNormalmode 16 20 24 ns t TX_CLKLowTime 2 t TXD[3:0],TX_ENDataSetuptoTX_CLK 100MbsNormalmode 10 ns 3 t TXD[3:0],TX_ENDataHoldfromTX_CLK 100MbsNormalmode 0 ns 4 t1 t2 TX_CLK t 3 t 4 TXD[3:0] ValidData TX_EN T0341-01 Figure9-4.100Mb/sMIITransmitTiming 82 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.5 100Mb/s MII Receive Timing Table9-5.100Mb/sMIIReceiveTiming PARAMETER(1) TESTCONDITIONS MIN TYP MAX UNIT t RX_CLKHighTime 1 100MbsNormalmode 16 20 24 ns t RX_CLKLowTime 2 t RX_CLKtoRXD[3:0],RX_DV,RX_ERDelay 100MbsNormalmode 10 30 ns 3 (1) RX_CLKmaybeheldloworhighforalongerperiodoftimeduringtransitionbetweenreferenceandrecoveredclocks.Minimumhigh andlowtimeswillnotbeviolated. t t 1 2 RX_CLK t 3 RXD[3:0] RX_DV ValidData RX_ER T0342-01 Figure9-5.100Mb/sMIIReceiveTiming 9.10.6 100Base-TX Transmit Packet Latency Timing Table9-6.100Base-TXTransmitPacketLatencyTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TX_CLKtoPMDOutputPairLatency 100MbsNormalmode(1) 4.8 bits(2) 1 (1) ForNormalmode,latencyisdeterminedbymeasuringthetimefromthefirstrisingedgeofTX_CLKoccurringaftertheassertionof TX_ENtothefirstbitofthe'J'codegroupasoutputfromthePMDOutputPair.1bittime=10nsin100Mbsmode. (2) 1bittimeisequal10nSin100Mb/smode. TX_CLK TX_EN TXD t 1 PMDOutputPair IDLE (J/K) DATA T0343-01 Figure9-6.100Base-TXTransmitPacketLatencyTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.7 100Base-TX Transmit Packet Deassertion Timing Table9-7.100Base-TXTransmitPacketDeassertionTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TX_CLKtoPMDOutputPairdeassertion 100MbsNormalmode 4.6 bits 1 TX_CLK TX_EN TXD t 1 PMDOutputPair DATA (T/R) IDLE DATA (T/R) IDLE T0344-01 Figure9-7.100Base-TXTransmitPacketDeassertionTiming 84 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.8 100Base-TX Transmit Timing (t and Jitter) R/F Table9-8.100Base-TXTransmitTiming(t andJitter) R/F PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 100MbsPMDOutputPairt andt (1) 3 4 5 ns R F t 1 100Mbst andt Mismatch(2) 500 ps R F t 100MbsPMDOutputPairTransmitJitter 1.4 ns 2 (1) Riseandfalltimestakenat10%and90%ofthe+1or-1amplitude. (2) NormalMismatchisthedifferencebetweenthemaximumandminimumofallriseandfalltimes. t 1 +1rise 90% 10% PMDOutputPair 10% 90% +1 fall t 1 –1rise t –1 fall 1 t 1 t 2 PMD OutputPair t Eye Pattern 2 T0345-01 Figure9-8.100Base-TXTransmitTiming(t andJitter) R/F Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.9 100Base-TX Receive Packet Latency Timing Table9-9.100Base-TXReceivePacketLatencyTiming PARAMETER TESTCONDITIONS(1) MIN TYP MAX UNIT(2) t CarrierSenseONDelay(3) 100MbsNormalmode 14 bits 1 t ReceiveDataLatency 100MbsNormalmode 19 bits 2 t Receivedatalatency(4) 100MbnormalmodewithfastRXDV 15 bits 2 detectionON (1) PMDInputPairvoltageamplitudeisgreaterthantheSignalDetectTurn-OnThresholdValue. (2) 1bittime=10nsin100Mbsmode (3) CarrierSenseOnDelayisdeterminedbymeasuringthetimefromthefirstbitofthe“J”codegrouptotheassertionofCarrierSense. (4) FastRXDVdetectioncouldbeenabledbysettingbit[1]ofCR1(address0x0009). PMD Input Pair IDLE (J/K) Data t 1 CRS t 2 RXD[3:0] RX_DV RX_ER T0346-01 Figure9-9.100Base-TXReceivePacketLatencyTiming 9.10.10 100Base-TX Receive Packet Deassertion Timing Table9-10.100Base-TXReceivePacketDeassertionTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t CarrierSenseOFFDelay(1) 100MbsNormalmode 19 bits(2) 1 (1) CarrierSenseOffDelayisdeterminedbymeasuringthetimefromthefirstbitofthe“T”codegrouptothedeassertionofCarrierSense. (2) 1bittime=10nsin100Mbsmode PMD Input Pair DATA (T/R) IDLE t 1 CRS T0347-01 Figure9-10.100Base-TXReceivePacketDeassertionTiming 86 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.11 10Mbs MII Transmit Timing Table9-11.10MbsMIITransmitTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TX_CLKLowTime 1 10MbsMIImode 190 200 210 ns t TX_CLKHighTime 2 t TXD[3:0],TX_ENDataSetuptoTX_CLK↑ 10MbsMIImode 25 ns 3 t TXD[3:0],TX_ENDataHoldfromTX_CLK↑ 10MbsMIImode 0 ns 4 An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown in Figure9-11,theMIIsignalsaresampledonthefallingedgeofTX_CLK. t t 1 2 TX_CLK t t 3 4 TXD[3:0] ValidData TX_EN Figure9-11.10MbsMIITransmitTiming 9.10.12 10Mb/s MII Receive Timing Table9-12.10Mb/sMIIReceiveTiming PARAMETER(1) TESTCONDITIONS MIN TYP MAX UNIT t RX_CLKHighTime 1 160 200 240 ns t RX_CLKLowTime 2 t RX_CLKrisingedgedelayfromRXD[3:0],RX_DVValid 10MbsMIImode 100 ns 3 t RX_CLKtoRXD[3:0],RX_DVDelay 10MbsMIImode 100 ns 4 (1) RX_CLKmaybeheldlowforalongerperiodoftimeduringtransitionbetweenreferenceandrecoveredclocks.Minimumhighandlow timeswillnotbeviolated. t t 1 2 RX_CLK t 3 t 4 RXD[3:0] ValidData RX_DV T0349-01 Figure9-12.10Mb/sMIIReceiveTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.13 10Base-T Transmit Timing (Start of Packet) Table9-13.10Base-TTransmitTiming(StartofPacket) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT(1) t TransmitOutputDelayfromtheFallingEdgeofTX_CLK 10MbsMIImode 5.8 bits 1 (1) (1)1bittime=100nsin10Mb/s. TX_CLK TX_EN TXD t 1 PMDOutputPair Figure9-13.10Base-TTransmitTiming(StartofPacket) 9.10.14 10Base-T Transmit Timing (End of Packet) Table9-14.10Base-TTransmitTiming(EndofPacket) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t EndofPacketHighTime(with‘0’endingbit) 250 310 ns 1 t EndofPacketHighTime(with‘1’endingbit) 250 310 ns 2 TX_CLK TX_EN t 1 PMDOutputPair 0 0 t 2 PMDOutputPair 1 1 Figure9-14.10Base-TTransmitTiming(EndofPacket) 88 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.15 10Base-T Receive Timing (Start of Packet) Table9-15.10Base-TReceiveTiming(StartofPacket) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t CarrierSenseTurnOnDelay(PMDInputPairtoCRS) 550 1000 ns 1 t RX_DVLatency(1) 14 bits 2 Measurementshownfrom t ReceiveDataLatency 14 bits 3 SFD (1) 10Base-TRX_DVLatencyismeasuredfromfirstbitofdecodedSFDonthewiretotheassertionofRX_DV 1stSFD Bit Decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD t 1 CRS RX_CLK t 2 RX_DV t 3 RXD[3:0] 0000 Preamble SFD Data Figure9-15.10Base-TReceiveTiming(StartofPacket) 9.10.16 10Base-T Receive Timing (End of Packet) Table9-16.10Base-TReceiveTiming(EndofPacket) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t CarrierSenseTurnOffDelay 1.8 μs 1 1 0 1 IDLE PMD Input Pair RX_CLK t 1 CRS Figure9-16.10Base-TReceiveTiming(EndofPacket) Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.17 10Mb/s Jabber Timing Table9-17.10Mb/sJabberTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t JabberActivationTime 100 1 10Mb/sMIImode ms t JabberDeactivationTime 500 2 TX_EN t1 PMD Output Pair t2 COL Figure9-17.10Mb/sJabberTiming 9.10.18 10Base-T Normal Link Pulse Timing Table9-18.10Base-TNormalLinkPulseTiming PARAMETER(1) TESTCONDITIONS MIN TYP MAX UNIT t PulsePeriod 16 ms 1 10Mb/sMIImode t PulseWidth 100 ns 2 (1) Transmittiming t 1 t 2 Normal Link Pulse(s) T0358-01 Figure9-18.10Base-TNormalLinkPulseTiming 90 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.19 Auto-Negotiation Fast Link Pulse (FLP) Timing Table9-19.Auto-NegotiationFastLinkPulse(FLP)Timing PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ClockPulsetoClockPulsePeriod 125 μs 1 t ClockPulsetoDataPulsePeriod Data=1 62 μs 2 t Clock,DataPulseWidth 114 ns 3 t FLPBursttoFLPBurstPeriod 16 ms 4 t BurstWidth 2 ms 5 t 1 t 2 t3 t3 Fast Link Pulse(s) Clock Data Clock Pulse Pulse Pulse t 4 t 5 FLPBurst FLPBurst T0359-01 Figure9-19.Auto-NegotiationFastLinkPulse(FLP)Timing 9.10.20 100Base-TX Signal Detect Timing Table9-20.100Base-TXSignalDetectTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t SDInternalTurn-onTime 100 μs 1 t InternalTurn-offTime 200 μs 2 PMD Input Pair t t 1 2 SD+ Intermal T0360-01 NOTE: ThesignalamplitudeonPMDInputPairmustbeTP-PMDcompliant. Figure9-20.100Base-TXSignalDetectTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.21 100Mbs Loopback Timing Table9-21.100MbsLoopbackTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 100Mbsexternalloopback 241 242 243 100Mbsexternalloopback–fastRX_DVmode 201 202 203 t TX_ENtoRX_DVLoopback 100Mbsanalogloopback 232 233 234 ns 1 100MbsPCSInputloopback 120 121 122 100MbsMIIloopback 8 9 10 TX_CLK TX_EN TXD[3:0] CRS t 1 RX_CLK RX_DV RXD[3:0] T0361-01 (1) Due to the nature of the descrambler function, all 100Base-TX Loopback modes cause an initial dead-time of up to 550 μs during whichtimenodataispresentatthereceiveMIIoutputs.The100Base-TXtimingspecifiedisbasedondevicedelaysaftertheinitial 550µsdead-time. (2) MeasurementismadefromthefirstrisingedgeofTX_CLKafterassertionofTX_EN. (3) Externalloopbackwasmeasuredusingveryshortexternalcable(approximately10cm). (4) SinceMIIloopbackintroduceextremeshortroundtripdelay,somehostswouldusePCSInputloopback(Mainlyin100BT). Figure9-21.100MbsLoopbackTiming 92 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.22 10Mbs Internal Loopback Timing Table9-22.10MbsInternalLoopbackTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TX_ENtoRX_DVLoopback 10Mbsinternalloopbackmode 1.7 μs 1 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0362-01 (1) MeasurementismadefromthefirstrisingedgeofTX_CLKafterassertionofTX_EN. (2) Analogloopbackwasused.LoopingtheTXtoRXattheanaloginput/outputstage. Figure9-22.10MbsInternalLoopbackTiming 9.10.23 RMII Transmit Timing Table9-23.RMIITransmitTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 50MHzReference t XIClockPeriod 20 1 Clock t2 TXD[1:0]andTX_ENdatasetuptoX1rising 1.4 ns VDD_IO=3.3V 2.0 t TXD[1:0]andTX_ENdataholdtoX1rising 3 VDD_IO=2.5V 4.9 t XIClocktoPMDOutputPairLatency 12 bits 4 t 1 XI t2 t3 TXD[1:0] Valid Data TX_EN t 4 PMD Output Pair Symbol Figure9-23.RMIITransmitTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 9.10.24 RMII Receive Timing Table9-24.RMIIReceiveTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t XIClockPeriod 50MHzReferenceClock 20 1 ns t RXD[1:0],CRS_DV,RX_DVandRX_ERoutputdelayfromXIrising 4 10.8 14 2 FromJKsymbolonPMD t CRSONdelay ReceivePairtoinitial 17.6 3 assertionofCRS_DV FromTRsymbolonPMD t CRSOFFdelay ReceivePairtoinitial 26.2 bits 4 assertionofCRS_DV FromsymbolonReceive t RXD[1:0]andRX_ERlatency Pair.*Elasticitybufferset 29.7 5 todefaultvalue(01) 50MHz“Recoveredclock” t RX_CLKClockPeriod whileworkingin“RMII 20 6 receiveclock”mode ns RXD[1:0],CRS_DV,RX_DVandRX_ERoutputdelayfromRX_CLK Whileworkingin“RMII t 3.8 7 rising receiveclock”mode PMD Input Pair Idle (J/K) Data (TR) Data t5 t4 XI t2 t1 t2 t2 t RX_DV 3 CRS_DV t 2 RXD[1:0] RX_ER RX_CLK t7 t6 t7 t7 Figure9-24.RMIIReceiveTiming NOTE 1. PertheRMIISpecification,outputdelaysassumea25pFload. 2. CRS_DVisassertedasynchronouslyinordertominimizelatencyofcontrolsignals throughthePHY.CRS_DVmaytogglesynchronouslyattheendofthepackettoindicate CRSde-assertion. 3. RX_DVissynchronoustoXI.WhilenotpartoftheRMIIspecification,thissignalis providedtosimplifyrecoveryofreceivedata. 4. “RMIIreceiveclock”modeisnotpartoftheRMIIspecificationthatallowssynchronization oftheMAC-PHYRXinterfaceinRMIImode.Settingregister0x000Abit[0]isrequiredto activatethismode. 94 ElectricalSpecifications Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 9.10.25 Isolation Timing Table9-25.IsolationTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT FromDeassertionofS/WorH/WResettotransitionfromIsolatetoNormal t 71 ns 1 mode H/W or S/W Reset t 1 MODE ISOLATE NORMAL T0365-01 Figure9-25.IsolationTiming Copyright©2012–2016,TexasInstrumentsIncorporated ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 www.ti.com 10 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(January2014)toRevisionC Page • Deleted"SD_IN"...................................................................................................................... 6 • Changed"WOL(Wake-OnLAN)"to"EnergySaving" ......................................................................... 34 • Changed"WOL(Wake-OnLAN)"to"EnergySaving" ......................................................................... 34 • DeletedBit[14]FiberModeControl............................................................................................... 54 • Changed"ActiveWOL"to"ActiveEnergySaving"............................................................................. 59 • Changed"PassiveWOL"to"PassiveEnergySaving"......................................................................... 59 • DeletedFiberModeControlRegister(FIBCR).................................................................................. 69 • DeletedFiberModeControlRegister2(FIBCR2).............................................................................. 70 • DeletedFiberModeControlRegister3(FIBCR3).............................................................................. 70 • DeletedRedundantrow"Powerdissipation200mW" ......................................................................... 76 • DeletedDCCharacteristics,SD_IN............................................................................................... 78 • V -maxvaluedeleted,200-mVtypvalueadded............................................................................ 78 TH1 96 RevisionHistory Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

TLK105 TLK106 www.ti.com SLLSEB8C–AUGUST2012–REVISEDAPRIL2016 ChangesfromRevisionA(March2013)toRevisionB Page • Changed"LowPowerConsumption:<205mWPHYand275mWwithCenterTap(Typical)"to"LowPower Consumption:SingleSupply:<205mWPHY275mWwithCenterTap(Typical)DualSupplies:<126mWPHY and200mWwithCenterTap(Typical)"............................................................................................ 1 • Changed"EnablesimplementationofIEEE1588TimeStampingattheMAC"to"LowDeterministicLatency SupportsIEEE1588Implementations"............................................................................................ 1 • Reorderdfeatureslist................................................................................................................ 1 • Changed"MIIandRMIIInterfaces"to"MIIandRMIICapabilities"............................................................ 1 • Changed"BusI/OProtection-±16kVJEDECHBM"to"HBMESDprotectiononRD±andTD±of16kV".............. 1 • Addedbulletitem"VariableI/Ovoltagerange:1.8Vto3.3V"................................................................... 1 • Changed"Error-FreeOperationupto150MetersUnderTypicalConditions"to"Error-Free100Base-T Operationupto150MetersUnderTypicalConditionsError-Free10Base-TOperationupto300MetersUnder TypicalConditions"................................................................................................................... 1 • UpdatedtoincludevariableIOcapability-changedsignalname"VDD33_IO"to"VDD_IO".............................. 7 • AddedvariableIOcapability ........................................................................................................ 9 • ChangedRX_ERtodottedlinetoindicateoptionalsignal.................................................................... 19 • ChangedrecommendedtransformerfromPulseHX1188toPulseHX1198................................................ 35 • AddedPowerBackOffControlRegister(0AEh)................................................................................ 38 • Correctedregistersummarytablestoshowextendedregistersbeginningat020h........................................ 38 • UpdatedRMIIControlandStatusRegisterbit5description.................................................................. 64 • Deleted"AllowthesystemtoresetthePHYusingregisteraccess."........................................................ 68 • Addedoperatingconditionsforsingleanddualsupplies...................................................................... 76 • AddedvariableIOcapability....................................................................................................... 78 • Changedtitlefrom"ActivePower"to"ActivePower,SingleSupplyOperation"............................................ 79 • AddedDualSupplyOperationtable.............................................................................................. 79 Copyright©2012–2016,TexasInstrumentsIncorporated RevisionHistory 97 SubmitDocumentationFeedback ProductFolderLinks:TLK105TLK106

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLK105RHBR NRND VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TLK105 & no Sb/Br) TLK105RHBT NRND VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TLK105 & no Sb/Br) TLK106RHBR NRND VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 0 TLK106 & no Sb/Br) TLK106RHBT NRND VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 0 TLK106 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLK105RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TLK105RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TLK106RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TLK106RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLK105RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLK105RHBT VQFN RHB 32 250 210.0 185.0 35.0 TLK106RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLK106RHBT VQFN RHB 32 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

PACKAGE OUTLINE RHB0032B VQFN - 1 mm max height SCALE 2.500 PLASTIC QUAD FLATPACK - NO LEAD A 5.1 B 4.9 PIN 1 INDEX AREA 0.5 5.1 0.3 4.9 0.3 0.2 DETAIL OPTIONAL TERMINAL TYPICAL C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 2.9 0.1 (0.2) TYP 9 16 28X 0.5 EXPOSED THERMAL PAD 8 17 2X 33 SYMM 3.5 SEE TERMINAL DETAIL 1 24 0.3 32X 0.2 32 25 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.05 0.5 32X 0.3 4223216/A 08/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHB0032B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 2.9) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (R0.05) TYP (1.2) TYP 33 SYMM (4.8) 28X (0.5) 8 ( 0.2) TYP 17 VIA 9 16 (4.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4223216/A 08/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHB0032B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.27) (0.735) TYP 32 25 32X (0.6) 1 24 33 32X (0.25) (R0.05) TYP (0.735) TYP SYMM (4.8) 28X (0.5) 8 17 METAL TYP 9 16 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33 76.7% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223216/A 08/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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