TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 Micropower Supply Voltage Supervisors CheckforSamples:TLC7701,TLC7725,TLC7703,TLC7733,TLC7705 FEATURES 1 DRB PACKAGE • Power-OnResetGenerator • AutomaticResetGenerationAfterVoltage Drop • PrecisionVoltageSensor • Temperature-CompensatedVoltageReference • ProgrammableDelayTimebyExternal Capacitor • SupplyVoltageRange...2Vto6V • DefinedRESETOutputfromV ≥1V DD • Power-DownControlSupportforStaticRAM WithBatteryBackup • MaximumSupplyCurrentof16µA • PowerSavingTotem-PoleOutputs • TemperatureRange...Upto–55°Cto125°C APPLICATIONS • MedicalImaging DESCRIPTION The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputerandmicroprocessorsystems. During power-on, RESET is asserted when V DD reaches 1 V. After minimum V (≥2 V) is DD established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (V ) remains below the threshold I(SENSE) voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, t , is determined by an external d capacitor: t =2.1×104× C d T Where C isinfarads T t isinseconds d SPACER Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time,t ,hasexpired. d 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1994–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. DESCRIPTION (CONTINUED) In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By drivingthechipselect(CS)ofthememorycircuitwiththeRESEToutputoftheTLC77xxandwiththeCONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C; the TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C; and the TLC77xxM is characterized for operationoverthefullMilitarytemperaturerangeof–55°Cto125°C. The3x3mmDRBpackageisalsoavailableasanon-magneticpackageformedicalimagingapplication. AVAILABLEOPTIONS PACKAGEDDEVICES THRESHOLD TA VOL(TVA)GE OUTSLMINAELL(D)(1) CACRHRIPIER CERDAIPMIC CEDRUAAMLIC PLAS(TPI)CDIP SMTHAILNLSOHURTILNIKNE SMANLOLLOEUATDLINE (FK) (JG) FLATPACK(U) (PW)(2) (DRB) 1.1 TCLC7701ID — — — TCLC7701IP TCLC7701IPWR — 2.25 TLC7725ID — — — TLC7725IP TLC7725IPWR — –40°Cto 2.63 TLC7703ID — — — TLC7703IP TLC7703IPWR — 85°C 2.93 TLC7733ID — — — TLC7733IP TLC7733IPWR — 4.55 TLC7705ID — — — TLC7705IP TLC7705IPWR — 1.1 TLC7701IDBR — — — — — TLC7701IDRBT-NM 1.1 TLC7701QD — — — TLC7701QP TLC7701QPWR — 2.25 TLC7725QD — — — TLC7725QP TLC7725QPWR — –40°Cto 2.63 TLC7703QD — — — TLC7703QP TLC7703QPWR — 125°C 2.93 TLC7733QD — — — TLC7733QP TLC7733QPWR — 4.55 TLC7705QD — — — TLC7705QP TLC7705QPWR — –55°Cto 2.93 — — — — — — — 125°C 4.55 — — — — — — — (1) TheDpackageisavailabletapedandreeled.AddthesuffixRtothedevicetypewhenordering(e.g.,TLC7705QDR). (2) ThePWpackageisonlyavailableleft-endtapedandreeled(indicatedbytheRsuffixonthedevicetype;e.g.,TLC7705QPWR). Table1.FUNCTIONTABLE CONT RESIN V >V RESE RESET I(SENSE) IT+ ROL T L L False H L L L True H L L H False H L L H True L(1) H(1) H L False H L H L True H L H H False H L H H True H H(1) (1) RESETandRESETstatesshownarevalidfort>t . d 2 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 LOGIC SYMBOL (1) ThissymbolisinaccordancewithANSI/IEEEStd91-1984andIECPublication617-12. Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM 4 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT V Supplyvoltage(2) 7 V DD Inputvoltagerange,CONTROL,RESIN,SENSE(2) –0.3to7 V I Maximumlowoutputcurrent 10 mA OL I Maximumhighoutputcurrent, –10 mA OH I Inputclampcurrent,(VI<0orVI>VDD) ±10 mA IK I Outputclampcurrent,(VO0orVO>VDD) ±10 mA OK Continuoustotalpowerdissipation SeeDissipationRatingTable TL77xxI –40to84 °C Operatingfree-air T TL77xxQ –40to125 °C A temperaturerange TL77xxM –55to125 °C T Storagetemperaturerange –65to150 °C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoGND. DISSIPATION RATINGS T ≤25°C DERATINGFACTOR T =85°C T =125°C PACKAGE A A A POWERRATING ABOVET =25°C POWERRATING POWERRATING A D 725mW 5.8mW/°C 377mW 145mW DRB FK 1375mW 11.0mW/°C 715mW 275mW JG 1050mW 8.4mW/°C 546mW 210mW P 1000mW 8.0mW/°C 520mW 200mW PW 525mW 4.2mW/°C 273mW 105mW U 700mW 5.5mW/°C 370mW 150mW RECOMMENDED OPERATING CONDITIONS atspecifiedtemperaturerange MIN MAX UNIT V Supplyvoltage 2 6 V DD V Inputvoltage 0 V V I DD V High-levelinputvoltageatRESINandCONTROL(1) 0.7×V V IH DD V Low-levelinputvoltageatRESINandCONTROL(1) 0.2×V V IL DD I High-leveloutputcurrent –2 mA OH I Low-leveloutputcurrent 2 mA OL Δt/ΔV inputtransitionriseandfallrateatRESINandCONTROL 100 ns/V TLC77xxI –40 85 Operatingfree-air T TLC77xxQ –40 125 °C A temperaturerange TLC77xxM –55 125 (1) Toensurealowsupplycurrent,V shouldbekept<0.3VandV >V –0.3V. IL IH DD Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com ELECTRICAL CHARACTERISTICS overrecommendedoperatingconditions(1)(unlessotherwisenoted) TLC77xx PARAMETER TESTCONDITIONS UNIT MIN TYP MAX VDD=2V 1.8 High-leveloutput IOH=–20µA VDD=2.7V 2.5 VOH voltage VDD=4.5V 4.3 V IOH=2–mA VDD=4.5V 3.7 VDD=2V 0.2 Low-Leveloutput IOL=20µA VDD=2.7V 0.2 VOL voltage VDD=4.5V 0.2 V IOL=2mA VDD=4.5V 0.5 TCLC7701 1.04 1.1 1.16 TLC7725 2.18 2.25 2.32 Negative-goinginputthresholdvoltage, VIT– SENSE(2) TLC7703 VDD=2Vto6V 2.56 2.63 2.70 mV TLC7733 2.86 2.93 3 TLC7705 4.47 4.55 4.63 TCLC7701 30 TLC7725 Vhus Hysteresisvoltage,SENSE TLC7703 VDD=2Vto6V mV 70 TLC7733 TLC7705 Vres Power-upresetvoltage(3) IOL=20µA 1 V RESIN VI=0VtoVDD 2 CONTROL VI=VDD 7 15 II Inputcurrent µA SENSE VI=5V 5 10 SENSE,TLC7701only VI=5V 2 IDD Supplycurrent RCEOSNITNR=OVLD=D,0SVE,NOSuEtp=utVsDoDp≥enVITmax+0.2V, 9 16 µA VDD=5V,VCT=0, IDD(d) Supplycurrentduringtd RESIN=VDD,SENSE=VDD, 120 150 µA CONTROL=0V,Outputsopen CI Inputcapacitance,SENSE VI=0VtoVDD 50 pF (1) AllcharacteristicsaremeasuredwithC =0.1µF. T (2) Toensurebeststabilityofthethresholdvoltage,abypasscapacitor(ceramic,0.1mF)shouldbeconnectednearthesupplyterminals. (3) ThelowestsupplyvoltageatwhichRESETbecomesactive.ThesymbolV isnotcurrentlylistedwithinEIAorJEDECstandardsfor res semiconductorsymbology.RisetimeofV ≥15µs/V. DD 6 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 ELECTRICAL CHARACTERISTICS overrecommendedoperatingconditions(1)(unlessotherwisenoted) TLC77xxM PARAMETER TESTCONDITIONS UNIT MIN TYP(2) MAX T =25°C 1.8 A V =2V V DD T =–55°Cto125°C 1.7 A T =25°C 2.5 A I =–20µA V =2.7V V OH DD High-leveloutput TA=–55°Cto125°C 2.3 V OH voltage T =25°C 4.3 A V =4.5V V DD T =–55°Cto125°C 4.2 A T =25°C 3.7 A I =–2µA V =4.5V V OH DD T =–55°Cto125°C 3.6 A T =25°C 0.2 A V =2V V DD T =–55°Cto125°C 0.2 A T =25°C 0.2 A I =–20µA V =2.7V V OL DD Low-leveloutput TA=–55°Cto125°C 0.2 V OL voltage T =25°C 0.2 A V =4.5V V DD T =–55°Cto125°C 0.2 A I =2mA T =25°C 0.5 OL A V =4.5V V DD T =–55°Cto125°C 0.5 A Negative-goinginputthreshold TLC7733 2.86 2.93 3.1 VIT– voltage,SENSE (3) TLC7705 VDD=2Vto6V 4.3 4.5 4.8 V V Hysteresisvoltage,SENSE V =2Vto6V 70 mV hys DD V Power-upresetvoltage(2) I =20µA 1 V res OL RESIN V =0VtoV 2 I DD CONTROL V =V 7 15 I DD I Inputcurrent µA I SENSE V =5V 5 10 I SENSE,TLC7701only V =5V 2 I RESIN=VDD, SENSE=V ≥V max+0.2V I Supplycurrent DD IT 9 16 µA DD CONTROL=0V, Outputsopen TLC7733 V =0, V =3.3V 250 CT DD RESIN=VDD, 120 150 I Supplycurrentduringt CONTROL=0V, µA DD(d) d TLC7705 V =5V SENSE=V , DD DD Outputsopen C Inputcapacitance,SENSE V =0VtoV 50 pF I I DD (1) AllcharacteristicsaremeasuredwithC =0.1µF. T (2) TypicalvaluesapplyatT =25°C. A (3) Toensurebeststabilityofthethresholdvoltage,abypasscapacitor(ceramic,0.1mF)shouldbeconnectednearthesupplyterminals. Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com SWITCHING CHARACTERISTICS atV =5V,R =2kΩ,C =50pF,T =25°C(unlessotherwisenoted) DD L L A MEASURED TLC77xx PARAMETER FROM TO TESTCONDITIONS UNIT MIN TYP MAX (INPUT) (OUTPUT) RESET RESIN=0.7×VDD, td Delaytime VI(SENSE)≥VIT+ and CONTROL=0.2×VDD,CT=100nF, 1.1 2.1 4.2 ms RESET TA=Fullrange,Seetimingdiagram Propagationdelaytime,low- tPLH to-high-leveloutput 20 RESET Propagationdelaytime,high- tPHL to-low-leveloutput VIH=VIT+max+0.2V,VIL=VIT-min–0.2V, 5 SENSE RESIN=0.7×VDD,CONTROL=0.2×VDD, µs tPLH Ptor-ohpigahg-aletivoenldoeultapyuttime,low- CT=NC(1) 5 RESET Propagationdelaytime,high- tPHL to-low-leveloutput 20 Propagationdelaytime,low- tPLH to-high-leveloutput 20 µs RESET tPHL Ptor-olopwa-gleavtieolnoduetplauyttime,high- RESIN VSIEHN=S0E.7=×VVITD+mD,aVxIL+=00.2.2V×,VDD, 40 ns tPLH Ptor-ohpigahg-aletivoenldoeultapyuttime,low- CCOTN=TNRCO(1L)=0.2×VDD, 45 RESET Propagationdelaytime,high- tPHL to-low-leveloutput 20 µs Propagationdelaytime,low- tPLH to-high-leveloutput VIH=0.7×VDD,VIL=0.2×VDD, 38 ns CONTROL RESET SENSE=VIT+max+0.2V,RESIN=0.7×VDD, tPHL Ptor-olopwa-gleavtieolnoduetplauyttime,high- CT=NC(1) 38 ns Low-levelminimumpulse SENSE VIH=VIT+max+0.2V,VIL=VIT-min–0.2V, durationtoswitchRESET andRESET RESIN VIL=0.2×VDD,VIH=0.7×VDD tr Risetime RESET 10%to90% and tf Falltime RESET 90%to10% (1) NC=Nocapacitor,andincludesupto100-pFprobeandjigcapacitance. 8 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 SWITCHING CHARACTERISTICS atV =5V,R =2kΩ,C =50pF,T =25°C(unlessotherwisenoted) DD L L A MEASURED TLC77xxM PARAMETER FROM TO TESTCONDITIONS TA UNIT MIN TYP MAX (INPUT) (OUTPUT) RESET RESIN=2.7V,CONTROL=0.4V, td Delaytime VI(SENSE)≥VIT+ REaSndET CT=100nF,Seetimingdiagram Fullrange 1.1 2.1 4.2 ms 25°C 20 tPLH Ptoimurotepp,ualtgoawt-ioton-hdigehla-ylevel SENSE RESET VVRIIEHLS==INVVIIT=T-+m2min.7a-xV0+.,2C0VO.2,NVT,ROL=0.4V, Fu2ll5r°aCnge 245 µs RESET CT=NC(1) µs Fullrange 7 25°C 5 tPHL Ptoimurotepp,uahtgiagthio-tno-dloewla-ylevel SENSE RESET VVRIIEHLS==INVVIIT=T-+m2min.7a-xV0+.,2C0VO.2,NVT,ROL=0.4V, Fu2ll5r°aCnge 207 µs RESET CT=NC(1) µs Fullrange 24 25°C 20 tPLH Ptoimurotepp,ualtgoawt-ioton-hdigehla-ylevel RESIN RESET VSCIEOHNN=ST2ER.7O=VLV,=ITV+0ImL.4=axV0,+.40V.2, V, Fu2ll5r°aCnge 2445 µs RESET CT=NC(1) ns Fullrange 65 25°C 40 tPHL Ptoimurotepp,uahtgiagthio-tno-dloewla-ylevel RESIN RESET VSCIEOHNN=ST2ER.7O=VLV,=ITV+0ImL.4=axV0,+.40V.2, V, Fu2ll5r°aCnge 6200 ns RESET CT=NC(1) µs Fullrange 24 Propagationdelay 25°C 38 tPLH toimutep,ultow-to-high-level CONTROL RESET VSIEHN=S2E.7=VV,ITV+ImL=ax0+.40V.2, V, Fullrange 58 ns Propagationdelay RESIN=2.7V, 25°C 38 tPHL time,high-to-low-level CT=NC(1) ns output FullRange 58 Lpouwls-eledvuerlamtioinnimum SENSE VVIIHL==VVIITT-+mmina-x0+.20V.2V, Fullrange 3 µs RESIN VIL=0.4V,VIH=2.7V 1 tr Risetime RESET 10%to90% 8 and Fullrange ns/V tf Falltime RESET 90%to10% 4 (1) NC=Nocapacitor,andincludesupto100-pFprobeandjigcapacitance. Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure1. RESETandRESETOutputConfigurations Figure2. InputPulseDefinitionWaveforms 10 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 TYPICAL CHARACTERISTICS NORMALIZEDINPUTTHRESHOLDVOLTAGE SUPPLYCURRENT vs vs TEMPERATURE SUPPLYVOLTAGE Figure3. Figure4. HIGH-LEVELOUTPUTVOLTAGE LOW-LEVELOUTPUTVOLTAGE vs vs HIGH-LEVELOUTPUTCURRENT LOW-LEVELOUTPUTCURRENT Figure5. Figure6. Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com TYPICAL CHARACTERISTICS (continued) INPUTCURRENT MINIMUMPULSEDURATIONATSENSE vs vs INPUTVOLTAGEATSENSE SENSETHRESHOLDOVERDRIVE Figure7. Figure8. 12 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 www.ti.com SLVS087M–DECEMBER1994–REVISEDMARCH2012 APPLICATION INFORMATION Figure9. ResetControllerinaMicrocomputerSystem Figure10. DataRetentionDuringPowerDownUsingStaticCMOSRAMs Copyright©1994–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

TLC7701, TLC7725, TLC7703 TLC7733, TLC7705 SLVS087M–DECEMBER1994–REVISEDMARCH2012 www.ti.com ChangesfromRevisionL(February2003)toRevisionM Page • UpdatedtheDRBpackagePinOutdimensionsandOrderingInformation. ........................................................................ 1 14 SubmitDocumentationFeedback Copyright©1994–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TLC7701,TLC7725,TLC7703TLC7733,TLC7705

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9750901Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9750901Q2A TLC7733 MFKB 5962-9750901QPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9750901QPA TLC7733M 5962-9751301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9751301Q2A TLC7705 MFKB 5962-9751301QHA ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 9751301QHA TLC7705M 5962-9751301QPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9751301QPA TLC7705M TLC7701ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7701I & no Sb/Br) TLC7701IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7701I & no Sb/Br) TLC7701IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7701I & no Sb/Br) TLC7701IDRBT-NM ACTIVE SON DRB 8 250 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 7701N & no Sb/Br) TLC7701IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7701I & no Sb/Br) TLC7701IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7701IP & no Sb/Br) TLC7701IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7701 & no Sb/Br) TLC7701IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7701 & no Sb/Br) TLC7701IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7701 & no Sb/Br) TLC7701QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7701Q & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLC7701QDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7701Q & no Sb/Br) TLC7701QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7701Q & no Sb/Br) TLC7701QP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLC7701QP & no Sb/Br) TLC7701QPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD701 & no Sb/Br) TLC7701QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD701 & no Sb/Br) TLC7701QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD701 & no Sb/Br) TLC7701QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD701 & no Sb/Br) TLC7703ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7703I & no Sb/Br) TLC7703IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7703I & no Sb/Br) TLC7703IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7703IP & no Sb/Br) TLC7703IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM Y7703 & no Sb/Br) TLC7703IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM Y7703 & no Sb/Br) TLC7703IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7703 & no Sb/Br) TLC7703QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7703Q & no Sb/Br) TLC7703QDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7703Q & no Sb/Br) TLC7703QPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD703 & no Sb/Br) TLC7703QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD703 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLC7705ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7705I & no Sb/Br) TLC7705IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7705I & no Sb/Br) TLC7705IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7705IP & no Sb/Br) TLC7705IPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7705IP & no Sb/Br) TLC7705IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM Y7705 & no Sb/Br) TLC7705IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7705 & no Sb/Br) TLC7705MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9751301Q2A TLC7705 MFKB TLC7705MJG ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 TLC7705 MJG TLC7705MJGB ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9751301QPA TLC7705M TLC7705MUB ACTIVE CFP U 10 1 TBD Call TI N / A for Pkg Type -55 to 125 9751301QHA TLC7705M TLC7705QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7705Q & no Sb/Br) TLC7705QDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7705Q & no Sb/Br) TLC7705QPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD705 & no Sb/Br) TLC7705QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD705 & no Sb/Br) TLC7705QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD705 & no Sb/Br) TLC7725ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7725I & no Sb/Br) TLC7725IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7725I & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLC7725IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7725I & no Sb/Br) TLC7725IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7725I & no Sb/Br) TLC7725IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM Y7725 & no Sb/Br) TLC7725IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7725 & no Sb/Br) TLC7725QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7725Q & no Sb/Br) TLC7725QDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7725Q & no Sb/Br) TLC7725QDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7725Q & no Sb/Br) TLC7725QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD725 & no Sb/Br) TLC7725QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD725 & no Sb/Br) TLC7733ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7733I & no Sb/Br) TLC7733IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7733I & no Sb/Br) TLC7733IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7733I & no Sb/Br) TLC7733IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C7733I & no Sb/Br) TLC7733IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7733IP & no Sb/Br) TLC7733IPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC7733IP & no Sb/Br) TLC7733IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM Y7733 & no Sb/Br) TLC7733IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7733 & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TLC7733IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y7733 & no Sb/Br) TLC7733MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9750901Q2A TLC7733 MFKB TLC7733MJG ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 TLC7733 MJG TLC7733MJGB ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9750901QPA TLC7733M TLC7733QD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7733Q & no Sb/Br) TLC7733QDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7733Q & no Sb/Br) TLC7733QP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TLC7733QP & no Sb/Br) TLC7733QPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD733 & no Sb/Br) TLC7733QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD733 & no Sb/Br) TLC7733QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TD733 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC77 : •Automotive: TLC77-Q1 •Enhanced Product: TLC77-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 6

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC7701IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7701IDRBT-NM SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TLC7701IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7701QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7701QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7703IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7703IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7705IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7705IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7705QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7705QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7725IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7725IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7725QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7725QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7733IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC7733IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC7733QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC7733QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC7701IDR SOIC D 8 2500 350.0 350.0 43.0 TLC7701IDRBT-NM SON DRB 8 250 210.0 185.0 35.0 TLC7701IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7701QDR SOIC D 8 2500 350.0 350.0 43.0 TLC7701QPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7703IDR SOIC D 8 2500 350.0 350.0 43.0 TLC7703IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7705IDR SOIC D 8 2500 350.0 350.0 43.0 TLC7705IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7705QDR SOIC D 8 2500 350.0 350.0 43.0 TLC7705QPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7725IDR SOIC D 8 2500 350.0 350.0 43.0 TLC7725IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7725QDR SOIC D 8 2500 350.0 350.0 43.0 TLC7725QPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7733IDR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC7733IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC7733QDR SOIC D 8 2500 367.0 367.0 35.0 TLC7733QPWR TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page3

PACKAGE OUTLINE U0010A CFP - 2.03 mm max height SCALE 1.400 CERAMIC FLATPACK .27 MAX .045 MAX .010 .002 PIN 1 ID GLASS .005 MIN TYP TYP 1 10 8X .050 .005 .27 MAX GLASS 10X .017 .002 5 6 +.019 5X .32 .01 .241 5X .32 .01 -.003 .005 .001 +.013 .067 -.012 .045 .026 4225582/A 01/2020 NOTES: 1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

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PACKAGE OUTLINE DRB0008A VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C DIM A 0.00 OPT 1 OPT 2 1.5 0.1 (0.1) (0.2) 4X (0.23) EXPOSED (DIM A) TYP THERMAL PAD 4 5 2X 1.95 1.75 0.1 8 1 6X 0.65 0.37 8X 0.25 PIN 1 ID 0.1 C A B (OPTIONAL) (0.65) 0.05 C 0.5 8X 0.3 4218875/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.5) (0.65) SYMM 8X (0.6) (0.825) 8X (0.31) 1 8 SYMM (1.75) (0.625) 6X (0.65) 4 5 (R0.05) TYP ( 0.2) VIA TYP (0.23) (0.5) (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218875/A 01/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.65) 4X (0.23) SYMM METAL TYP 8X (0.6) 4X (0.725) 8X (0.31) 1 8 (2.674) SYMM (1.55) 6X (0.65) 4 5 (R0.05) TYP (1.34) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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