TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 (cid:1) Eight 8-Bit Voltage Output DACs N OR DW PACKAGE (cid:1) 5-V Single-Supply Operation (TOP VIEW) (cid:1) Serial Interface (cid:1) DACB 1 16 DACC High-Impedance Reference Inputs DACA 2 15 DACD (cid:1) Programmable 1 or 2 Times Output Range GND 3 14 REF1 (cid:1) Simultaneous Update Facility DATA 4 13 LDAC (cid:1) Internal Power-On Reset CLK 5 12 LOAD (cid:1) Low-Power Consumption VDD 6 11 REF2 DACE 7 10 DACH (cid:1) Half-Buffered Output DACF 8 9 DACG applications (cid:1) Programmable Voltage Sources (cid:1) Digitally Controlled Amplifiers/Attenuators (cid:1) Mobile Communications (cid:1) Automatic Test Equipment (cid:1) Process Monitoring and Control (cid:1) Signal Synthesis description The TLC5628C and TLC5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two times the reference voltages and GND and are monotonic. The device is simple to use, running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5628C and TLC5628I are over a simple three-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word comprises eightbits of data, three DAC select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high-noise immunity. The 16-terminal small-outline (D) package allows digital control of analog functions in space-critical applications. The TLC5628C is characterized for operation from 0°C to 70°C. The TLC5628I is characterized for operation from –40°C to 85°C. The TLC5628C and TLC5628I do not require external trimming. AVAILABLE OPTIONS PACKAGE SMALL OUTLINE PLASTIC DIP TA (DW) (N) 0°C to 70°C TLC5628CDW TLC5628CN –40°C to 85°C TLC5628IDW TLC5628IN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 functional block diagram 14 REF1 + – DAC + 2 9 8 × 2 – DACA Latch Latch DAC + 15 8 × 2 – DACD Latch Latch REF2 11 + – DAC + 7 8 × 2 – DACE Latch Latch DAC + 10 8 × 2 – DACH Latch Latch 5 CLK 4 Serial Power-On DATA Interface 13 Reset 12 LOAD LDAC Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. CLK 5 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock applied to the CLK terminal. DACA 2 O DAC A analog output DACB 1 O DAC B analog output DACC 16 O DAC C analog output DACD 15 O DAC D analog output DACE 7 O DAC E analog output DACF 8 O DAC F analog output DACG 9 O DAC G analog output DACH 10 O DAC H analog output DATA 4 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially. Each data bit is clocked into the register on the falling edge of the clock signal. GND 3 I Ground return and reference terminal LDAC 13 I Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is taken from high to low. LOAD 12 I Serial interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data into the output latch and immediately produces the analog voltage at the DAC output terminal. REF1 14 I Reference voltage input to DAC ABCD. This voltage defines the analog output range. REF2 11 I Reference voltage input to DAC EFGH. This voltage defines the analog output range. VDD 6 I Positive supply voltage 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 detailed description The TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2 is used by DACE through DACH. Each DAC output is buffered by a configurable-gain output amplifier, that can be programmed to times 1 or times 2 gain. On power up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D|E|F|G|H)(cid:3)REF(cid:1)CODE(cid:1)(1(cid:2)RNG bit value) O 256 where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word. Table 1. Ideal Output Transfer D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE 0 0 0 0 0 0 0 0 GND 0 0 0 0 0 0 0 1 (1/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 0 1 1 1 1 1 1 1 (127/256) × REF (1+RNG) 1 0 0 0 0 0 0 0 (128/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG) data interface With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4. CLK tsu(DATA-CLK) tsu(LOAD-CLK) tv(DATA-CLK) DATA A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0 tsu(CLK-LOAD) tw(LOAD) LOAD DAC Update Figure 1. LOAD-Controlled Update (LDAC = Low) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 data interface (continued) CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0 tsu(LOAD–LDAC) LOAD tw(LDAC) LDAC DAC Update Figure 2. LDAC-Controlled Update CLK Low CLK ÎÎÎÎÎ ÎÎÎ ÎÎÎ DATA A2 A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0 ÎÎÎÎÎ ÎÎÎ ÎÎÎ LOAD LDAC Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low) CLK Low CLK ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ DATÎA ÎÎÎÎ A2 A1 A0 RNÎG ÎÎÎD7 D6 D5 D4 D3 D2 D1 D0 ÎÎÎÎ LOAD LDAC Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 2. Serial Input Decode A2 A1 A0 DAC UPDATED 0 0 0 DACA 0 0 1 DACB 0 1 0 DACC 0 1 1 DACD 1 0 0 DACE 1 0 1 DACF 1 1 0 DACG 1 1 1 DACH 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 linearity, offset, and gain error using single-end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground. The output voltage remains at 0 V until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown in Figure 5. Output Voltage 0 V DAC Code Negative Offset Figure 5. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces the breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground. For a DAC, linearity is measured between the zero-input code (all inputs are 0) and the full-scale code (all inputs are 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full-scale code and the lowest code that produces a positive output voltage. The code is calculated from the maximum specification for the negative offset voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 equivalent of inputs and outputs INPUT CIRCUIT OUTPUT CIRCUIT VDD VDD _ Input from Decoded DAC + DAC Register String Vref × 1 Voltage Output Input Output 84 kW To DAC Resistor Range × 2 ISINK String Select 60 m A 84 kW Typical GND GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (V – GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V + 0.3 V ID DD Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V + 0.3 V DD Operating free-air temperature range, T :TLC5628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A TLC5628I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 4.75 5.25 V High-level voltage, VIH 0.8 VDD V Low-level voltage, VIL 0.8 V Reference voltage, Vref [A|B|C|D|E|F|G|H] VDD–1.5 V Analog full-scale output voltage, RL = 10 kW 3.5 V Load resistance, RL 10 kW Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) 50 ns Valid time, data input valid after CLK↓, tv(DATA-CLK) (see Figures 1 and 2) 50 ns Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) 50 ns Setup time, LOAD↑ to CLK↓, tsu(LOAD-CLK) (see Figure 1) 50 ns Pulse duration, LOAD, tw(LOAD) (see Figure 1) 250 ns Pulse duration, LDAC, tw(LDAC) (see Figure 2) 250 ns Setup time, LOAD↑ to LDAC↓, tsu(LOAD-LDAC) (see Figure 2) 0 ns CLK frequency 1 MHz TLC5628C 0 70 °C OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTAA TLC5628I –40 85 °C 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 electrical characteristics over recommended operating free-air temperature range, V = 5 V ± 5%, DD V = 2 V, × 1 gain output range (unless otherwise noted) ref PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level input current VI = VDD ±10 m A IIL Low-level input current VI = 0 V ±10 m A IO(sink) Output sink current 20 m A EEaacchh DDAACC oouuttppuutt IO(source) Output source current 2 mA Input capacitance 15 CCii ppFF Reference input capacitance 15 IDD Supply current VDD = 5 V 4 mA Iref Reference input current VDD = 5 V, Vref = 2 V ±10 m A EL Linearity error (end point corrected) Vref = 2 V, ×2 gain (see Note 1) ±1 LSB ED Differential-linearity error Vref = 2 V, ×2 gain (see Note 2) ±0.9 LSB EZS Zero-scale error Vref = 2 V, ×2 gain (see Note 3) 0 30 mV Zero-scale-error temperature coefficient Vref = 2 V, ×2 gain (see Note 4) 10 m V/°C EFS Full-scale error Vref = 2 V, ×2 gain (see Note 5) ±60 mV Full-scale-error temperature coefficient Vref = 2 V, ×2 gain (see Note 6) ±25 m V/°C PSRR Power supply rejection ratio See Notes 7 and 8 0.5 mV/V NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 kW . 6. Full-scale error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage. operating characteristics over recommended operating free-air temperature range, V = 5 V ± 5%, DD V = 2 V, × 1 gain output range (unless otherwise noted) ref TEST CONDITIONS MIN TYP MAX UNIT Output slew rate CL = 100 pF, RL = 10 kW 1 V/m s Output settling time To ±0.5 LSB, CL = 100 pF, RL = 10 kW , See Note 9 10 m s Large signal bandwidth Measured at –3 dB point 100 kHz Digital crosstalk CLK = 1-MHz square wave measured at DACA-DACD –50 dB Reference feedthrough See Note 10 –60 dB Channel-to-channel isolation See Note 11 –60 dB Reference input bandwidth See Note 12 100 kHz NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ±0.5 LSB starting from an initial output voltage equal to zero. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 Vpp at 10 kHz. 12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital input code. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION TLC5628 DACA DACB • • 10 kW CL = 100 pF • DACH Figure 6. Slew, Settling Time, and Linearity Measurements TYPICAL CHARACTERISTICS POSITIVE RISE AND SETTLING TIME NEGATIVE FALL AND SETTLING TIME LDAC LDAC 6 6 VDD = 5 V e – V VTCADo dD=e =2 05 50° CVto FF Hex e – V TCRAoa nd=ge 2 eF5 =F°C ×to2 00 Hex g 4 Range = ×2 g 4 a a Vref = 2 V olt Vref = 2 V olt V V ut ut p p ut ut O 2 O 2 – – O O V V 0 0 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 t – Time – m s t – Time – m s Figure 7 Figure 8 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 TYPICAL CHARACTERISTICS DAC OUTPUT VOLTAGE DAC OUTPUT VOLTAGE vs vs OUTPUT LOAD OUTPUT LOAD 4 5 4.8 3.5 V 4.6 – – V ge 3 Voltage 44..42 ut Volta 2.5 put 4 Outp 2 Out C A C 3.8 D 1.5 A – D – O 3.6 VDD = 5 V, VO 1 V 3.4 Vref = 2.5 V, VDD = 5 V, Range = 2x Vref = 3.5 V, 0.5 3.2 Range = 1x 3 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 RL – Output Load – kW RL – Output Load – kW Figure 9 Figure 10 OUTPUT SOURCE CURRENT SUPPLY CURRENT vs vs OUTPUT VOLTAGE TEMPERATURE 8 1.2 VDD = 5 V A 7 TA = 25°C 1.15 m Vref = 2 V – Range = ×2 nt 6 Input Code = 255 A 1.1 e m VDD = 5 V e Curr 5 ent – 1.05 RInapnugt eC =o d×e2 = 255 Vref = 2V ourc Curr 1 S 4 y utput 3 Suppl 0.95 O – – D ce) 2 ID 0.9 r u o s 0.85 O( 1 I 0.8 0 –50 0 50 100 0 1 2 3 4 5 t – Temperature – °C VO – Output Voltage – V Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 TYPICAL CHARACTERISTICS RELATIVE GAIN RELATIVE GAIN vs vs FREQUENCY FREQUENCY 0 10 –2 0 –4 B –10 B –6 d ain – d –8 Gain – –20 e G –10 ve elativ –12 Relati –30 G – R –14 G – –40 VTAD D= =25 5° CV Vref = 2 Vdc + 0.5 Vpp –16 VDD = 5 V Input Code = 255 TA = 25°C –50 –18 Vref = 1.25 Vdc + 2 Vpp Input Code = 255 –60 –20 1 10 100 1000 10000 1 10 100 1000 f – Frequency – kHz f – Frequency – kHz Figure 13 Figure 14 APPLICATION INFORMATION TLC5628 _ VO DACA + DACB • R • • DACH NOTE A: Resistor R (cid:1) 10 kW Figure 15. Output Buffering Scheme 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 DIM 0.020 (0,51) 0.010 (0,25) M 0.410 0.510 0.610 0.710 0.014 (0,35) A MAX (10,41) (12,95) (15,49) (18,03) 16 9 0.400 0.500 0.600 0.700 A MIN (10,16) (12,70) (15,24) (17,78) 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.010 (0,25) NOM 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°–8° 0.050 (1,27) A 0.016 (0,40) Seating Plane 0.012 (0,30) 0.004 (0,10) 0.104 (2,65) MAX 0.004 (0,10) 4040000/B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 DIM 0.775 0.775 0.920 0.975 A A MAX (19,69) (19,69) (23.37) (24,77) 16 9 0.745 0.745 0.850 0.940 A MIN (18,92) (18,92) (21.59) (23,88) 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.310 (7,87) 0.035 (0,89) MAX 0.020 (0,51) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0°–15° 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 2-Jan-2007 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty TLC5628CDW ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628CDWG4 ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628CDWR ACTIVE SOIC DW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628CDWRG4 ACTIVE SOIC DW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628CN ACTIVE PDIP N 16 25 Pb-Free CUNIPD N/AforPkgType (RoHS) TLC5628CNE4 ACTIVE PDIP N 16 25 Pb-Free CUNIPD N/AforPkgType (RoHS) TLC5628IDW ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628IDWG4 ACTIVE SOIC DW 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628IDWR ACTIVE SOIC DW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628IDWRG4 ACTIVE SOIC DW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TLC5628IN ACTIVE PDIP N 16 25 Pb-Free CUNIPD N/AforPkgType (RoHS) TLC5628INE4 ACTIVE PDIP N 16 25 Pb-Free CUNIPD N/AforPkgType (RoHS) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 2-Jan-2007 InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) TLC5628CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TLC5628IDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC5628CDWR SOIC DW 16 2000 346.0 346.0 33.0 TLC5628IDWR SOIC DW 16 2000 346.0 346.0 33.0 PackMaterials-Page2

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