TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 10-BIT DIGITAL-TO-ANALOG CONVERTERS FEATURES DESCRIPTION • 10-BitCMOSVoltageOutputDACinan The TLC5615 is a 10-bit voltage output 8-TerminalPackage digital-to-analog converter (DAC) with a buffered • 5VSingleSupplyOperation reference input (high impedance). The DAC has an output voltage range that is two times the reference • 3-WireSerialInterface voltage, and the DAC is monotonic. The device is • High-ImpedanceReferenceInputs simple to use, running from a single supply of 5V. A • VoltageOutputRange:2TimestheReference power-on-reset function is incorporated to ensure InputVoltage repeatablestart-upconditions. • InternalPower-OnReset Digital control of the TLC5615 is over a three-wire • LowPowerConsumption:1.75mWMax serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and • UpdateRateof1.21MHz microcontroller devices. The device receives a 16-bit • SettlingTimeto0.5LSB:12.5m sTyp data word to produce the analog output. The digital • MonotonicOverTemperature inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include • Pin-CompatibleWiththeMaximMAX515 theSPI™,QSPI™,andMicrowire™standards. APPLICATIONS The 8-terminal small-outline D package allows digital • Battery-PoweredTestInstruments control of analog functions in space-critical applications. The TLC5615C is characterized for • DigitalOffsetandGainAdjustment operation from 0(cid:176) C to +70(cid:176) C. The TLC5615I is • BatteryOperated/RemoteIndustrialControls characterizedforoperationfrom–40(cid:176) Cto+85(cid:176) C. • MachineandMotionControlDevices • CellularTelephones D,P,ORDGKPACKAGE (TOPVIEW) DIN 1 8 VDD SCLK 2 7 OUT CS 3 6 REFIN DOUT 4 5 AGND Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPI,QSPIaretrademarksofMotorola,Inc. MicrowireisatrademarkofNationalSemiconductorCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1996–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONALBLOCKDIAGRAM _ REFIN + DAC + _(cid:1)2 OUT (Voltage Output) AGND R R Power-ON Reset 10-Bit DAC Register Control CS Logic 2 (LSB) (MSB) 4 SCLK 0s Dummy 10 Data Bits Bits DIN 16-Bit Shift Register DOUT TerminalFunctions TERMINAL I/O DESCRIPTION NAME NO. DIN 1 I Serialdatainput SCLK 2 I Serialclockinput CS 3 I Chipselect,activelow DOUT 4 O Serialdataoutputfordaisychaining AGND 5 Analogground REFIN 6 I Referenceinput OUT 7 O DACanalogvoltageoutput V 8 Positivepowersupply DD PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document,orseetheTIwebsiteatwww.ti.com. 2 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) UNIT Supplyvoltage(V toAGND) 7V DD DigitalinputvoltagerangetoAGND –0.3VtoV +0.3V DD ReferenceinputvoltagerangetoAGND –0.3VtoV +0.3V DD OutputvoltageatOUTfromexternalsource V +0.3V DD Continuouscurrentatanyterminal – 20mA Operatingfree-airtemperaturerange,T TLC5615C 0(cid:176) Cto+70(cid:176) C A TLC5615I –40(cid:176) Cto+85(cid:176) C Storagetemperaturerange,T –65(cid:176) Cto+150(cid:176) C stg Leadtemperature1,6mm(1/16inch)fromcasefor10seconds +260(cid:176) C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,V 4.5 5 5.5 V DD High-leveldigitalinputvoltage,V 2.4 V IH Low-leveldigitalinputvoltage,V 0.8 V IL Referencevoltage,V toREFINterminal 2 2.048 V –2 V ref DD Loadresistance,R 2 kW L TLC5615C 0 70 (cid:176) C Operatingfree-airtemperature,T A TLC5615I 40 85 (cid:176) C ELECTRICAL CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,V =5V– 5%,V =2.048V(unlessotherwisenoted) DD ref STATICDACSPECIFICATIONS PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Resolution 10 bits Integralnonlinearity,endpointadjusted(INL) V =2.048V, See (1) – 1 LSB ref Differentialnonlinearity(DNL) V =2.048V, See (2) – 0.1 – 0.5 LSB ref E Zero-scaleerror(offseterroratzeroscale) V =2.048V, See (3) – 3 LSB ZS ref Zero-scale-errortemperaturecoefficient V =2.048V, See (4) 3 ppm/(cid:176) C ref E Gainerror V =2.048V, See (5) – 3 LSB G ref Gain-errortemperaturecoefficient V =2.048V, See (6) 1 ppm/(cid:176) C ref Zeroscale 80 PSRR Power-supplyrejectionratio See (7)(8) dB Gain 80 Analogfullscaleoutput R =100kW 2V (1023/1024) V L ref (1) Therelativeaccuracyorintegralnonlinearity(INL),sometimesreferredtoaslinearityerror,isthemaximumdeviationoftheoutputfrom thelinebetweenzeroandfullscaleexcludingtheeffectsofzerocodeandfull-scaleerrors(seetext).Testedfromcode3tocode1024. (2) Thedifferentialnonlinearity(DNL),sometimesreferredtoasdifferentialerror,isthedifferencebetweenthemeasuredandideal1LSB amplitudechangeofanytwoadjacentcodes.Monotonicmeanstheoutputvoltagechangesinthesamedirection(orremainsconstant) asachangeinthedigitalinputcode.Testedfromcode3tocode1024. (3) Zero-scaleerroristhedeviationfromzero-voltageoutputwhenthedigitalinputcodeiszero(seetext). (4) Zero-scale-errortemperaturecoefficientisgivenby:E TC=[E (T )–E (T )]/V · 106/(T –T ). ZS ZS max ZS min ref max min (5) Gainerroristhedeviationfromtheidealoutput(V –1LSB)withanoutputloadof10kW excludingtheeffectsofthezero-scaleerror. ref (6) Gaintemperaturecoefficientisgivenby:E TC=[E (T )–E (T )]/V · 106/(T –T ). G G max G min ref max min (7) Zero-scale-errorrejectionratio(EZS-RR)ismeasuredbyvaryingtheV from4.5Vto5.5Vdcandmeasuringtheproportionofthis DD signalimposedonthezero-codeoutputvoltage. (8) Gain-errorrejectionratio(EG-RR)ismeasuredbyvaryingtheV from4.5Vto5.5Vdcandmeasuringtheproportionofthissignal DD imposedonthefull-scaleoutputvoltageaftersubtractingthezero-scalechange. SubmitDocumentationFeedback 3

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 VOLTAGE OUTPUT (OUT) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Voltageoutputrange R =10kW 0 V –0.4 V O L DD Outputloadregulationaccuracy V =2V, R =2kW 0.5 LSB O(OUT) L I Outputshortcircuitcurrent OUTtoV orAGND 20 mA OSC DD V Outputvoltage,low-level I £ 5mA 0.25 V OL(low) O(OUT) V Outputvoltage,high-level I £ –5mA 4.75 V OH(high) O(OUT) REFERENCEINPUT(REFIN) V Inputvoltage 0 V –2 V I DD r Inputresistance 10 MW i C Inputcapacitance 5 pF i DIGITALINPUTS(DIN,SCLK,CS) V High-leveldigitalinputvoltage 2.4 V IH V Low-leveldigitalinputvoltage 0.8 V IL I High-leveldigitalinputcurrent V =V – 1 m A IH I DD I Low-leveldigitalinputcurrent V =0 –1 m A IL I C Inputcapacitance 8 pF i DIGITALOUTPUT(DOUT) V Outputvoltage,high-level I =–2mA V –1 V OH O DD V Outputvoltage,low-level I =2mA 0.4 V OL O POWERSUPPLY V Supplyvoltage 4.5 5 5.5 V DD VDD=5.5V,Noload, V =0 150 250 m A Allinputs=0VorV ref DD I Powersupplycurrent DD VDD=5.5V,Noload, V =2.048V 230 350 m A Allinputs=0VorV ref DD ANALOGOUTPUTDYNAMICPERFORMANCE V =1V at1kHz+2.048Vdc, Signal-to-noise+distortion,S/(N+D) ref PP 60 dB code=1111111111(1) (1) Thelimitingfrequencyvalueat1V isdeterminedbytheoutput-amplifierslewrate. PP DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1) PARAMETER MIN NOM MAX UNIT t Setuptime,DINbeforeSCLKhigh 45 ns su(DS) t Holdtime,DINvalidafterSCLKhigh 0 ns h(DH) t Setuptime,CSlowtoSCLKhigh 1 ns su(CSS) t Setuptime,CShightoSCLKhigh 50 ns su(CS1) t Holdtime,SCLKlowtoCSlow 1 ns h(CSH0) t Holdtime,SCLKlowtoCShigh 0 ns h(CSH1) t Pulseduration,minimumchipselectpulsewidthhigh 20 ns w(CS) t Pulseduration,SCLKlow 25 ns w(CL) t Pulseduration,SCLKhigh 25 ns w(CH) OUTPUT SWITCHING CHARACTERISTICS PARAMETER TESTCONDITIONS MIN NOM MAX UNIT t Propagationdelaytime,DOUT C =50pF 50 ns pd(DOUT) L 4 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 OPERATING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,V =5V– 5%,V =2.048V(unlessotherwisenoted) DD ref PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGOUTPUTDYNAMICPERFORMANCE SR Outputslewrate CTL==+12050(cid:176)pCF, RL=10kW , 0.3 0.5 V/m s A ts Outputsettlingtime TRo=0.51L0SkWB,, CL=100pF, (1) 12.5 m s L Glitchenergy DIN=All0stoall1s 5 nV-s REFERENCEINPUT(REFIN) Referencefeedthrough REFIN=1V at1kHz+2.048Vdc (2) –80 dB PP Referenceinput REFIN=0.2V +2.048Vdc 30 kHz bandwidth(f–3dB) PP (1) Settlingtimeisthetimefortheoutputsignaltoremainwithin– 0.5LSBofthefinalmeasuredvalueforadigitalinputcodechangeof000 hexto3FFhexor3FFhexto000hex. (2) ReferencefeedthroughismeasuredattheDACoutputwithaninputcode=000hexandaV input=2.048Vdc+1V at1kHz. ref pp PARAMETER MEASUREMENT INFORMATION CS th(CSH0) tsu(CSS) tw(CS) ÎÎÎ tw(CH) tw(CL) th(CSH1) ÎÎÎtsu(CÎS1) ÎÎÎ ÎÎÎÎ SCLK ÎÎÎ ÎÎÎÎ ÎSee ÎNoteÎ A See Note C ÎSÎee NÎoteÎ A ÎÎÎtsÎu(DSÎ) th(DH) ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ DÎIN ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ tpd(DOUT) DOUT Previous LSB MSB LSB See Note B NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge Figure1.TimingDiagram SubmitDocumentationFeedback 5

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 TYPICAL CHARACTERISTICS OUTPUTSINKCURRENT OUTPUTSOURCECURRENT vs vs OUTPUTPULLDOWNVOLTAGE OUTPUTPULLUPVOLTAGE 20 30 18 VDD = 5 V VDD = 5 V VREFIN = 2.048 V VREFIN = 2.048 V 16 TA = 25°C A 25 TA = 25°C m ent - mA 1142 urrent - 20 r C ur e k C 10 urc 15 n o Si S ut 8 ut utp 6 utp 10 O O - O 4 - O I I 5 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 VO - Output Pulldown Voltage - V VO - Output Pullup Voltage - V Figure2. Figure3. SUPPLYCURRENT V TOV RELATIVEGAIN REFIN (OUT) vs vs TEMPERATURE INPUTFREQUENCY 280 4 VDD = 5 V 2 VREFIN = 0.2 VPP + 2.048 V dc 240 TA = 25°C 0 A 200 m B nt - - d -2 e n Curr 160 Gai -4 pply 120 ative -6 u el S R - - -8 D 80 G D I -10 VDD = 5 V 40 VREFIN = 2.048 V -12 TA = 25°C 0 -14 -60 -40 -20 0 20 40 60 80 100 120 140 1 100 1 k 10 k 100 k t - Temperature - °C fI - Input Frequency - Hz Figure4. Figure5. 6 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE+DISTORTION vs INPUTFREQUENCYATREFIN 70 VDD = 5 V 60 TA = 25°C B VREFIN = 4 VPP d - n 50 o rti o Dist 40 + e s oi 30 N o- T al- 20 n g Si 10 0 1 k 10 k 100 k 300 k Frequency - Hz Figure6. 0.2 B S 0.15 L – y 0.1 rit a 0.05 e n nli 0 o N al –0.05 nti –0.1 e r Diffe–0.15 –0.2 0 255 511 767 1023 Input Code Figure7. DifferentialNonlinearityWithInputCode 1 B 0.8 S L 0.6 – y 0.4 arit 0.2 e n 0 nli o –0.2 N al –0.4 r g –0.6 e nt –0.8 I –1 0 255 511 767 1023 Input Code Figure8. IntegralNonlinearityWithInputCode SubmitDocumentationFeedback 7

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 APPLICATION INFORMATION GENERAL FUNCTION The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the samepolarityasthereferenceinput(seeTable1). AninternalcircuitresetstheDACregistertoallzerosonpowerup. DIN SCLK CS DOUT REFIN + Resistor + _ String _ OUT DAC R R AGND VDD 5 V 0.1 m F Figure9.TLC5615TypicalOperatingCircuit Table1.BinaryCodeTable(0Vto2V Output) Gain=2 REFIN , INPUT(1) OUTPUT 1111 1111 11(00) 2(cid:1)V (cid:2)1023 REFIN 1024 : : 1000 0000 01(00) 2(cid:1)V (cid:2) 513 REFIN 1024 1000 0000 00(00) 2(cid:2)VREFIN(cid:3)1501224(cid:1)VREFIN 0111 1111 11(00) 2(cid:1)V (cid:2)511 REFIN 1024 : : 0000 0000 01(00) 2(cid:1)V (cid:2) 1 REFIN 1024 0000 0000 00(00) 0V (1) A10-bitdatawordwithtwobitsbelowtheLSBbit(sub-LSB)with0valuesmustbewrittensincetheDACinputlatchis12bitswide. 8 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 BUFFER AMPLIFIER Theoutputbuffer has a rail-to-rail output with short circuit protection and can drive a 2kW load with a 100pF load capacitance.Settlingtimeis12.5m stypicaltowithin0.5LSBoffinalvalue. EXTERNAL REFERENCE The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10MW and the REFIN input capacitance is typically 5pF independent of input code.ThereferencevoltagedeterminestheDACfull-scaleoutput. LOGIC INTERFACE The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels. SERIAL CLOCK AND UPDATE RATE Figure1showstheTLC5615timing.Themaximumserialclockrateis: 1 f(SCLK)max (cid:2) tw(cid:3)CH(cid:4)(cid:1)tw(cid:3)CL(cid:4) orapproximately14MHz.Thedigitalupdaterateislimitedbythechip-selectperiod,whichis: (cid:4) (cid:5) tp(CS) (cid:3)16(cid:1) tw(cid:4)CH(cid:5)(cid:2)tw(cid:4)CL(cid:5) (cid:2)tw(cid:4)CS(cid:5) andisequalto820nswhichisa1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5m s limits theupdaterateto80kHzforfull-scaleinputsteptransitions. SERIAL INTERFACE When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significantbitfirst.TherisingedgeoftheSLCKinputshiftsthedataintotheinputregister. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clockedintotheinputregister.AllCStransitionsshouldoccurwhentheSCLKinputislow. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequencewiththeMSBfirstcanbeusedasshowninFigure10: 12 Bits 10 Data Bits x x MSB LSB 2 Extra (Sub-LSB) Bits x = don’t care Figure10.12-BitInputDataSequence or16bitsofdatacanbetransferredasshowninFigure11withthe4upperdummybitsfirst. 16 Bits 4 Upper Dummy Bits 10 Data Bits x x MSB LSB 2 Extra (Sub-LSB) Bits x = don’t care Figure11.16-BitInputDataSequence SubmitDocumentationFeedback 9

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. WhendaisychainingmultipleTLC5615devices,thedatarequires4upperdummybits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal(seeFigure1). Thetwo extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data convertertransfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The hardwareconnectionsareshowninFigure12andFigure13. The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC inputregisterinonewritecycle. SCLK SK DIN SO Microwire TLC5615 Port CS I/O DOUT SI NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired. Figure12.MicrowireConnection SCLK SCK DIN MOSI TLC5615 SPI/QSPI CS I/O Port DOUT MISO CPOL = 0, CPHA = 0 NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer. Figure13.SPI/QSPIConnection DAISY-CHAINING DEVICES DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, t (CS low to SCLK high), is greater than the sum of the setup time, su(CSS) t , plus the propagation delay time, t , for proper timing (see digital input timing requirements section). su(DS) pd(DOUT) The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT remainsatthevalueofthelastdatabitanddoesnotgointoahigh-impedancestate. LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltagemaynotchangewiththefirstcodedependingonthemagnitudeoftheoffsetvoltage. 10 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supplyrailisground,theoutputcannotdrivebelowgroundandclampstheoutputat0V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage toovercomethenegativeoffsetvoltage,resultinginthetransferfunctionshowninFigure14. Output Voltage 0 V DAC Code Negative Offset Figure14.EffectofNegativeOffset(SingleSupply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dottedlineiftheoutputbuffercoulddrivebelowthegroundrail. For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. For the TLC5615, the zero-scale (offset) error is – 3LSB maximum. The code is calculated from the maximum specificationforthenegativeoffset. POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT Printed circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connectingtheDACAGNDterminaltothesystemanaloggroundplanemakingsure that analog ground currents arewellmanagedandtherearenegligiblevoltagedropsacrossthegroundplane. A 0.1m F ceramic-capacitor bypass should be connected between V and AGND and mounted with short leads DD as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digitalpowersupply. Figure15showsthegroundplanelayoutandbypassingtechnique. Analog Ground Plane 1 8 2 7 0.1 m F 3 6 4 5 Figure15.Power-SupplyBypassing SAVING POWER Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output loadwhenthesystemisnotusingtheDAC. SubmitDocumentationFeedback 11

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 AC CONSIDERATIONS DigitalFeedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthroughistestedbyholdingCShighandtransmitting0101010101fromDINtoDOUT. AnalogFeedthrough Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to REFIN,andmonitoringtheDACoutput. 12 SubmitDocumentationFeedback

TLC5615C, TLC5615I www.ti.com SLAS142E–OCTOBER1996–REVISEDJUNE2007 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromDRevision(August2003)toERevision ............................................................................................... Page • AddedESDstatement.......................................................................................................................................................... 2 • Changed—movedpackageoptiontablefromfrontpage.................................................................................................... 2 SubmitDocumentationFeedback 13

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC5615CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 5615C & no Sb/Br) TLC5615CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 5615C & no Sb/Br) TLC5615CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM 0 to 70 AEM & no Sb/Br) TLC5615CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM 0 to 70 AEM & no Sb/Br) TLC5615CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 5615C & no Sb/Br) TLC5615CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC5615CP & no Sb/Br) TLC5615ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 5615I & no Sb/Br) TLC5615IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 85 AEN & no Sb/Br) TLC5615IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 85 AEN & no Sb/Br) TLC5615IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 5615I & no Sb/Br) TLC5615IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 5615I & no Sb/Br) TLC5615IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC5615IP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC5615CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLC5615CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC5615IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC5615CDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 TLC5615CDR SOIC D 8 2500 340.5 338.1 20.6 TLC5615IDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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