(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 (cid:1) Trimmed Offset Voltage: (cid:1) Low Noise...Typically 32 nV/√Hz at TLC27M7...500 µV Max at 25°C, f = 1 kHz VDD = 5 V (cid:1) Low Power...Typically 2.1 mW at 25°C, (cid:1) Input Offset Voltage Drift...Typically V = 5 V DD 0.1 µV/Month, Including the First 30 Days (cid:1) Output Voltage Range Includes Negative (cid:1) Wide Range of Supply Voltages Over Rail Specified Temperature Ranges: (cid:1) High Input impedance...1012 Ω Typ 0°C to 70°C...3 V to 16 V (cid:1) ESD-Protection Circuitry −40°C to 85°C...4 V to 16 V (cid:1) −55°C to 125°C...4 V to 16 V Small-Outline Package Option Also (cid:1) Available in Tape and Reel Single-Supply Operation (cid:1) (cid:1) Designed-In Latch-Up Immunity Common-Mode Input Voltage Range Extends Below the Negative Rail (C-Suffix, I-Suffix Types) DISTRIBUTION OF TLC27M7 D, JG, P OR PW PACKAGE FK PACKAGE INPUT OFFSET VOLTAGE (TOP VIEW) (TOP VIEW) 30ÎÎÎÎÎÎÎÎÎÎÎ T 340 Units Tested From 2 Wafer Lots 11OINUT− 12 87 2VOCCUT NC 1OU NCVDDNC % 25ÎTVÎAD D= 2Î=5 5°C VÎÎÎÎÎÎÎÎ 1IN+ 3 6 2IN− − P Package GND 4 5 2IN+ NC 43 2 1 20 1918 NC nits 20 1INNC− 56 1176 2NOCUT e of U 15 g 1IN+ 7 15 2IN− a NC 8 14 NC cent 10 9 10 11 12 13 r e P 5 C D C+ C N N NN N G 2I 0 −800 −400 0 400 800 NC − No internal connection VIO − Input Offset Voltage − µV AVAILABLE OPTIONS PACKAGE TA AVVTIIOO 2mm5aa°Cxx SMALL OUTLINE CHIP CARRIER CERAMIC DIP PLASTIC DIP TSSOP (D) (FK) (JG) (P) (PW) 500 µV TLC27M7CD — — TLC27M7CP — 2 mV TLC27M2BCD — — TLC27M2BCP — 00°°CC ttoo 7700°°CC 5 mV TLC27M2ACD — — TLC27M2ACP — 10 mV TLC27M2CD — — TLC27M2CP TLC27M2CPW 500 µV TLC27M7ID — — TLC27M7IP — 2 mV TLC27M2BID — — TLC27M2BIP — −−4400°°CC ttoo 8855°°CC 5 mV TLC27M2AID — — TLC27M2AIP — 10 mV TLC27M2ID — — TLC27M2IP TLC27M2IPW 500 µV TLC27M7MD TLC27M7MFK TLC27M7MJG TLC27M7MP — −−5555°°CC ttoo 112255°°CC 10 mV TLC27M2MD TLC27M2MFK TLC27M2MJG TLC27M2MP — The D and PW package are available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. LinCMOS is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. (cid:14)(cid:15)(cid:12)(cid:19)(cid:20)(cid:3)(cid:1)(cid:17)(cid:12)(cid:18) (cid:19)(cid:8)(cid:1)(cid:8) (cid:10)(cid:11)(cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:10)(cid:23)(cid:11) (cid:10)(cid:28) (cid:29)(cid:30)(cid:24)(cid:24)(cid:31)(cid:11)(cid:27) (cid:26)(cid:28) (cid:23)(cid:22) !(cid:30)"#(cid:10)(cid:29)(cid:26)(cid:27)(cid:10)(cid:23)(cid:11) $(cid:26)(cid:27)(cid:31)% Copyright  1987 − 2008, Texas Instruments Incorporated (cid:14)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:28) (cid:29)(cid:23)(cid:11)(cid:22)(cid:23)(cid:24)(cid:25) (cid:27)(cid:23) (cid:28)!(cid:31)(cid:29)(cid:10)(cid:22)(cid:10)(cid:29)(cid:26)(cid:27)(cid:10)(cid:23)(cid:11)(cid:28) !(cid:31)(cid:24) (cid:27)&(cid:31) (cid:27)(cid:31)(cid:24)(cid:25)(cid:28) (cid:23)(cid:22) (cid:1)(cid:31)’(cid:26)(cid:28) (cid:17)(cid:11)(cid:28)(cid:27)(cid:24)(cid:30)(cid:25)(cid:31)(cid:11)(cid:27)(cid:28) (cid:28)(cid:27)(cid:26)(cid:11)$(cid:26)(cid:24)$ ((cid:26)(cid:24)(cid:24)(cid:26)(cid:11)(cid:27))% (cid:14)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:10)(cid:23)(cid:11) !(cid:24)(cid:23)(cid:29)(cid:31)(cid:28)(cid:28)(cid:10)(cid:11)* $(cid:23)(cid:31)(cid:28) (cid:11)(cid:23)(cid:27) (cid:11)(cid:31)(cid:29)(cid:31)(cid:28)(cid:28)(cid:26)(cid:24)(cid:10)#) (cid:10)(cid:11)(cid:29)#(cid:30)$(cid:31) (cid:27)(cid:31)(cid:28)(cid:27)(cid:10)(cid:11)* (cid:23)(cid:22) (cid:26)## !(cid:26)(cid:24)(cid:26)(cid:25)(cid:31)(cid:27)(cid:31)(cid:24)(cid:28)% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 description The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose bipolar devices.These devices use Texas Instruments silicon-gate LinCMOStechnology, which provides offset voltage stability far exceeding the stability available with conventional metal-gate processes. The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices ideal for applications which have previously been reserved for general-purpose bipolar products, but with only a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 µV). These advantages, in combination with good common-mode rejection and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M2 and TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up. The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 equivalent schematic (each amplifier) VDD P3 P4 R6 R1 R2 N5 IN− P5 P6 P1 P2 IN+ C1 R5 OUT N3 N1 N2 N4 N6 N7 R3 D1 R4 D2 R7 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V ID DD Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V I DD Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA I Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA O Total current into V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA DD Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN−. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section). DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW P 1000 mW 8.0 mW/°C 640 mW 520 mW recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UUNNIITT MIN MAX MIN MAX MIN MAX Supply voltage, VDD 3 16 4 16 4 16 V VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5 CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee,, VVIICC VV VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 Operating free-air temperature, TA 0 70 −40 85 −55 125 °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27M2C TLC27M2AC PARAMETER TEST CONDITIONS TLC27M2BC UNIT TAA† TLC27M7C MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22CC RS = 50 Ω, RI = 100 kΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277MM22AACC RS = 50 Ω, RI = 100 kΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 220 2000 TTLLCC2277MM22BBCC RS = 50 Ω, RI = 100 kΩ Full range 3000 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 185 500 TTLLCC2277MM77CC RS = 50 Ω, RI = 100 kΩ Full range 1500 Average temperature coefficient of input 25°C to αVIO offset voltage 70°C 1.7 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 70°C 7 300 ppAA 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 70°C 40 600 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) −0.2 Full range to V 3.5 25°C 3.2 3.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ 0°C 3 3.9 VV 70°C 3 4 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 25 170 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 110000 kkΩΩ 0°C 15 200 VV//mmVV 70°C 15 140 25°C 65 91 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 91 ddBB 70°C 60 92 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 92 ddBB 70°C 60 94 25°C 210 560 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, 0°C 250 640 µµAA NNoo llooaadd 70°C 170 440 †Full range is 0°C to 70°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC27M2C TLC27M2AC PARAMETER TEST CONDITIONS TA† TLC27M2BC UNIT TLC27M7C MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22CC RS = 50 Ω, RL = 100 kΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277MM22AACC RS = 50 Ω, RL = 100 kΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 224 2000 TTLLCC2277MM22BBCC RS = 50 Ω, RL = 100 kΩ Full range 3000 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 TTLLCC2277MM77CC RS = 50 Ω, RL = 100 kΩ Full range 1900 Average temperature coefficient of input 25°C to αVIO offset voltage 70°C 2.1 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 70°C 7 300 ppAA 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 70°C 50 600 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) −0.2 Full range to V 8.5 25°C 8 8.7 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ 0°C 7.8 8.7 VV 70°C 7.8 8.7 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 25 275 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 110000 kkΩΩ 0°C 15 320 VV//mmVV 70°C 15 230 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 94 ddBB 70°C 60 94 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 92 ddBB 70°C 60 94 25°C 285 600 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, 0°C 345 800 µµAA NNoo llooaadd 70°C 220 560 †Full range is 0°C to 70°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27M2I TLC27M2AI PARAMETER TEST CONDITIONS TA† TLC27M2BI UNIT TLC27M7I MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22II RS = 50 Ω, RL = 100 kΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277MM22AAII RS = 50 Ω, RL = 100 kΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 220 2000 TTLLCC2277MM22BBII RS = 50 Ω, RL = 100 kΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 185 500 TTLLCC2277MM77II RS = 50 Ω, RL = 100 kΩ Full range 2000 Average temperature coefficient of input 25°C to αVIO offset voltage 85°C 1.7 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 85°C 24 1000 ppAA 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 85°C 200 2000 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) −0.2 Full range to V 3.5 25°C 3.2 3.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ −40°C 3 3.9 VV 85°C 3 4 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 25 170 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 110000 kkΩΩ −40°C 15 270 VV//mmVV 85°C 15 130 25°C 65 91 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 90 ddBB 85°C 60 90 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 91 ddBB 85°C 60 94 25°C 210 560 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −40°C 315 800 µµAA NNoo llooaadd 85°C 160 400 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted) TLC27M2I TLC27M2AI PARAMETER TEST CONDITIONS TA† TLC27M2BI UNIT TLC27M7I MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22II RS = 50 Ω, RL = 100 kΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277MM22AAII RS = 50 Ω, RL = 100 kΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 224 2000 TTLLCC2277MM22BBII RS = 50 Ω, RL = 100 kΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 TTLLCC2277MM77II RS = 50 Ω, RL = 100 kΩ Full range 2900 Average temperature coefficient of input 25°C to αVIO offset voltage 85°C 2.1 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 85°C 26 1000 ppAA 25°C 0.7 60 IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 85°C 220 200 pA 0 −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) −0.2 Full range to V 8.5 25°C 8 8.7 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ −40°C 7.8 8.7 VV 85°C 7.8 8.7 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 25 275 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 110000 kkΩΩ −40°C 15 390 VV//mmVV 85°C 15 220 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 93 ddBB 85°C 60 94 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 91 ddBB 85°C 60 94 25°C 285 600 IIDDDD SSuuppppllyy ccuurrrreenntt VVOO == 55 VV,, VVIICC == 55 VV,, −40°C 450 900 µµAA NNoo llooaadd 85°C 205 520 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27M2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC27M7M UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22MM RS = 50 Ω, RL = 100 kΩ Full range 12 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 185 500 mmVV TTLLCC2277MM77MM RS = 50 Ω, RL = 100 kΩ Full range 3750 Average temperature coefficient of input 25°C to αVIO offset voltage 125°C 1.7 µV/°C 25°C 0.1 60 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 125°C 1.4 15 nA 25°C 0.6 60 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 125°C 9 35 nA 0 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) 0 Full range to V 3.5 25°C 3.2 3.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ −55°C 3 3.9 VV 125°C 3 4 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 25 170 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 110000 kkΩΩ −55°C 15 290 VV//mmVV 125°C 15 120 25°C 65 91 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 89 ddBB 125°C 60 91 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 91 ddBB 125°C 60 94 25°C 210 560 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −55°C 340 880 µµAA NNoo llooaadd 125°C 140 360 †Full range is −55°C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC27M2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC27M7M UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277MM22MM RS = 50 Ω, RL = 100 kΩ Full range 12 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 mmVV TTLLCC2277MM77MM RS = 50 Ω, RL = 100 kΩ Full range 4300 Average temperature coefficient of input 25°C to αVIO offset voltage 125°C 2.1 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 125°C 1.8 15 ppAA 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 125°C 10 35 ppAA 0 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) 0 Full range to V 8.5 25°C 8 8.7 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 110000 kkΩΩ −55°C 7.8 8.6 VV 125°C 7.8 8.8 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 25 275 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 110000 kkΩΩ −55°C 15 420 VV//mmVV 125°C 15 190 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 93 ddBB 125°C 60 93 25°C 70 93 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 91 ddBB 125°C 60 94 25°C 285 600 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, −55°C 490 1000 µµAA NNoo llooaadd 125°C 180 480 †Full range is −55°C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 operating characteristics at specified free-air temperature, VDD = 5 V TLC27M2C TLC27M2AC PARAMETER TEST CONDITIONS TA TLC27M2BC UNIT TLC27M7C MIN TYP MAX 25°C 0.43 VVII((PPPP)) == 11 VV 0°C 0.46 RRLL == 110000 kkΩ,, 70°C 0.36 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.40 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV 0°C 0.43 70°C 0.34 Vn Equivalent input noise voltage fS =e e1 FkiHguz,re 2 RS = 20 Ω, 25°C 32 nV/√Hz 25°C 55 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 0°C 60 kHz 70°C 50 25°C 525 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, 0°C 600 kHz 70°C 400 25°C 40° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 41° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 70°C 39° operating characteristics at specified free-air temperature, V = 10 V DD TLC27M2C TLC27M2AC PARAMETER TEST CONDITIONS TA TLC27M2BC UNIT TLC27M7C MIN TYP MAX 25°C 0.62 VVII((PPPP)) == 11 VV 0°C 0.67 RRLL == 110000 kkΩ,, 70°C 0.51 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.56 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV 0°C 0.61 70°C 0.46 Vn Equivalent input noise voltage fS =e e1 FkiHguz,re 2 RS = 20 Ω, 25°C 32 nV/√Hz 25°C 35 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 0°C 40 kkHHzz 70°C 30 25°C 635 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, 0°C 710 kkHHzz 70°C 510 25°C 43° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 44° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 70°C 42° POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 operating characteristics at specified free-air temperature, V = 5 V DD TLC27M2I TLC27M2AI PARAMETER TEST CONDITIONS TA TLC27M2BI UNIT TLC27M7I MIN TYP MAX 25°C 0.43 VVII((PPPP)) == 11 VV −40°C 0.51 RRLL == 110000 kkΩ,, 85°C 0.35 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.40 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV −40°C 0.48 85°C 0.32 Vn Equivalent input noise voltage fS =e e1 FkiHguz,re 2 RS = 20 Ω, 25°C 32 nV/√Hz 25°C 55 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −40°C 75 kkHHzz 85°C 45 25°C 525 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −40°C 770 kkHHzz 85°C 370 25°C 40° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 43° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 85°C 38° operating characteristics at specified free-air temperature, V = 10 V DD TLC27M2I TLC27M2AI PARAMETER TEST CONDITIONS TA TLC27M2BI UNIT TLC27M7I MIN TYP MAX 25°C 0.62 VVII((PPPP)) == 11 VV −40°C 0.77 RRLL == 110000 kkΩ,, 85°C 0.47 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.56 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV −40°C 0.70 85°C 0.44 Vn Equivalent input noise voltage fS =e e1 FkiHguz,re 2 RS = 20 Ω, 25°C 32 nV/√Hz 25°C 35 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −40°C 45 kkHHzz 85°C 25 25°C 635 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −40°C 880 kkHHzz 85°C 480 25°C 43° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 46° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 85°C 41° 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 operating characteristics at specified free-air temperature, VDD = 5 V TLC27M2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC27M7M UUNNIITT MIN TYP MAX 25°C 0.43 VVII((PPPP)) == 11 VV −55°C 0.54 RRLL == 110000 kkΩ,, 125°C 0.29 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.40 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV −55°C 0.49 125°C 0.28 Vn Equivalent input noise voltage fS =e e1 FkiHguz,re 2 RS = 20 Ω, 25°C 32 nV/√Hz 25°C 55 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −55°C 80 kkHHzz 125°C 40 25°C 525 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −55°C 850 kkHHzz 125°C 330 25°C 40° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 44° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 125°C 36° operating characteristics at specified free-air temperature, V = 10 V DD TLC27M2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC27M7M UUNNIITT MIN TYP MAX 25°C 0.62 VVII((PPPP)) == 11 VV −55°C 0.81 RRLL == 110000 kkΩ,, 125°C 0.38 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.56 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV −55°C 0.73 125°C 0.35 Vn Equivalent input noise voltage f = 1 kHz, RS = 20 Ω, 25°C 32 nV/√Hz See Figure 2 25°C 35 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV00OO00HH kk,,ΩΩ,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −55°C 50 kkHHzz 125°C 20 25°C 635 BB11 UUnniittyy ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −55°C 960 kkHHzz 125°C 440 25°C 43° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 47° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 125°C 39° POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION single-supply versus split-supply test circuits Because the TLC27M2 and TLC27M7 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. VDD VDD+ − − VO VO VI + VI + CL RL CL RL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 1. Unity-Gain Amplifier 2 kΩ 2 kΩ VDD VDD+ 20 Ω − − 1/2 VDD 20 Ω VO VO + + 20 Ω 20 Ω VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 2. Noise-Test Circuit 10 kΩ 10 kΩ 100 Ω VDD 100 Ω VDD+ VI − VI − VO VO + 1/2 VDD + CL CL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 3. Gain-of-100 Inverting Amplifier 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION input bias current Because of the high input impedance of the TLC27M2 and TLC27M7 operational amplifiers, attempts to measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements: 1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution—many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 5 8 8 5 V = VIC 1 4 Figure 4. Isolation Metal Around Device Inputs (JG and P packages) low-level output voltage To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION input offset voltage temperature coefficient Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage, since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing to minimize error. full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached. (a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal test time Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7 α VIO Temperature coefficient Distribution 8, 9 vvss HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt 1100,, 1111 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee vvss SSuuppppllyy vvoollttaaggee 1122 vs Free-air temperature 13 vvss CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee 1144,, 1155 vvss DDiiffffeerreennttiiaall iinnppuutt vvoollttaaggee 1166 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee vvss FFrreeee--aaiirr tteemmppeerraattuurree 1177 vs Low-level output current 18, 19 vvss SSuuppppllyy vvoollttaaggee 2200 AAVVDD DDiiffffeerreennttiiaall vvoollttaaggee aammpplliiffiiccaattiioonn vvss FFrreeee--aaiirr tteemmppeerraattuurree 2211 vs Frequency 32, 33 IIB/IIO Input bias and input offset current vs Free-air temperature 22 VIC Common-mode input voltage vs Supply voltage 23 vvss SSuuppppllyy vvoollttaaggee 2244 IIDDDD SSuuppppllyy ccuurrrreenntt vs Free-air temperature 25 vvss SSuuppppllyy vvoollttaaggee 2266 SSRR SSlleeww rraattee vs Free-air temperature 27 Normalized slew rate vs Free-air temperature 28 VO(PP) Maximum peak-to-peak output voltage vs Frequency 29 vvss FFrreeee--aaiirr tteemmppeerraattuurree 3300 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh vs Supply voltage 31 vvss SSuuppppllyy vvoollttaaggee 3344 φφ mm PPhhaassee mmaarrggiinn vvss FFrreeee--aaiirr tteemmppeerraattuurree 3355 vs Capacitive loads 36 Vn Equivalent input noise voltage vs Frequency 37 φ Phase shift vs Frequency 32, 33 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLC27M2 DISTRIBUTION OF TLC27M2 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 60 60 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ 612 Amplifiers Tested From 4 Wafer Lots 612 Amplifiers Tested From 4 Wafer Lots ÎÎVDDÎ = 5Î V ÎÎÎÎÎÎÎÎ ÎVDÎD =Î 10 VÎÎÎÎÎÎÎÎ 50 TA = 25°C 50 TA = 25°C P Package P Package % % s − 40 s − 40 nit nit U U e of 30 e of 30 g g a a nt nt e e c 20 c 20 er er P P 10 10 0 0 −5 −4 −3 −2 −1 0 1 2 3 4 5 −5 −4 −3 −2 −1 0 1 2 3 4 5 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV Figure 6 Figure 7 DISTRIBUTION OF TLC27M2 AND TLC27M7 DISTRIBUTION OF TLC27M2 AND TLC27M7 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT 60 60 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 224 Amplifiers Tested From 6 Wafer Lots 224 Amplifiers Tested From 6 Wafer Lots ÎÎVDDÎ = 5Î V ÎÎÎÎÎÎÎÎ ÎVÎDD =Î 10 ÎV ÎÎÎÎÎÎÎÎ 50 TA = 25°C to 125°C 50 TA = 25°C to 125°C P Package P Package % Outliers: % Outliers: s − 40 (1) 33.0 µV/°C s − 40 (1) 34.6 µV/°C nit nit U U e of 30 e of 30 g g a a nt nt e e erc 20 erc 20 P P 10 10 0 0 −10 −8 −6 −4 −2 0 2 4 6 8 10 −10 −8 −6 −4 −2 0 2 4 6 8 10 αVIO − Temperature Coefficient − µV/°C αVIO − Temperature Coefficient − µV/°C Figure 8 Figure 9 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 5 16 VID = 100 mV ÁVÁID= Á100 ÁmVÁ e − V 4 TA = 25°C e − V 14 ÎÎVDÎÎD =ÎÎ 16 VÎÎÎÎÁTAÎÎÁ = 2Á5°CÁÁ ag ag 12 olt ÎÎÎÎ olt ut V 3 ÎÎÎÎÎVDÎD =Î 5 VÎ ut V 10 p p vel Out ÎVÎDD =Î 4 VÎ vel Out 8 ÎÎVDÎÎD = ÎÎ10 VÎÎ h-Le 2 VDD = 3 V h-Le 6 g g ÁHiÁ ÁÁHi − − 4 ÁH HÁ1 ÁÁH H OO OO VV VV ÁÁ ÁÁ 2 0 0 0 −2 −4 −6 −8 −10 0 −10 −20 −30 −40 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 10 Figure 11 HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 16 ÁÁÁÁ VDD −1.6 ÁVIDÁ = 1Á00 mÁV IOH = −5 mA ge − V 1142 ÁRTALÁ == 2150Á°0C kÁΩ ge − V VVDDDD −−11..78 ÎÎVDDÎ = 5 ÎV VID = 100 mA Volta Volta ut 10 ut VDD −1.9 p p ut ut h-Level O 86 h-Level O VDVDD D− 2−.21 ÎÎVDÎÎD =ÎÎ 10 ÎÎV g g Á− HiÁ4 Á− HiÁVDD −2.2 ÁOH OHÁ ÁOH OHÁ ÁVVÁ2 ÁVVÁVDD −2.3 0 VDD −2.4 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 12 Figure 13 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 700 500 VDD = 5 V VDD = 10 V e − mV 660500 TIOAL = = 2 55 °mCA e − mV 450 ITOAL = = 2 55 °mCA g g a a olt olt V 550 V put VID = −100 mV put 400 Out 500 Out VID = −100 mV w-Level 450 w-Level 350 VVIIDD == −−12. 5V V o o − L 400 − L ÁOL OLÁ VID = −1 V ÁOL OLÁ300 ÁVVÁ350 ÁVVÁ 300 250 0 1 2 3 4 0 1 2 3 4 5 6 7 8 7 10 VIC − Common-Mode Input Voltage − V VIC − Common-Mode Input Voltage − V Figure 14 Figure 15 LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE 800 900 IOL = 5 mA IOL = 5 mA mV 700 VIC = |VID/2| mV 800 VID = −1 V − TA = 25°C − VIC = 0.5 V ge 600 ge 700 a a olt olt 600 VDD = 5 V put V 500 VDD = 5 V put V 500 ut ut O 400 O el el 400 v v Le 300 Le VDD = 10 V ow- VDD = 10 V ow- 300 ÁL − LÁL 200 ÁÁL − LL 200 ÁOÁO ÁÁOO VV 100 VV 100 ÁÁ ÁÁ 0 0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −75 −50 −25 0 25 50 75 100 125 VID − Differential Input Voltage − V TA − Free-Air Temperature − °C Figure 16 Figure 17 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT ÁÁÁÁÁ 1 3 ÁÁVIDÁ = −Á1 VÁ ge − V 00..89ÁÁÁÁVTAIC ÁÁ= = 2 05ÁÁ.°5C VÁÁ VDD = 5 V ge − V 2.5 TVVAIICD = == 2 −05.1°5C VV ÎÎVÎÎDD =ÎÎ 16ÎÎ V a a Volt 0.7 VDD = 4 V Volt 2 utput 0.6 VDD = 3 V utput ÎÎVDÎÎD =ÎÎ 10 VÎÎ O 0.5 O 1.5 el el v v Le 0.4 Le w- w- 1 ÁLoÁ 0.3 ÁLoÁ − − ÁVVOL ÁOL 0.2 ÁVVOL OLÁ0.5 ÁÁ ÁÁ 0.1 0 0 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 18 Figure 19 LARGE-SIGNAL LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 500 500 ÎÎÎÎ TA = −55°C 450 RL = 100 kΩ 450 ÎRLÎ = 10Î0 kΩÎ −40°C al V 400 al V 400 erenti − V/m 350 0°C erenti − V/m 350 ÎÎÎÎ al Diff ation 300 7205°°CC al Diff ation 300 ÎVDÎD =Î 10 VÎ n c n c e-Sig mplifi 250 85°C e-Sig mplifi 250 arg e A 200 125°C arg e A 200 ÁÁVD − LÁÁVDVoltag 150 ÁÁÁÁVD − LVDVoltag 150 ÎÎVDÎÎD =ÎÎ 5 VÎÎ AA 100 AA 100 ÁÁ ÁÁ 50 50 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 20 Figure 21 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† INPUT BIAS CURRENT AND INPUT OFFSET COMMON-MODE CURRENT INPUT VOLTAGE POSITIVE LIMIT vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE A10000 16 − p VDD = 10 V TA = 25°C d Offset Currents 1010000 SVeICe =N o5 tVe A ÎÎIÎÎIB ÎÎ nput Voltage − V 111024 s an ÎIIÎO ode I 8 a M put Bi 10 mon- 6 n m − i ÁCoÁ 4 nd IIO IIO 1 ÁVVIC − ICÁ 2 a ÁÁ B B IIII 0.1 0 25 45 65 85 105 125 0 2 4 6 8 10 12 14 16 TA − Free-Air Temperature − °C VDD − Supply Voltage − V NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically. Figure 22 Figure 23 SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 800 500 VO = VDD/2 450 VO = VDD/2 700 No Load TA = −55°C No Load 400 A A ÁµDD − Supply Current − ADDÁ345600000000 −7240050°°°°CCCC ÁÁµDD − Supply Current − ADDÁÁ122335050500000 ÎÎÎÎVDÎÎD = 5ÎÎ V ÎÎÎÎVDÎÎD =ÎÎ 10 ÎÎV ÁIIÁ200 ÁIIÁ 125°C 100 100 50 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 24 Figure 25 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† SLEW RATE SLEW RATE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 0.9 0.9 AV = 1 VIPP = 1 V AV = 1 µsV/ 00..78 ÎRCSTÎAeLLe === F Î 212ig500°u0 pCÎ rkFeΩ 1Î µsV/ 00..78 ÁÁVVÁÁID(PDP ÁÁ=) =1 05ÁÁ .V5 VÁÁ RSCeLLe == F 12ig00u0 p rkFeΩ 1 − − ÁÎÁÎÁÎÁÎÁÎ ate ate 0.6 VDD = 10 V w R 0.6 w R ÁÎVÁÎI(PPÁÎ) = ÁÎ1 VÁÎ e e Sl Sl 0.5 − − SR 0.5 SR 0.4 ÁÁÁÁÁ VDD = 5 V 0.4 0.3 ÁVÁI(PPÁ) = Á1 VÁÁÁÁÁÁ VDD = 5 V ÁVÁI(PPÁ) = 2Á.5 VÁ 0.3 0.2 0 2 4 6 8 10 12 14 16 − 75 − 50 − 25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 26 Figure 27 MAXIMUM PEAK-TO-PEAK OUTPUT NORMALIZED SLEW RATE VOLTAGE vs vs FREE-AIR TEMPERATURE FREQUENCY 1.4 V 10 − AV = 1 e 1.3 VI(PP) = 1 V ag 9 ÎÎÎÎ 1.2 VDD = 10 V RCLL == 12000 p kFΩ ut Volt 8 ÎVDÎD =Î 10 VÎ Rate 1.1 VDD = 5 V Outp 7 TTAA == 12255°C°C w ak 6 TA = −55°C Sle 1 Pe d o- 5 malize 0.9 Peak-t 4 ÎÎVDÎÎD =ÎÎ 5 VÎÎ or 0.8 m N u 3 m 0.7 axi 2 ÎRLÎ = 1Î00 kÎΩ Î M − ÎSeÎe FiÎgureÎ 1 Î 0.6 P) 1 P 0.5 VO( 0 −75 −50 −25 0 25 50 75 100 125 1 10 100 1000 TA − Free-Air Temperature − °C f − Frequency − kHz Figure 28 Figure 29 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE ÁÁÁÁÁ ÁÁÁÁÁ 900 800 ÁÁVDDÁ = 5Á V Á ÁVÁI = Á10 mÁV Á ÁÁVI = Á10 mÁV Á 750 ÁCÁL =Á 20 pÁF Á kHz 800 ÁÁSCeLe = ÁF 2ig0u ÁprFe 3Á kHz ÁSTÁAee = ÁF 2ig5°uÁCre 3Á − − 700 h h dt 700 dt wi wi 650 d d n n a a n B 600 n B 600 ai ai G G y- y- 550 nit 500 nit U U − − 500 B1 B1 400 B1 B1 450 300 400 −75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA − Free-Air Temperature − C VDD − Supply Voltage − V Figure 30 Figure 31 LARGE-SCALE DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 10 7 VDD = 5 V 10 6 RL = 100 kΩ ntial 105 TA = 25°C 0° e n Signal Differ Amplificatio 1100 34 ÎÎAVÎÎD ÎÎ 6300°° se Shift Large- oltage 102 90° Pha − V Phase Shift ÁVD ÁVD 10 120° ÁAAÁ 1 150° 0.1 180° 0 10 100 1 k 10 k 100 k 1 M f − Frequency − Hz Figure 32 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS† LARGE-SCALE DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 10 7 VDD = 10 V 10 6 RL = 100 kΩ al TA = 25°C nti 105 0° e n Differ catio 10 4 ÎÎÎ 30° Signal Amplifi 10 3 ÎAÎVDÎ 60° se Shift Large- oltage 102 90° Pha Á− ÁV Phase Shift ÁVD VDÁ 10 120° AA ÁÁ 1 150° 0.1 180° 0 10 100 1 k 10 k 100 k 1 M f − Frequency − Hz Figure 33 PHASE MARGIN PHASE MARGIN vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 50° 45° VI = 10 mV VDD = 5 V 48° TCAL == 2250° pCF 43° VCIL = = 1 200 m pVF See Figure 3 See Figure 3 Margin 46° Margin 41° ÁÁφ m − Phase mÁÁ4424°° ÁÁφ m − Phase mÁÁ39° 37° 40° 38° 35° 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − C Figure 34 Figure 35 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS PHASE MARGIN vs CAPACITIVE LOAD 44° VDD = 5 V 42° VI = 10 mV TA = 25°C 40° See Figure 3 n gi ar 38° M e as 36° h P ÁÁ− m m 34° ÁφÁ 32° 30° 28° 0 10 20 30 40 50 60 70 80 90 100 CL − Capacitive Load − pF Figure 36 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY ÁÁ300 ÁHzÁ VDD = 5 V Hz RS = 20 Ω ÁV/V/Á250 TA = 25°C nn − See Figure 2 e g olta 200 V e s Noi 150 ut p n nt I 100 e al v ui q 50 E − Vn Vn 0 1 10 100 1000 f −Frequency − Hz Figure 37 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION single-supply operation While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground, as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38). The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to implement the voltage divider, thus minimizing power consumption. The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: 1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require RC decoupling. VDD R4 R3 VI R1 R2 − VREF (cid:1)(cid:3) VDD R1(cid:4) (cid:2) R3 VO V (cid:1) V –V R4 (cid:2) V + O REF I R2 REF VREF R3 C 0.01µF Figure 38. Inverting Amplifier With Voltage Reference − Power Output Logic Logic Logic + Supply (a) COMMON SUPPLY RAILS − Power Output Logic Logic Logic + Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION input characteristics The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at V −1 V at T = 25°C and at V −1.5 V at all other temperatures. DD A DD The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7 very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 40). The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise currents. − VI + VO VI −+ VO − VO VI + (c) UNITY-GAIN AMPLIFIER (b) INVERTING AMPLIFIER (a) NONINVERTING AMPLIFIER Figure 40. Guard-Ring Schemes output characteristics The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION (a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD 2.5 V − VO VI + CL Tf A= 1= k2H5°zC VI(PP) = 1 V −2.5 V (c) CL = 190 pF, RL = NO LOAD (d) TEST CIRCUIT Figure 41. Effect of Capacitive Loads and Test Circuit output characteristics (continued) Although the TLC27M2 and TLC27M7 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor (R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages P to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION output characteristics (continued) VDD VI + IP RP − VO C IP R2 R1 IL RL − V (cid:5)V VO R (cid:1) DD O + P I (cid:2) I (cid:2) I F L P IP = Pullup current required by the op- erational amplifier (typically 500 µA) Figure 42. Resistive Pullup to Increase V Figure 43. Compensation for Input Capacitance OH feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically. electrostatic-discharge protection The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode. latch-up Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and TLC27M7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION 1N4148 470 kΩ 100 kΩ 5 V 1/2 − TLC27M2 5 V IS 1/2 100 kΩ 47 kΩ VO VI + TLC27M7 + − 2N3821 R2 68 kΩ 1 µF 100 kΩ C2 R1 C1 2.2 nF R 68 kΩ 2.2 nF NOTES: VO(PP) ≈ 2 V NOTES: VI = 0 V to 3 V fO (cid:1) 2(cid:1)(cid:6)R1R12C1C2 IS (cid:1) VRI Figure 44. Wien Oscillator Figure 45. Precision Low-Current Sink 5 V Gain Control 1 MΩ (see Note A) 100 kΩ 1µ F − + + 10 kΩ + − − + − 1/2 0.1 µF TLC27M2 1 kΩ 100 kΩ 0.1 µF 100 kΩ NOTE A: Low to medium impedance dynamic mike Figure 46. Microphone Preamplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION 10 MΩ VDD − 1/2 1 kΩ TLC27M2 − + 1/2 VO TLC27M2 VREF + 15 nF 100 kΩ 150 pF NOTES: VDD = 4 V to 15 V Vref = 0 V to VDD − 2 V Figure 47. Photo-Diode Amplifier With Ambient Light Rejection 1 MΩ VDD 33 pF − VO + 1/2 TLC27M2 1N4148 100 kΩ 100 kΩ NOTES: VDD = 8 V to 16 V VO = 5 V, 10 mA Figure 48. 5-V Low-Power Voltage Regulator 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5) (cid:2)(cid:10)(cid:11)(cid:3)(cid:6)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:8)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:8)(cid:1)(cid:17)(cid:12)(cid:18)(cid:8)(cid:2) (cid:8)(cid:6)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008 APPLICATION INFORMATION 5 V 0.1 µ F 1 MΩ VI + 0.22 µF VO − 1/2 TLC27M2 1 MΩ 100 kΩ 100 kΩ 10 kΩ 0.1 µF Figure 49. Single-Rail AC Amplifiers POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27M2ACD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2AC & no Sb/Br) TLC27M2ACDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2AC & no Sb/Br) TLC27M2ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2AC & no Sb/Br) TLC27M2ACP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M2AC & no Sb/Br) TLC27M2ACPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M2AC & no Sb/Br) TLC27M2AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2AI & no Sb/Br) TLC27M2AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2AI & no Sb/Br) TLC27M2AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2AI & no Sb/Br) TLC27M2AIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TLC27M2AI & no Sb/Br) TLC27M2BCD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2BC & no Sb/Br) TLC27M2BCDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2BC & no Sb/Br) TLC27M2BCDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2BC & no Sb/Br) TLC27M2BCP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M2BC & no Sb/Br) TLC27M2BID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2BI & no Sb/Br) TLC27M2BIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2BI & no Sb/Br) TLC27M2BIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2BI & no Sb/Br) TLC27M2BIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TLC27M2BI & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27M2CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2C & no Sb/Br) TLC27M2CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M2C & no Sb/Br) TLC27M2CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M2CP & no Sb/Br) TLC27M2CPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M2CP & no Sb/Br) TLC27M2CPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 P27M2 & no Sb/Br) TLC27M2CPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 P27M2 & no Sb/Br) TLC27M2CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 P27M2 & no Sb/Br) TLC27M2ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2I & no Sb/Br) TLC27M2IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2I & no Sb/Br) TLC27M2IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M2I & no Sb/Br) TLC27M2IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TLC27M2IP & no Sb/Br) TLC27M2IPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 P27M2I & no Sb/Br) TLC27M2IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 P27M2I & no Sb/Br) TLC27M2IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 P27M2I & no Sb/Br) TLC27M2MD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 27M2M & no Sb/Br) TLC27M2MDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 27M2M & no Sb/Br) TLC27M7CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M7C & no Sb/Br) TLC27M7CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M7C & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27M7CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 27M7C & no Sb/Br) TLC27M7CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TLC27M7CP & no Sb/Br) TLC27M7CPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 P27M7 & no Sb/Br) TLC27M7ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M7I & no Sb/Br) TLC27M7IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 27M7I & no Sb/Br) TLC27M7IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TLC27M7IP & no Sb/Br) TLC27M7IPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TLC27M7IP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC27M2ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1 TLC27M2CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27M2IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27M7CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M7CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1 TLC27M7IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC27M2ACDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2AIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2BCDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2BIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27M2CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27M2IDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27M7CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M7CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27M7IDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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