(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 (cid:1) Trimmed Offset Voltage: D, JG, OR P PACKAGE TLC27L7...500 µV Max at 25°C, (TOP VIEW) V = 5 V DD (cid:1) 1OUT 1 8 VDD Input Offset Voltage Drift . . . Typically 1IN− 2 7 2OUT 0.1 µV/Month, Including the First 30 Days 1IN+ 3 6 2IN− (cid:1) Wide Range of Supply Voltages Over GND 4 5 2IN+ Specified Temperature Range: 0°C to 70°C...3 V to 16 V −40°C to 85°C...4 V to 16 V FK PACKAGE −55°C to 125°C...4 V to 16 V (TOP VIEW) T (cid:1) Single-Supply Operation C OU C DDC (cid:1) N 1 NV N Common-Mode Input Voltage Range Extends Below the Negative Rail (C-Suffix, 3 2 1 20 19 I-Suffix Types) NC 4 18 NC (cid:1) Ultra-Low Power...Typically 95 µW 1IN− 5 17 2OUT NC 6 16 NC at 25°C, V = 5 V DD 1IN+ 7 15 2IN− (cid:1) Output Voltage Range Includes Negative NC 8 14 NC Rail 9 10 11 12 13 (cid:1) High Input Impedance...1012 Ω Typ C D C+ C (cid:1) N N NN N ESD-Protection Circuitry G 2I (cid:1) Small-Outline Package Option Also NC − No internal connection Available in Tape and Reel (cid:1) Designed-In Latch-Up immunity DISTRIBUTION OF TLC27L7 INPUT OFFSET VOLTAGE description 3Î0 ÎÎÎÎÎÎÎÎÎÎ 335 Units Tested From 2 Wafer Lots The TLC27L2 and TLC27L7 dual operational ÎÎÎÎÎÎÎÎÎÎÎ VDD = 5 V amplifiers combine a wide range of input offset 25 TA = 25°C voltage grades with low offset voltage drift, high % P Package − input impedance, extremely low power, and high s 20 gain. nit U AVAILABLE OPTIONS e of 15 g a PACKAGE nt e 10 TA AVTIO 2m5a°Cx OSUMTALLINLE CACRHRIPIER CERDAIPMIC PLADSIPTIC Perc (D) (FK) (JG) (P) 5 550000 µµVV TTLLCC2277LL77CCDD TTLLCC2277LL77CCPP 00°°CC 22 mmVV TTLLCC2277LL22BBCCDD TTLLCC2277LL22BBCCPP ttoo —— —— 0 55 mmVV TTLLCC2277LL22AACCDD TTLLCC2277LL22AACCPP 7700°°CC 10 mV TLC27L2CD TLC27L2CP −800 −400 0 400 800 550000 µµVV TTLLCC2277LL77IIDD TTLLCC2277LL77IIPP VIO − Input Offset Voltage − µV −−4400°°CC 22 mmVV TTLLCC2277LL22BBIIDD TTLLCC2277LL22BBIIPP ttoo —— —— 55 mmVV TTLLCC2277LL22AAIIDD TTLLCC2277LL22AAIIPP 8855°°CC 10 mV TLC27L2ID TLC27L2IP −55°C TLC27L7MD 550000 µµVV TTLLCC2277LL77MMFFKK TTLLCC2277LL77MMJJGG TTLLCC2277LL77MMPP ttoo TTLLCC2277LL22MMDD 125°C 10 mV TLC27L2MDRG4 TLC27L2MFK TLC27L2MJG TLC27L2MP The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC27L7CDR). LinCMOS is a trademark of Texas Instruments. (cid:14)(cid:15)(cid:12)(cid:19)(cid:20)(cid:3)(cid:1)(cid:17)(cid:12)(cid:18) (cid:19)(cid:7)(cid:1)(cid:7) (cid:9)(cid:10)(cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:9)(cid:23)(cid:10) (cid:9)(cid:28) (cid:29)(cid:30)(cid:24)(cid:24)(cid:31)(cid:10)(cid:27) (cid:26)(cid:28) (cid:23)(cid:22) !(cid:30)"#(cid:9)(cid:29)(cid:26)(cid:27)(cid:9)(cid:23)(cid:10) $(cid:26)(cid:27)(cid:31)% Copyright  2005, Texas Instruments Incorporated (cid:14)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:28) (cid:29)(cid:23)(cid:10)(cid:22)(cid:23)(cid:24)(cid:25) (cid:27)(cid:23) (cid:28)!(cid:31)(cid:29)(cid:9)(cid:22)(cid:9)(cid:29)(cid:26)(cid:27)(cid:9)(cid:23)(cid:10)(cid:28) !(cid:31)(cid:24) (cid:27)&(cid:31) (cid:27)(cid:31)(cid:24)(cid:25)(cid:28) (cid:23)(cid:22) (cid:1)(cid:31)’(cid:26)(cid:28) (cid:17)(cid:10)(cid:28)(cid:27)(cid:24)(cid:30)(cid:25)(cid:31)(cid:10)(cid:27)(cid:28) (cid:28)(cid:27)(cid:26)(cid:10)$(cid:26)(cid:24)$ ((cid:26)(cid:24)(cid:24)(cid:26)(cid:10)(cid:27))% (cid:14)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:9)(cid:23)(cid:10) !(cid:24)(cid:23)(cid:29)(cid:31)(cid:28)(cid:28)(cid:9)(cid:10)* $(cid:23)(cid:31)(cid:28) (cid:10)(cid:23)(cid:27) (cid:10)(cid:31)(cid:29)(cid:31)(cid:28)(cid:28)(cid:26)(cid:24)(cid:9)#) (cid:9)(cid:10)(cid:29)#(cid:30)$(cid:31) (cid:27)(cid:31)(cid:28)(cid:27)(cid:9)(cid:10)* (cid:23)(cid:22) (cid:26)## !(cid:26)(cid:24)(cid:26)(cid:25)(cid:31)(cid:27)(cid:31)(cid:24)(cid:28)% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 description (continued) These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage stability far exceeding the stability available with conventional metal-gate processes. The extremely high input impedance, low bias currents, and low power consumption make these cost-effective devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7 (500 µV). These advantages, in combination with good common-mode rejection and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up. The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The C-Suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C. equivalent schematic (each amplifier) VDD P3 P4 R6 R1 R2 N5 IN− P5 P6 P1 P2 IN+ C1 R5 OUT N3 N1 N2 N4 N6 N7 R3 D1 R4 D2 R7 GND 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V DD Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V DD Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V I DD Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA I Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA O Total current into V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA DD Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN−. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section). DISSIPATION RATING TABLE TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW — FK 1375 mW 11 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW P 1000 mW 8 mW/°C 640 mW 520 mW — recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UUNNIITT MIN MAX MIN MAX MIN MAX Supply voltage, VDD 3 16 4 16 4 16 V VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5 CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee,, VVIICC VV VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 Operating free-air temperature, TA 0 70 −40 85 −55 125 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27L2C TLC27L2AC PARAMETER TEST CONDITIONS TA† TLC27L2BC UNIT TLC27L7C MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277LL22CC RS = 50 Ω, RL = 1 MΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277LL22AACC RS = 50 Ω, RL = 1 MΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 204 2000 TTLLCC2277LL22BBCC RS = 50 Ω, RL = 1 MΩ Full range 3000 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 170 500 TTLLCC2277LL77CC RS = 50 Ω, RL = 1 MΩ Full range 1500 AAvveerraaggee tteemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt 2255°CC ttoo αVVIIOO offset voltage 70°C 11..11 µVV//°°CC 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 70°C 7 300 ppAA 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 70°C 50 600 ppAA −−00..22 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR ((sseeee NNoottee 55)) −−00..22 FFuullll rraannggee ttoo VV 3.5 25°C 3.2 4.1 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ 0°C 3 4.1 VV 70°C 3 4.2 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 50 700 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 11 MMΩΩ 0°C 50 700 VV//mmVV 70°C 50 380 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 95 ddBB 70°C 60 95 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 97 ddBB 70°C 60 98 25°C 20 34 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, 0°C 24 42 µµAA NNoo llooaadd 70°C 16 28 †Full range is 0°C to 70°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC27L2C TLC27L2AC PARAMETER TEST CONDITIONS TA† TLC27L2BC UNIT TLC27L7C MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277LL22CC RS = 50 Ω, RL = 1 MΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277LL22AACC RS = 50 Ω, RL = 1 MΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 235 2000 TTLLCC2277LL22BBCC RS = 50 Ω, RL = 1 MΩ Full range 3000 µV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 TTLLCC2277LL77CC RS = 50 Ω, RL = 1 MΩ Full range 1900 Average temperature coefficient of input 25°C to αVIO offset voltage 70°C 1 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 70°C 8 300 ppAA 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 70°C 50 600 ppAA −−00..22 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR ((sseeee NNoottee 55)) −−00..22 FFuullll rraannggee ttoo VV 8.5 25°C 8 8.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ 0°C 7.8 8.9 VV 70°C 7.8 8.9 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 50 860 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 11 MMΩΩ 0°C 50 1025 VV//mmVV 70°C 50 660 25°C 65 97 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 97 ddBB 70°C 60 97 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 97 ddBB 70°C 60 98 25°C 29 46 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, 0°C 36 66 µµAA NNoo llooaadd 70°C 22 40 †Full range is 0°C to 70°C. NOTES: 4 The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5 This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27L2I TLC27L2AI PARAMETER TEST CONDITIONS TA† TLC27L2BI UNIT TLC27L7I MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277LL22II RS = 50 Ω, RL = 1 MΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277LL22AAII RS = 50 Ω, RL = 1 MΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 240 2000 TTLLCC2277LL22BBII RS = 50 Ω, RL = 1 MΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 170 500 TTLLCC2277LL77II RS = 50 Ω, RL = 1 MΩ Full range 2000 AAvveerraaggee tteemmppeerraattuurree ccooeeffffiicciieenntt ooff 2255°CC ttoo αVVIIOO input offset voltage 85°C 11..11 µVV//°°CC 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 85°C 24 1000 ppAA 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 85°C 200 2000 ppAA −−00..22 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR ((sseeee NNoottee 55)) −−00..22 FFuullll rraannggee ttoo VV 3.5 25°C 3.2 4.1 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ −40°C 3 4.1 VV 85°C 3 4.2 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 50 480 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall AAVVDD vvoollttaaggee aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 11 MMΩΩ −40°C 50 900 VV//mmVV 85°C 50 330 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 95 ddBB 85°C 60 95 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 97 ddBB 85°C 60 98 25°C 20 34 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −40°C 31 54 µµAA NNoo llooaadd 85°C 15 26 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC27L2I TLC27L2AI PARAMETER TEST CONDITIONS TA† TLC27L2BI UNIT TLC27L7I MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC2277LL22II RS = 50 Ω, RL = 1 MΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC2277LL22AAII RS = 50 Ω, RL = 1 MΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 235 2000 TTLLCC2277LL22BBII RS = 50 Ω, RL = 1 MΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 TTLLCC2277LL77II RS = 50 Ω, RL = 1 MΩ Full range 2900 AAvveerraaggee tteemmppeerraattuurree ccooeeffffiicciieenntt ooff iinnppuutt 2255°CC ttoo αVVIIOO offset voltage 85°C 11 µVV//°°CC 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 85°C 26 1000 ppAA 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 85°C 220 2000 ppAA −−00..22 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR ((sseeee NNoottee 55)) −−00..22 FFuullll rraannggee ttoo VV 8.5 25°C 8 8.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ −40°C 7.8 8.9 VV 85°C 7.8 8.9 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 50 860 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 11 MMΩΩ −40°C 50 1550 VV//mmVV 85°C 50 585 25°C 65 97 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 97 ddBB 85°C 60 98 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 97 ddBB 85°C 60 98 25°C 29 46 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, −40°C 49 86 µµAA NNoo llooaadd 85°C 20 36 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC27L2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC27L7M UUNNIITT MIN TYP MAX TTLLCC2277LL22MM VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 mmVV RS = 50 Ω, RL = 1 MΩ Full range 12 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee TTLLCC2277LL77MM VVOO == 11..44 VV,, VVIICC == 00,, 25°C 170 500 µµVV RS = 50 Ω, RL = 1 MΩ Full range 3750 AAvveerraaggee tteemmppeerraattuurree ccooeeffffiicciieenntt ooff 2255°CC ttoo ααVVIIOO input offset voltage 125°C 11..44 µµVV//°°CC 25°C 0.1 60 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 125°C 1.4 15 nA 25°C 0.6 60 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 22..55 VV,, VVIICC == 22..55 VV 125°C 9 35 nA 00 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR ((sseeee NNoottee 55)) 00 FFuullll rraannggee ttoo VV 3.5 25°C 3.2 4.1 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ −55°C 3 4.1 VV 125°C 3 4.2 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 50 500 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 11 MMΩΩ −55°C 25 1000 VV//mmVV 125°C 25 200 25°C 65 94 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 95 ddBB 125°C 60 85 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 97 ddBB 125°C 60 98 25°C 20 34 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −55°C 35 60 µµAA NNoo llooaadd 125°C 14 24 †Full range is −55°C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC27L2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC27L7M UUNNIITT MIN TYP MAX TTLLCC2277LL22MM VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 mmVV RS = 50 Ω, RL = 1 MΩ Full range 12 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee TTLLCC2277LL77MM VVOO == 11..44 VV,, VVIICC == 00,, 25°C 190 800 µµVV RS = 50 Ω, RL = 1 MΩ Full range 4300 AAvveerraaggee tteemmppeerraattuurree ccooeeffffiicciieenntt ooff 2255°CC ttoo ααVVIIOO input offset voltage 125°C 11..44 µµVV//°°CC 25°C 0.1 60 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 125°C 1.8 15 nA 25°C 0.7 60 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) VVOO == 55 VV,, VVIICC == 55 VV 125°C 10 35 nA 00 −−00..33 2255°CC ttoo ttoo VV CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR ((sseeee NNoottee 55)) 00 FFuullll rraannggee ttoo VV 8.5 25°C 8 8.9 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 11 MMΩΩ −55°C 7.8 8.8 VV 125°C 7.8 9 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 50 860 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 11 MMΩΩ −55°C 25 1750 VV//mmVV 125°C 25 380 25°C 65 97 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 97 ddBB 125°C 60 91 25°C 70 97 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 97 ddBB 125°C 60 98 25°C 29 46 IIDDDD SSuuppppllyy ccuurrrreenntt ((ttwwoo aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, −55°C 56 96 µµAA NNoo llooaadd 125°C 18 30 †Full range is −55 °C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 operating characteristics, V = 5 V DD TLC27L2C TLC27L2AC PARAMETER TEST CONDITIONS TA TLC27L2BC UNIT TLC27L7C MIN TYP MAX 25°C 0.03 VVII((PPPP)) == 11 VV 0°C 0.04 RRLL == 11 MMΩ,, 70°C 0.03 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.03 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV 0°C 0.03 70°C 0.02 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 5 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 0°C 6 kkHHzz 70°C 4.5 25°C 85 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, 0°C 100 kkHHzz 70°C 65 25°C 34° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 36° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 70°C 30° operating characteristics, V = 10 V DD TLC27L2C TLC27L2AC PARAMETER TEST CONDITIONS TA TLC27L2BC UNIT TLC27L7C MIN TYP MAX 25°C 0.05 VVII((PPPP)) == 11 VV 0°C 0.05 RRLL == 11 MMΩ,, 70°C 0.04 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.04 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV 0°C 0.05 70°C 0.04 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 1 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 0°C 1.3 kkHHzz 70°C 0.9 25°C 110 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, 0°C 125 kkHHzz 70°C 90 25°C 38° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 40° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 70°C 34° 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 operating characteristics, VDD = 5 V TLC27L2I TLC27L2AI PARAMETER TEST CONDITIONS TA TLC27L2BI UNIT TLC27L7I MIN TYP MAX 25°C 0.03 VVII((PPPP)) == 11 VV −40°C 0.04 RRLL == 11 MMΩ,, 85°C 0.03 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.03 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV −40°C 0.04 85°C 0.02 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 5 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VRRVOOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −40°C 7 kkHHzz 85°C 4 25°C 85 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VSSVeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −40°C 130 kkHHzz 85°C 55 25°C 34° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 38° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 85°C 29° operating characteristics, VDD = 10 V TLC27L2I TLC27L2AI PARAMETER TEST CONDITIONS TA TLC27L2BI UNIT TLC27L7I MIN TYP MAX 25°C 0.05 VVII((PPPP)) == 11 VV −40°C 0.06 RRLL == 11 MMΩ,, 85°C 0.03 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.04 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV −40°C 0.05 85°C 0.03 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 1 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VRRVOOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −40°C 1.4 kkHHzz 85°C 0.8 25°C 110 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VSSVeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −40°C 155 kkHHzz 85°C 80 25°C 38° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 42° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 85°C 32° POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 operating characteristics, V = 5 V DD TLC27L2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC27L7M UUNNIITT MIN TYP MAX 25°C 0.03 VVII((PPPP)) == 11 VV −55°C 0.04 RRLL == 11 MMΩ,, 125°C 0.02 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.03 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 22..55 VV −55°C 0.04 125°C 0.02 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 5 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −55°C 8 kkHHzz 125°C 3 25°C 85 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −55°C 140 kkHHzz 125°C 45 25°C 34° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 39° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 125°C 25° operating characteristics, VDD = 10 V TLC27L2M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC27L7M UUNNIITT MIN TYP MAX 25°C 0.05 VVII((PPPP)) == 11 VV −55°C 0.06 RRLL == 11 MMΩ,, 125°C 0.03 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 ppFF,, 25°C 0.04 VV//µss SSeeee FFiigguurree 11 VVII((PPPP)) == 55..55 VV −55°C 0.06 125°C 0.03 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee ffS ==e e11 FkkiHHguzz,,re 2 RRSS == 2200 ΩΩ,, 2255°°CC 6688 nnVV//√√HHzz 25°C 1 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11VV MMOOHHΩΩ,,,, CCSSeeLLee == FF 22iigg00uu pprreeFF,, 11 −55°C 1.5 kkHHzz 125°C 0.7 25°C 110 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 ppFF,, −55°C 165 kkHHzz 125°C 70 25°C 38° φφmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 43° CCLL == 2200 ppFF,, SSeeee FFiigguurree 33 125°C 29° 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION single-supply versus split-supply test circuits Because the TLC27L2 and TLC27L7 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown in Figure 1. The use of either circuit gives the same result. VDD VDD+ − − VO VO VI + VI + CL RL CL RL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 1. Unity-Gain Amplifier 2 kΩ 2 kΩ VDD VDD+ 20 Ω − − 1/2 VDD VO VO + + 20 Ω 20 Ω 20 Ω VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 2. Noise-Test Circuit 10 kΩ 10 kΩ 100 Ω VDD 100 Ω VDD+ VI − VI − VO VO + 1/2 VDD + CL CL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 3. Gain-of-100 Inverting Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION input bias current Because of the high input impedance of the TLC27L2 and TLC27L7 operational amplifiers, attempts to measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements: 1. Isolate the device from other potential leakage sources.Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 8 5 V = VIC 1 4 Figure 4. Isolation Metal Around Device Inputs (JG and P packages) low-level output voltage To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to Figure 14 through Figure 19 in the Typical Characteristics of this data sheet. input offset voltage temperature coefficient Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing to minimize error. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (see Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached. (a) f = 100 kHz (b) BOM > f > 100 kHz (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal test time Inadequate test time is a frequent problem, especially when testing CMOS high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7 αVIO Temperature coefficient of input offset voltage Distribution 8, 9 vvss HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt 1100,, 1111 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee vvss SSuuppppllyy vvoollttaaggee 1122 vs Free-air temperature 13 vvss DDiiffffeerreennttiiaall iinnppuutt vvoollttaaggee 1144,,1166 VVVOOOLLL LLLooowww---llleeevvveeelll ooouuutttpppuuuttt vvvooollltttaaagggeee vvvsss FFFrrreeeeee---aaaiiirrr ttteeemmmpppeeerrraaatttuuurrreee 111555,,,111777 vvss LLooww--lleevveell oouuttppuutt ccuurrrreenntt 1188,, 1199 vvss SSuuppppllyy vvoollttaaggee 2200 AAVVDD LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee aammpplliiffiiccaattiioonn vvss FFrreeee--aaiirr tteemmppeerraattuurree 2211 vs Frequency 32, 33 IIB Input bias current vs Free-air temperature 22 IIO Input offset current vs Free-air temperature 22 VIC Common-mode input voltage vs Supply voltage 23 vvss SSuuppppllyy vvoollttaaggee 2244 IIDDDD SSuuppppllyy ccuurrrreenntt vs Free-air temperature 25 vvss SSuuppppllyy vvoollttaaggee 2266 SSRR SSlleeww rraattee vs Free-air temperature 27 Normalized slew rate vs Free-air temperature 28 VO(PP) Maximum peak-to-peak output voltage vs Frequency 29 vvss FFrreeee--aaiirr tteemmppeerraattuurree 3300 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh vs Supply voltage 31 vvss SSuuppppllyy vvoollttaaggee 3344 φφmm PPhhaassee mmaarrggiinn vvss FFrreeee--aaiirr tteemmppeerraattuurree 3355 vs Capacitive Load 36 Vn Equivalent input noise voltage vs Frequency 37 Phase shift vs Frequency 32, 33 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLC27L2 DISTRIBUTION OF TLC27L2 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 70 70 905 Amplifiers Tested From 6 Wafer Lots 905 Amplifiers Tested From 6 Wafer Lots 60 TVAD D= =25 5° CV 60 VTAD D= =25 1°0C V P Package P Package % 50 % 50 Units − 40 Units − 40 Percentage of 3200 Percentage of 2300 10 10 0 0 −5 −4 −3 −2 −1 0 1 2 3 4 5 −5 −4 −3 −2 −1 0 1 2 3 4 5 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV Figure 6 Figure 7 DISTRIBUTION OF TLC27LC AND TLC27L7 DISTRIBUTION OF TLC27LC AND TLC27L7 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT 70 70 356 Amplifiers Tested From 8 Wafer Lots 356 Amplifiers Tested From 8 Wafer Lots VDD = 5 V VDD = 10 V 60 TA = 25°C to 125°C 60 TA = 25°C to 125°C P Package P Package % 50 Outliers: % 50 Outliers: − (1) 19.2 µV/°C − (1) 18.7 µV/°C nits (1) 12.1 µV/°C nits (1) 11.6 µV/°C U 40 U 40 of of e e g g a 30 a 30 nt nt e e c c Per 20 Per 20 10 10 0 0 −10 −8 −6 −4 −2 0 2 4 6 8 10 −10 −8 −6 −4 −2 0 2 4 6 8 10 αVIO − Temperature Coefficient − µV/°C αVIO − Temperature Coefficient − µV/°C Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 5 16 VID = 100 mV VID = 100 mV V TA = 25°C V 14 ÎÎÎÎÎTA = 25°C e − 4 e − ÎVÎDD =Î 16 ÎV Î ag ag 12 Volt VDD = 5 V Volt ut 3 ut 10 p p ut VDD = 4 V ut vel O vel O 8 VDD = 10 V h-Le 2 VDD = 3 V h-Le 6 g g ÁHiÁ ÁHiÁ − − 4 ÁH HÁ1 ÁH HÁ OO OO ÁVVÁ ÁVVÁ2 0 0 0 −2 −4 −6 −8 −10 0 −5 −10 −15 −20 −25 −30 −35 −40 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 10 Figure 11 HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 16 VDD −1.6 ÎÎÎÎÎ ÁÁÁÁÁ Voltage − V 1124 ÎÎÎVTRÎÎÎAILD = == 2ÎÎÎ 11500° 0kCÎÎÎ ΩmVÎÎÎÎ Voltage − V −−11..87 VDD = 5 VÁÁIVOIDHÁ == 1−0Á50 m mAÁA ÁHigh-Level Output Á1068 ÁHigh-Level Output Á −−21−..219 VDD = 10 V ÁH − HÁ4 ÁH − ÁH −2.2 ÁVOVOÁ2 ÁVOVÁO −2.3 0 −2.4 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 20 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 12 Figure 13 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE 700 500 VDD = 5 V VDD = 10 V − mV ITOAL = = 2 55 °mCA − mV 450 TIOAL = = 2 55 °mCA e 600 e g g a a Volt Volt put VID = −100 mV put 400 Out 500 Out VID = −100 mV evel evel 350 VID = −1 V w-L w-L VID = −2.5 V o o − L 400 − L ÁOL ÁOL VID = −1 V ÁÁOL OL 300 ÁVVÁ ÁÁVV 300 250 0 0.5 1 1.5 2 2.5 3 3.3 4 0 1 2 3 4 5 6 7 8 9 10 VIC − Common-Mode Input Voltage − V VIC − Common-Mode Input Voltage − V Figure 14 Figure 15 LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE ÁÁÁÁ 800 900 ÁIÁOL Á= 5 mÁA − mV 700 TIVOAICL = == 2 55|V °mCIDA/2| − mV 870000 ÁÁVVÁÁIIDC ==ÁÁ −0.15ÁÁ VV e 600 e g g a a olt olt 600 VDD = 5 V V 500 ÎÎÎÎ V put ÎVDÎD = Î5 V Î put 500 Out 400 Out el el 400 ÎÎÎÎÎ v v Le 300 ÎÎÎÎÎ Le ÎÎVDDÎ = 1Î0 VÎ ow- ÎVÎDDÎ = 10Î V Î ow- 300 Á− LÁ200 ÁÁ− L Á200 L L L L OO OO ÁVVÁ100 ÁÁVV Á100 0 0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −75 −50 −25 0 25 50 75 100 125 VID − Differential Input Voltage − V TA − Free-Air Temperature − °C Figure 16 Figure 17 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT ÎÎÎÎÎ 1 3 ÎÎÎÎVID ÎÎ= −1ÎÎ V ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 0.9 VID = −1 V ge − V 0.8ÎÎÎÎTVAIC = ÎÎ= 2 05.°ÎÎ5C V ÎÎ ÎÎVDDÎ = 5Î V Î ge − V 2.5 ÎÎÎVTAIC ÎÎÎ= = 2 05.ÎÎΰ5C VÎÎÎÎÎÎÎ VDD = 16 V Volta 0.7 VDD = 4 V Volta 2 utput 0.6 VDD = 3 V utput VDD = 10 V O 0.5 O 1.5 el el ev 0.4 ev L L w- w- 1 ÁLoÁ0.3 ÁLoÁ − − ÁL LÁ0.2 ÁL ÁL OO OO ÁVVÁ ÁVVÁ0.5 0.1 0 0 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 18 Figure 19 LARGE-SIGNAL LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 2000 2000 TA = −55°C 1800 RL = 1 MΩ 1800 RL = 1 MΩ −40°C al V 1600 al V 1600 al Differenti ation − V/m 11240000 TA Î=2 05°°ÎCC al Differenti ation − V/m 11420000 VDD = 10 V n c n c arge-Sig e Amplifi 1080000 ÎÎ70°ÎÎC arge-Sig e Amplifi 1080000 ÁL g ÎÎÁLÁg ÁD − Dolta 600 85°C ÁD − DÁolta 600 AVAVV AVAVV VDD = 5 V Á 400 125°C ÁÁ 400 200 200 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 20 Figure 21 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† COMMON-MODE INPUT BIAS CURRENT AND INPUT OFFSET CURRENT INPUT VOLTAGE POSITIVE LIMIT vs vs FREE-AIR TEMPERATURE ÁÁÁÁ SUPPLY VOLTAGE 10000 A ÁÁÁÁ 16 p VDD = 10 V nts − ÁSVÁeICe =NÁ o5 tVe ÁA V 14 TA = 25°C et Curre 1000 ÁÁÁÁ ÎIIBÎ oltage − 12 s V Off 100 ut 10 s and ÎIÎIO de Inp 8 a o Bi 10 M nput mon- 6 nd IIO − IIIO 1 ÁVI − ComCÁ4 a VI 2 B B ÁÁ IIII 0.1 25 45 65 85 105 125 0 TA − Free-Air Temperature − °C 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically. Figure 22 Figure 23 SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 90 60 VO = VDD/2 TA = −55°C VO = VDD/2 80 No Load No Load 50 70 µnt − mAA 60 −40°C µnt − mAA 40 urre 50 urre VDD = 10 V y C 0°C y C 30 pl 40 pl p p Su 25°C Su ÁD − DÁ30 70°C ÁD − DÁ20 ÁIDIDÁ20 ÁIDIDÁ VDD = 5 V 125°C 10 10 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 24 Figure 25 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† SLEW RATE SLEW RATE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 0.07 0.07 AV = 1 VDD = 10 V RL =1 MΩ 0.06 RVIL(P =P1) M= Ω1 V 0.06 VI(PP) = 5.5 V CAVL == 210 pF CL = 20 pF See Figure 1 µss 0.05 TA = 25°C µss 0.05 − V/ See Figure 1 − V/ VDD = 10 V ate 0.04 ate 0.04 VI(PP) = 1 V R R w w Sle 0.03 Sle 0.03 − − SR SR VDD = 5 V 0.02 0.02 VI(PP) = 1 V VDD = 5 V 0.01 0.01 VI(PP) = 2.5 V 0.00 0.00 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 26 Figure 27 NORMALIZED SLEW RATE MAXIMUM-PEAK-TO-PEAK OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREQUENCY V 1.4 − 10 AV = 1 ge 1.3 ÎÎVDDÎ = 1Î0 VÎ VRILP =P1 = M 1Ω V Volta 9 w Rate 11..12 ÎVDÎÎD =ÎÎ 5 VÎÎÎÎ CL = 20 pF eak Output 876 ÎÎVDÎÎD = ÎÎ10 VÎÎ TTTAAA === −122555°5C°°CC zed Sle 0.19 ak-to-P 5 ÎÎVÎÎDD =ÎÎ 5 VÎÎ ali Pe 4 m Ám Á or 0.8 u N ÁmÁ 3 xi 0.7 ÁMaÁ 2 RL = 1 MΩ − See Figure 1 0.6 P) 1 P O( 0.5 V 0 −75 −50 −25 0 25 50 75 100 125 0.1 1 10 100 TA − Free-Air Temperature − °C f − Frequency − kHz Figure 28 Figure 29 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 150 140 VDD = 5 V VI = 10 mV VI = 10 mV 130 CL = 20 pF kHz130 SCeLe = F 2ig0u preF 3 kHz 120 TA = 25°C − − See Figure 3 h h dt110 dt 110 wi wi d d n n 100 a a B 90 B n n ai ai 90 G G y- y- nit 70 nit 80 U U − − 1 1 1 1 70 BB BB 50 60 30 50 −75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA − Free-Air Temperature − °C VDD − Supply Voltage − V Figure 30 Figure 31 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 107 VDD = 10 V 106 RL = 1 MΩ TA = 25°C al nti 105 0° e n Differ catio 104 30° Signal Amplifi 103 AVD 60° se Shift Large- oltage 102 90° Pha Á− ÁV ÎÎPhaÎse SÎhiftÎ ÁVD VDÁ 101 120° AA ÁÁ 1 150° 0.1 180° 1 10 100 1 k 10 k 100 k 1 M f − Frequency − Hz Figure 32 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS† LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 10 7 VDD = 10 V 10 6 RL = 1 MΩ TA = 25°C al nti 10 5 0° e n Differ catio 10 4 30° Large-Signal oltage Amplifi 1100 23 ÎÎÎAÎVDÎ 6900°° Phase Shift Á− ÁV ÎPÎhasÎe ShÎift Î D D ÁVÁV 10 1 120° AA ÁÁ 1 150° 0.1 180° 1 10 100 1 k 10 k 100 k 1 M f − Frequency − Hz Figure 33 PHASE MARGIN PHASE MARGIN vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 42° 40° VI = 10 mV VDD = 5 mV CL = 20 pF VI = 10 mV 40° TA = 25°C 36° CL = 20 pF See Figure 3 See Figure 3 n 38° n rgi rgi 32° a a M M se 36° se a a h h Á− P Á− PÁ28° Áφm m 34° Áφm mÁ 24° 32° 30° 20° −75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 34 Figure 35 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS PHASE MARGIN EQUIVALENT INPUT NOISE VOLTAGE vs vs CAPACITIVE LOAD FREQUENCY 37° ÁÁ200 VDD = 5 mV ÁzHzÁ VDD = 5 V H 35° TVAI = = 1 205 m°CV ÁÁ− nV/nV/ÁÁ175 RTAS == 2250° ΩC See Figure 3 ge 150 See Figure 2 a gin 33° Volt ar e 125 M s e oi s 31° N ha ut 100 P p ÁÁφm − mÁÁ29° alent In 75 v ui 50 27° Eq − N Vn 25 V 25° 0 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 CL − Capacitive Load − pF f − Frequency − Hz Figure 36 Figure 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION single-supply operation While the TLC27L2 and TLC27L7 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38). The low input bias current of the TLC27L2 and TLC27L7 permits the use of very large resistive values to implement the voltage divider, thus minimizing power consumption. The TLC27L2 and TLC27L7 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: 1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require RC decoupling. VDD R4 R1 R2 VI − VO V (cid:1) V R3 + REF DDR1 (cid:2) R3 (cid:3) (cid:4) VREF V (cid:1) V –V R4 (cid:2) V R3 C O REF I R2 REF 0.01 µF Figure 38. Inverting Amplifier With Voltage Reference − Power VO Logic Logic Logic Supply + (a) COMMON SUPPLY RAILS − Power VO + Logic Logic Logic Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION input characteristics The TLC27L2 and TLC27L7 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at VDD −1 V at TA = 25°C and at VDD −1.5 V at all other temperatures. The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L2 and TLC27L7 very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC27L2 and TLC27L7 are well suited for low-level signal processing; however, leakage currents on printed circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 40). Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC27L2 and TLC27L7 result in a low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise currents. − VI − − VO VO VO VI + + VI + (a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER Figure 40. Guard-Ring Schemes output characteristics The output stage of the TLC27L2 and TLC27L7 is designed to sink and source relatively high amounts of current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC27L2 and TLC27L7 were measured using a 20-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION output characteristics (continued) (a) CL = 20 pF, RL = NO LOAD (b) CL = 260 pF, RL = NO LOAD 2.5 V − TA = 25°C f = 1 kHz VO VI(PP) = 1 V VI + CL −2.5 V (c) CL = 310 pF, RL = NO LOAD (d) TEST CIRCUIT Figure 41. Effect of Capacitive Loads and Test Circuit Although the TLC27L2 and TLC27L7 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor (R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages P to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low values of R , a voltage offset from 0 V at the output occurs. Second, pullup resistor R acts as a P P drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION output characteristics (continued) VDD VI + IP RP − VO C IF R2 R1 IL RL − VO + V –V R (cid:1) DD O P I (cid:2) I (cid:2) I F L P ÁÁÁÁÁÁÁÁÁ IP = Pullup current required Áby tÁhe oÁperÁationÁal aÁmpÁlifierÁ Á (typically 500 µA) ÁÁÁÁÁÁÁÁÁ Figure 43. Compensation for Figure 42. Resistive Pullup to Increase V Input Capacitance OH feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically. electrostatic discharge protection The TLC27L2 and TLC27L7 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling these devices, as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode. latch-up Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L2 and TLC27L7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION 1/2 + TLC27L2 500 kΩ VO1 − 5 V 500 kΩ + VO2 − 1/2 TLC27L2 0.1 µF 500 kΩ 500 kΩ Figure 44. Multivibrator 100 kΩ VDD 100 kΩ Set + − 1/2 Reset TLC27L2 100 kΩ 33 kΩ NOTE: VDD = 5 V to 16 V Figure 45. Set/Reset Flip-Flop 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION VDD 1/2 VI + TLC27L7 VO − 90 kΩ VDD C S1 X1 B TLC4066 1 A SELECT: S1 S2 1 AV 10 100 C 9 kΩ S2 X2 Analog B 2 A Switch 2 1 kΩ NOTE: VDD = 5 V to 12 V Figure 46. Amplifier With Digital Gain Selection 10 kΩ VDD 20 kΩ VI − VO + 1/2 TLC27L2 100 kΩ NOTE: VDD = 5 V to 16 V Figure 47. Full-Wave Rectifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:7)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:4)(cid:8)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:5) (cid:2)(cid:9)(cid:10)(cid:3)(cid:11)(cid:12)(cid:13) (cid:14)(cid:15)(cid:16)(cid:3)(cid:17)(cid:13)(cid:17)(cid:12)(cid:18) (cid:19)(cid:20)(cid:7)(cid:2) (cid:12)(cid:14)(cid:16)(cid:15)(cid:7)(cid:1)(cid:17)(cid:12)(cid:18)(cid:7)(cid:2) (cid:7)(cid:11)(cid:14)(cid:2)(cid:17)(cid:21)(cid:17)(cid:16)(cid:15)(cid:13) SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005 APPLICATION INFORMATION 0.016 µF 5 V 10 kΩ 10 kΩ VI + VO 0.016 µF − 1/2 TLC27L2 NOTE: Normalized to fc = 1 kHz and RL = 10 kΩ Figure 48. Two-Pole Low-Pass Butterworth Filter R2 100 kΩ VDD R1 10 kΩ VIA − R1 VO 10 kΩ VIB + 1/2 TLC27L7 R2 100 kΩ NOTE: VDD = 5 V to 16 V (cid:3) (cid:4) V (cid:1) R2 V –V O R1 IB IA Figure 49. Difference Amplifier 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27L2ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2AC & no Sb/Br) TLC27L2ACDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2AC & no Sb/Br) TLC27L2ACDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2AC & no Sb/Br) TLC27L2ACP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC27L2AC & no Sb/Br) TLC27L2AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2AI & no Sb/Br) TLC27L2AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2AI & no Sb/Br) TLC27L2AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2AI & no Sb/Br) TLC27L2AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC27L2AI & no Sb/Br) TLC27L2BCD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2BC & no Sb/Br) TLC27L2BCDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2BC & no Sb/Br) TLC27L2BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2BC & no Sb/Br) TLC27L2BCP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC27L2BC & no Sb/Br) TLC27L2BID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2BI & no Sb/Br) TLC27L2BIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2BI & no Sb/Br) TLC27L2BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2BI & no Sb/Br) TLC27L2BIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC27L2BI & no Sb/Br) TLC27L2CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27L2CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2C & no Sb/Br) TLC27L2CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L2C & no Sb/Br) TLC27L2CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC27L2CP & no Sb/Br) TLC27L2CPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC27L2CP & no Sb/Br) TLC27L2CPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P27L2 & no Sb/Br) TLC27L2CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P27L2 & no Sb/Br) TLC27L2ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2I & no Sb/Br) TLC27L2IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2I & no Sb/Br) TLC27L2IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2I & no Sb/Br) TLC27L2IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L2I & no Sb/Br) TLC27L2IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC27L2IP & no Sb/Br) TLC27L2IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y27L2 & no Sb/Br) TLC27L2IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y27L2I & no Sb/Br) TLC27L2MD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 27L2M & no Sb/Br) TLC27L2MDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 27L2M & no Sb/Br) TLC27L2MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 27L2M & no Sb/Br) TLC27L7CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L7C & no Sb/Br) TLC27L7CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 27L7C & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC27L7CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC27L7CP & no Sb/Br) TLC27L7CPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P27L7 & no Sb/Br) TLC27L7ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L7I & no Sb/Br) TLC27L7IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L7I & no Sb/Br) TLC27L7IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L7I & no Sb/Br) TLC27L7IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 27L7I & no Sb/Br) TLC27L7IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC27L7IP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC27L2, TLC27L2M : •Catalog: TLC27L2 •Military: TLC27L2M NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC27L2ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1 TLC27L2CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27L2IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L2IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27L2MDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L7CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27L7CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1 TLC27L7IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC27L2ACDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2AIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2BCDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2BIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27L2CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27L2IDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L2IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27L2MDRG4 SOIC D 8 2500 350.0 350.0 43.0 TLC27L7CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27L7CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27L7IDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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