(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 (cid:1) Trimmed Offset Voltage: TLC279...900 µV Max at 25°C, D, J, N, OR PW PACKAGE (TOP VIEW) V = 5 V DD (cid:1) Input Offset Voltage Drift...Typically 0.1 µV/Month, Including the First 30 Days 1OUT 1 14 4OUT (cid:1) 1IN− 2 13 4IN− Wide Range of Supply Voltages Over 1IN+ 3 12 4IN+ Specified Temperature Range: 0°C to 70°C...3 V to 16 V VDD 4 11 GND −40°C to 85°C...4 V to 16 V 2IN+ 5 10 3IN+ −55°C to 125°C...4 V to 16 V 2IN− 6 9 3IN− (cid:1) 2OUT 7 8 3OUT Single-Supply Operation (cid:1) Common-Mode Input Voltage Range FK PACKAGE Extends Below the Negative Rail (C-Suffix (TOP VIEW) and I-Suffix Versions) − T T − (cid:1) Low Noise...Typically 25 nV/√Hz N OU COU N 1I 1 N4 4I at f = 1 kHz (cid:1) Output Voltage Range Includes Negative 3 2 1 20 19 1IN+ 4 18 4IN+ Rail NC 5 17 NC (cid:1) High Input Impedance...1012 Ω Typ VDD 6 16 GND (cid:1) ESD-Protection Circuitry NC 7 15 NC (cid:1) Small-Outline Package Option Also 2IN+ 8 14 3IN+ 9 10 11 12 13 Available in Tape and Reel (cid:1) Designed-In Latch-Up Immunity N − UT NCUT N − 2I 2O 3O 3I description NC − No internal connection The TLC274 and TLC279 quad operational amplifiers combine a wide range of input offset DISTRIBUTION OF TLC279 voltage grades with low offset voltage drift, high INPUT OFFSET VOLTAGE input impedance, low noise, and speeds 30 approaching that of general-purpose BiFET 290 Units Tested From 2 Wafer Lots devices. VDD = 5 V 25 TA = 25°C These devices use Texas Instruments silicon- N Package gate LinCMOS technology, which provides % offset voltage stability far exceeding the stability s − 20 available with conventional metal-gate nit U processes. e of 15 g The extremely high input impedance, low bias a nt currents, and high slew rates make these e c 10 cost-effective devices ideal for applications which er P have previously been reserved for BiFET and NFET products. Four offset voltage grades are 5 available (C-suffix and I-suffix types), ranging from the low-cost TLC274 (10 mV) to the high- precision TLC279 (900 µV). These advantages, in 0 −1200 −600 0 600 1200 combination with good common-mode rejection VIO − Input Offset Voltage − µV and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. LinCMOS is a trademark of Texas Instruments. (cid:17)(cid:18)(cid:15)(cid:24)(cid:23)(cid:3)(cid:1)(cid:20)(cid:15)(cid:21) (cid:24)(cid:8)(cid:1)(cid:8) (cid:12)(cid:13)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:12)(cid:27)(cid:13) (cid:12)! "#(cid:28)(cid:28)$(cid:13)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:12)"(cid:30)(cid:31)(cid:12)(cid:27)(cid:13) ((cid:30)(cid:31)$) Copyright  2001, Texas Instruments Incorporated (cid:17)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:13)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:12)(cid:26)(cid:12)"(cid:30)(cid:31)(cid:12)(cid:27)(cid:13)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:1)$+(cid:30)! (cid:20)(cid:13)!(cid:31)(cid:28)#(cid:29)$(cid:13)(cid:31)! !(cid:31)(cid:30)(cid:13)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:13)(cid:31)-) (cid:17)(cid:28)(cid:27)(#"(cid:31)(cid:12)(cid:27)(cid:13) %(cid:28)(cid:27)"$!!(cid:12)(cid:13). ((cid:27)$! (cid:13)(cid:27)(cid:31) (cid:13)$"$!!(cid:30)(cid:28)(cid:12)’- (cid:12)(cid:13)"’#($ (cid:31)$!(cid:31)(cid:12)(cid:13). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 description (continued) In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC274 and TLC279. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up. The TLC274 and TLC279 incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES CCHHIIPP TA AVTIO 2m5a°Cx OSUMTALLINLE CACRHRIPIER CERDAIPMIC PLADSIPTIC TSSOP FORM (PW) (Y) (D) (FK) (J) (N) 900 µV TLC279CD — — TLC279CN — — 2 mV TLC274BCD — — TLC274BCN — — 0°C to 70°C 5 mV TLC274ACD — — TLC274ACN — — 10 mV TLC274CD — — TLC274CN TLC274CPW TLC274Y 990000 µµVV TTLLCC227799IIDD —— —— TTLLCC227799IINN —— —— 22 mmVV TTLLCC227744BBIIDD —— —— TTLLCC227744BBIINN —— —— −−4400°°CC ttoo 8855°°CC 55 mmVV TTLLCC227744AAIIDD —— —— TTLLCC227744AAIINN —— —— 10 mV TLC274ID — — TLC274IN — — 900 µV TLC279MD TLC279MFK TLC279MJ TLC279MN — — −55°C to 125°C 10 mV TLC274MD TLC274MFK TLC274MJ TLC274MN — — The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC279CDR). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 equivalent schematic (each amplifier) VDD P3 P4 R6 R1 R2 N5 IN− P5 P6 P1 P2 IN+ C1 R5 OUT N3 N1 N2 N4 N6 N7 R3 D1 R4 D2 R7 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TLC274Y chip information These chips, when properly assembled, display characteristics similar to the TLC274C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS VDD (14) (13) (12) (11) (10) (9) (8) (4) (3) 1IN+ + (1) (2) 1OUT 1IN− − (5) (7) + 2IN+ 2OUT (6) − 2IN− (10) 68 3IN+ + (8) (9) 3OUT 3IN− − (12) (14) + 4IN+ 4OUT (13) − 4IN− 11 (1) (2) (3) (4) (5) (6) (7) GND 108 CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACK SIDE OF CHIP. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V DD Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V ID DD Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V I DD Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA I Output current, l (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA O Total current into V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA DD Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at the noninverting input with respect to the inverting input. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section). DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D 950 mW 7.6 mW/°C 608 mW 494 mW — FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW N 1575 mW 12.6 mW/°C 1008 mW 819 mW — PW 700 mW 5.6 mW/°C 448 mW — — recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UUNNIITT MIN MAX MIN MAX MIN MAX Supply voltage, VDD 3 16 4 16 4 16 V VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5 CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee,, VVIICC VV VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 Operating free-air temperature, TA 0 70 −40 85 −55 125 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC274C, TLC274AC, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC274BC, TLC279C UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744CC RS = 50 Ω, RL = 10 kΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC227744AACC RS = 50 Ω, RL = 10 kΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 340 2000 TTLLCC227744BBCC RS = 50 Ω, RL = 10 kΩ Full range 3000 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 320 900 TTLLCC227799CC RS = 50 Ω, RL = 10 kΩ Full range 1500 Average temperature coefficient of input 25°C to αVIO offset voltage 70°C 1.8 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 70°C 7 300 ppAA VVOO == 22..55 VV,, VVIICC == 22..55 VV 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 70°C 40 600 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) −0.2 Full range to V 3.5 25°C 3.2 3.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ 0°C 3 3.8 VV 70°C 3 3.8 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 5 23 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 1100 kkΩΩ 0°C 4 27 VV//mmVV 70°C 4 20 25°C 65 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 84 ddBB 70°C 60 85 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 94 ddBB 70°C 60 96 25°C 2.7 6.4 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, 0°C 3.1 7.2 mmAA NNoo llooaadd 70°C 2.3 5.2 †Full range is 0°C to 70°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC274C, TLC274AC, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC274BC, TLC279C UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744CC RS = 50 Ω, RL = 10 kΩ Full range 12 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC227744AACC RS = 50 Ω, RL = 10 kΩ Full range 6.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 390 2000 TTLLCC227744BBCC RS = 50 Ω, RL = 10 kΩ Full range 3000 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 370 1200 TTLLCC227799CC RS = 50 Ω, RL = 10 kΩ Full range 1900 Average temperature coefficient of 25°C to αVIO input offset voltage 70°C 2 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 70°C 7 300 ppAA VVOO ==..55 VV,, VVIICC == 55 VV 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 70°C 50 600 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) −0.2 Full range to V 8.5 25°C 8 8.5 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ 0°C 7.8 8.5 VV 70°C 7.8 8.4 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 0°C 0 50 mmVV 70°C 0 50 25°C 10 36 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 1100 kkΩΩ 0°C 7.5 42 VV//mmVV 70°C 7.5 32 25°C 65 85 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn 0°C 60 88 ddBB 70°C 60 88 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV 0°C 60 94 ddBB 70°C 60 96 25°C 3.8 8 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, 0°C 4.5 8.8 mmAA NNoo llooaadd 70°C 3.2 6.8 †Full range is 0°C to 70°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC274I, TLC274AI, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC274BI, TLC279I UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744II RS = 50 Ω, RL = 10 kΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC227744AAII RS = 50 Ω, RL = 10 kΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 340 2000 TTLLCC227744BBII RS = 50 Ω, RL = 10 kΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 320 900 TTLLCC227799II RS = 50 Ω, RL = 10 kΩ Full range 2000 αVIO Aofvfseerat gveo lttaegmeperature coefficient of input 258°5C°C to 1.8 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 85°C 24 1000 ppAA VVOO == 22..55 VV,, VVIICC == 22..55 VV 25°C 0.6 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 85°C 200 2000 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) −0.2 Full range to V 3.5 25°C 3.2 3.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ −40°C 3 3.8 VV 85°C 3 3.8 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 5 23 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 1100 kkΩΩ −40°C 3.5 32 VV//mmVV 85°C 3.5 19 25°C 65 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 81 ddBB 85°C 60 86 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 92 ddBB 85°C 60 96 25°C 2.7 6.4 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −40°C 3.8 8.8 mmAA NNoo llooaadd 85°C 2.1 4.8 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 10 V (unless otherwise noted) DD TLC274I, TLC274AI, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC274BI, TLC279I UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744II RS = 50 Ω, RL = 10 kΩ Full range 13 mmVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 0.9 5 TTLLCC227744AAII RS = 50 Ω, RL = 10 kΩ Full range 7 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVOO == 11..44 VV,, VVIICC == 00,, 25°C 390 2000 TTLLCC227744BBII RS = 50 Ω, RL = 10 kΩ Full range 3500 µVV VVOO == 11..44 VV,, VVIICC == 00,, 25°C 370 1200 TTLLCC227799II RS = 50 Ω, RL = 10 kΩ Full range 2900 Average temperature coefficient of input 25°C to αVIO offset voltage 85°C 2 µV/°C 25°C 0.1 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 85°C 26 1000 ppAA VVOO == 55 VV,, VVIICC == 55 VV 25°C 0.7 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 85°C 220 2000 ppAA −0.2 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) −0.2 Full range to V 8.5 25°C 8 8.5 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ −40°C 7.8 8.5 VV 85°C 7.8 8.5 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −40°C 0 50 mmVV 85°C 0 50 25°C 10 36 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 1100 kkΩΩ −40°C 7 47 VV//mmVV 85°C 7 31 25°C 65 85 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −40°C 60 87 ddBB 85°C 60 88 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −40°C 60 92 ddBB 85°C 60 96 25°C 3.8 8 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, −40°C 5.5 10 mmAA NNoo llooaadd 85°C 2.9 6.4 †Full range is −40°C to 85°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 5 V (unless otherwise noted) DD TLC274M, TLC279M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744MM RS = 50 Ω, RL = 10 kΩ Full range 12 mmVV VVIIOO IInnppuutt ooffffsseett vvoollttaaggee TTLLCC227799MM VVROOS === 5110..44 Ω VV,,, VVRIILCC = == 1 000,, kΩ Ful2l 5ra°nCge 320 3970500 µVV αVIO Aofvfseerat gveo lttaegmeperature coefficient of input 2152°5C° Cto 2.1 µV/°C 25°C 0.1 60 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 125°C 1.4 15 nA VVOO == 22..55 VV,, VVIICC == 22..55 VV 25°C 0.6 60 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 125°C 9 35 nA 0 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 4 4.2 VVIICCRR (see Note 5) 0 Full range to V 3.5 25°C 3.2 3.8 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ −55°C 3 3.8 VV 125°C 3 3.8 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 5 23 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 00..2255 VV ttoo 22 VV,, RRLL == 1100 kkΩΩ −55°C 3.5 35 VV//mmVV 125°C 3.5 16 25°C 65 80 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 81 ddBB 125°C 60 84 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 90 ddBB 125°C 60 97 25°C 2.7 6.4 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 22..55 VV,, VVIICC == 22..55 VV,, −55°C 4 10 mmAA NNoo llooaadd 125°C 1.9 4.4 †Full range is −55°C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics at specified free-air temperature, V = 10 V (unless) otherwise noted) DD TLC274M, TLC279M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† UUNNIITT MIN TYP MAX VVOO == 11..44 VV,, VVIICC == 00,, 25°C 1.1 10 TTLLCC227744MM RS = 50 Ω, RL = 10 kΩ Full range 12 mmVV VVIIOO IInnppuutt ooffffsseett vvoollttaaggee TTLLCC227799MM VVROOS === 5110..44 Ω VV,,, VVRIILCC = == 1 000,, kΩ Ful2l 5ra°nCge 370 14230000 µVV αVIO Aofvfseerat gveo lttaegmeperature coefficient of input 2152°5C° Cto 2.2 µV/°C 25°C 0.1 60 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ((sseeee NNoottee 44)) 125°C 1.8 15 nA VVOO == 55 VV,, VVIICC == 55 VV 25°C 0.7 60 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ((sseeee NNoottee 44)) 125°C 10 35 nA 0 −0.3 25°C to to V CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee 9 9.2 VVIICCRR (see Note 5) 0 Full range to V 8.5 25°C 8 8.5 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == 110000 mmVV,, RRLL == 1100 kkΩΩ −55°C 7.8 8.5 VV 125°C 7.8 8.4 25°C 0 50 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIDD == −−110000 mmVV,, IIOOLL == 00 −55°C 0 50 mmVV 125°C 0 50 25°C 10 36 LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee AAVVDD aammpplliiffiiccaattiioonn VVOO == 11 VV ttoo 66 VV,, RRLL == 1100 kkΩΩ −55°C 7 50 VV//mmVV 125°C 7 27 25°C 65 85 CCMMRRRR CCoommmmoonn--mmooddee rreejjeeccttiioonn rraattiioo VVIICC == VVIICCRRmmiinn −55°C 60 87 ddBB 125°C 60 86 25°C 65 95 SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo kkSSVVRR ((∆∆VVDDDD//∆∆VVIIOO)) VVDDDD == 55 VV ttoo 1100 VV,, VVOO == 11..44 VV −55°C 60 90 ddBB 125°C 60 97 25°C 3.8 8 IIDDDD SSuuppppllyy ccuurrrreenntt ((ffoouurr aammpplliiffiieerrss)) VVOO == 55 VV,, VVIICC == 55 VV,, −55°C 6.0 12 mmAA NNoo llooaadd 125°C 2.5 5.6 †Full range is −55°C to 125°C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 operating characteristics at specified free-air temperature, V = 5 V DD TLC274C, TLC274AC, TLC274AC, PARAMETER TEST CONDITIONS TAA TLC274BC, TLC279C UNIT MIN TYP MAX 25°C 3.6 VVIIPPPP == 11 VV 0°C 4 RRLL == 1100 Ω,, 70°C 3 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 2.9 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 22..55 VV 0°C 3.1 70°C 2.5 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 320 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 0°C 340 kkHHzz 70°C 260 25°C 1.7 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 PPFF,, 0°C 2 MMHHzz 70°C 1.3 25°C 46° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 47° CCLL == 2200 PPFF,, 70°C 44° operating characteristics at specified free-air temperature, V = 10 V DD TLC274C, TLC274AC, TLC274AC, PARAMETER TEST CONDITIONS TAA TLC274BC, TLC279C UNIT MIN TYP MAX 25°C 5.3 VVIIPPPP == 11 VV 0°C 5.9 RRLL == 1100 Ω,, 70°C 4.3 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 4.6 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 55..55 VV 0°C 5.1 70°C 3.8 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 200 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 0°C 220 kkHHzz 70°C 140 25°C 2.2 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 PPFF,, 0°C 2.5 MMHHzz 70°C 1.8 25°C 49° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, 0°C 50° CCLL == 2200 PPFF,, SSeeee FFiigguurree 33 70°C 46° 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 operating characteristics at specified free-air temperature, V = 5 V DD TLC274I, TLC274AI, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC274BI, TLC279I UUNNIITT MIN TYP MAX 25°C 3.6 VVIIPPPP == 11 VV −40°C 4.5 RRLL == 1100 kkΩ,, 85°C 2.8 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 2.9 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 22..55 VV −40°C 3.5 85°C 2.3 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 320 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 −40°C 380 kkHHzz 85°C 250 25°C 1.7 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 PPFF,, −40°C 2.6 MMHHzz 85°C 1.2 25°C 46° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 49° CCLL == 2200 PPFF,, SSeeee FFiigguurree 33 85°C 43° operating characteristics at specified free-air temperature, V = 10 V DD TLC274I, TLC274AI, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA TLC274BI, TLC279I UUNNIITT MIN TYP MAX 25°C 5.3 VVIIPPPP == 11 VV −40°C 6.7 RRLL == 1100 Ω,, 85°C 4 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 4.6 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 55..55 VV −40°C 5.8 85°C 3.5 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 200 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 −40°C 260 kkHHzz 85°C 130 25°C 2.2 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ==ee FF1100iigg uummrrVVee,, 33 CCLL == 2200 PPFF,, −40°C 3.1 MMHHzz 85°C 1.7 25°C 49° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −40°C 52° CCLL == 2200 PPFF,, SSeeee FFiigguurree 33 85°C 46° POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 operating characteristics at specified free-air temperature, V = 5 V DD TLC274M, TLC279M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA UUNNIITT MIN TYP MAX 25°C 3.6 VVIIPPPP == 11 VV −55°C 4.7 RRLL == 1100 kkΩ,, 125°C 2.3 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 2.9 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 22..55 VV −55°C 3.7 125°C 2 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 320 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 −55°C 400 kHz 125°C 230 25°C 1.7 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ee== FF 11iigg00uu mmrreeVV ,,33 CCLL == 2200 PPFF,, −55°C 2.9 MHz 125°C 1.1 25°C 46° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 49° CCLL == 2200 PPFF,, SSeeee FFiigguurree 33 125°C 41° operating characteristics at specified free-air temperature, V = 10 V DD TLC274M, TLC279M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA UUNNIITT MIN TYP MAX 25°C 5.3 VVIIPPPP == 11 VV −55°C 7.1 RRLL == 1100 Ω ,, 125°C 3.1 SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn CCLL == 2200 PPFF,, 25°C 4.6 VV//µss SSeeee FFiigguurree 11 VVIIPPPP == 55..55 VV −55°C 6.1 125°C 2.7 Vn Equivalent input noise voltage fS =e e 1 F ikgHurze, 2 RS = 20 Ω, 25°C 25 nV/√Hz 25°C 200 BBOOMM MMaaxxiimmuumm oouuttppuutt--sswwiinngg bbaannddwwiiddtthh VVRROOLL ==== 11 VV00 OOkkΩΩHH,,,, CCSSeeLLee == FF 22iigg00uu PPrreeFF ,,11 −55°C 280 kkHHzz 125°C 110 25°C 2.2 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh VVSSeeII ee== FF 11iigg00uu mmrreeVV ,,33 CCLL == 2200 PPFF,, −55°C 3.4 MMHHzz 125°C 1.6 25°C 49° φmm PPhhaassee mmaarrggiinn VVII == 1100 mmVV,, ff == BB11,, −55°C 52° CCLL == 2200 PPFF,, SSeeee FFiigguurree 33 125°C 44° 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 electrical characteristics, V = 5 V, T = 25°C (unless otherwise noted) DD A TLC274Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX VO = 1.4 V, VIC = 0, VIO Input offset voltage RS = 50 Ω, RL = 10 kΩ 1.1 10 mV IIO Input offset current (see Note 4) 0.1 pA VVOO == 22..55 VV,, VVIICC == 22..55 VV IIB Input bias current (see Note 4) 0.6 pA −0.2 −0.3 VICR Common-mode input voltage range (see Note 5) to to V 4 4.2 VOH High-level output voltage VID = 100 mV, RL = 10 kΩ 3.2 3.8 V VOL Low-level output voltage VID = −100 mV, IOL = 0 0 50 mV AVD Large-signal differential voltage amplification VO = 0.25 V to 2 V, RL = 10 kΩ 5 23 V/mV CMRR Common-mode rejection ratio VIC = VICRmin 65 80 dB kSVR Supply-voltage rejection ratio (∆VDD/∆VIO) VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB VO = 2.5 V, VIC = 2.5 V, IDD Supply current (four amplifiers) No load 2.7 6.4 mA electrical characteristics, V = 10 V, T = 25°C (unless otherwise noted) DD A TLC274Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX VO = 1.4 V, VIC = 0, VIO Input offset voltage RS = 50 Ω, RL = 10 kΩ 1.1 10 mV IIO Input offset current (see Note 4) 0.1 pA VVOO == 55 VV,, VVIICC == 55 VV IIB Input bias current (see Note 4) 0.7 pA −0.2 −0.3 VICR Common-mode input voltage range (see Note 5) to to V 9 9.2 VOH High-level output voltage VID = 100 mV, RL = 10 kΩ 8 8.5 V VOL Low-level output voltage VID = −100 mV, IOL = 0 0 50 mV AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ 10 36 V/mV CMRR Common-mode rejection ratio VIC = VICRmin 65 85 dB kSVR Supply-voltage rejection ratio (∆VDD/∆VIO) VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB VO = 5 V, VIC = 5 V, IDD Supply current (four amplifiers) No load 3.8 8 mA NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 operating characteristics, V = 5 V, T = 25°C DD A TLC274Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn RRLL == 1100 kkΩΩ,, CCLL == 2200 PPFF,, VIPP = 1 V 3.6 VV//µss See Figure 1 VIPP = 2.5 V 2.9 Vn Equivalent input noise voltage f = 1 kHz, RS = 20 Ω, See Figure 2 25 nV/√Hz VO = VOH, CL = 20 PF, RL = 10 kΩ, BOM Maximum output-swing bandwidth See Figure 1 320 kHz B1 Unity-gain bandwidth VI = 10 mV, CL = 20 PF, See Figure 3 1.7 MHz φm Phase margin VI = 10 mV, f = B1, CL = 20 PF, 46° See Figure 3 operating characteristics, V = 10 V, T = 25°C DD A TLC274Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX SSRR SSlleeww rraattee aatt uunniittyy ggaaiinn RRLL == 1100 kkΩΩ,, CCLL == 2200 PPFF,, VIPP = 1 V 5.3 VV//µss See Figure 1 VIPP = 5.5 V 4.6 Vn Equivalent input noise voltage f = 1 kHz, RS = 20 Ω, See Figure 2 25 nV/√Hz VO = VOH, CL = 20 PF, RL = 10 kΩ, BOM Maximum output-swing bandwidth See Figure 1 200 kHz B1 Unity-gain bandwidth VI = 10 mV, CL = 20 PF, See Figure 3 2.2 MHz φm Phase margin VI = 10 mV, f = B1, CL = 20 PF, 49° See Figure 3 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 PARAMETER MEASUREMENT INFORMATION single-supply versus split-supply test circuits Because the TLC274 and TLC279 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. VDD VDD+ − − VO VO VI + VI + CL RL CL RL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 1. Unity-Gain Amplifier 2 kΩ 2 kΩ VDD VDD+ 20 Ω − − 1/2 VDD 20 Ω VO VO + + 20 Ω 20 Ω VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 2. Noise-Test Circuit 10 kΩ 10 kΩ VDD VDD+ 100 Ω 100 Ω VI − VI − VO VO 1/2 VDD + + CL CL VDD− (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 3. Gain-of-100 Inverting Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 PARAMETER MEASUREMENT INFORMATION input bias current Because of the high input impedance of the TLC274 and TLC279 operational amplifiers, attempts to measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements: 1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 7 1 V = VIC 8 14 Figure 4. Isolation Metal Around Device Inputs (J and N packages) low-level output voltage To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet. input offset voltage temperature coefficient Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing to minimize error. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 PARAMETER MEASUREMENT INFORMATION full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure5). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached. (a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal test time Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7 αVIO Temperature coefficient of input offset voltage Distribution 8, 9 vvss HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt 1100,, 1111 VVOOHH HHiigghh--lleevveell oouuttppuutt vvoollttaaggee vvss SSuuppppllyy vvoollttaaggee 1122 vs Free-air temperature 13 vvss CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee 1144,, 1155 vvss DDiiffffeerreennttiiaall iinnppuutt vvoollttaaggee 1166 VVOOOLLL LLooww--lleevveell oouuttppuutt vvoollttaaggee vvss FFrreeee--aaiirr tteemmppeerraattuurree 1177 vs Low-level output current 18, 19 vvss SSuuppppllyy vvoollttaaggee 2200 AAVVDD LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee aammpplliiffiiccaattiioonn vvss FFrreeee--aaiirr tteemmppeerraattuurree 2211 vs Frequency 32, 33 IIB Input bias current vs Free-air temperature 22 IIO Input offset current vs Free-air temperature 22 VIC Common-mode input voltage vs Supply voltage 23 vvss SSuuppppllyy vvoollttaaggee 2244 IIDDDD SSuuppppllyy ccuurrrreenntt vs Free-air temperature 25 vvss SSuuppppllyy vvoollttaaggee 2266 SSRR SSlleeww rraattee vs Free-air temperature 27 Normalized slew rate vs Free-air temperature 28 VO(PP) Maximum peak-to-peak output voltage vs Frequency 29 vvss FFrreeee--aaiirr tteemmppeerraattuurree 3300 BB11 UUnniittyy--ggaaiinn bbaannddwwiiddtthh vs Supply voltage 31 vvss SSuuppppllyy vvoollttaaggee 3344 φφmm PPhhaassee mmaarrggiinn vvss FFrreeee--aaiirr tteemmppeerraattuurree 3355 vs Load capacitance 36 Vn Equivalent input noise voltage vs Frequency 37 Phase shift vs Frequency 32, 33 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLC274 DISTRIBUTION OF TLC274 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 60 60 ÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑ 753 Amplifiers Tested From 6 Wafer Lots 753 Amplifiers Tested From 6 Wafer Lots ÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑ 50 TVAD=D 2=5 °5C V 50 TVAD D= =25 1°0C V % N Package % N Package s − 40 s − 40 nit nit U U e of 30 e of 30 g g a a nt nt e e c 20 c 20 er er P P 10 10 0 0 −5 −4 −3 −2 −1 0 1 2 3 4 5 −5 −4 −3 −2 −1 0 1 2 3 4 5 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV Figure 6 Figure 7 DISTRIBUTION OF TLC274 AND TLC279 DISTRIBUTION OF TLC274 AND TLC279 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT 60 ÑÑÑÑÑÑÑÑÑÑÑÑ 60ÑÑÑÑÑÑÑÑÑÑÑÑ 324 Amplifiers Tested From 8 Wafer Lots ÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑ324 ÑAmpÑlifieÑrs TÑesteÑd FrÑom Ñ8 WaÑfer ÑLotsÑ VDD = 5 V VDD = 10 V 50 TA = 25°C to 125°C 50 TA = 25°C to 125°C N Package N Package % Outliers: % Outliers: nits − 40 (1) 20.5 V/°C nits − 40 (1) 21.2 V/C U U ge of 30 ge of 30 nta nta Perce 20 Perce 20 10 10 0 0 −10 −8 −6 −4 −2 0 2 4 6 8 10 −10 −8 −6 −4 −2 0 2 4 6 8 10 αVIO − Temperature Coefficient − µV/°C αVIO − Temperature Coefficient − µV/°C Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† Q HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT 5 16 VID = 100 mV VID = 100 mV TA = 25°C 14 TA = 25°C − V 4 − V VDD = 16 V e e 12 g g a a Volt VDD = 5 V Volt 10 ut 3 ut p p Out VDD = 4 V Out 8 el el VDD = 10 V Lev 2 VDD = 3 V Lev 6 h- h- g g Hi Hi 4 − 1 − H H O O V V 2 0 0 0 −2 −4 −6 −8 −10 0 −5 −10 −15 −20 −25 −30 −35 −40 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 10 Figure 11 HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 16 VDD−1.6 VID = 100 mV IOH = −5 mA e − V 1142 TRAL == 2150° kCΩ ge − V VVDDDD−−11..78 VDD = 5 V VID = 100 mA g a ut Volta 10 put Volt VDD−1.9 Outp 8 Out VDD−2 el vel VDD = 10 V v e h-Le 6 gh-L VDD−2.1 − Hig 4 − Hi VDD−2.2 H H O VO 2 V VDD−2.3 0 VDD−2.4 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 12 Figure 13 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE 700 500 VDD = 5 V VDD = 10 V 650 V IOL = 5 mA V IOL = 5 mA − m TA = 25°C − m 450 TA = 25°C e 600 e g g a a put Volt 550 VID = −100 mV put Volt 400 ut 500 ut VID = −100 mV O O Level 450 Level 350 VVIIDD == −−21. 5V V w- w- o o L 400 L − − 300 L VID = −1 V L O O V 350 V 300 250 0 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 VIC − Common-Mode Input Voltage − V VIC − Common-Mode Input Voltage − V Figure 14 Figure 15 LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE 800 900 IOL = 5 mA IOL = 5 mA V 700 VIC = |VID/2| V 800 VID = −1 V − m TA = 25°C − m 700 VIC = 0.5 V e 600 e g g a a olt olt 600 VDD = 5 V V 500 V put VDD = 5 V put 500 ut 400 ut O O el el 400 ev 300 ev VDD = 10 V L L w- VDD = 10 V w- 300 o o L 200 L − − 200 L L O O V 100 V 100 0 0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −75 −50 −25 0 25 50 75 100 125 VID − Differential Input Voltage − V TA − Free-Air Temperature − °C Figure 16 Figure 17 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 1 3 VID = −1 V VID = −1 V e − V 00..89 TVAIC = = 2 05.°5C V VDD = 5 V e − V 2.5 TVAIC = = 2 05.°5C V ÑÑVÑÑDD =ÑÑ 16ÑÑ V ÑÑ ag 0.7 ag olt VDD = 4 V olt 2 put V 0.6 VDD = 3 V put V VDD = 10 V ut 0.5 ut 1.5 O O vel 0.4 vel e e w-L 0.3 w-L 1 o o L L − 0.2 − OL OL 0.5 V V 0.1 0 0 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 18 Figure 19 LARGE-SIGNAL LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 60 50 TA = −55°C RL = 10 kΩ 45 RL = 10 kΩ ential V/mV 50 ÑTAÑ = 0°ÑC ential V/mV 40 VDD = 10 V Differ on − 40 Differ on − 35 al ati al ati 30 n c n c Sig plifi 30 Sig plifi 25 arge- e Am ÑTÑA = Ñ25°CÑ arge- e Am 20 VDD = 5 V ÁÁVD − LÁÁVDVoltag 20 ÑÑTTÑÑAA == ÑÑ18255°C°ÑÑC ÁÁVD − LVDÁÁVoltag 15 AA AA 10 ÁÁ 10 ÁÁ 5 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 20 Figure 21 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† INPUT BIAS CURRENT AND INPUT OFFSET CURRENT COMMON-MODE vs INPUT VOLTAGE POSITIVE LIMIT FREE-AIR TEMPERATURE vs SUPPLY VOLTAGE 10000 A p VDD = 10 V 16 nts − SVeICe =N o5 tVe A V 14 TA = 25°C urre 1000 ÑÑÑ e − Offset C 100 ÑIIÑB ÑÑÑ ut Voltag 1102 d p as an ÑIIÑO ode In 8 Bi 10 M ut n- p o 6 n m − I m o O 1 C 4 II − d C an VI 2 B II 0.1 25 45 65 85 105 125 0 TA − Free-Air Temperature − °C 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically. Figure 22 Figure 23 SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 10 8 9 VO = VDD/2 VO = VDD/2 7 No Load No Load 8 TA = −55°C A A 6 m m Supply Current − 4657 ÑÑTÑÑA =ÑÑ 25°CÑÑ ÑTAÑ = 0Ñ°C Supply Current − 435 VDD = 10 V − DD 3 − DD 2 VDD = 5 V I 2 ÑÑÑÑ I TA = 70°C ÑÑÑÑÑÑÑÑÑ 1 1 ÑÑTA =Ñ 125Ñ°CÑ 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 24 Figure 25 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† SLEW RATE SLEW RATE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 8 8 AV = 1 ÑÑÑÑÑAV = 1 7 RVILP =P 1=0 1 k VΩ 7 ÑÑVVÑÑDIPDP =ÑÑ= 150.5ÑÑ V V ÑÑSRCeLLe == F 12ig00u kprFΩe 1 6 CL = 20 pF 6 µs TA = 25°C s ew Rate − V/ 45 See Figure 1 µw Rate − V/ 54 VVDIPDP == 110 V V SR − Sl 3 R − Sle 3 2 S VDD = 5 V 2 VIPP = 1 V 1 1 VDD = 5 V VIPP = 2.5 V 0 0 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 26 Figure 27 NORMALIZED SLEW RATE MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREQUENCY 1.5 V 10 − 1.4 AVVIP =P 1= 1 V age 9 VDD = 10 V 1.3 VDD = 10 V RCLL == 1200 kpΩF ut Volt 8 TA = 125°C w Rate 11..21 VDD = 5 V ak Outp 67 TTAA == −255°5C°C e e malized Sl 0.19 Peak-to-P 45 VDD = 5 V r m No 0.8 mu 3 xi 0.7 Ma 2 RL = 10 kΩ − See Figure 1 0.6 P) 1 P 0.5 VO( 0 −75 −50 −25 0 25 50 75 100 125 10 100 1000 10000 TA − Free-Air Temperature − °C f − Frequency − kHz Figure 28 Figure 29 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 3 2.5 VDD = 5 V VI = 10 mV VI = 10 mV CL = 20 pF MHz 2.5 SCeLe = F 2ig0u prFe 3 MHz STAee = F 2ig5°uCre 3 width − width − 2 Gain Band 2 Gain Band − Unity- 1.5 − Unity- 1.5 B1 B1 1 1 −75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA − Free-Air Temperature − °C VDD − Supply Voltage − V Figure 30 Figure 31 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 107 VDD = 5 V 106 RL = 10 kΩ al TA = 25°C nti 105 0° e n Differ catio 104 30° nal plifi AVD Sig Am 103 60° hift ÁVD − Large-VDÁVoltage 10120 Phase Shift 1920°0° Phase S ÁAAÁ 1 150° 0.1 180° 10 100 1 k 10 k 100 k 1 M 10 M f − Frequency − Hz Figure 32 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS† LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 107 VDD = 10 V 106 RL = 10 kΩ al TA = 25°C nti 105 0° e n Differ catio 104 30° nal plifi AVD Á− Large-SigÁVoltage Am 110023 Phase Shift 6900°° Phase Shift ÁVD ÁVD 10 120° AA ÁÁ 1 150° 0.1 180° 10 100 1 k 10 k 100 k 1 M 10 M f − Frequency − Hz Figure 33 PHASE MARGIN PHASE MARGIN vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 53° 50° 52° VDD = 5 V 48° VI = 10 mV 51° CL = 20 pF See Figure 3 Margin 50° Margin 46° − Phase 4498°° − Phase 44° m m φ 47° VI = 10 mV φ CL = 20 pF 42° 46° TA = 25°C See Figure 3 45° 40° 0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125 VDD − Supply Voltage − V TA − Free-Air Temperature − °C Figure 34 Figure 35 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 TYPICAL CHARACTERISTICS PHASE MARGIN EQUIVALENT INPUT NOISE VOLTAGE vs vs LOAD CAPACITANCE FREQUENCY 50° 400 z VDD = 5 V H VDD = 5 V VI = 10 mV V/ RS = 20 Ω 45° TA = 25°C n TA = 25°C n See Figure 3 ge − 300 See Figure 2 Margi 40° Volta hase Noise 200 − Pm 35° nput φ nt I e val 100 30° ui q E − n V 25° 0 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 CL − Capacitive Load − pF f − Frequency − Hz Figure 36 Figure 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION single-supply operation While the TLC274 and TLC279 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38). The low input bias current of the TLC274 and TLC279 permits the use of very large resistive values to implement the voltage divider, thus minimizing power consumption. The TLC274 and TLC279 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: 1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require R decoupling. C VDD R4 R1 R3 R2 VREF = VDD R1 + R3 VI − + VO VO = (VREF − VI)RR42 + VREF VREF C R3 0.01 µF Figure 38. Inverting Amplifier With Voltage Reference − Power VO Logic Logic Logic Supply + (a) COMMON SUPPLY RAILS − Power Logic Logic Logic VO + Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION input characteristics The TLC274 and TLC279 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at V − 1 V at T = 25°C and at V − 1.5 V at all other temperatures. DD A DD The use of the polysilicon-gate process and the careful input circuit design gives the TLC274 and TLC279 very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC274 and TLC279 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 40). Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC274 and TLC279 result in a very low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise currents. − VI − − VO VO VO VI + + VI + (a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER Figure 40. Guard-Ring Schemes output characteristics The output stage of the TLC274 and TLC279 is designed to sink and source relatively high amounts of current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC274 and TLC279 were measured using a 20-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION output characteristics (continued) (a) CL = 20 pF, RL = NO LOAD (b) CL = 130 pF, RL = NO LOAD 2.5 V − VO VI + CL TA = 25°C f = 1 kHz VIPP = 1 V −2.5 V (c) CL = 150 pF, RL = NO LOAD (d) TEST CIRCUIT Figure 41. Effect of Capacitive Loads and Test Circuit Although the TLC274 and TLC279 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor (R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the P use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between approximately 60 Ω and 180 Ω, depending on how hard the op amp input is driven. With very low values of R , P a voltage offset from 0 V at the output occurs. Second, pullup resistor R acts as a drain load to N4 and the gain P of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION output characteristics (continued) VDD C VI + IP RP − VO − IF VO + R2 R1 IL RL Rp = VDD − VO Figure 43. Compensation for IF + IL + IP Input Capacitance IP = Pullup current required by the operational amplifier (typically 500 µA) Figure 42. Resistive Pullup to Increase V OH feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically. electrostatic discharge protection The TLC274 and TLC279 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature-dependent and have the characteristics of a reverse-biased diode. latch-up Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC274 and TLC279 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION 10 kΩ 10 kΩ 0.016 µF 0.016 µF 10 kΩ VI − 1/4 10 kΩ − TLC274 5 V 1/4 10 kΩ + TLC274 − 1/4 + TLC274 Low Pass + HIgh Pass 5 kΩ Band Pass R = 5 kΩ (3/d−1) (see Note A) NOTE A: d = damping factor, 1/Q Figure 44. State-Variable Filter 12 V VI + H.P. 5082-2835 1/4 TLC274 + 1/4 − TLC274 VO 0.5 µF N.O. − Mylar Reset 100 kΩ Figure 45. Positive-Peak Detector 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION VI (see Note A) 1.2 kΩ 100 kΩ 0.47 µF 4.7 kΩ TL431 − 20 kΩ 1/4 1 kΩ TIP31 0.1 µF TLC274 15 Ω + TIS193 + 250 µF, 25 V − VO (see Note B) 10 kΩ 47 kΩ 0.01 µF 22 kΩ 110 Ω NOTES: B. VI = 3.5 V to 15 V C. VO = 2 V, 0 to 1 A Figure 46. Logic-Array Power Supply 9 V VO (see Note A) 0.1 µF 10 kΩ 9 V C 1/4 100 kΩ − TLC274 R2 1/4 10 kΩ TLC274 VO (see Note B) + 100 kΩ 1 R1 R1 fO = 4C(R2) R2 47 kΩ R3 NOTES: A. VO(PP) = 8 V B. VO(PP) = 4 V Figure 47. Single-Supply Function Generator POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:11) (cid:2)(cid:12)(cid:13)(cid:3)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:19)(cid:3)(cid:20)(cid:16)(cid:20)(cid:15)(cid:21) (cid:22)(cid:23)(cid:8)(cid:24) (cid:15)(cid:17)(cid:19)(cid:18)(cid:8)(cid:1)(cid:20)(cid:15)(cid:21)(cid:8)(cid:2) (cid:8)(cid:14)(cid:17)(cid:2)(cid:20)(cid:25)(cid:20)(cid:19)(cid:18)(cid:16) SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001 APPLICATION INFORMATION 5 V VI− + 1/4 10 kΩ 100 kΩ TLC279 − − 1/4 TLC279 VO + 10 kΩ − R1, 10 kΩ 1/4 10 kΩ 95 kΩ (see Note A) TLC279 VI+ + −5 V NOTE C: CMRR adjustment must be noninductive. Figure 48. Low-Power Instrumentation Amplifier 5 V − 1/4 R R TLC274 VO 10 MΩ 10 MΩ VI + 2C 540 pF f (cid:1) 1 NOTCH 2(cid:1)RC R/2 5 MΩ C C 270 pF 270 pF Figure 49. Single-Supply Twin-T Notch Filter 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC274ACD ACTIVE SOIC D 14 50 Green (RoHS Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274AC & no Sb/Br) TLC274ACDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274AC & no Sb/Br) TLC274ACN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274ACN & no Sb/Br) TLC274ACNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274ACN & no Sb/Br) TLC274AID ACTIVE SOIC D 14 50 Green (RoHS Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274AI & no Sb/Br) TLC274AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274AI & no Sb/Br) TLC274AIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC274AIN & no Sb/Br) TLC274BCD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274BC & no Sb/Br) TLC274BCDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274BC & no Sb/Br) TLC274BCDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274BC & no Sb/Br) TLC274BCN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274BCN & no Sb/Br) TLC274BCNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274BCN & no Sb/Br) TLC274BID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274BI & no Sb/Br) TLC274BIDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274BI & no Sb/Br) TLC274BIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274BI & no Sb/Br) TLC274BIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274BI & no Sb/Br) TLC274BIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC274BIN & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC274CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274C & no Sb/Br) TLC274CDB ACTIVE SSOP DB 14 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274CDBG4 ACTIVE SSOP DB 14 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274CDBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274CDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274C & no Sb/Br) TLC274CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274C & no Sb/Br) TLC274CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274C & no Sb/Br) TLC274CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274CN & no Sb/Br) TLC274CNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC274CN & no Sb/Br) TLC274CNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC274 & no Sb/Br) TLC274CPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 P274 & no Sb/Br) TLC274ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274I & no Sb/Br) TLC274IDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274I & no Sb/Br) TLC274IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC274I & no Sb/Br) TLC274IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC274IN & no Sb/Br) TLC274INE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC274IN & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC274IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 P274 & no Sb/Br) TLC274IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y274 & no Sb/Br) TLC274IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Y274 & no Sb/Br) TLC274MD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 TLC274M & no Sb/Br) TLC274MDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 TLC274M & no Sb/Br) TLC274MDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 TLC274M & no Sb/Br) TLC279CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC279C & no Sb/Br) TLC279CDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC279C & no Sb/Br) TLC279CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TLC279C & no Sb/Br) TLC279CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TLC279CN & no Sb/Br) TLC279ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC279I & no Sb/Br) TLC279IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TLC279I & no Sb/Br) TLC279IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TLC279IN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 5-Apr-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC274ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC274AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC274CDBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1 TLC274CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC274CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC274CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TLC274CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLC274IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLC274MDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC279CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC279IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Apr-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC274ACDR SOIC D 14 2500 350.0 350.0 43.0 TLC274AIDR SOIC D 14 2500 350.0 350.0 43.0 TLC274CDBR SSOP DB 14 2000 367.0 367.0 38.0 TLC274CDR SOIC D 14 2500 350.0 350.0 43.0 TLC274CDR SOIC D 14 2500 333.2 345.9 28.6 TLC274CNSR SO NS 14 2000 367.0 367.0 38.0 TLC274CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLC274IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLC274MDRG4 SOIC D 14 2500 350.0 350.0 43.0 TLC279CDR SOIC D 14 2500 350.0 350.0 43.0 TLC279IDR SOIC D 14 2500 350.0 350.0 43.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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