Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 TL97x Output Rail-To-Rail Very-Low-Noise Operational Amplifiers 1 Features 3 Description • Rail-to-RailOutputVoltageSwing: The TL97x family of single, dual, and quad 1 operational amplifiers operates at voltages as low as ±2.4VatV = ±2.5V CC ±1.35 V and features output rail-to-rail signal swing. • VeryLowNoiseLevel:4nV/√Hz The TL97x boast characteristics that make them • Ultra-LowDistortion:0.003% particularly well suited for portable and battery- • HighDynamicFeatures:12MHz,5V/μs suppliedequipment.Verylownoiseandlowdistortion characteristics make them ideal for audio • OperatingRange:2.7Vto12V preamplification. • Latch-UpPerformanceExceeds100mAPer The TL971 is housed in the space-saving 5-pin SOT- JESD78,ClassII 23 package, which simplifies board design because • ESDPerformanceTestedPerJESD22 of the ability to be placed anywhere (outside – 2000-VHuman-BodyModel dimensionsare2.8mm× 2.9mm). – 1500-VCharged-DeviceModel DeviceInformation(1) 2 Applications PARTNUMBER PACKAGE(PIN) BODYSIZE(NOM) SOIC(8) 4.90mm×3.90mm • PortableEquipment TL971 SOT-23(5) 2.80mm×2.90mm – MusicPlayers MSOP(8) 3.00mm×3.00mm – Tablets PDIP(8) 9.60mm×6.40mm – CellPhones TL972 SOIC(8) 4.90mm×3.90mm • InstrumentationandSensors TSSOP(8) 3.00mm×4.40mm • ProfessionalAudioCircuits PDIP(14) 19.30mm×6.40mm TL974 SOIC(14) 8.60mm×3.90mm TSSOP(14) 5.00mm×4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic RIN VIN + VOUT RG RF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.........................................9 2 Applications........................................................... 1 8.3 FeatureDescription...................................................9 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................10 4 SimplifiedSchematic............................................. 1 9 ApplicationandImplementation........................ 11 9.1 TypicalApplication .................................................11 5 RevisionHistory..................................................... 2 10 PowerSupplyRecommendations..................... 13 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 13 7 Specifications......................................................... 4 11.1 LayoutGuidelines.................................................13 7.1 AbsoluteMaximumRatings......................................4 11.2 LayoutExample....................................................13 7.2 ESDRatings..............................................................4 12 DeviceandDocumentationSupport................. 15 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................4 12.1 RelatedLinks........................................................15 7.5 ElectricalCharacteristics...........................................5 12.2 Trademarks...........................................................15 7.6 TypicalCharacteristics..............................................5 12.3 ElectrostaticDischargeCaution............................15 12.4 Glossary................................................................15 8 DetailedDescription.............................................. 9 13 Mechanical,Packaging,andOrderable 8.1 Overview...................................................................9 Information........................................................... 15 5 Revision History ChangesfromRevisionG(May2012)toRevisionH Page • AddedApplications,DeviceInformationtable,PinFunctionstable,ESDRatingstable,ThermalInformationtable, TypicalCharacteristics,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 ChangesfromRevisionF(December2009)toRevisionG Page • ChangedslewrateMINvalue................................................................................................................................................ 5 2 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 6 Pin Configuration and Functions TL971...DBV PACKAGE TL971...D PACKAGE TL972...D, DGK, P, OR PW PACKAGE TL972...DRG PACKAGE TL974...D, N, OR PW PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) (TOPVIEW) (TOPVIEW) VOICUNCT+– 123 54 IVNC–C+ IINNNC+– 123 876 VNOCCUCT+ OIINNU11T+–1 123 876 VOINCU2CT–+2 OINU1T–1 12 87 OVCUCT+2 OIINNU11T+–1 123 111432 OIINNU44T+–4 VCC– 4 5 NC VCC– 4 5 IN2+ IN1+ 3 6 IN2– VCC+ 4 11 VCC– VCC– 4 5 IN2+ IN2+ 5 10 IN3+ NC–No internal connection IN2– 6 9 IN3– OUT2 7 8 OUT3 PinFunctions PIN TL971 TL971 TL972 TL974 TYPE DESCRIPTION NAME D,DGK,P, DBV D DRG D,N,PW PW IN+ 3 3 — — — I Noninvertinginput IN– 4 2 — — — I Invertinginput IN1+ — — 3 3 3 I Noninvertinginput IN1– — — 2 2 2 I Invertinginput IN2+ — — 5 5 5 I Noninvertinginput IN2– — — 6 6 6 I Invertinginput IN3+ — — — — 10 I Noninvertinginput IN3– — — — — 9 I Invertinginput IN4+ — — — — 12 I Noninvertinginput IN4– — — — — 13 I Invertinginput 1 NC — 5 — — — — NoConnect 8 OUT 1 6 — — — O Output OUT1 — — 1 1 1 O Output OUT2 — — 7 7 7 O Output OUT3 — — — — 8 O Output OUT4 — — — — 14 O Output VCC+ 5 7 8 8 4 - Positivesupply VCC– 2 4 4 4 11 - Negativesupply Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange 2.7 15 V CC V Differentialinputvoltage(2) ±1V V ID V Inputvoltagerange(3) V –0.3 V +0.3 V IN CC– CC+ T Maximumjunctiontemperature 150 °C J T Storagetemperaturerange –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Differentialvoltagesforthenoninvertinginputterminalarewithrespecttotheinvertinginputterminal. (3) TheinputandoutputvoltagesmustneverexceedV +0.3V. CC 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) 2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101, V allpins(2) 1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions MIN MAX UNIT V Supplyvoltage 2.7 12 V CC V Common-modeinputvoltage V +1.15 V –1.15 V ICM CC– CC+ T Operatingfree-airtemperature –40 125 °C A 7.4 Thermal Information THERMALMETRIC(1) TL971 TL972 TL974 D(2) DBV(2) D(2) DGK(3) DRG(3) P(2) PW(2) D(2) N(2) PW(2) UNIT 8PINS 5PINS 8PINS 14PINS Package thermal R impedance, 97 206 97 172 44 85 149 86 80 113 °C/W θJA junctionto freeair (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport(SPRA953). (2) PackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (3) PackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. 4 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 7.5 Electrical Characteristics V =2.5V,V =–2.5V,full-rangeT =–40°Cto125°C(unlessotherwisenoted) CC+ CC– A PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A 25°C 1 4 V Inputoffsetvoltage mV IO Fullrange 6 αV Inputoffsetvoltagedrift V =0V,V =0V 25°C 5 μV/°C IO ICM O I Inputoffsetcurrent V =0V,V =0V 25°C 10 150 nA IO ICM O 25°C 200 750 I Inputbiascurrent V =0V,V =0V nA IB ICM O Fullrange 1000 V Common-modeinputvoltage 25°C –1.35 1.35 V ICM CMRR Common-moderejectionratio V =±1.35V 25°C 60 85 dB ICM SVR Supply-voltagerejectionratio V =±2Vto±3V 25°C 60 70 dB CC A Large-signalvoltagegain R =2kΩ 25°C 70 80 dB VD L V High-leveloutputvoltage R =2kΩ 25°C 2 2.4 V OH L V Low-leveloutputvoltage R =2kΩ 25°C –2.4 –2 V OL L 25°C 1.2 1.4 I Outputsourcecurrent mA source V =±2.5V Fullrange 1 OUT 25°C 50 80 I Outputsinkcurrent mA sink V =±2.5V Fullrange 25 OUT 25°C 2 2.8 I Supplycurrent(peramplifier) Unitygain,Noload mA CC Fullrange 3.2 GBWP Gainbandwidthproduct f=100kHz,R =2kΩ,C =100pF 25°C 8.5 12 MHz L L 25°C 2.8 5 SR Slewrate A =1,V =±1V V/μs V IN Fullrange 2.8 Φm Phasemarginatunitygain R =2kΩ,C =100pF 25°C 60 ° L L Gm Gainmargin R =2kΩ,C =100pF 25°C 10 dB L L V Equivalentinputnoisevoltage f=100kHz 25°C 4 nV/√Hz n THD Totalharmonicdistortion f=1kHz,A =–1,R =10kΩ 25°C 0.003 % v L 7.6 Typical Characteristics 60 200 60 200 50 fΦOMM==86.43.M7°Hz 160 50 Φ˜fOM==1674.3.4M°Hz 160 40 120 40 120 30 80 30 80 B 20 40 ° B 20 40 ° d – d – Gain– 100 -040 Phase Gain– 100 -040 Phase -10 -80 -10 -80 --3200 VRCCLLC===11200.07kkΩ©pVF --116200 --3200 VRCCLLC===115000VkkΩ©pF --116200 -40 -200 -40 -200 11.Ek+03 11.0Ek+04 11.E00+k05 1.E1+M06 1.E1+00M7 1.E1+000M8 1.E1+k03 11.E0+k04 11.E0+00k5 1.1EM+06 1.1E0+M07 11.E00+M08 f–Frequency–Hz f–Frequency–Hz Figure1.GainAndPhasevsFrequency Figure2.GainAndPhasevsFrequency Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Typical Characteristics (continued) 1 1 VCC=5V VCC=2.7V VIN=1Vrms f=1kHz Gain=-1V/V Gain=-1V/V 0.1 % 0.1 D–% 0.01 Noise– RL=2kkΩ RL=10kkΩ TH D+ RL=2kkΩ◊ TH 0.01 0.001 RL=10kkΩ◊ 0.0001 0.001 1.E1+001 11.E0+002 1.E1+k03 1.1E0+k04 1.E10+00k5 0 0.25 0.5 0.75 1 1.25 1.5 Frequency–Hz OutputVoltage–Vrms Figure3.TotalHarmonicDistortionvsFrequency Figure4.TotalHarmonicDistortion+NoisevsOutput Voltage 1 100 VCC=5V f=1kHz Gain=-1V/V Hz) 0.1 qrt(Hz √s % V/V/ nn – – Noise 0.01 Noise 10 THD+ RL=2kkˆΩ oltage 0.001 utV VCC=10V RL=10kkΩˆ Inp RS=100Ω© AV=40dB 1 0.0001 1.E1+001 1.E10+002 1.E1+k03 1.E1+00k4 1.1E0+00k5 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 f–Frequency–Hz OutputVoltage–Vrms Figure6.InputVoltageNoisevsFrequency Figure5.TotalHarmonicDistortion+NoisevsOutput Voltage 20 32 CL=250pF 28 CL=130pF Hz 16 MHz 24 M ct– uct– 20 CL=30pF du 12 od Pro hPr 16 width 8 dwidt 12 d n n a Ba nB 8 ain 4 Gai G 4 0 0 2 4 6 8 10 12 14 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 SupplyVoltage–V OutputCurrent–mA Figure8.GainBandwidthProductvsSupplyVoltage Figure7.GainBandwidthProductvsOutputCurrent 6 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 Typical Characteristics (continued) 100 100 90 90 CL=30pF 80 80 PhaseMargin–° 45670000 PhaseMargin–° 3456700000 CCLL==123500ppFF 30 20 20 10 10 0 0 2 4 6 8 10 12 14 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 SupplyVoltage–V OutputCurrent–mA Figure10.PhaseMarginvsSupplyVoltage Figure9.PhaseMarginvsOutputCurrent 20 18 CL=30pF 16 CL=130pF B 14 CL=250pF d – 12 Margin 10 V/div ain 8 0.25 G 6 4 2 0 2 4 6 8 10 12 14 SupplyVoltage–V 1µs/div Figure11.GainMarginvsSupplyVoltage Figure12.InputResponse 100 10 VIN-=-0.2V 90 V VIN+=0V – 80 e ag 1 70 olt V B 60 ply VCC=2.7V VCC=5V PSRR–d 4500 getoSup 0.1 a 30 Volt 0.01 ut 20 p ut O 10 0.001 0 1.0E.0-012 1.E0.-101 1.E1+00 1.E1+001 1.E1+k03 1.1E0+k04 11.E0+00k5 1.E1M+06 OutputCurrent–mA Frequency–Hz Figure14.OutputVoltagevsOutputCurrent Figure13.Power-SupplyRippleRejectionvsFrequency Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Typical Characteristics (continued) 100 12 11 10 Fall ℵΩ 10 9 ance– V/µs 78 Rise mped 1 ate– 6 utI VCC=2.7V wR 5 p e ut Sl 4 O 0.1 3 2 VCC=5V 1 0.01 1.E1+0002 1.E1k+03 1.1E0+k04 11.E0+00k5 1.E1M+06 0 2 4 6 8 10 12 14 16 Frequency–Hz SupplyVoltage–V Figure15.OutputImpedancevsFrequency Figure16.SlewRatevsSupplyVoltage 8 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 8 Detailed Description 8.1 Overview The TL97x family of operational amplifiers operates at voltages as low as ±1.35 V and features output rail-to-rail signal swing. The TL97x boast characteristics that make them particularly well suited for portable and battery- supplied equipment. Very low noise and low distortion characteristics make them ideal for audio preamplification. TheTL97xfamilycomesinsingle,dual,andquadoperationalamplifierpackagesofvaryingsizes. The TL971 is housed in the space-saving 5-pin SOT-23 package, which simplifies board design because of the abilitytobeplacedanywhere(outsidedimensionsare2.8mm× 2.9mm). 8.2 Functional Block Diagram VCC+ 1.4 mA IN± IN+ OUT VCC± 8.3 Feature Description 8.3.1 SlewRate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input.TheTL97xdeviceshavea5V/μsslewrate. 8.3.2 Unity-GainBandwidth The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without greatlydistortingthesignal.TheTL97xdeviceshavea12-MHzunity-gainbandwidth. Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Feature Description (continued) 8.3.3 LowTotalHarmonicDistortion Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The TL97x devices have a very low THD of 0.003% meaning that they will add little harmonic distortion when used in audio signalapplications. 8.3.4 OperatingVoltage The TL97x devices are fully specified and ensured for operation from 2.7 V to 12 V. In addition, many specificationsapplyfrom –40°Cto125°C. 8.4 Device Functional Modes The TL97x devices are powered on when the supply is connected. Each of these devices can be operated as a singlesupplyoperationalamplifierordualsupplyamplifierdependingontheapplication. 10 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Typical Application The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current asnecessarytotheoutputload. 12 V V OUT + V IN Figure17. Voltagefollowerschematic 9.1.1 DesignRequirements • InputatpositiveTerminal • Outputrangeof0Vto12V • Inputrangeof0Vto12V • Short-circuitfeedbacktonegativeinputforunitygain 9.1.2 DetailedDesignProcedure 9.1.2.1 OutputVoltageSwing The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply rails.Forthisamplifier,theoutputvoltagemustbewithin ±12V. 9.1.2.2 SupplyandInputVoltage For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 12 V, the supply voltage must be 15 V. Using a negative voltage on the lower rail rather than ground, allows the amplifiertomaintainlinearityforthefullrangeofinputs. Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Typical Application (continued) 9.1.3 ApplicationCurvesforOutputCharacteristics 12 1 10 0 ±1 8 OUT (V) 6 O (mA) ±±32 V II 4 ±4 2 ±5 0 ±6 0 2 4 6 8 10 12 0 2 4 6 8 10 12 VIN (V) VIN (V) C001 C002 Figure18.OutputVoltagevsInputVoltage Figure19.CurrentDrawnbyInputofVoltageFollower(I ) IO vsInputVoltage 12 10 8 A) m C ( 6 C I 4 2 0 0 2 4 6 8 10 12 VIN (V) C003 Figure20.CurrentDawnfromSupply(I ) CC vsInputVoltage 12 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 10 Power Supply Recommendations TheTL97xdevicesarespecifiedforoperationfrom2.7to12V;manyspecificationsapplyfrom-40 °Cto125°C. CAUTION Supply voltages larger than 15 V can permanently damage the device (see the AbsoluteMaximumRatings). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. 11 Layout 11.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodPCBlayoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to CircuitBoardLayoutTechniques,SLOA089. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposedtoinparallelwiththenoisytrace. • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting inputminimizesparasiticcapacitance,asshowninLayoutExample. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakagecurrentsfromnearbytracesthatareatdifferentpotentials. 11.2 Layout Example RIN VIN + VOUT RG RF Figure21. OperationalAmplifierSchematicforNoninvertingConfiguration Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 SLOS467H–OCTOBER2006–REVISEDJANUARY2015 www.ti.com Layout Example (continued) Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines RF as possible NC NC VS+ Use low-ESR, ceramic RG bypass capacitor GND IN1í VCC+ VIN IN1+ OUT RIN VCCí NC GND Only needed for dual-supply operation GND VS- (or GND for single supply) VOUT Ground (GND) plane on another layer Figure22. OperationalAmplifierBoardLayoutforNoninvertingConfiguration 14 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL971 TL972 TL974

TL971,TL972,TL974 www.ti.com SLOS467H–OCTOBER2006–REVISEDJANUARY2015 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY TL971 Clickhere Clickhere Clickhere Clickhere Clickhere TL972 Clickhere Clickhere Clickhere Clickhere Clickhere TL974 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TL971 TL972 TL974

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL971ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 & no Sb/Br) TL971IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 & no Sb/Br) TL971IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 & no Sb/Br) TL972ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 & no Sb/Br) TL972IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TSA & no Sb/Br) TL972IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 & no Sb/Br) TL972IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 & no Sb/Br) TL972IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TL972IP & no Sb/Br) TL972IPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TL972IP & no Sb/Br) TL972IPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 & no Sb/Br) TL972IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 & no Sb/Br) TL974ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL974I & no Sb/Br) TL974IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL974I & no Sb/Br) TL974IN ACTIVE PDIP N 14 25 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 TL974IN (RoHS) TL974INE4 ACTIVE PDIP N 14 25 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 TL974IN (RoHS) TL974IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z974 & no Sb/Br) TL974IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 Z974 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL971, TL972, TL974 : •Automotive: TL971-Q1, TL972-Q1, TL974-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TL971IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL972IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TL972IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL972IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL974IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL974IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TL971IDR SOIC D 8 2500 340.5 338.1 20.6 TL972IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TL972IDR SOIC D 8 2500 340.5 338.1 20.6 TL972IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL974IDR SOIC D 14 2500 333.2 345.9 28.6 TL974IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

None

None

None

None

None

None

None

None

PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated