(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 (cid:1) Controlled Baseline NS PACKAGE − One Assembly/Test Site, One Fabrication (TOP VIEW) Site (cid:1) Extended Temperature Performance of CA2 1 16 NC −55°C to 125°C VCC − 2 15 CB2 (cid:1) CA2′ 3 14 CB2′ Enhanced Diminishing Manufacturing A1 4 13 GND Sources (DMS) Support Y 5 12 B1 (cid:1) Enhanced Product-Change Notification Y 6 11 Z (cid:1) Qualification Pedigree† A2 7 10 Z (cid:1) Excellent Dynamic Range VCC + 8 9 B2 (cid:1) Wide Bandwidth (cid:1) Built-In Temperature Compensation NC — No internal connection (cid:1) Log Linearity (30-dB Sections)...1 dB Typ (cid:1) Wide Input Voltage Range †Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION This amplifier circuit contains four 30-dB logarithmic stages. Gain in each stage is such that the output of each stage is proportional to the logarithm of the input voltage over the 30-dB input voltage range. Each half of the circuit contains two of these 30-dB stages summed together in one differential output that is proportional to the sum of the logarithms of the input voltages of the two stages. The four stages may be interconnected to obtain a theoretical input voltage range of 120-dB. In practice, this permits the input voltage range typically to be greater than 80-dB with log linearity of ±0.5-dB (see application data). Bandwidth is from dc to 40 MHz. This circuit is useful in data compression and analog compensation. This logarithmic amplifier is used in log IF circuitry as well as video and log amplifiers. The TL441M is characterized for operation over the full military temperature range of −55°C to 125°C. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING −55°C to 125°C SOP (NS) Tape and reel TL441MNSREP TL441MEP †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:7)(cid:11)(cid:8)(cid:17)(cid:18)(cid:15)(cid:1)(cid:12)(cid:8)(cid:19) (cid:17)(cid:10)(cid:1)(cid:10) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:20)(cid:23)(cid:21) (cid:20)(cid:28) (cid:29)(cid:30)(cid:24)(cid:24)(cid:31)(cid:21)(cid:27) (cid:26)(cid:28) (cid:23)(cid:22) !(cid:30)"#(cid:20)(cid:29)(cid:26)(cid:27)(cid:20)(cid:23)(cid:21) $(cid:26)(cid:27)(cid:31)% Copyright  2004, Texas Instruments Incorporated (cid:7)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:28) (cid:29)(cid:23)(cid:21)(cid:22)(cid:23)(cid:24)(cid:25) (cid:27)(cid:23) (cid:28)!(cid:31)(cid:29)(cid:20)(cid:22)(cid:20)(cid:29)(cid:26)(cid:27)(cid:20)(cid:23)(cid:21)(cid:28) !(cid:31)(cid:24) (cid:27)&(cid:31) (cid:27)(cid:31)(cid:24)(cid:25)(cid:28) (cid:23)(cid:22) (cid:1)(cid:31)’(cid:26)(cid:28) (cid:12)(cid:21)(cid:28)(cid:27)(cid:24)(cid:30)(cid:25)(cid:31)(cid:21)(cid:27)(cid:28) (cid:28)(cid:27)(cid:26)(cid:21)$(cid:26)(cid:24)$ ((cid:26)(cid:24)(cid:24)(cid:26)(cid:21)(cid:27))% (cid:7)(cid:24)(cid:23)$(cid:30)(cid:29)(cid:27)(cid:20)(cid:23)(cid:21) !(cid:24)(cid:23)(cid:29)(cid:31)(cid:28)(cid:28)(cid:20)(cid:21)* $(cid:23)(cid:31)(cid:28) (cid:21)(cid:23)(cid:27) (cid:21)(cid:31)(cid:29)(cid:31)(cid:28)(cid:28)(cid:26)(cid:24)(cid:20)#) (cid:20)(cid:21)(cid:29)#(cid:30)$(cid:31) (cid:27)(cid:31)(cid:28)(cid:27)(cid:20)(cid:21)* (cid:23)(cid:22) (cid:26)## !(cid:26)(cid:24)(cid:26)(cid:25)(cid:31)(cid:27)(cid:31)(cid:24)(cid:28)% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 FUNCTIONAL LOGIC DIAGRAM (one half) Σ A1 Log (B1) −15 dB Log Y (Z) CA2 (CB2) A2 Log Y (Z) (B2) −15 dB Log CA2′ (CB2′) Y ∝ log A1 + log A2; Z ∝ log B1 + log B2 where: A1, A2, B1, and B2 are in dBV, 0 dBV = 1 V. CA2, CA2′, CB2, and CB2′ are detector compensation inputs. SCHEMATIC 8 VCC + 6 10 Y Z 5 11 Y Z 7 9 A2 B2 4 12 A1 B1 13 GND 3 14 CA2′ CB2′ 1 15 CA2 CB2 2 VCC− 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted)† TL441−EP VCC+ 8 V SSuuppppllyy vvoollttaaggeess ((sseeee NNoottee 11)) VCC− −8 V Input voltage (see Note 1) 6 V Output sink current (any one output) 30 mA θJA Package thermal impedance (see Notes 2 and 3) 83°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C Tstg Storage temperature range (see Note 4) −65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages, except differential out voltages, are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Peak-to-peak input voltage for each 30-dB stage 0.01 1 V Operating free-air temperature, TA −55 125 °C ELECTRICAL CHARACTERISTICS, VCC± = ±6 V, TA = 25(cid:1)C TEST PARAMETER MIN TYP MAX UNIT FIGURE Differential output offset voltage 1 ±25 ±70 mV Quiescent output voltage 2 5.45 5.6 5.85 V DC scale factor (differential output), each 3-dB stage, −35 dBV to −5 dBV 3 7 8 11 mV/dB AC scale factor (differential output) 8 mV/dB DC error at −20 dBV (midpoint of −35 dBV to −5 dBV range) 3 1 2.6 dB Input impedance 500 Ω Output impedance 200 Ω Rise time, 10% to 90% points, CL = 24 pF 4 20 35 ns Supply current from VCC+ 2 14.5 18.5 23 mA Supply current from VCC− 2 −6 −8.5 −10.5 mA Power dissipation 2 123 162 201 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERATURE RANGE, VCC± = ±6 V (unless otherwise noted) PARAMETER TEST FIGURE MIN MAX UNIT Differential output offset voltage 1 ±125 mV Quiescent output voltage 2 5.3 5.85 V DC scale factor (differential output) each 30-dB stage, −35 dBV to −5 dBV 3 6 11 mV/dB TA = −55°C 4 DDCC eerrrroorr aatt −−2200 ddBBVV ((mmiiddppooiinntt ooff −−3355 ddBBVV ttoo −−55 ddBBVV rraannggee)) 33 ddBB TA = 125°C 3 Supply current from VCC+ 2 10 31 mA Supply current from VCC− 2 −4.5 −15 mA Power dissipation 2 87 276 mW PARAMETER MEASUREMENT INFORMATION VCC+ VCC− ICC + VCC+ VCC− ICC− CA2 CA2′ VCC+ VCC− CA2 CA2′ VCC +VCC − A1 Y A1 Y A2 Y A2 Y DVM B1 Z B1 Z B2 Z B2 Z CB2 CB2′ GND CB2 CB2′ GND VO • • PD = VCC+ ICC+ + VCC− ICC− Figure 1 Figure 2 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 VCC+ VCC− CA2 CA2′ VCC+ VCC− A1 Y A2 Y DVM B1 Z (cid:2) (cid:3) B2 Z V –V mV out(560mV) out(18mV) CB2 CB2′ GND ScaleFactor(cid:1) 18 mV DC 30dBV 100 mV Power (cid:2) (cid:3) 560 mV Supply –0.5V –0.5V Vout(100mV) out(560mV) out(18mV) Error(cid:1) ScaleFactor Figure 3 VCC+ VCC− CI 1000 pF CA2 CA2′ VCC+ VCC− Atten A1 Y A2 Y Tektronix 100 mV B1 Z Sampling Scope 0 mV B2 Z With Digital Pulse CB2 CB2′ GND Readout or Equivalent Generator 50 Ω CL CL NOTES: A. The input pulse has the following characteristics: tw = 200 ns, tr ≤ 2 ns, tf ≤ 2 ns, PRR ≤ 10 MHz. B. Capacitor CI consists of three capacitors in parallel: 1 µF, 0.1 µF, and 0.01 µF. C. CL includes probe and jig capacitance. Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT OFFSET VOLTAGE QUIESCENT OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 60 8 V m 7 age − 50 e − V 6 et Volt 40 Voltag 5 ut Offs 30 Output 4 utp nt 3 ntial O 20 uiesce 2 e Q Differ 10 VSeCeC F±i g=u ±re6 1V 1 VSeCeC F±i g=u ±re6 2V 0 0 − 75 − 50 − 25 0 25 50 75 100 125 − 75 − 50 − 25 0 25 50 75 100 125 TA −Free-Air Temperature −°C TA −Free-Air Temperature −°C Figure 5 Figure 6 DC SCALE FACTOR DC ERROR vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE V 12 V 2.0 B B mV/d 10 e − d 1.8 − ng 1.6 put) V Ra 1.4 ut 8 B al O 30-d 1.2 nti 6 of 1.0 r (Differe 4 Midpoint 00..86 cto at cale Fa 2 VSeCeC F±i g=u ±re6 3V C Error 00..42 VSeCeC F±i g=u ±re6 3V S D C 0 0 D − 75 − 50 − 25 0 25 50 75 100 125 − 75 − 50 − 25 0 25 50 75 100 125 TA −Free-Air Temperature −°C TA −Free-Air Temperature −°C Figure 7 Figure 8 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 OUTPUT RISE TIME vs LOAD CAPACITANCE 25 ns 20 − e m Ti e 15 s Ri ut p Out 10 VCC± = ±6 V − TA = 25°C t r See Figure 4, outputs 5 loaded symmetrically 0 0 5 10 15 20 25 30 CL − Load Capacitance − pF Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 APPLICATION INFORMATION Although designed for high-performance applications such as infrared detection, this device has a wide range of applications in data compression and analog computation. Basic Logarithmic Function Functional Block Diagram The basic logarithmic response is derived from the exponential current-voltage relationship of INPUT Log Log INPUT A1 B1 collector current and base-emitter voltage. This relationship is given in the equation: −15 dB −15 dB m • V = In [(I + I )/I ] Log Log BE C CES CES where: CA2 CB2 IC = collector current INPUAT2 Log Log IBN2PUT ICES = collector current at VBE = 0 −15 dB −15 dB m = q/kT (in V − 1) Log Log V = base-emitter voltage BE CA2’ Σ Σ CB2’ The differential input amplifier allows dual-polarity Y Y Z Z inputs, is self-compensating for temperature variations, and is relatively insensitive to Outputs common-mode noise. Figure 10 Logarithmic Sections As can be seen from the schematic, there are eight differential pairs. Each pair is a 15-dB log subsection, and each input feeds two pairs, for a range of 30-dB per stage. Four compensation points are available to allow slight variations in the gain (slope) of the two individual 15-dB stages of input A2 and B2. By slightly changing the voltage on any of the compensation pins from their quiescent values, the gain of that particular 15-dB stage can be adjusted to match the other 15-dB stage in the pair. The compensation pins also can be used to match the transfer characteristics of input A2 to A1 or B2 to B1. The log stages in each half of the circuit are summed by directly connecting their collectors together and summing through a common-base output stage. The two sets of output collectors are used to give two log outputs, Y and Y (or Z and Z), which are equal in amplitude, but opposite in polarity. This increases the versatility of the device. By proper choice of external connections, linear amplification, and linear attenuation many different applications requiring logarithmic signal processing are possible. Input Levels The recommended input voltage range of any one stage is given as 0.01 V to 1 V. Input levels in excess of 1 V may result in a distorted output. When several log sections are summed together, the distorted area of one section overlaps with the next section and the resulting distortion is insignificant. However, there is a limit to the amount of overdrive that can be applied. As the input drive reaches ±3.5 V, saturation occurs, clamping the collector-summing line and severely distorting the output. Therefore, the signal to any input must be limited to approximately ±3 V to ensure a clean output. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 Output Levels Differential-output-voltage levels are low, generally less than 0.6 V. As demonstrated in Figure 11, the output swing and the slope of the output response can be adjusted by varying the gain by means of the slope control. The coordinate origin also can be adjusted by positioning the offset of the output buffer. Circuits Figure 11 through Figure 18 show typical circuits using this logarithmic amplifier. Operational amplifiers not otherwise designated are TLC271. For operation at higher frequencies, the TL592 is recommended instead of the TLC271. TYPICAL TRANSFER CHARACTERISTICS 1.4 1.2 Adjusted for Increased 1.0 Slope and Offset V − e 0.8 g a olt 0.6 V ut p ut 0.4 O 0.2 Adjusted For Minimum 0 Slope With Zero Offset − 0.2 10 − 4 10 −3 10 −2 10 −1 1 101 Input Voltage − V A1 Y Origin + − + 1/2 TL441 − Input A2 GND Y Output Slope Figure 11. Output Slope and Origin Adjustment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 TRANSFER CHARACTERISTICS of TWO TYPICAL INPUT STAGES 0.4 0.3 V − e g a olt 0.2 V ut p ut O 0.1 0 0.001 0.01 0.1 1 10 Input Voltage − V 2 kΩ, 1% 2 kΩ, 1% B1 Z 1/2 20 kΩ + TL441 − 2 kΩ, 1% Output Input B2 GND Z 2 kΩ, 1% Figure 12. Utilization of Separate Stages 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 TRANSFER CHARACTERISTICS WITH BOTH SIDES PARALLELED 0.4 0.3 V − e g a olt 0.2 V ut p ut O 0.1 0 0.001 0.01 0.1 1 10 Input Voltage − V 2 kΩ, 1% 2 kΩ, 1% A1 Y A2 Y 20 kΩ + TL441 − B1 Z Input 2 kΩ, 1% Output B2 Z GND 2 kΩ, 1% Figure 13. Utilization of Paralleled Inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 TRANSFER CHARACTERISTICS 0.8 0.7 0.6 V − e 0.5 g a olt 0.4 V ut p ut 0.3 O 0.2 0.1 0 10 − 4 10 −3 10 −2 10 −1 1 101 Input Voltage − V 2 kΩ 2 kΩ A1 Y 1 kΩ VCC + = 4 V 15 kΩ + A2 Y − Origin + TL441 910 Ω VCC − = − 4 V 20 kΩ − B1 Z 5 kΩ VCC + = 4 V Input 1 kΩ 2 kΩ + B2 Z − Slope Output 100 Ω 910 Ω VCC − = − 4 V 5 kΩ 5 kΩ 100 Ω NOTES: A. nputs are limited by reducing the supply voltages for the input amplifiers to ±4 V. B. The gains of the input amplifiers are adjusted to achieve smooth transitions. Figure 14. Logarithmic Amplifier With Input Voltage Range Greater Than 80 dB 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 R R R R A1 Y + TL441 Input A2 R − A Y + OUTPUT W see + − A1 1/2 Y (see Note B) Note A + TL441 − A2 Y − Z R B1 + Input B2 Z − B R R R R NOTES: A. Connections shown are for multiplication. For division, Z and Z connections are reversed. B. Output W may need to be amplified to give actual product or quotient of A and B. C. R designates resistors of equal value, typically 2 kΩ to 10 kΩ. Multiplication: W = A • B ⇒ log W = log A + log B, or W = a(logaA + logaB) Division: W = A/B ⇒ log W = log A − log B, or W = a(logaA + logaB) Figure 15. Multiplication or Division R nR R R A1 Y 1/2 − Input A TL441 R + − B1 Z Output + A2 Y + + TL14/241 W − B2 Z − R nR R NOTE: R designates resistors of equal value, typically 2 kΩ to 10 kΩ. The power to which the input variable is raised is fixed by setting nR. Output W may need to be amplified to give the correct value. Exponential: W = An ⇒ log W = n log A, or W = a(n loga A) Figure 16. Raising a Variable to a Fixed Power POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:1)(cid:13)(cid:14)(cid:12)(cid:15) (cid:10)(cid:14)(cid:7)(cid:2)(cid:12)(cid:16)(cid:12)(cid:6)(cid:11) SGLS268 − OCTOBER 2004 2 kΩ 2 kΩ Input Slope A Origin − Output + A1 1/2 Y W 20 kΩ + TL441 A2 Y − 2 kΩ 2 kΩ NOTE: Adjust the slope to correspond to the base “a”. Exponential to any base: W = a. Figure 17. Raising a Fixed Number to a Variable Power 2.2 kΩ TL592 0.2 µF A1 Y Input TL592 20 kΩ ++ Output 1 + A2 −− 0.2 µF 1 − 0.2 µF Y Open 2.2 kΩ 50 Ω 50 Ω 1 kΩ 1 kΩ TL441 Gain Adj. Gain Adj. = 400 Ω 2.2 kΩ TL592 0.2 µF For 30 dB Z B1 20 kΩ ++ Output −− 0.2 µF 2 Input TL592 2 + B2 Z − 2.2 kΩ Open 0.2 µF CA2 CA2’CB2CB2’ 1 kΩ 1 kΩ 50 Ω 50 Ω 1kΩ0 1kΩ0 Gain Adj. Gain Adj. = 400 Ω For 30 dB VCC − Figure 18. Dual-Channel RF Logarithmic Amplifier With 50-dB Input Range Per Channel at 10 MHz 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL441MNSREP ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 TL441MEP & no Sb/Br) V62/05603-01XE ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 TL441MEP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL441-EP : •Catalog: TL441 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TL441MNSREP SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TL441MNSREP SO NS 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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