TL431A, B Series, NCV431A, B Series, SCV431A Programmable Precision References www.onsemi.com The TL431A, B integrated circuits are three−terminal programmable shunt regulator diodes. These monolithic IC voltage references operate as a low temperature coefficient zener which is programmable from V to 36 V with two external resistors. These ref devices exhibit a wide operating current range of 1.0 mA to 100 mA with a typical dynamic impedance of 0.22 (cid:2). The characteristics of Pin 1. Reference these references make them excellent replacements for zener diodes in 2. Anode many applications such as digital voltmeters, power supplies, and op 12 3. Cathode 1 2 3 3 amp circuitry. The 2.5 V reference makes it convenient to obtain a STRAIGHT LEAD BENT LEAD stable reference from 5.0 V logic supplies, and since the TL431A, B BULK PACK TAPE & REEL operates as a shunt regulator, it can be used as either a positive or AMMO PACK negative voltage reference. TO−92 TO−92 LP SUFFIX LPRA, LPRE, LPRM, Features CASE 29−11 LPRP SUFFIX • Programmable Output Voltage to 36 V CASE 29−11 • Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B) • Low Dynamic Output Impedance, 0.22 (cid:2) Typical PDIP−8 • P SUFFIX Sink Current Capability of 1.0 mA to 100 mA CASE 626 • Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical 8 • 1 Micro8(cid:2) Temperature Compensated for Operation over Full Rated Operating DM SUFFIX Temperature Range CASE 846A • Low Output Noise Voltage • Cathode 1 8 Reference NCV/SCV Prefixes for Automotive and Other Applications N/C 2 7 N/C Requiring Unique Site and Control Change Requirements; N/C 3 6 Anode AEC−Q100 Qualified and PPAP Capable N/C 4 5 N/C • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS (Top View) Compliant 8 Cathode 1 8 Reference 1 2 7 Anode Anode SOIC−8 3 6 D SUFFIX N/C 4 5 N/C CASE 751 (Top View) This is an internally modified SOIC−8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC−8 package. ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 14 of this data sheet. © Semiconductor Components Industries, LLC, 1995 1 Publication Order Number: January, 2019 − Rev. 40 TL431/D

TL431A, B Series, NCV431A, B Series, SCV431A Cathode (K) Cathode (K) Reference (R) 800 800 Anode Reference (A) (R) 20 pF Figure 1. Symbol Reference Cathode 3.28 k 150 (R) + (K) 4.0 k 20 pF 10 k - 2.4 k 7.2 k 2.5 Vref 1.0 k Anode (A) 800 Figure 2. Representative Block Diagram This device contains 12 active transistors. Anode (A) Figure 3. Representative Schematic Diagram Component values are nominal MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.) Rating Symbol Value Unit Cathode to Anode Voltage VKA 37 V Cathode Current Range, Continuous IK −100 to +150 mA Reference Input Current Range, Continuous Iref −0.05 to +10 mA Operating Junction Temperature TJ 150 °C Operating Ambient Temperature Range TA °C TL431I, TL431AI, TL431BI −40 to +85 TL431C, TL431AC, TL431BC 0 to +70 NCV431AI, NCV431B, TL431BV, SCV431AI −40 to +125 Storage Temperature Range Tstg −65 to +150 °C Total Power Dissipation @ TA = 25°C PD W Derate above 25°C Ambient Temperature D, LP Suffix Plastic Package 0.70 P Suffix Plastic Package 1.10 DM Suffix Plastic Package 0.52 Total Power Dissipation @ TC = 25°C PD W Derate above 25°C Case Temperature D, LP Suffix Plastic Package 1.5 P Suffix Plastic Package 3.0 ESD Rating (Note 1) V Human Body Model per JEDEC JESD22−A114F HBM >2000 Machine Model per JEDEC JESD22−A115C MM >200 Charged Device Model per JEDEC JESD22−C101E CDM >500 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latch−up protection and exceeds ±100 mA per JEDEC standard JESD78. RECOMMENDED OPERATING CONDITIONS Condition Symbol Min Max Unit Cathode to Anode Voltage VKA Vref 36 V Cathode Current IK 1.0 100 mA Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2

TL431A, B Series, NCV431A, B Series, SCV431A THERMAL CHARACTERISTICS D, LP Suffix P Suffix DM Suffix Characteristic Symbol Package Package Package Unit Thermal Resistance, Junction−to−Ambient R(cid:3)JA 178 114 240 °C/W Thermal Resistance, Junction−to−Case R(cid:3)JC 83 41 − °C/W ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431I TL431C Characteristic Symbol Min Typ Max Min Typ Max Unit Reference Input Voltage (Figure 1) Vref V VKA = Vref, IK = 10 mA TA = 25°C 2.44 2.495 2.55 2.44 2.495 2.55 TA = Tlow to Thigh (Note 2) 2.41 − 2.58 2.423 − 2.567 Reference Input Voltage Deviation Over (cid:4)Vref − 7.0 30 − 3.0 17 mV Temperature Range (Figure 1, Notes 3, 4) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to Change (cid:4)V mV/V ref in Cathode to Anode Voltage (cid:4)V IK = 10 mA (Figure 2), KA (cid:4)VKA = 10 V to Vref − −1.4 −2.7 − −1.4 −2.7 (cid:4)VKA = 36 V to 10 V − −1.0 −2.0 − −1.0 −2.0 Reference Input Current (Figure 2) Iref (cid:5)A IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C − 1.8 4.0 − 1.8 4.0 TA = Tlow to Thigh (Note 2) − − 6.5 − − 5.2 Reference Input Current Deviation Over (cid:4)Iref − 0.8 2.5 − 0.4 1.2 (cid:5)A Temperature Range (Figure 2, Note 3) IK = 10 mA, R1 = 10 k, R2 = ∞ Minimum Cathode Current For Regulation Imin − 0.5 1.0 − 0.5 1.0 mA VKA = Vref (Figure 1) Off−State Cathode Current (Figure 3) Ioff − 20 1000 − 20 1000 nA VKA = 36 V, Vref = 0 V Dynamic Impedance (Figure 1, Note 5) |ZKA| − 0.22 0.5 − 0.22 0.5 (cid:2) VKA = Vref, (cid:4)IK = 1.0 mA to 100 mA, f ≤ 1.0 kHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM; = 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM 3. Guaranteed by design. 4. The deviation parameter (cid:4)Vref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max DVref = Vref max -Vref min (cid:4)TA = T2 - T1 Vref min (cid:3) (cid:4) T1 Ambient Temperature T2 (cid:4)V The average temperature coefficient of the reference input voltage, (cid:6)Vref is defined as: Vref p(cid:2)pCm(cid:2) Vref @r(cid:4)e2fT5(cid:2)C X106 (cid:2) (cid:4)T(cid:4)(VVrefx@10265(cid:2)C) A A ref (cid:6)Vref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example:(cid:4)V (cid:2)8.0mV and slopeispositive, ref Vref@25(cid:2)C(cid:2)2.495V,(cid:4)TA(cid:2)70(cid:2)C (cid:6)Vref(cid:2)07.000(82.x49150)6(cid:2)45.8ppm(cid:5)(cid:2)C (cid:4)V 5. The dynamic impedance ZKA is defined as: |ZKA|(cid:2) (cid:4)IKA. When the device is programmed with two external resistors, R1 and R2, K (cid:3) (cid:4) (refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z (cid:6)| (cid:7)|Z | 1(cid:8)R1 KA KA R2 www.onsemi.com 3

TL431A, B Series, NCV431A, B Series, SCV431A ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431AI / TL431BC / TL431BI / NCV431AI/ TL431BV / SCV431AI TL431AC NCV431BV Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit Reference Input Voltage (Figure 1) Vref V VKA = Vref, IK = 10 mA TA = 25°C 2.47 2.495 2.52 2.47 2.495 2.52 2.485 2.495 2.505 TA = Tlow to Thigh (Note 6) 2.44 − 2.55 2.453 − 2.537 2.475 2.495 2.515 Reference Input Voltage Deviation Over (cid:4)Vref − 7.0 30 − 3.0 17 − 3.0 17 mV Temperature Range (Figure 1, Notes 7, 8) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to (cid:4)V mV/V ref Change in Cathode to Anode Voltage (cid:4)V IK = 10 mA (Figure 2), KA (cid:4)VKA = 10 V to Vref − −1.4 −2.7 − −1.4 −2.7 − −1.4 −2.7 (cid:4)VKA = 36 V to 10V − −1.0 −2.0 − −1.0 −2.0 − −1.0 −2.0 Reference Input Current (Figure 2) Iref (cid:5)A IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C − 1.8 4.0 − 1.8 4.0 − 1.1 2.0 TA = Tlow to Thigh (Note 6) − − 6.5 − − 5.2 − − 4.0 Reference Input Current Deviation Over (cid:4)Iref − 0.8 2.5 − 0.4 1.2 − 0.8 2.5 (cid:5)A Temperature Range (Figure 2, Note 7) IK = 10 mA, R1 = 10 k, R2 = ∞ Minimum Cathode Current For Regulation Imin − 0.5 1.0 − 0.5 1.0 − 0.5 1.0 mA VKA = Vref (Figure 1) Off−State Cathode Current (Figure 3) Ioff − 20 1000 − 20 1000 − 0.23 500 nA VKA = 36 V, Vref = 0 V Dynamic Impedance (Figure 1, Note 9) |ZKA| − 0.22 0.5 − 0.22 0.5 − 0.14 0.3 (cid:2) VKA = Vref, (cid:4)IK = 1.0 mA to 100 mA f ≤ 1.0 kHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM, TL431BIDM, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDR2G, SCV431AIDMR2G = 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM, SCV431AIDMR2G Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM = +125°C TL431BV, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G 7. Guaranteed by design. 8. The deviation parameter (cid:4)Vref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max (cid:4)Vref = Vref max -Vref min (cid:4)TA = T2 - T1 Vref min (cid:3) (cid:4) The average temperature coefficient of the reference input vTo1ltagAem,b (cid:6)ieVntr eTfe imsp deeraftiunreed asT:2 Vref p(cid:2)pCm(cid:2) Vre(cid:4)f @Vr(cid:4)e2fT5(cid:2)C X106 (cid:2) (cid:4)T(cid:4)(VVrefx@10265(cid:2)C) A A ref (cid:6)Vref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example:(cid:4)V (cid:2)8.0mV and slopeispositive, ref Vref@25(cid:2)C(cid:2)2.495V,(cid:4)TA(cid:2)70(cid:2)C (cid:6)Vref(cid:2)07.000(82.x49150)6(cid:2)45.8ppm(cid:5)(cid:2)C (cid:4)V 9. The dynamic impedance ZKA is defined as |ZKA|(cid:2) (cid:4)IKA When the device is programmed with two external resistors, R1 and R2, (refer K (cid:3) (cid:4) to Figure 2) the total dynamic impedance of the circuit is defined as: |Z (cid:6)| (cid:7)|Z | 1(cid:8)R1 KA KA R2 10.NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G Tlow = −40°C, Thigh = +125°C. NCV prefix is for automotive and other applications requiring unique site and control change requirements. www.onsemi.com 4

TL431A, B Series, NCV431A, B Series, SCV431A Input IK VKA Input IK VKA Input Ioff VKA R1 Iref Vref R2 V (cid:2)V (cid:2)(cid:3)(cid:2)1(cid:8)R1(cid:2)(cid:4)(cid:8)I (cid:2)(cid:3)(cid:2)R1 KA ref R2 ref Vref Figure 1. Test Circuit for VKA = Vref Figure 2. Test Circuit for VKA > Vref Figure 3. Test Circuit for Ioff 150 800 VKA = Vref VKA = Vref ODE CURRENT (mA) 150000 Input TA = 25°CIKVKA μODE CURRENT (A) 624000000 Input TA = 25°CIKVKA IMin I, CATHK -50 I, CATHK 0 -100 -200 -2.0 -1.0 0 1.0 2.0 3.0 -1.0 0 1.0 2.0 3.0 VKA, CATHODE VOLTAGE (V) VKA, CATHODE VOLTAGE (V) Figure 4. Cathode Current versus Figure 5. Cathode Current versus Cathode Voltage Cathode Voltage 2600 3.0 LTAGE (mV) 222555864000 InpuVtref IKVVIKKK A=A 1=0 V mreAf Vref Max = 2550 mV μRRENT (A) 2.5 O U 2.0 T V 2520 T C NPU 2500 Vref Typ = 2495 mV NPU 1.5 CE I 2480 CE I IK = 10 mA EN 2460 EN 1.0 Input VKA REFER 2440 Vref Min = 2440 mV REFER 0.5 10k Iref IK V, ref22442000 I, ref 0 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 6. Reference Input Voltage versus Figure 7. Reference Input Current versus Ambient Temperature Ambient Temperature www.onsemi.com 5

TL431A, B Series, NCV431A, B Series, SCV431A V) 0 A) 1.0 k m n LTAGE ( -8.0 ITKA = = 1 205 m°CA RRENT ( 100 O U V C UT DE 10 REFERENCE INP --1264 IRnRp21ut Vref IKVKA F-STATE CATHO 10..01 Input VVrKeAf == 03 6VIo VffVKA , ef OF ΔVr -32 I, off 0.01 0 10 20 30 40 -55 -25 0 25 50 75 100 125 VKA, CATHODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (5C) Figure 8. Change in Reference Input Figure 9. Off−State Cathode Current Voltage versus Cathode Voltage versus Ambient Temperature 100 0.320 ΩMPEDANCE () 10 15.00 k +- IGKONuDtput (cid:4)TA I=K =25 1°.C0 mA to 100 mA ΩMPEDANCE () 00..320800 V f(cid:4) ≤K A I11K 5=.. 000= (cid:2) V kk1rHe.-0fz mA to I1KO0u0t pmuAt C I C I 0.260 + GND MI MI A A YN 1.0 YN 0.240 D D |, A |, A K K 0.220 Z Z | | 0.1 0.200 1.0 k 10 k 100 k 1.0 M 10 M -55 -25 0 25 50 75 100 125 f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C) Figure 10. Dynamic Impedance Figure 11. Dynamic Impedance versus Frequency versus Ambient Temperature 60 80 E GAIN (dB) 5400 9.0 (cid:5)F 15(cid:2)k IK 230Output √Hz) 60 OLTAG 30 8.25(cid:2)k GND E (nV/ LOOP V 20 VOLTAG 40 VITKAK = A= 1 =20 5V m°reCAf , OPEN OL 100 ITKA = = 1 205 m°CA NOISE 20 Input IK Output V A -10 0 1.0 k 10 k 100 k 1.0 M 10 M 10 100 1.0 k 10 k 100 k f, FREQUENCY (MHz) f, FREQUENCY (Hz) Figure 12. Open−Loop Voltage Gain Figure 13. Spectral Noise Density versus Frequency www.onsemi.com 6

TL431A, B Series, NCV431A, B Series, SCV431A 3.0 TA = 25°C M Ionnpiutotr 114200 UnAsrteaable ProVgKraAm(Vm)ed C TA = 25°C 220 Output A Vref TAGE SWING (V) 21..00 Output f G=e P1nu0el0sra ektHorz 50 GND E CURRENT (mA) 1860000 CDB Sta511b.050le D Stable VOL 0 HOD 40 B B T 5.0 A 0 Input , CK 20 A A I 0 0 4.0 8.0 12 16 20 1.0 nF 10 nF 100 nF 1.0 (cid:5)F 10 (cid:5)F 100 (cid:5)F t, TIME ((cid:5)s) CL, LOAD CAPACITANCE Figure 14. Pulse Response Figure 15. Stability Boundary Conditions 150 150 IK IK 10 k V+ CL V+ CL Figure 16. Test Circuit For Curve A Figure 17. Test Circuit For Curves B, C, And D of Stability Boundary Conditions of Stability Boundary Conditions TYPICAL APPLICATIONS V+ Vout V+ Vout R1 R1 R2 R2 (cid:3) (cid:4) V (cid:2)(cid:2) 1(cid:8)R1 (cid:2)V (cid:3) (cid:4) out R2 ref V (cid:2)(cid:2) 1(cid:8)R1 (cid:2)V out R2 ref Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator www.onsemi.com 7

TL431A, B Series, NCV431A, B Series, SCV431A V+ Vout MC7805 R1 V+ In Out Vout Common R1 R2 R2 (cid:3) (cid:4) (cid:3) (cid:4) V (cid:2)(cid:2) 1(cid:8)R1 (cid:2)V V (cid:2)(cid:2) 1(cid:8)R1 (cid:2)V out R2 ref out R2 ref V (cid:2)V (cid:8)V V (cid:2)V (cid:8)5.0(cid:2)V in(min) out be out(min) ref V (cid:2)V out(min) ref Figure 20. Output Control for a Figure 21. Series Pass Regulator Three−Terminal Fixed Regulator V+ RCL Iout V+ Isink V I (cid:2) ref Sink R S V I (cid:2) ref out R CL RS Figure 22. Constant Current Source Figure 23. Constant Current Sink V+ Vout V+ Vout R1 R1 R2 R2 (cid:3) (cid:4) Vout(trip)(cid:2)(cid:2) 1(cid:8)RR12 (cid:2)Vref (cid:3) (cid:4) V (cid:2)(cid:2) 1(cid:8)R1 (cid:2)V out(trip) R2 ref Figure 24. TRIAC Crowbar Figure 25. SRC Crowbar www.onsemi.com 8

TL431A, B Series, NCV431A, B Series, SCV431A V+ Vout V+ l R1 R3 Vout Vin R2 R4 L.E.D. indicator is `on' when V+ is between the Vth = Vref Vin Vout upper and lower limits. < Vref V+ (cid:3) (cid:4) > Vref ≈2.0 V Lower(cid:2)Limit(cid:2)(cid:2) 1(cid:8)R1 (cid:2)V R2 ref (cid:3) (cid:4) Upper(cid:2)Limit(cid:2)(cid:2) 1(cid:8)R3 (cid:2)V R4 ref Figure 26. Voltage Monitor Figure 27. Single−Supply Comparator with Temperature−Compensated Threshold 25 V 38 V 1N5305 2.0 mA Tl = 330 to 8.0 (cid:2) 330 5.0 k 50 k 500 k 5.0 M 10 k TI + 1% 1% 1% 1% Calibrate 470 (cid:5)F 10 k(cid:2) 8.0 (cid:2) 360 k V 100 k(cid:2) 1.0 k(cid:2) V 1.0 VM(cid:2) - 25 V 1.0 (cid:5)F V Range LM11 Vout * Volume + *Thermalloy 0.05 (cid:5)F 47 k RX Rx(cid:2)Vout(cid:2)(cid:4)(cid:2)(cid:2)(cid:2)V(cid:2)Range-5.0 V ***THLPHe aMPts a6icn0kk2a 4og ne 56 k 10 k Tone25 k Figure 28. Linear Ohmmeter Figure 29. Simple 400 mW Phono Amplifier www.onsemi.com 9

TL431A, B Series, NCV431A, B Series, SCV431A 150 (cid:5)H @ 2.0 A Vin = 10 V to 20 V TIP115 Vout = 5.0 V Iout = 1.0 A 1.0 k 4.7 k 4.7 k 1N5823 MPSA20 0.01(cid:5)F 100 k + 2200 (cid:5)F + 4.7 k 470 (cid:5)F 0.1 (cid:5)F 2.2 k 10 51 k Figure 30. High Efficiency Step−Down Switching Converter Test Conditions Results Line Regulation Vin = 10 V to 20 V, Io = 1.0 A 53 mV (1.1%) Load Regulation Vin = 15 V, Io = 0 A to 1.0 A 25 mV (0.5%) Output Ripple Vin = 10 V, Io = 1.0 A 50 mVpp P.A.R.D. Output Ripple Vin = 20 V, Io = 1.0 A 100 mVpp P.A.R.D. Efficiency Vin = 15 V, Io = 1.0 A 82% www.onsemi.com 10

TL431A, B Series, NCV431A, B Series, SCV431A APPLICATIONS INFORMATION The TL431 is a programmable precision reference which P2(cid:2) 1 (cid:2) 1 (cid:2)60kHz is used in a variety of ways. It serves as a reference voltage 2(cid:7)R C 2(cid:7)*10M*0.265pF P2 P2 in circuits where a non−standard reference voltage is needed. Other uses include feedback control for driving an Z1(cid:2) 1 (cid:2) 1 (cid:2)500kHz optocoupler in power supplies, voltage monitor, constant 2(cid:7)R C 2(cid:7)*15.9k*20pF Z1 P1 current source, constant current sink and series pass In addition, there is an external circuit pole defined by the regulator. In each of these applications, it is critical to load: maintain stability of the device at various operating currents and load capacitances. In some cases the circuit designer can estimate the stabilization capacitance from the stability P (cid:2) 1 L 2(cid:7)R C boundary conditions curve provided in Figure 15. However, L L Also, the transfer dc voltage gain of the TL431 is: these typical curves only provide stability information at specific cathode voltages and at a specific load condition. Additional information is needed to determine the G(cid:2)G R GoR capacitance needed to optimize phase margin or allow for M GM L Example 1: process variation. A simplified model of the TL431 is shown in Figure 31. I (cid:2)10mA,R (cid:2)230(cid:2),C (cid:2)0.Definethetransfergain. When tested for stability boundaries, the load resistance is C L L 150 (cid:2). The model reference input consists of an input The DC gain is: transistor and a dc emitter resistance connected to the device anode. A dependent current source, Gm, develops a current G(cid:2)G R GoR (cid:2) whose amplitude is determined by the difference between M GM L the 1.78 V internal reference voltage source and the input (2.138)(1.0M)(1.25(cid:5))(230)(cid:2)615(cid:2)56dB transistor emitter voltage. A portion of Gm flows through compensation capacitance, C . The voltage across C 8.25k P2 P2 Loopgain(cid:2)G (cid:2)218(cid:2)47dB drives the output dependent current source, Go, which is 8.25k(cid:8)15k connected across the device cathode and anode. The resulting transfer function Bode plot is shown in Model component values are: Figure 32. The asymptotic plot may be expressed as the V = 1.78 V following equation: ref Gm = 0.3 + 2.7 exp (−I /26 mA) C (cid:3) (cid:4) where I is the device cathode current and Gm is in mhos jf C 1(cid:8) 500kHz Go = 1.25 (Vcp2) (cid:5)mhos. Av(cid:2)615 (cid:3) (cid:4)(cid:3) (cid:4) jf jf 1(cid:8) 1(cid:8) Resistor and capacitor typical values are shown on the 8.0kHz 60kHz model. Process tolerances are ±20% for resistors, ±10% for The Bode plot shows a unity gain crossover frequency of capacitors, and ±40% for transconductances. approximately 600 kHz. The phase margin, calculated from An examination of the device model reveals the location the equation, would be 55.9 degrees. This model matches the of circuit poles and zeroes: Open−Loop Bode Plot of Figure 12. The total loop would have a unity gain frequency of about 300 kHz with a phase P1(cid:2) 1 (cid:2) 1 (cid:2)7.96kHz margin of about 44 degrees. 2(cid:7)R C 2(cid:7)*1.0M*20pF GM P1 www.onsemi.com 11

TL431A, B Series, NCV431A, B Series, SCV431A VCC RL Input CL 3 15 k Cathode 9.0 (cid:5)F RP2 Go Ref 10 M 1.0 (cid:5)mho Vref 1 1.78 V GM CP1 500 k +- Rr1e6f R1.G0M M 20 pF RZ1 C0.P2265 pF 8.25 k 15.9 k Anode 2 Figure 31. Simplified TL431 Device Model TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY Note that the transfer function now has an extra pole 60 formed by the load capacitance and load resistance. dB) 50 Note that the crossover frequency in this case is about GAIN ( 40 250 kHz, having a phase margin of about −46 degrees. E Therefore, instability of this circuit is likely. AG 30 T OL TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP P V 20 80 O O 10 L - EN 0 B) 60 P d Av, O -10 GAIN ( 40 -20 P O 101 102 103 104 105 106 107 O L f, FREQUENCY (Hz) N- 20 E Figure 32. Example 1 Circuit Open Loop Gain Plot P O Example 2. Av, 0 I = 7.5 mA, R = 2.2 k(cid:2), C = 0.01 (cid:5)F. Cathode tied to C L L reference input pin. An examination of the data sheet -20 stability boundary curve (Figure 15) shows that this value of 101 102 103 104 105 106 load capacitance and cathode current is on the boundary. f, FREQUENCY (Hz) Define the transfer gain. Figure 33. Example 2 Circuit Open Loop Gain Plot The DC gain is: With three poles, this system is unstable. The only hope G(cid:2)G R GoR (cid:2) for stabilizing this circuit is to add a zero. However, that can M GM L only be done by adding a series resistance to the output (2.323)(1.0M)(1.25(cid:5))(2200)(cid:2)6389(cid:2)76dB capacitance, which will reduce its effectiveness as a noise The resulting open loop Bode plot is shown in Figure 33. filter. Therefore, practically, in reference voltage The asymptotic plot may be expressed as the following applications, the best solution appears to be to use a smaller equation: value of capacitance in low noise applications or a very (cid:3) (cid:4) large value to provide noise filtering and a dominant pole jf 1(cid:8) rolloff of the system. 500kHz Av(cid:2)615 (cid:3) (cid:4)(cid:3) (cid:4)(cid:3) (cid:4) jf jf jf 1(cid:8) 1(cid:8) 1(cid:8) 8.0kHz 60kHz 7.2kHz www.onsemi.com 12

TL431A, B Series, NCV431A, B Series, SCV431A ORDERING INFORMATION Marking Device Code Operating Temperature Range Package Code Shipping Information† Tolerance TL431ACDG AC 1.0% TL431BCDG BC 98 Units / Rail 0.4% TL431CDG C SOIC−8 2.2% TL431ACDR2G AC (Pb−Free) 1.0% TL431BCDR2G BC 2500 / Tape & Reel 0.4% TL431CDR2G C 2.2% TL431ACDMR2G TAC 1.0% Micro8 TL431BCDMR2G TBC 4000 / Tape & Reel 0.4% (Pb−Free) TL431CDMR2G T−C 2.2% TL431ACPG ACP 1.0% PDIP−8 TL431BCPG BCP 50 Units / Rail 0.4% (Pb−Free) TL431CPG CP 2.2% TL431ACLPG ACLP 0°C to 70°C 1.0% TL431BCLPG BCLP 2000 Units / Bag 0.4% TL431CLPG CLP 2.2% TL431ACLPRAG ACLP 1.0% TL431BCLPRAG BCLP 0.4% TL431CLPRAG CLP 2.2% TO−92 2000 / Tape & Reel TL431ACLPREG ACLP 1.0% (Pb−Free) TL431BCLPREG BCLP 0.4% TL431CLPREG CLP 2.2% TL431ACLPRPG ACLP 2000 / Tape & Ammo Box 1.0% TL431BCLPRMG BCLP 0.4% TL431CLPRMG CLP 2000 / Fan−Fold 2.2% TL431CLPRPG CLP TL431AIDG AI 1.0% TL431BIDG BI 98 Units / Rail 0.4% TL431IDG I SOIC−8 2.2% TL431AIDR2G AI (Pb−Free) 1.0% TL431BIDR2G BI 2500s / Tape & Reel 0.4% TL431IDR2G I 2.2% TL431AIDMR2G TAI 1.0% Micro8 TL431BIDMR2G TBI 4000 / Tape & Reel 0.4% (Pb−Free) TL431IDMR2G T−I 2.2% TL431AIPG AIP 1.0% PDIP−8 TL431BIPG BIP 50 Units / Rail 0.4% −40°C to 85°C (Pb−Free) TL431IPG IP 2.2% TL431AILPG AILP 1.0% TL431BILPG BILP 2000 Units / Bag 0.4% TL431ILPG ILP 2.2% TL431AILPRAG AILP 1.0% TL431BILPRAG BILP TO−92 0.4% 2000 / Tape & Reel SC431ILPRAG ILP (Pb−Free) 2.2% TL431ILPRAG ILP TL431AILPRMG AILP 1.0% TL431AILPRPG 2000 / Tape & Ammo Box TL431ILPRPG ILP 2.2% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 13

TL431A, B Series, NCV431A, B Series, SCV431A ORDERING INFORMATION Marking Device Code Operating Temperature Range Package Code Shipping Information† Tolerance TL431BVDG SOIC−8 98 Units / Rail BV TL431BVDR2G (Pb−Free) 2500 / Tape & Reel TL431BVDMR2G Micro8 TBV 4000 / Tape & Reel 0.4% (Pb−Free) TL431BVLPG TO−92 2000 Units / Bag BVLP TL431BVLPRAG (Pb−Free) 2000 / Tape & Reel TL431BVPG PDIP−8 BVP 50 Units / Rail 0.4% (Pb−Free) −40°C to 125°C NCV431AIDMR2G* RAN Micro8 4000 / Tape & Reel SCV431AIDMR2G* RAP (Pb−Free) 1% NCV431AIDR2G* SOIC−8 AV 2500 / Tape & Reel (Pb−Free) NCV431BVDMR2G* Micro8 NVB 4000 / Tape & Reel (Pb−Free) 0.4% NCV431BVDR2G* SOIC−8 BV 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. MARKING DIAGRAMS SOIC−8 Micro8 PDIP−8 TO−92 (TO−226) D SUFFIX CASE 846A CASE 626 CASE 29 CASE 751 8 8 8 TL431 431xx xxx TL431xxx xxxx ALY(cid:5)W AYW(cid:5) AWL ALYW(cid:5) (cid:5) YYWWG (cid:5) 1 1 1 8 xxxx = See Specific Marking Code TL431 A = Assembly Location ALYWx (cid:5) WL, L = Wafer Lot YY, Y = Year 1 WW, W = Work Week (Exception for the TL431CD (cid:5) or G = Pb−Free Package and TL431ID only) (Note: Microdot may be in either location) www.onsemi.com 14

TL431A, B Series, NCV431A, B Series, SCV431A PACKAGE DIMENSIONS TO−92 (TO−226) CASE 29−11 ISSUE AN A NOTES: B STRAIGHT LEAD 1. DIMENSIONING AND TOLERANCING PER ANSI BULK PACK Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. R 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND P BEYOND DIMENSION K MINIMUM. L SEATING INCHES MILLIMETERS PLANE K DIM MIN MAX MIN MAX A 0.175 0.205 4.45 5.20 B 0.170 0.210 4.32 5.33 C 0.125 0.165 3.18 4.19 D 0.016 0.021 0.407 0.533 X X D G 0.045 0.055 1.15 1.39 G H 0.095 0.105 2.42 2.66 J 0.015 0.020 0.39 0.50 H J K 0.500 --- 12.70 --- L 0.250 --- 6.35 --- V C N 0.080 0.105 2.04 2.66 P --- 0.100 --- 2.54 SECTION X−X R 0.115 --- 2.93 --- 1 N V 0.135 --- 3.43 --- N R A B BENT LEAD N1O.TEDSIM:ENSIONING AND TOLERANCING PER TAPE & REEL ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. AMMO PACK 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P P AND BEYOND DIMENSION K MINIMUM. T MILLIMETERS SPELAATNIENG K DIM MIN MAX A 4.45 5.20 B 4.32 5.33 C 3.18 4.19 D 0.40 0.54 X X D G 2.40 2.80 G J 0.39 0.50 K 12.70 --- J N 2.04 2.66 V P 1.50 4.00 C R 2.93 --- V 3.43 --- SECTION X−X 1 N www.onsemi.com 15

TL431A, B Series, NCV431A, B Series, SCV431A PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE E1 NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM 1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW www.onsemi.com 16

TL431A, B Series, NCV431A, B Series, SCV431A PACKAGE DIMENSIONS Micro8(cid:6) CASE 846A−02 ISSUE J DD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED HE E 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. MILLIMETERS INCHES PIN 1 ID e DIM MIN NOM MAX MIN NOM MAX A −− −− 1.10 −− −− 0.043 b8 PL A1 0.05 0.08 0.15 0.002 0.003 0.006 0.08 (0.003) M T B S A S b 0.25 0.33 0.40 0.010 0.013 0.016 c 0.13 0.18 0.23 0.005 0.007 0.009 D 2.90 3.00 3.10 0.114 0.118 0.122 E 2.90 3.00 3.10 0.114 0.118 0.122 e 0.65 BSC 0.026 BSC SEATING −T− PLANE L 0.40 0.55 0.70 0.016 0.021 0.028 0.038 (0.0015) A HE 4.75 4.90 5.05 0.187 0.193 0.199 A1 c L RECOMMENDED SOLDERING FOOTPRINT* 8X 8X0.48 0.80 5.25 0.65 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 17

TL431A, B Series, NCV431A, B Series, SCV431A PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 −X− ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER A ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 8 5 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR 1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL 4 IN EXCESS OF THE D DIMENSION AT −Y− K MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES C NX 45(cid:2) DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 SEATING B 3.80 4.00 0.150 0.157 PLANE −Z− C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 0.10 (0.004) G 1.27 BSC 0.050 BSC H D M J HJ 00..1109 00..2255 00..000047 00..001100 K 0.40 1.27 0.016 0.050 M 0 (cid:2) 8 (cid:2) 0 (cid:2) 8 (cid:2) 0.25 (0.010)M Z Y S X S N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:3) (cid:4) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com TL431/D 18