Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 TL08xx JFET-Input Operational Amplifiers 1 Features 3 Description • LowPowerConsumption:1.4mA/chTypical The TL08xx JFET-input operational amplifier family is 1 designed to offer a wider selection than any • WideCommon-ModeandDifferentialVoltage previously developed operational amplifier family. Ranges Each of these JFET-input operational amplifiers • LowInputBiasCurrent:30pATypical incorporates well-matched, high-voltage JFET and • LowInputOffsetCurrent:5pATypical bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias • OutputShort-CircuitProtection and offset currents, and low offset-voltage • LowTotalHarmonicDistortion:0.003%Typical temperaturecoefficient. • HighInputImpedance:JFETInputStage DeviceInformation(1) • Latch-Up-FreeOperation PARTNUMBER PACKAGE BODYSIZE(NOM) • HighSlewRate:13V/μsTypical TL084xD SOIC(14) 8.65mm×3.91mm • Common-ModeInputVoltageRange TL08xxFK LCCC(20) 8.89mm×8.89mm IncludesV CC+ TL084xJ CDIP(14) 19.56mm×6.92mm 2 Applications TL084xN PDIP(14) 19.3mm×6.35mm TL084xNS SO(14) 10.3mm×5.3mm • Tablets TL084xPW TSSOP(14) 5.0mm×4.4mm • Whitegoods (1) For all available packages, see the orderable addendum at • Personalelectronics theendofthedatasheet. • Computers SchematicSymbol TL081 TL082 (EACHAMPLIFIER) TL084 (EACHAMPLIFIER) OFFSET N1 IN+ + IN+ + OUT OUT IN− − IN− − OFFSET N2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.......................................14 2 Applications........................................................... 1 8.3 FeatureDescription.................................................14 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................14 4 RevisionHistory..................................................... 2 9 ApplicationsandImplementation...................... 15 9.1 ApplicationInformation............................................15 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplications ...............................................15 6 Specifications......................................................... 5 9.3 SystemExamples...................................................16 6.1 AbsoluteMaximumRatings .....................................5 10 PowerSupplyRecommendations..................... 18 6.2 ESDRatings..............................................................5 11 Layout................................................................... 18 6.3 RecommendedOperatingConditions.......................5 6.4 ThermalInformation..................................................6 11.1 LayoutGuidelines.................................................18 6.5 ElectricalCharacteristicsforTL08xC,TL08xxC,and 11.2 LayoutExamples...................................................19 TL08xI........................................................................ 6 12 DeviceandDocumentationSupport................. 20 6.6 ElectricalCharacteristicsforTL08xMandTL084x...7 12.1 DocumentationSupport........................................20 6.7 OperatingCharacteristics..........................................7 12.2 RelatedLinks........................................................20 6.8 DissipationRatingTable...........................................8 12.3 CommunityResources..........................................20 6.9 TypicalCharacteristics..............................................9 12.4 Trademarks...........................................................20 7 ParameterMeasurementInformation................13 12.5 ElectrostaticDischargeCaution............................20 8 DetailedDescription............................................ 14 12.6 Glossary................................................................20 8.1 Overview.................................................................14 13 Mechanical,Packaging,andOrderable Information........................................................... 20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionH(January2014)toRevisionI Page • AddedPinConfigurationandFunctionssection,StorageConditionstable,ESDRatingstable,FeatureDescription section,DeviceFunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendations section,Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderable Informationsection ................................................................................................................................................................ 1 • AddedApplications................................................................................................................................................................. 1 • MovedTypicalCharacteristicsintoSpecificationssection. ................................................................................................... 9 ChangesfromRevisionG(September2004)toRevisionH Page • UpdateddocumenttonewTIdatasheetformat-nospecificationchanges......................................................................... 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 5 Pin Configuration and Functions TL082FKPackage 20-PinLCCC TL081andTL081xD,P,andPSPackage TopView 8-PinSOIC,PDIP,andSO TopView T + U C C O C CC OFFSETN1 1 8 NC N 1 N VN IN− 2 7 VCC+ NC 43 2 1 20 1918 NC IN+ 3 6 OUT 1IN− 5 17 2OUT VCC− 4 5 OFFSETN2 NC 6 16 NC 1IN+ 7 15 2IN− NC 8 14 NC TL082andTL082xD,JG,P,PSandPWPackage 9 10 11 12 13 8-PinSOIC,CDIP,PDIP,SO,andTSSOP TopView C −C+ C N CCN2IN N 1OUT 1 8 VCC+ V 1IN− 2 7 2OUT 1IN+ 3 6 2IN− TL084FKPackage VCC− 4 5 2IN+ 20-PinLCCC TopView − UT UT − TL084andTL084xD,J,N,NSandPWPackage N O CO N 14-PinSOIC,CDIP,PDIP,SO,andTSSOP 1I 1 N4 4I TopView 3 2 1 20 19 1IN+ 4 18 4IN+ 1OUT 1 14 4OUT NC 5 17 NC 1IN− 2 13 4IN− VCC+ 6 16 VCC− 1IN+ 3 12 4IN+ NC 7 15 NC VCC+ 4 11 VCC− 2IN+ 8 14 3IN+ 2IN+ 5 10 3IN+ 9 10 11 12 13 2IN− 6 9 3IN− − T CT − 2OUT 7 8 3OUT N U NU N 2I 2O 3O 3I PinFunctions PIN TL081 TL082 TL084 SOIC, I/O DESCRIPTION NAME SOIC,PDIP, SOIC, CDIP, CDIP,PDIP, LCCC LCCC SO PDIP,SO, SO,TSSOP TSSOP 1IN– — 2 5 2 3 I Negativeinput 1IN+ — 3 7 3 4 I Positiveinput 1OUT — 1 2 1 2 O Output 2IN– — 6 15 6 9 I Negativeinput 2IN+ — 5 12 5 8 I Positiveinput 2OUT — 7 17 7 10 O Output 3IN– — — — 9 13 I Negativeinput 3IN+ — — — 10 14 I Positiveinput 3OUT — — — 8 12 O Output 4IN– — — — 13 19 I Negativeinput 4IN+ — — — 12 18 I Positiveinput 4OUT — — — 14 20 O Output Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com PinFunctions(continued) PIN TL081 TL082 TL084 SOIC, I/O DESCRIPTION NAME SOIC,PDIP, SOIC, CDIP, CDIP,PDIP, LCCC LCCC SO PDIP,SO, SO,TSSOP TSSOP IN– 2 — — — — I Negativeinput IN+ 3 — — — — I Positiveinput 1 1 3 4 5 6 8 7 NC 8 — 9 — — Donotconnect 11 11 13 14 15 16 18 17 OFFSET 1 — — — — — Inputoffsetadjustment N1 OFFSET 5 — — — — — Inputoffsetadjustment N2 OUT 6 — — — — O Output V 4 4 10 11 16 — Powersupply CC– V 7 8 20 4 6 — Powersupply CC+ 4 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VCC+ Supplyvoltage(2) 18 V VCC– –18 VID Differentialinputvoltage(3) ±30 V VI Inputvoltage(2)(4) ±15 V Durationofoutputshortcircuit(5) Unlimited Continuoustotalpowerdissipation SeeDissipationRatingTable TL08_C TL08_AC 0 70 TL08_BC TA Operatingfree-airtemperature TL08_I –40 85 °C TL084Q –40 125 TL08_M –55 125 Operatingvirtualjunctiontemperature 150 °C TC Casetemperaturefor60seconds FKpackage TL08_M 260 °C Leadtemperature1,6mm(1/16 JorJGpackage TL08_M 300 °C inch)fromcasefor10seconds Tstg Storagetemperature –65 150 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialvoltages,arewithrespecttothemidpointbetweenV andV . CC+ CC− (3) DifferentialvoltagesareatIN+,withrespecttoIN−. (4) Themagnitudeoftheinputvoltagemustneverexceedthemagnitudeofthesupplyvoltageor15V,whicheverisless. (5) Theoutputmaybeshortedtogroundortoeithersupply.Temperatureand/orsupplyvoltagesmustbelimitedtoensurethatthe dissipationratingisnotexceeded. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 1000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) 1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage 5 15 V CC+ V Supplyvoltage –5 –15 V CC– V Common-modevoltage V +4 V –4 V CM CC– CC+ TL08xM –55 125 TL08xQ –40 125 T Ambienttemperature °C A TL08xI –40 85 TL08xC 0 70 Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com 6.4 Thermal Information TL08xx D(SOIC) N(PDIP) NS(SO) P(PDIP) PS(SO) PW(TSSOP) THERMALMETRIC(1) UNIT 8PINS 14 14PINS 14PINS {PIN {PIN 8PINS 14 PINS COUNT} COUNT} PINS PINS PINS Junction-to-ambient RθJA thermalresistance(2)(3) 97 86 76 80 85 95 149 113 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. (2) MaximumpowerdissipationisafunctionofT ,R ,andT .Themaximumallowablepowerdissipationatanyallowableambient J(max) θJA A temperatureisP =(T –T )/R .OperatingattheabsolutemaximumT of150°Ccanaffectreliability. D J(max) A θJA J (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. 6.5 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI V =±15V(unlessotherwisenoted) CC± TL081C,TL082C, TL081AC,TL082AC, TL081BC,TL082BC, TL081I,TL082I, PARAMETER CONTDEISTTIONS TA(1) TL084C TL084AC TL084BC TL084I UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 25°C 3 15 3 6 2 3 3 6 VIO Ivnopltuatgoeffset VROS==500, Ω Full 20 7.5 5 9 mV range Temperature coefficientof αVIO ionfpfsuett VROS==500, Ω raFnuglle 18 18 18 18 μV/°C voltage 25°C 5 200 5 100 5 100 5 100 pA Inputoffset IIO current(2) VO=0 Full 2 2 2 10 nA range 25°C 30 400 30 200 30 200 30 200 pA Inputbias IIB current(2) VO=0 Full 10 7 7 20 nA range Common- –12 –12 –12 –12 mode VICR inputvoltage 25°C ±11 to ±11 to ±11 to ±11 to V 15 15 15 15 range Maximum RL=10kΩ 25°C ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 peak VOM output RL≥10kΩ Full ±12 ±12 ±12 ±12 V vsowlitnagge RL≥2kΩ range ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12 Large-signal 25°C 25 200 50 200 50 200 50 200 AVD dvoifflteargeential VROL≥=2±1k0ΩV, Full 15 15 25 25 V/mV amplification range Unity-gain B1 bandwidth 25°C 3 3 3 3 MHz Input ri resistance 25°C 1012 1012 1012 1012 Ω Common- mode VIC=VICRmin, CMRR rejection VO=0, 25°C 70 86 75 86 75 86 75 86 dB ratio RS=50Ω Supply- voltage VCC=±15Vto ±9V, kSVR rreajteioction VO=0, 25°C 70 86 80 86 80 86 80 86 dB (ΔVCC±/ΔVIO) RS=50Ω (1) Allcharacteristicsaremeasuredunderopen-loopconditionswithzerocommon-modevoltage,unlessotherwisespecified.Fullrangefor T is0°Cto70°CforTL08_C,TL08_AC,TL08_BCand–40°Cto85°CforTL08_I. A (2) InputbiascurrentsofanFET-inputoperationalamplifierarenormaljunctionreversecurrents,whicharetemperaturesensitive,as showninFigure13.Pulsetechniquesmustbeusedthatmaintainthejunctiontemperatureasclosetotheambienttemperatureas possible. 6 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI (continued) V =±15V(unlessotherwisenoted) CC± TL081C,TL082C, TL081AC,TL082AC, TL081BC,TL082BC, TL081I,TL082I, PARAMETER CONTDEISTTIONS TA(1) TL084C TL084AC TL084BC TL084I UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Supply ICC c(euarrcehnt VNOo=loa0d, 25°C 1.4 2.8 1.4 2.8 1.4 2.8 1.4 2.8 mA amplifier) Crosstalk VO1/VO2 attenuation AVD=100 25°C 120 120 120 120 dB 6.6 Electrical Characteristics for TL08xM and TL084x V =±15V(unlessotherwisenoted) CC± TL081M,TL082M TL084Q,TL084M PARAMETER TESTCONDITIONS(1) TA UNIT MIN TYP MAX MIN TYP MAX 25°C 3 6 3 9 VIO Inputoffsetvoltage VO=0,RS=50Ω mV Fullrange 9 15 Temperature αVIO coefficientofinput VO=0,RS=50Ω Fullrange 18 18 μV/°C offsetvoltage 25°C 5 100 5 100 pA IIO Inputoffsetcurrent(2) VO=0 125°C 20 20 nA 25°C 30 200 30 200 pA IIB Inputbiascurrent(2) VO=0 125°C 50 50 nA –12 –12 Common-mode VICR inputvoltagerange 25°C ±11 to ±11 to V 15 15 RL=10kΩ 25°C ±12 ±13.5 ±12 ±13.5 Maximumpeak VOM outputvoltageswing RL≥10kΩ Fullrange ±12 ±12 V RL≥2kΩ ±10 ±12 ±10 ±12 Large-signaldifferential 25°C 25 200 25 200 AVD voltageamplification VO=±10V,RL≥2kΩ Fullrange 15 15 V/mV B1 Unity-gainbandwidth 25°C 3 3 MHz ri Inputresistance 25°C 1012 1012 Ω CMRR Common-mode VIC=VICRmin, 25°C 80 86 80 86 dB rejectionratio VO=0,RS=50Ω Supply-voltage kSVR r(ΔejVeCctCio±/nΔVraIOti)o VVCOC==0±,1R5SV=t5o0±Ω9V, 25°C 80 86 80 86 dB Supplycurrent ICC (eachamplifier) VO=0,Noload 25°C 1.4 2.8 1.4 2.8 mA VO1/VO2 Crosstalkattenuation AVD=100 25°C 120 120 dB (1) Allcharacteristicsaremeasuredunderopen-loopconditions,withzerocommon-modeinputvoltage,unlessotherwisespecified. (2) InputbiascurrentsofaFET-inputoperationalamplifierarenormaljunctionreversecurrents,whicharetemperaturesensitive,asshown inFigure13.Pulsetechniquesmustbeusedthatmaintainthejunctiontemperaturesasclosetotheambienttemperatureaspossible. 6.7 Operating Characteristics V =±15V,T =25°C(unlessotherwisenoted) CC± A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VI=10V,RL=2kΩ,CL=100pF, 8(1) 13 SeeFigure19 SR Slewrateatunitygain V =10V,R =2kΩ,C =100pF, V/μs I L L T =−55°Cto125°C, 5(1) A SeeFigure19 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com Operating Characteristics (continued) V =±15V,T =25°C(unlessotherwisenoted) CC± A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT tr Rise-time VI=20V,RL=2kΩ,CL=100pF, 0.05 μs overshootfactor SeeFigure19 20% Equivalentinputnoise f=1kHz 18 nV/√Hz V R =20Ω n voltage S f=10Hzto10kHz 4 μV Equivalentinputnoise I R =20Ω, f=1kHz 0.01 pA/√Hz n current S Vrms=6V,A =1,R ≤1kΩ,R ≥2kΩ, THD Totalharmonicdistortion I VD S L 0.003% f=1kHz, 6.8 Dissipation Rating Table T ≤25°C DERATING DERATE T =70°C T =85°C T =125°C PACKAGE A A A A POWERRATING FACTOR ABOVET POWERRATING POWERRATING POWERRATING A D(14pin) 680mW 7.6mW/°C 60°C 604m/W 490mW 186mW FK 680mW 11.0mW/°C 88°C 680m/W 680mW 273mW J 680mW 11.0mW/°C 88°C 680m/W 680mW 273mW JG 680mW 8.4mW/°C 69°C 672m/W 546mW 210mW 8 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 6.9 Typical Characteristics Dataathighandlowtemperaturesareapplicableonlywithintheratedoperatingfree-airtemperaturerangesofthevarious devices.TheFigurenumbersreferencedinthefollowinggraphsarelocatedinParameterMeasurementInformation. Table1.TableofGraphs Figure versusFrequency Figure1,Figure2,Figure3 versusFree-airtemperature Figure4 V Maximumpeakoutputvoltage OM versusLoadresistance Figure5 versusSupplyvoltage Figure6 Large-signaldifferentialvoltage versusFree-airtemperature Figure7 amplification versusLoadresistance Figure8 A VD versusFrequencywithfeed-forward Differentialvoltageamplification Figure9 compensation P Totalpowerdissipation versusFree-airtemperature Figure10 D versusFree-airtemperature Figure11 I Supplycurrent CC versusSupplyvoltage Figure12 I Inputbiascurrent versusFree-airtemperature Figure13 IB Large-signalpulseresponse versusTime Figure14 V Outputvoltage versusElapsedtime Figure15 O CMRR Common-moderejectionratio versusFree-airtemperature Figure16 V Equivalentinputnoisevoltage versusFrequency Figure17 n THD Totalharmonicdistortion versusFrequency Figure18 ±15 ±15 −oltageVOutput V ±1±21.05 VVCCCC±±==±±1150 V V RTSAeLe== F 21i50g° uCkrΩe 2 oltage−VOutput V ±1±21.05 VVCCCC±±==±±1105 VV STRAeLe== F 22i5 gk°uCΩre 2 Peak ±7.5 Peak ±7.5 m m mu ±5 VCC±=±5 V mu ±5 Maxi Maxi VCC±=±5 V −MM ±2.5 M−M ±2.5 OO OO VV VV 0 0 100 1 k 10 k 100 k 1 M 10 M 100 1 k 10 k 100 k 1 M 10 M f−Frequency−Hz f−Frequency−Hz Figure1.MaximumPeakOutputVoltage Figure2.MaximumPeakOutputVoltage vs vs Frequency Frequency Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com ±15 ±15 oltage−Vm Peak Output V ±±1±721..505 TA= 25°C TA=−55°CVRSeCLeC= ±F 2=i gk±uΩ1r5e V2 oltage−Vm Peak Output V ±±1±721..055 RRLL== 120 k kΩΩ Maximu ±5 TA= 125°C Maximu ±5 VVOM−OM ±2.5 VVOM−OM ±2.5 VSeCeC ±F=ig±u1r5e V2 0 0 −75 −50 −25 0 25 50 75 100 125 10 k 40 k 100 k 400 k 1 M 4 M 10 M f−Frequency−Hz TA−Free-Air Temperature−°C Figure3.MaximumPeakOutputVoltage Figure4.MaximumPeakOutputVoltage vs vs Frequency Free-AirTemperature ±15 ±15 oltage−VV ±12.5 VTSAeCeC= ± F2=i5g°±uC1r5e V2 oltage−VV ±12.5 RTAL== 2150° CkΩ ut ±10 ut ±10 p p ut ut O O Peak ±7.5 Peak ±7.5 m m mu ±5 mu ±5 Maxi Maxi M−M ±2.5 M−M ±2.5 VOVO 8 VOVO 8 0 0 0.1 0.2 0.4 0.7 1 2 4 7 10 0 2 4 6 8 10 12 14 16 RL−Load Resistance−kΩ |VCC±|−Supply Voltage−V Figure5.MaximumPeakOutputVoltage Figure6.MaximumPeakOutputVoltage vs vs LoadResistance SupplyVoltage 1000 106 VCC±=±5 V to±15 V 400 RL= 2 kΩ ntialmV 200 ntial 105 TA= 25°C −Large-Signal DiffereaAmpgelification−V/ 112400000 –Large-Signal DiffereVoltaAmpgelification 111000234 DVAoimflftpearlgiefeinctaiatilon 04950°°° Phase Shift AAVDVolt 4 VCC±=±15 V AAVD 101 Phase Shift 135° 2 VROL== 2± 1k0Ω V 1 1 180° −75 −50 −25 0 25 50 75 100 125 1 10 100 1 k 10 k 100 k 1 M 10 M TA−Free-Air Temperature−°C f−Frequency−Hz Figure7.Large-SignalDifferentialVoltageAmplification Figure8.Large-SignalDifferentialVoltageAmplificationand vs PhaseShift Free-AirTemperature vs Frequency 10 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 106 250 mV VCC±=±15 V 225 VNCo CS±ig=n±a1l5 V ation−V/ 105 STCAe2e ==F 23ig5 p°uFCre3 −mW 127050 No Load mplific 104 pation 150 TL084, TL085 A si ge 103 Dis 125 Volta ower 100 TL082, TL083 Differential 11020 −Total PD 5705 TL081 − P 25 D V A 1 0 100 1 k 10 k 100 k 1 M 10 M −75 −50 −25 0 25 50 75 100 125 f−FrequencyWithFeed-ForwardCompensation−Hz TA−Free-AirTemperature°−C Figure9.DifferentialVoltageAmplification Figure10.TotalPowerDissipation vs vs FrequencywithFeed-ForwardCompensation Free-AirTemperature 2 2 A VCC±=±15 V A TA= 25°C m 1.8 No Signal m 1.8 No Signal − No Load − No Load mplifier 11..46 mplifier 11..46 A A Per 1.2 Per 1.2 nt nt urre 1 urre 1 ply C 0.8 ply C 0.8 up 0.6 up 0.6 S S CC−±C 0.4 CC−C± 0.4 IIC 0.2 IIC 0.2 0 0 −75 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA−Free-Air Temperature−°C |VCC±|−Supply Voltage−V Figure11.SupplyCurrentperAmplifier Figure12.SupplyCurrentperAmplifier vs vs Free-AirTemperature SupplyVoltage 100 6 VCC±=±15 V −V VRCLC=± 2= k±Ω15 V A ages 4 TCAL== 2150°0C pF −n 10 oltV Output urrent utput 2 C O as 1 nd 0 −Input Bi −Input a −2 IIB 0.1 VndO −4 Input a VI −6 0.01 0 0.5 1 1.5 2 2.5 3 3.5 −50 −25 0 25 50 75 100 125 t−Time−µs TA−Free-AirTemperature−°C Figure14.Voltage-FollowerLarge-SignalPulseResponse Figure13.InputBiasCurrent vs Free-AirTemperature Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com 28 89 VCC±=±15 V 24 dB RL= 10 kΩ − 88 o mV 20 Rati − on 87 age 16 VCC±=±15 V ecti putVolt 12 CTRALL=== 21250 k°0ΩC pF ode Rej 86 Out 8 See Figure 1 n-M − mo 85 VO 4 om C − 84 0 R R M C −4 83 0 0.2 0.4 0.6 0.8 1.0 1.2 −75 −50 −25 0 25 50 75 100 125 t−ElapsedTime–µs TA−Free-AirTemperature−°C Figure15.OutputVoltage Figure16.Common-ModeRejectionRatio vs vs ElapsedTime Free-AirTemperature zHz 50 VCC±=±15 V 1 VCC±=±15 V oltage−nV/HVnV/ 40 ARTAVSD== = 2 25 10°C0Ω stortion−% 00..14 AVTAVI(RD=M = S2 1)5=°C 6 V Noise 30 nic Di 0.04 ut mo quivalent Inp 1200 otaD−Tl Har 00.0.0014 E H − T n V 0 0.001 10 40 100 400 1 k 4 k 10 k 40 k100 k 100 400 1 k 4 k 10 k 40 k100 k f−Frequency−Hz f−Frequency−Hz Figure17.EquivalentInputNoiseVoltage Figure18.TotalHarmonicDistortion vs vs Frequency Frequency 12 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 7 Parameter Measurement Information 10 kΩ 1 kΩ − VI − OUT OUT + VI + RL CL= 100 pF CL= 100 pF RL= 2 kΩ Figure19.TestFigure1 Figure20.TestFigure2 100 kΩ TL081 IN− − C2 OUT IN+ + N2 C1 500 pF N1 100 kΩ IN− − N1 OUT + 1.5 kΩ VCC− Figure21.TestFigure3 Figure22.TestFigure4 Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com 8 Detailed Description 8.1 Overview The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well- matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. Offset adjustment andexternalcompensationoptionsareavailablewithintheTL08xxfamily. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to +125°C. The M-suffixdevicesarecharacterizedforoperationoverthefullmilitarytemperaturerangeof −55°Cto+125°C. 8.2 Functional Block Diagram VCC+ IN+ IN− 64Ω OUT 128Ω 64Ω C1 1080Ω 1080Ω VCC− OFFSET N1 OFFSET N2 TL081 Only 8.3 Feature Description 8.3.1 TotalHarmonicDistortion Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion(THD)isameasureofharmonicdistortionsaccumulatedbyasignalinanaudiosystem.Thesedevices have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when used in audiosignalapplications. 8.3.2 SlewRate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input.Thesedeviceshavea13-V/μsslewrate. 8.4 Device Functional Modes These devices are powered on when the supply is connected. This device can be operated as a single-supply operationalamplifierordual-supplyamplifierdependingontheapplication. 14 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TL08x series of operational amplifiers can be used in countless applications. The few applications in this sectionshowprinciplesusedinallapplicationsoftheseparts. 9.2 Typical Applications 9.2.1 InvertingAmplifierApplication A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negativevoltagespositive. RF Vsup+ RI V OUT + V IN Vsup- Figure23. SchematicforInvertingAmplifierApplication 9.2.1.1 DesignRequirements The supply voltage must be chosen such that it is larger than the input voltage range and output range. For instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodatethisapplication. 9.2.1.2 DetailedDesignProcedure Determinethegainrequiredbytheinvertingamplifier: (1) (2) Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was determined by Equation3. (3) Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com Typical Applications (continued) 9.2.1.3 ApplicationCurve 2 VIN 1.5 VOUT 1 0.5 olts 0 V -0.5 -1 -1.5 -2 0 0.5 1 1.5 2 Time (ms) Figure24. Inputandoutputvoltagesoftheinvertingamplifier 9.3 System Examples 9.3.1 GeneralApplications RF= 100 kΩ VCC+ − 15 V R1 R2 TL081 3.3 kΩ Output Input + Output − C3 TL081 VCC− CF= 3.3µF + 1 kΩ −15V R3 R1 = R2 = 2(R3) = 1.5 MΩ C1 C2 C3 C1 = C2 = = 110 pF 3.3 kΩ 2 9.1 kΩ 1 f = 1 fo= 2πR1 C1 = 1 kHz 2πRFCF Figure25.0.5-HzSquare-WaveOscillator Figure26.High-QNotchFilter VCC+ 6sinωt 1N4148 −15 V 1 MΩVCC+ −+TL084 OutputA 18V pCFC+ 18 pF1 kΩ (se1e8 N koΩteA) Input 1µF +T−L084 VCC+ 88.4kΩ +−1T/L208V2CC− 88.4 kΩ +−1T/L208V2CC+ 6 cosωt − 18 pF VCC− 1 kΩ TL084 Output B 15 V 100 kΩ 100 kΩ VCC+ + 88.4 kΩ 1N4148 (se1e8 N koΩteA) 100 kΩ VCC+ A.Theseresistorvaluesmaybeadjustedforasymmetricaloutput. 100µF 100 kΩ − TL084 OutputC + Figure27.Audio-DistributionAmplifier Figure28.100-kHzQuadratureOscillator 16 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 System Examples (continued) 16 kΩ 16 kΩ 220 pF 220 pF 43 kΩ 30 kΩ 43 kΩ 30 kΩ 43 kΩ VCC+ VCC+ 220 pF VCC+ 220 pF VCC+ Input 1−/4 43 kΩ − 43 kΩ −1/4 43 kΩ − TL084 1/4 TL084 1/4 Output + TL084 + TL084 B + + 1.5 kΩ VCC− 1.5 kΩ VCC− VCC− VCC− OutputA OutputA OutputB 2 kHz/div 2 kHz/div Second-Order Bandpass Filter Cascaded Bandpass Filter fo= 100 kHz, Q = 30, GAIN = 4 fo= 100 kHz, Q = 69, GAIN = 16 Figure29.Positive-FeedbackBandpassFilter Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com 10 Power Supply Recommendations CAUTION Supplyvoltageslargerthan36Vforasingle-supplyoroutsidetherangeof ±18Vfora dual-supply can permanently damage the device (see the Absolute Maximum Ratings ). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedancepowersupplies.Formoredetailedinformationonbypasscapacitorplacement,refertotheLayout. 11 Layout 11.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodPCBlayoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance powersourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to CircuitBoardLayoutTechniques,(SLOA089). • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposedtoinparallelwiththenoisytrace. • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting inputminimizesparasiticcapacitance,asshowninLayoutExamples. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakagecurrentsfromnearbytracesthatareatdifferentpotentials. 18 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B www.ti.com SLOS081I–FEBRUARY1977–REVISEDMAY2015 11.2 Layout Examples Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines RF as possible NC NC VS+ Use low-ESR, ceramic RG bypass capacitor GND IN1í VCC+ VIN IN1+ OUT RIN VCCí NC GND Only needed for dual-supply operation GND VS- (or GND for single supply) VOUT Ground (GND) plane on another layer Figure30. OperationalAmplifierBoardLayoutforNoninvertingConfiguration RIN VIN + VOUT RG RF Figure31. OperationalAmplifierSchematicforNoninvertingConfiguration Copyright©1977–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B SLOS081I–FEBRUARY1977–REVISEDMAY2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Formoreinformation,seethefollowing: • CircuitBoardLayoutTechniques,SLOA089. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY TL081 Clickhere Clickhere Clickhere Clickhere Clickhere TL081A Clickhere Clickhere Clickhere Clickhere Clickhere TL081B Clickhere Clickhere Clickhere Clickhere Clickhere TL082 Clickhere Clickhere Clickhere Clickhere Clickhere TL082A Clickhere Clickhere Clickhere Clickhere Clickhere TL082B Clickhere Clickhere Clickhere Clickhere Clickhere TL084 Clickhere Clickhere Clickhere Clickhere Clickhere TL084A Clickhere Clickhere Clickhere Clickhere Clickhere TL084B Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©1977–2015,TexasInstrumentsIncorporated ProductFolderLinks:TL081 TL081A TL081B TL082 TL082ATL082B TL084 TL084A TL084B

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9851501Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851501Q2A TL082MFKB 5962-9851501QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9851501QPA TL082M 5962-9851503Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851503Q2A TL084 MFKB 5962-9851503QCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL081ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 081AC & no Sb/Br) TL081ACDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 081AC & no Sb/Br) TL081ACP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL081ACP & no Sb/Br) TL081BCD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 081BC & no Sb/Br) TL081BCDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 081BC & no Sb/Br) TL081BCP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL081BCP & no Sb/Br) TL081BCPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL081BCP & no Sb/Br) TL081CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C & no Sb/Br) TL081CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C & no Sb/Br) TL081CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL081CP & no Sb/Br) TL081CPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL081CP & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL081CPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T081 & no Sb/Br) TL081ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I & no Sb/Br) TL081IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I & no Sb/Br) TL081IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL081IP & no Sb/Br) TL082ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACDE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082AC & no Sb/Br) TL082ACP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL082ACP (RoHS) TL082ACPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082A & no Sb/Br) TL082BCD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082BC & no Sb/Br) TL082BCDE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082BC & no Sb/Br) TL082BCDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082BC & no Sb/Br) TL082BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082BC & no Sb/Br) TL082BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 082BC & no Sb/Br) TL082BCP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL082BCP (RoHS) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL082BCPE4 ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL082BCP (RoHS) TL082CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C & no Sb/Br) TL082CDE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C & no Sb/Br) TL082CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C & no Sb/Br) TL082CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C & no Sb/Br) TL082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C & no Sb/Br) TL082CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL082CP & no Sb/Br) TL082CPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082 & no Sb/Br) TL082CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082 & no Sb/Br) TL082CPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082 & no Sb/Br) TL082CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082 & no Sb/Br) TL082CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T082 & no Sb/Br) TL082ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I & no Sb/Br) TL082IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I & no Sb/Br) TL082IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I & no Sb/Br) TL082IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I & no Sb/Br) TL082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I & no Sb/Br) TL082IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL082IP & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL082IPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL082IP & no Sb/Br) TL082IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 Z082 & no Sb/Br) TL082MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851501Q2A TL082MFKB TL082MJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 TL082MJG TL082MJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9851501QPA TL082M TL084ACD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC & no Sb/Br) TL084ACDE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC & no Sb/Br) TL084ACDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC & no Sb/Br) TL084ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC & no Sb/Br) TL084ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC & no Sb/Br) TL084ACN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL084ACN & no Sb/Br) TL084ACNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A & no Sb/Br) TL084BCD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC & no Sb/Br) TL084BCDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC & no Sb/Br) TL084BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC & no Sb/Br) TL084BCN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL084BCN & no Sb/Br) TL084BCNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL084BCN & no Sb/Br) TL084CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL084CDE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) TL084CDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) TL084CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) TL084CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) TL084CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C & no Sb/Br) TL084CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL084CN & no Sb/Br) TL084CNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL084CN & no Sb/Br) TL084CNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL084 & no Sb/Br) TL084CPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T084 & no Sb/Br) TL084CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T084 & no Sb/Br) TL084CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T084 & no Sb/Br) TL084ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I & no Sb/Br) TL084IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I & no Sb/Br) TL084IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I & no Sb/Br) TL084IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I & no Sb/Br) TL084IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL084IN & no Sb/Br) TL084INE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL084IN & no Sb/Br) TL084MFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TL084MFK Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL084MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9851503Q2A TL084 MFKB TL084MJ ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 TL084MJ TL084MJB ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL084QD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q & no Sb/Br) TL084QDG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q & no Sb/Br) TL084QDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q & no Sb/Br) TL084QDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M : •Catalog: TL082, TL084 •Automotive: TL082-Q1, TL082-Q1 •Military: TL082M, TL084M NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications Addendum-Page 7

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TL081ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TL084BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TL084CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TL084IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084QDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TL081ACDR SOIC D 8 2500 340.5 338.1 20.6 TL081BCDR SOIC D 8 2500 340.5 338.1 20.6 TL081CDR SOIC D 8 2500 340.5 338.1 20.6 TL081IDR SOIC D 8 2500 340.5 338.1 20.6 TL082ACDR SOIC D 8 2500 367.0 367.0 35.0 TL082ACDR SOIC D 8 2500 340.5 338.1 20.6 TL082BCDR SOIC D 8 2500 340.5 338.1 20.6 TL082CDR SOIC D 8 2500 367.0 367.0 35.0 TL082CDR SOIC D 8 2500 340.5 338.1 20.6 TL082CPWR TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TL082IDR SOIC D 8 2500 340.5 338.1 20.6 TL082IDR SOIC D 8 2500 367.0 367.0 35.0 TL082IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL084ACDR SOIC D 14 2500 367.0 367.0 38.0 TL084ACDR SOIC D 14 2500 333.2 345.9 28.6 TL084ACNSR SO NS 14 2000 367.0 367.0 38.0 TL084BCDR SOIC D 14 2500 333.2 345.9 28.6 TL084CDR SOIC D 14 2500 367.0 367.0 38.0 TL084CDR SOIC D 14 2500 333.2 345.9 28.6 TL084CDRG4 SOIC D 14 2500 333.2 345.9 28.6 TL084CNSR SO NS 14 2000 367.0 367.0 38.0 TL084CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TL084IDR SOIC D 14 2500 333.2 345.9 28.6 TL084QDR SOIC D 14 2500 350.0 350.0 43.0 TL084QDRG4 SOIC D 14 2500 350.0 350.0 43.0 PackMaterials-Page3

None

None

None

PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

None

None

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

None

PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated