TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 (cid:0) (cid:0) Direct Upgrades to TL07x and TL08x BiFET On-Chip Offset-Voltage Trimming for Operational Amplifiers Improved DC Performance and Precision (cid:0) Faster Slew Rate (20 V/µs Typ) Without Grades Are Available (1.5 mV, TL051A) Increased Power Consumption TL051 TL052 TL054 D OR P PACKAGE D, P, OR PS PACKAGE D, DB, N, OR NS PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) OFFSET N1 1 8 NC 1OUT 1 8 VCC+ 1OUT 1 14 4OUT IN– 2 7 VCC+ 1IN– 2 7 2OUT 1IN– 2 13 4IN– IN+ 3 6 OUT 1IN+ 3 6 2IN– 1IN+ 3 12 4IN+ VCC– 4 5 OFFSET N2 VCC– 4 5 2IN+ VCC+ 4 11 VCC– 2IN+ 5 10 3IN+ 2IN– 6 9 3IN– 2OUT 7 8 3OUT description/ordering information The TL05x series of JFET-input operational amplifiers offers improved dc and ac characteristics over the TL07x and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. Texas Instruments improved BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies. The TL05x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 ORDERING INFORMATION TA AVTIO 2m5a°Cx PACKAGE† POARRDT ENRUAMBBLEER MTOAPR-KSIINDGE TL051ACP TL051ACP PPDDIIPP ((PP)) TTuubbee ooff 5500 TL052ACP TL052ACP 800 µV Tube of 75 TL051ACD 051AC SOIC (D) Tube of 75 TL052ACD 005522AACC Reel of 2500 TL052ACDR TL051CP TL051CP PPDDIIPP ((PP)) TTuubbee ooff 5500 TL052CP TL052CP PDIP (N) Tube of 25 TL054ACN TL054ACN Tube of 75 TL051CD TTLL005511CC Reel of 2500 TL051CDR 00°°CC ttoo 7700°°CC 1.5 mV Tube of 75 TL052CD SSOOIICC ((DD)) TTLL005522CC Reel of 2500 TL052CDR Tube of 50 TL054ACD TTLL005544CC Reel of 2500 TL054ACDR SOP (PS) Reel of 2000 TL052CPSR TL052 SSOP (DB) Reel of 2000 TL054CDBR TL054 PDIP (N) Tube of 25 TL054CN TL054CN Tube of 50 TL054CD 44 mmVV SSOOIICC ((DD)) TTLL005544CC Reel of 2500 TL054CDR SOP (NS) Reel of 2000 TL054CNSR TL054 PDIP (P) Tube of 50 TL052AIP TL052AI 800 µV Tube of 75 TL052AID SSOOIICC ((DD)) 005522AAII Reel of 2500 TL052AIDR PDIP (N) Tube of 25 TL054AIN TL054AIN TL051IP TL051IP PPDDIIPP ((PP)) TTuubbee ooff 5500 TL052IP TL052IP Tube of 75 TL051ID TL051I –4400°°CC ttoo 8855°°CC 11.55 mmVV Tube of 75 TL052ID TTLL005522II SOIC (D) Reel of 2500 TL052IDR Tube of 50 TL054AID TTLL005544AAII Reel of 2500 TL054AIDR PDIP (N) Tube of 25 TL054IN TL054IN 4 mV Tube of 50 TL054ID SSOOIICC ((DD)) TTLL005544II Reel of 2500 TL054IDR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 symbol (each amplifier) IN– – OUT IN+ + equivalent schematic (each amplifier) VCC+ Q10 Q2 Q15 JF3 Q3 Q7 Q6 Q16 Q11 Q13 IN+ D1 Q12 R7 R9 IN– R5 OUT JF1 JF2 R8 C1 Q4 Q14 Q17 Q8 Q1 Q5 Q9 OFFSET N1 R10 D2 See Note A OFFSET N2 R4 R6 R1 R2 R3 VCC– NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x. ACTUAL DEVICE COMPONENT COUNT† COMPONENT TL051 TL052 TL054 Transistors 20 34 62 Resistors 10 19 37 Diodes 2 3 5 Capacitors 1 2 4 †These figures include all four amplifiers and all ESD, bias, and trim circuitry. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V CC+ Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V CC– Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Input voltage range, V (any input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V I Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA I Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80 mA Total current into V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA CC+ Total current out of V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA CC– Duration of short-circuit current at (or below) 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Package thermal impedance, θ (see Notes 4 and 5): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W JA D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package (14 pin) . . . . . . . . . . . . . . . . . . . 96°C/W N package (14 pin) . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package (14 pin) . . . . . . . . . . . . . . . . . . . 76°C/W P package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 85°C/W PS package (8 pin) . . . . . . . . . . . . . . . . . . . . 95°C/W Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Lead temperature 1,6 mm (1/16inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. 2. Differential voltages are at IN+ with respect to IN–. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions C SUFFIX I SUFFIX UUNNIITT MIN MAX MIN MAX VCC± Supply voltage ±5 ±15 ±5 ±15 V VCC± = ±5 V –1 4 –1 4 VVIICC CCoommmmoonn-mmooddee iinnppuutt vvoollttaaggee VCC± = ±15 V –11 11 –11 11 VV TA Operating free-air temperature 0 70 –40 85 °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL051C and TL051AC electrical characteristics at specified free-air temperature TL051C, TL051AC PARAMETER TEST CONDITIONS TA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.75 3.5 0.59 1.5 TTLL005511CC Full range 4.5 2.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee 25°C 0.55 2.8 0.35 0.8 mmVV TTLL005511AACC Full range 3.8 1.8 VVOO == 00, 25°C to (cid:0)(cid:0) Temperature coefficient RVRISSC == = 55 000, ΩΩ TL051C 70°C 8 8 µµVV//°°CC VIO of input offset voltage‡ 25°C to TL051AC 8 8 25 70°C Input offset-voltage 25°C 0.04 0.04 µV/mo long-term drift§ VOO = 0, VIICC = 0, 25°C 4 100 5 100 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt See Figure 5 70°C 0.02 1 0.025 1 nA VOO = 0, VIICC = 0, 25°C 20 200 30 200 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt See Figure 5 70°C 0.15 4 0.2 4 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR voltage range –1 –11 VV Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ output voltage swing 25°C 2.5 3.8 11.5 12.7 VV RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– output voltage swing 25°C –2.3 –3.2 –11 –12 VV RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 59 50 105 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn¶¶ttiiall RL = 2 kΩ 0°C 30 65 60 129 V/mV 70°C 20 46 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF 25°C 65 85 75 93 CMRR CCoommmmoonn-mmooddee VVIC = VVICRmmiinn, 0°C 65 84 75 92 dB rreejjeeccttiioonn rraattiioo VVOO == 00, RRSS == 5500 ΩΩ 70°C 65 84 75 91 25°C 75 99 75 99 SSuuppppllyy-vvoollttaaggee rreejjeeccttiioonn kSVR rraattiioo ((∆∆VVCCCC±±//∆∆VVIIOO)) VO = 0, RS = 50 Ω 0°C 75 98 75 98 dB 70°C 75 97 75 97 25°C 2.6 3.2 2.7 3.2 ICCCC Supplyy current VOO = 0, No load 0°C 2.7 3.2 2.8 3.2 mA 70°C 2.6 3.2 2.7 3.2 †Full range is 0°C to 70°C. ‡This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. §Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL051C and TL051AC operating characteristics at specified free-air temperature TL051C, TL051AC PARAMETER TEST CONDITIONS TA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 16 13 20 PPosiittiive sllew ratte SR+ at unity gain‡ Full 16.4 11 22.6 RLL = 2 kΩ,, CLL = 100 pF,, range VV//µµss See Figure 1 25°C 15 13 18 NNegattiive sllew ratte SR– at unity gain‡ Full 16 11 19.3 range 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 nnss VI(PP) = ±10 mV, 25°C 55 57 tf Fall time RRCCLLL === 112200 kk00ΩΩ p,FF, 0°C 54 56 See Figgures 1 and 2 70°C 62 64 25°C 24 19 Overshoot factor 0°C 24 19 % 70°C 24 19 Eqquivalent input noise f = 10 Hz 25°C 75 75 VVn voltage§ RS = 20 Ω, f = 1 kHz 25°C 18 18 30 nnVV//√√HHzz See Figure 3 Peak-to-peak equivalent f = 10 Hz to VN(PP) input noise voltage 10 kHz 25°C 4 4 µV Equivalent input In noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003 0.003 % f = 1 kHz 25°C 3 3.1 B1 Unity-gain bandwidth VVI = 1100 mVV, RRL = 22 kkΩΩ, 0°C 3.2 3.3 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 70°C 2.7 2.8 25°C 59 62 φm PPggaahhiiaannssee mmaarrggiinn aatt uunniittyy VVCCILL = == 11 220055 mm pVVFF,,, RSRSeeLee = FF 22iigg kkuuΩΩrree, 44 0°C 58 62 deg 70°C 59 62 †Full range is 0°C to 70°C. ‡For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. §This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL051I and TL051AI electrical characteristics at specified free-air temperature TL051I, TL051AI PARAMETER TEST CONDITIONS TAA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.75 3.5 0.59 1.5 TTLL005511II Full range 5.3 3.3 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee 25°C 0.55 2.8 0.35 0.8 mmVV TTLL005511AAII Full range 4.6 2.6 VVOO == 00, 25°C to (cid:0)(cid:0) Temperature coefficient of RVRISSC == = 55 000, ΩΩ TL051I 85°C 7 8 µµVV//°°CC VIO input offset voltage‡ 25°C to TL051AI 85°C 8 8 25 Input offset-voltage 25°C 0.04 0.04 µV/mo long-term drift§ VOO = 0, VIICC = 0, 25°C 4 100 5 100 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt See Figure 5 85°C 0.06 10 0.07 10 nA VOO = 0, VIICC = 0, 25°C 20 200 30 200 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt See Figure 5 85°C 0.6 20 0.7 20 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR voltage range –1 –11 VV Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ output voltage swing 25°C 2.5 3.8 11.5 12.7 VV RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– output voltage swing 25°C –2.3 –3.2 –11 –12 VV RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 59 50 105 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn¶¶ttiiall RL = 2 kΩ –40°C 30 74 60 145 V/mV 85°C 20 43 30 76 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF CCoommmmoonn-mmooddee VVIICC = VVIICCRRmmiinn,, 25°C 65 85 75 93 CMRR rreejjeeccttiioonn rraattiioo VO = 0, –40°C 65 83 75 90 dB RS = 50 Ω 85°C 65 84 75 93 25°C 75 99 75 99 kSVR SSrraauuttiippoopp ((ll∆∆yy-VVvvCCoollCCttaa±±gg//ee∆∆ VVrreeIIOOjjee))ccttiioonn VVRROSS === 550000, ΩΩ –40°C 75 98 75 98 dB 85°C 75 99 75 99 25°C 2.6 3.2 2.7 3.2 ICC Supply current VO = 0, No load –40°C 2.4 3.2 2.6 3.2 mA 85°C 2.5 3.2 2.6 3.2 †Full range is –40°C to 85°C ‡This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. §Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL051I and TL051AI operating characteristics at specified free-air temperature TL051I, TL051AI PARAMETER TEST CONDITIONS TA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 16 13 20 PPosiittiive sllew ratte SR+ at unity gain‡ Full 11 RLL = 2 kΩ,, CLL = 100 pF,, range VV//µµss See Figure 1 25°C 15 13 18 NNegattiive sllew ratte SR– at unity gain‡ Full 11 range 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 nnss VI((PP)) = ±10 mV, 25°C 55 57 tf Fall time RRL = 22 kkΩΩ, –40°C 51 53 CCLL == 110000 pFF, See Figgures 1 and 2 85°C 64 65 25°C 24 19 Overshoot factor –40°C 24 19 % 85°C 24 19 Eqquivalent input noise f = 10 Hz 25°C 75 75 VVn voltage§ RS = 20 Ω, f = 1 kHz 25°C 18 18 30 nnVV//√√HHzz See Figure 3 Peak-to-peak equivalent f = 10 Hz to VN(PP) input noise voltage 10 kHz 25°C 4 4 µV Equivalent input In noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003 0.003 % f = 1 kHz 25°C 3 3.1 B1 Unity-gain bandwidth VVI = 1100 mVV, RRL = 22 kkΩΩ, –40°C 3.5 3.6 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 85°C 2.6 2.7 25°C 59 62 φm PPggaahhiiaannssee mmaarrggiinn aatt uunniittyy VVCCILL = == 11 220055 mm pVVFF,,, RSRSeeLee = FF 22iigg kkuuΩΩrree, 44 –40°C 58 61 deg 85°C 59 62 †Full range is –40°C to 85°C. ‡For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. §This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL052C and TL052AC electrical characteristics at specified free-air temperature TL052C, TL052AC PARAMETER TEST CONDITIONS TAA† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.73 3.5 0.65 1.5 TTLL005522CC Full range 4.5 2.5 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee mmVV 25°C 0.51 2.8 0.4 0.8 VVO = 00, TTLL005522AACC Full range 3.8 1.8 VVIICC == 00, RRSS = 5500 ΩΩ TTLL005522CC 25°C to 88 88 (cid:0)(cid:0) Temperature coefficient 70°C µµVV//°°CC VIO of input offset voltage‡ 25°C to TTLL005522AACC 88 66 2255 70°C Ilonnpgu-tt oefrfmse dt-rvifot§ltage RVOS == 500, Ω VIC = 0, 25°C 0.04 0.04 µV/mo IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VOO = 0,, VVIICC == 00, 25°C 4 100 5 100 pA See Figure 5 70°C 0.02 1 0.025 1 nA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VOO = 0,, VVIICC == 00, 25°C 20 200 30 200 pA See Figure 5 70°C 0.15 4 0.2 4 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR VV voltage range –1 –11 Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ VV output voltage swing 25°C 2.5 3.8 11.5 12.7 RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– VV output voltage swing 25°C –2.3 –3.2 –11 –12 RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 59 50 105 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn¶¶ttiiall RL = 2 kΩ 0°C 30 65 60 129 V/mV 70°C 20 46 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF 25°C 65 85 75 93 CMRR CCrreeoojjeemmccmmttiioooonnnn rr-aammttiiooooddee VVVVIOOC === 00VV,,ICRmmiinn, RS = 50 Ω 0°C 65 84 75 92 dB 70°C 65 84 75 91 †Full range is 0°C to 70°C. ‡This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. §Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶For VCC± =±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL052C and TL052AC electrical characteristics at specified free-air temperature (continued) TL052C, TL052AC PARAMETER TEST CONDITIONS TAA VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 75 99 75 99 SSupplly-vollttage rejjecttiion kSVR rraattiioo ((∆∆VVCCCC±±//∆∆VVIIOO)) VO = 0, RS = 50 Ω 0°C 75 98 75 98 dB 70°C 75 97 75 97 25°C 4.6 5.6 4.8 5.6 SSupplly currentt ICC VO = 0, No load 0°C 4.7 6.4 4.8 6.4 mA ((ttwwoo aammplliiffiieerrss)) 70°C 4.4 6.4 4.6 6.4 VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL052C and TL052AC operating characteristics at specified free-air temperature TL052C, TL052AC PARAMETER TEST CONDITIONS TAA† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 17.8 9 20.7 SSRR++ SSlleeww rraattee aatt uunniittyy ggaaiinn RL = 2 kΩ, CL = 100 pF, Full range 8 VV//µµss Neggative slew rate See Figure 1 25°C 15.4 9 17.8 SSRR– at unity gain‡ Full range 8 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 nnss VI((PP)) = ±10 mV, 25°C 55 57 tf Fall time RRL = 22 kkΩΩ, 0°C 54 56 CCLL == 110000 pFF, See Figgures 1 and 2 70°C 62 64 25°C 24 19 Overshoot factor 0°C 24 19 % 70°C 24 19 Eqquivalent input noise f = 10 Hz 25°C 71 71 VVn voltage§ RS = 20 Ω, f = 1 kHz 25°C 19 19 30 nnVV//√√HHzz See Figure 3 Peak-to-peak equivalent f = 10 Hz to VN(PP) input noise current 10 kHz 25°C 4 4 µV Equivalent input In noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003 0.003 % f = 1 kHz 25°C 3 3 B1 Unity-gain bandwidth VVI = 1100 mVV, RRL = 22 kkΩΩ, 0°C 3.2 3.2 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 70°C 2.6 2.7 25°C 60 63 φm PPggaahhiiaannssee mmaarrggiinn aatt uunniittyy VVCCILL = == 11 220055 mm pVVFF,,, RRSSeeLee = FF 22iigg kkuuΩΩrree, 44 0°C 59 63 deg 70°C 60 63 †Full range is 0°C to 70°C. ‡For VCC± =±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) =±5 V. §This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± =±15 V, VO(RMS) = 6 V. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL052I and TL052AI electrical characteristics at specified free-air temperature TL052I, TL052AI PARAMETER TEST CONDITIONS TAA† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.73 3.5 0.65 1.5 TTLL005522II Full range 5.3 3.3 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee mmVV 25°C 0.51 2.8 0.4 0.8 VVO = 00, TTLL005522AAII Full range 4.6 2.6 VVIICC == 00,, RS = 50 Ω TL052I 25°C to 7 6 85°C (cid:0)(cid:0)VIO TTemperatture coeffffiiciientt‡‡ 25°C to µµVV//°°CC TL052AI 6 6 25 85°C Ilonnpgu-tt oefrfmse dt-rvifot§ltage VROS == 500, Ω VIC = 0, 25°C 0.04 0.04 µV/mo IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VOO = 0,, VIICC = 0,, 25°C 4 100 5 100 pA See Figure 5 85°C 0.06 10 0.07 10 nA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VOO = 0,, VIICC = 0,, 25°C 20 200 30 200 pA See Figure 5 85°C 0.6 20 0.7 20 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR VV voltage range –1 –11 Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ VV output voltage swing 25°C 2.5 3.8 11.5 12.7 RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– VV output voltage swing 25°C –2.3 –3.2 –11 –12 RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 59 50 105 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn¶¶ttiiall RL = 2 kΩ –40°C 30 74 60 145 V/mV 85°C 20 43 30 76 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF 25°C 65 85 75 93 CMRR CCrreeoojjeemmccmmttiioooonnnn rr-aammttiiooooddee VVVVOOIC === 00VV,,ICRmmiinn, RS = 50 Ω –40°C 65 83 75 90 dB 85°C 65 84 75 93 †Full range is –40°C to 85°C. ‡This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters §Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL052I and TL052AI electrical characteristics at specified free-air temperature (continued) TL052I, TL052AI PARAMETER TEST CONDITIONS TAA VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 75 99 75 99 SSupplly-vollttage rejjecttiion kSVR rraattiioo ((∆∆VVCCCC±±//∆∆VVIIOO)) VO = 0, RS = 50 Ω –40°C 75 98 75 98 dB 85°C 75 99 75 99 25°C 4.6 5.6 4.8 5.6 SSupplly currentt ICC VO = 0, No load –40°C 4.5 6.4 4.7 6.4 mA ((ttwwoo aammplliiffiieerrss)) 85°C 4.4 6.4 4.6 6.4 VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL052I and TL052AI operating characteristics at specified free-air temperature TL052I, TL052AI PARAMETER TEST CONDITIONS TAA† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 17.8 9 20.7 SSRR++ SSllew ratte att uniitty gaiin‡‡ RLL = 2 kΩ,, CLL = 100 pF,, Full range 8 VV//µµss Neggative slew rate at See Figure 1 25°C 15.4 9 17.8 SSRR– unity gain‡ Full range 8 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 nnss VVII((PPPP)) == ±±1100 mmVV,, 25°C 55 57 tf Fall time RL = 2 kΩ, CL = 100 pF, –40°C 51 53 See Figures 1 and 2 85°C 64 65 25°C 24% 19% Overshoot factor –40°C 24% 19% % 85°C 24% 19 Eqquivalent input noise f = 10 Hz 25°C 71 71 VVn voltage§ RS = 20 Ω, f = 1 kHz 25°C 19 19 30 nnVV//√√HHzz See Figure 3 Peak-to-peak equivalent f = 10 Hz to VN(PP) input noise current 10 kHz 25°C 4 4 µV Equivalent input noise In current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003 0.003 % f = 1 kHz 25°C 3 3 B1 Unity-gain bandwidth VVI = 1100 mVV, RRL = 22 kkΩΩ, –40°C 3.5 3.6 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 85°C 2.5 2.6 25°C 60 63 φm PPggaahhiiaannssee mmaarrggiinn aatt uunniittyy VVCCILL = == 11 220055 mm pVVFF,,, RRSSeeLee = FF 22iigg kkuuΩΩrree, 44 –40°C 58 61 deg 85°C 60 63 †Full range is –40°C to 85°C. ‡For VCC± =±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) =±5 V. §This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± =±15 V, VO(RMS) = 6 V. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL054C and TL054AC electrical characteristics at specified free-air temperature TL054C, TL054AC PARAMETER TEST CONDITIONS TA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.64 5.5 0.56 4 TTLL005544CC Full range 7.7 6.2 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee 25°C 0.57 3.5 0.5 1.5 mmVV TTLL005544AACC Full range 5.7 3.7 VVOO == 00, 25°C to VIC = 0, TL054C 25 23 (cid:0)(cid:0) Temperature coefficient RRSS = 5500 ΩΩ 70°C µµVV//°°CC VIO of input offset voltage 25°C to TL054AC 24 23 70°C Input offset-voltage 25°C 0.04 0.04 µV/mo long-term drift‡ VOO = 0, VIICC = 0, 25°C 4 100 5 100 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt See Figure 5 70°C 0.02 1 0.025 1 nA VOO = 0, VIICC = 0, 25°C 20 200 30 200 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt See Figure 5 70°C 0.15 4 0.2 4 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR voltage range –1 –11 VV Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ output voltage swing 25°C 2.5 3.8 11.5 12.7 VV RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– output voltage swing 25°C –2.3 –3.2 –11 –12 VV RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 72 50 133 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn§§ttiiall RL = 2 kΩ 0°C 30 88 60 173 V/mV 70°C 20 57 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF 25°C 65 84 75 92 CMRR CCoommmmoonn-mmooddee VVIC = VVICRmmiinn, 0°C 65 84 75 92 dB rreejjeeccttiioonn rraattiioo VVOO == 00, RRSS == 5500 ΩΩ 70°C 65 84 75 93 25°C 75 99 75 99 kSVR SSrraauuttiippoopp ((ll∆∆yy-VVvvCCoollCCttaa±±gg//ee∆∆ VVrreeIIOOjjee))ccttiioonn VVVVOOCC ==± 00 =, ±±55 VV RRttooSS ±± ==11 5555 00VV ,ΩΩ 0°C 75 99 75 99 dB 70°C 75 99 75 99 25°C 8.1 11.2 8.4 11.2 SSuuppppllyy ccuurrrreenntt ICC VO = 0, No load 0°C 8.2 12.8 8.5 12.8 mA ((ffoouurr aammplliiffiieerrss)) 70°C 7.9 11.2 8.2 11.2 VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB †Full range is 0°C to 70°C. ‡Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. §For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V.B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL054C and TL054AC operating characteristics at specified free-air temperature TL054C, TL054C PARAMETER TEST CONDITIONS TA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX Positive slew rate 25°C 15.4 10 17.8 SSRR++ at unity gain 0°C 15.7 8 17.9 RLL = 2 kΩ, CLL = 100 pF, 70°C 14.4 8 17.5 VV//µµss Neggative slew rate at See Figure 1 and Note 7 25°C 13.9 10 15.9 SSRR– unity gain‡ 0°C 14.3 8 16.1 70°C 13.3 8 15.5 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 VI(PP) = ±10 mV, 25°C 55 57 nnss tf Fall time RRL = 22 kkΩΩ, 0°C 54 56 CCLL == 110000 pFF, 70°C 62 64 SSeeee FFiigguurreess 11 aanndd 22 25°C 24% 19% Overshoot factor 0°C 24% 19% % 70°C 24% 19 VVn Evoqqlutaivgael§ent input noise RS = 20 Ω, ff == 110 k HHzz 2255°°CC 7251 7251 45 nnVV//√√HHzz Peak-to-peak equivalent See Figure 3 f = 10 Hz to VN(PP) input noise voltage 10 kHz 25°C 4 4 µV Equivalent input In f = 1 kHz 25°C 0.01 0.01 pA/√Hz noise current THD Total harmonic RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003 0.003 % distortion¶ f = 1 kHz 25°C 2.7 2.7 B1 Unity-gain bandwidth VVI = 1100 mmVV, RRL = 22 kkΩΩ, 0°C 3 3 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 70°C 2.4 2.4 25°C 61 64 φm PPuunnhhiiaattyyss eegg aammiinnaarrggiinn aatt VVCCIILL == == 11 220055 mm pVVFF,, RSRSeeLLee == FF 22iigg kkuuΩΩrree, 44 0°C 60 64 deg 70°C 61 63 †Full range is 0°C to 70°C. ‡For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. §This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL054I and TL054AI electrical characteristics at specified free-air temperature TL054I, TL054AI PARAMETER TEST CONDITIONS TAA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX 25°C 0.64 5.5 0.56 4 TTLL005544II Full range 8.8 7.3 VVIIOO IInnpuutt ooffffsseett vvoollttaaggee mmVV 25°C 0.57 3.5 0.5 1.5 TTLL005544AAII Full range 6.8 4.8 VVOO == 00, 25°C to VIC = 0, TL054I 25 24 (cid:0)(cid:0) Temperature coefficient of RRSS = 5500 ΩΩ 85°C µµVV//°°CC VIO input offset voltage 25°C to TL054AI 25 23 85°C Input offset voltage 25°C 0.04 0.04 µV/mo long-term drift‡ VOO = 0, VIICC = 0, 25°C 4 100 5 100 pA IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt See Figure 5 85°C 0.06 10 0.07 10 nA VOO = 0, VIICC = 0, 25°C 20 200 30 200 pA IIIIBB IInnppuutt bbiiaass ccuurrrreenntt See Figure 5 85°C 0.6 20 0.7 20 nA –1 –2.3 –11 –12.3 25°C to to to to Common-mode input 4 5.6 11 15.6 VVIICCRR voltage range –1 –11 VV Full range to to 4 11 25°C 3 4.2 13 13.9 RRLL == 1100 kkΩΩ Maximum positive peak Full range 3 13 VVOOMM+ output voltage swing 25°C 2.5 3.8 11.5 12.7 VV RRLL == 22 kkΩΩ Full range 2.5 11.5 25°C –2.5 –3.5 –12 –13.2 RRLL == 1100 kkΩΩ Maximum neggative peak Full range –2.5 –12 VVOOMM– output voltage swing 25°C –2.3 –3.2 –11 –12 VV RRLL == 22 kkΩΩ Full range –2.3 –11 25°C 25 72 50 133 AVD LLvvooallrttgaaegg-ees iiaagmmnapllll iiddffiiiiccffffaaettriiooennn§§ttiiall RL = 2 kΩ –40°C 30 101 60 212 V/mV 85°C 20 50 30 70 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF 25°C 65 84 75 92 CMRR CCoommmmoonn-mmooddee VVIC = VVICRmmiinn, –40°C 65 83 75 92 dB rreejjeeccttiioonn rraattiioo VVOO == 00, RRSS == 5500 ΩΩ 85°C 65 84 75 93 25°C 75 99 75 99 kSVR SSrraauuttiippoopp ((ll∆∆yy-VVvvCCoollCCttaa±±gg//ee∆∆ VVrreeIIOOjjee))ccttiioonn VVVVCOOC ==± 00 =, ±±55 VVRR ttSSoo ±±==11 555500 VV ΩΩ, –40°C 75 98 75 99 dB 85°C 75 99 75 99 25°C 8.1 11.2 8.4 11.2 SSuuppppllyy ccuurrrreenntt ICC VO = 0, No load –40°C 7.9 12.8 8.2 12.8 mA ((ffoouurr aammplliiffiieerrss)) 85°C 7.6 11.2 7.9 11.2 VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB †Full range is –40°C to 85°C. ‡Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. §For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TL054I and TL054AI operating characteristics at specified free-air temperature TL054I, TL054AI PARAMETER TEST CONDITIONS TAA†† VCC± = ±5 V VCC± = ±15 V UNIT MIN TYP MAX MIN TYP MAX Positive slew rate 25°C 15.4 10 17.8 SSRR++ at unity gain –40°C 16.4 8 18 RLL = 2 kΩ, CLL = 100 pF, 85°C 14 8 17.3 VV//µµss Neggative slew rate at See Figure 1 25°C 13.9 10 15.9 SSRR– unity gain‡ –40°C 14.7 8 16.1 85°C 13 8 15.3 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 nnss VVII((PPPP)) = ±±1100 mmVV,, RRLL = 22 kkΩΩ,, 25°C 55 57 tf Fall time CL = 100 pF, –40°C 51 53 See Figures 1 and 2 85°C 64 65 25°C 24 19 Overshoot factor –40°C 24 19 % 85°C 24 19 VVn Evoqqlutaivgael§ent input noise RS = 20 Ω, ff == 110 k HHzz 2255°°CC 7251 7251 45 nnVV//√√HHzz Peak-to-peak equivalent See Figure 3 f = 10 Hz to VN(PP) input noise voltage 10 kHz 25°C 4 4 µV Equivalent input In f = 1 kHz 25°C 0.01 0.01 pA/√Hz noise current THD Total harmonic distortion¶ RS = 1 kΩ, RL = 2 kΩ, 25°C 0.003% 0.003% % f = 1 kHz 25°C 2.7 2.7 B1 Unity-gain bandwidth VVI = 1100 mmVV, RRL = 22 kkΩΩ, –40°C 3.3 3.3 MHz CCLL == 2255 pFF, SSeeee FFiigguurree 44 85°C 2.3 2.4 25°C 61 64 φm PPuunnhhiiaattyyss eegg aammiinnaarrggiinn aatt VVCCIILL == == 11 220055 mm pVVFF,, RSRSeeLLee == FF 22iigg kkuuΩΩrree, 44 –40°C 59 62 deg 85°C 61 64 †Full range is –40°C to 85°C. ‡For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. §This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION VCC+ Overshoot – VO VI + 90% VCC– CL RL (see Note A) 10% NOTE A: CL includes fixture capacitance. tr Figure 1. Slew Rate, Rise/Fall Time, Figure 2. Rise-Time and Overshoot and Overshoot Test Circuit Waveform 2 kΩ 10 kΩ VCC+ VCC+ – VI – + VO 100 Ω + VO VCC– VCC– RS RS CL RL (see Note A) NOTE A: CL includes fixture capacitance. Figure 4. Unity-Gain Bandwidth and Figure 3. Noise-Voltage Test Circuit Phase-Margin Test Circuit typical values VCC+ Ground Shield Typical values, as presented in this data sheet – represent the median (50% point) of device + parametric performance. VCC– pA pA input bias and offset current At the picoamp-bias-current level typical of the TL05x and TL05xA, accurate measurement of the Figure 5. Input-Bias and Offset-Current Test Circuit bias current becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied, but with no device in the socket. The device then is inserted in the socket, and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements then are subtracted algebraically to determine the bias current of the device. noise Because of the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density is sample tested at f = 1 kHz. Texas Instruments also has additional noise-testing capability to meet specific application requirements. Please contact the factory for details. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6–11 (cid:0) Temperature coefficient of input offset voltage Distribution 12, 13, 14 V IO vs Common-mode input voltage 15 IIB Input bias current vs Free-air temperature 16 IIO Input offset current vs Free-air temperature 16 vs Supply voltage 17 VIC Common-mode input voltage range limits vs Free-air temperature 18 VO Output voltage vs Differential input voltage 19, 20 vs Supply voltage 21 VOM Maximum peak output voltage vs Output current 25, 26 vs Free-air temperature 27, 28 VO(PP) Maximum peak-to-peak output voltage vs Frequency 22, 23, 24 vs Load resistance 29 AVD Large-signal differential voltage amplification vs Frequency 30 vs Free-air temperature 31, 32, 33 vs Frequency 34, 35 CMRR Common-mode rejection ratio vs Free-air temperature 36 zo Output impedance vs Frequency 37 kSVR Supply-voltage rejection ratio vs Free-air temperature 38 vs Supply voltage 39 IOS Short-circuit output current vs Time 40 vs Free-air temperature 41 vs Supply voltage 42, 43, 44 ICC Supply current vs Free-air temperature 45, 46, 47 vs Load resistance 48–53 SR Slew rate vs Free-air temperature 54–59 Overshoot factor vs Load capacitance 60 Vn Equivalent input noise voltage vs Frequency 61, 62 THD Total harmonic distortion vs Frequency 63 vs Supply voltage 64, 65, 66 B1 Unity-gain bandwidth vs Free-air temperature 67, 68, 69 vs Supply voltage 70, 71, 72 φm Phase margin vs Load capacitance 73, 74, 75 vs Free-air temperature 76, 77, 78 Phase shift vs Frequency 30 Voltage-follower small-signal pulse response vs Time 79 Voltage-follower large-signal pulse response vs Time 80 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS DISTRIBUTION OF TL051 DISTRIBUTION OF TL051A INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 16 20 ÎÎÎÎÎÎÎÎÎÎ 433 Units Tested From 1 Wafer Lot 393 Units Tested From 1 Wafer Lot VCC± = ±15 V ÎVÎCC±Î = ±1Î5 VÎÎÎÎÎÎ TA = 25°C 16 ÎTPAÎ P =a c2Îk5a°gCeÎÎÎÎÎÎÎ 12 P Package % % – – s s nit nit 12 U U of 8 of e e g g a a nt nt 8 e e c c r r e e P P 4 4 0 0 –1.5 –1.1 –0.9–0.6–0.3 0 0.3 0.6 0.9 1.1 1.5 –900 –600 –300 0 300 600 900 VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – µV Figure 6 Figure 7 DISTRIBUTION OF TL052 DISTRIBUTION OF TL052A INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 15 20 476 Amplifiers Tested From 1 Wafer Lot 403 Amplifiers Tested From 1 Wafer Lot VCC± = ±15 V VCC± = ±15 V TA = 25°C TA = 25°C 12 – % P Package – % 15 P Package s s er er plifi 9 plifi m m of A of A 10 e e g 6 g a a nt nt e e c c er er 5 P P 3 0 0 –1.5 –1.2 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 1.2 1.5 –900 –600 –300 0 300 600 900 VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – µV Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS DISTRIBUTION OF TL054 DISTRIBUTION OF TL054A INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE 30 15 1140 Amplifiers Tested From 3 Wafer Lots 1048 Amplifiers Tested From 3 Wafer Lots VCC± = ±15 V VCC± = ±15 V % 25 TA = 25°C % 12 TNA P =a c2k5a°gCe – N Package – s s r 20 r e e plifi plifi 9 m m of A 15 of A e e g g 6 a a nt 10 nt e e c c r r e e P P 3 5 0 0 –4 –3 –2 –1 0 1 2 3 4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8 VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – mV Figure 10 Figure 11 DISTRIBUTION OF TL051 DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT ÎÎÎÎÎÎÎÎÎÎÎ 20 20 172 Amplifiers Tested From 2 Wafer Lots Î120Î UnÎits TÎesteÎd FrÎom Î2 WaÎfer ÎLotsÎ ÎVCÎC± =Î ±15Î V ÎÎÎÎÎÎÎ VCC± = ±15 V TA = 25°C to 125°C 16 TA = 25°C to 125°C P Package % P Package – % 1Î5 ÎOuÎtlier:Î OnÎe UnÎit atÎ –34Î.6 µVÎ/°CÎ – s s er Unit 12 plifi of Am ge of 10 nta 8 ge e a erc ent P c r e 5 4 P 0 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 –30 –20 –10 0 10 20 30 (cid:0) – Temperature Coefficient – µV/°C (cid:0) – Temperature Coefficient – µV/°C V V IO IO Figure 12 Figure 13 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS DISTRIBUTION OF TL054 INPUT BIAS CURRENT INPUT OFFSET VOLTAGE vs TEMPERATURE COEFFICIENT COMMON-MODE INPUT VOLTAGE ÎÎÎÎÎÎÎÎÎÎÎÎ 50 10 324 Amplifiers Tested From 3 Wafer Lots ÎÎÎÎÎÎÎÎVCÎC± Î= ±1Î5 VÎ VCC± = ±15 V TA = 25°C to 125°C TA = 25°C % 40 N Package A – n 5 s – er nt mplifi 30 Curre age of A 20 ut Bias 0 nt np ce – I er B –5 P I 10 I 0 –10 –60 –40 –20 0 20 40 60 –15 –10 –5 0 5 10 15 (cid:0)V – Temperature Coefficient – µV/°C VIC – Common-Mode Input Voltage – V IO Figure 14 Figure 15 INPUT BIAS CURRENT AND COMMON-MODE INPUT OFFSET CURRENT† INPUT VOLTAGE RANGE LIMITS vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE A 100 16 Currents – n 10 VVVCIOCC ==± 0 0= ±15 V age – V 128 TA = 25°C et olt ÎPoÎsitivÎe LiÎmitÎ d Offs 1 IIB put V 4 n n s a de I 0 Bia IIO Mo ÎNeÎgatiÎve LÎimitÎ nput 0.1 mon- –4 – I om –8 O C II 0.01 – d C an VI –12 B I I 0.001 –16 25 45 65 85 105 125 0 2 4 6 8 10 12 14 16 TA – Free-Air Temperature – °C |VCC±| – Supply Voltage – V Figure 16 Figure 17 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE RANGE LIMITS† OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE FREE-AIR TEMPERATURE 20 5 ÎÎVCÎÎC±ÎÎ = ±1ÎÎ5 VÎÎÎÎÎÎÎ 4ÎÎÎTVÎÎÎAC C=ÎÎα 2 =5° ±CÎÎÎ5 VÎ 15 V – ÎPoÎsitivÎe LiÎmitÎ 3 e g 10 Volta – V 2 ut 5 ge 1 p a ode In 0 ut Volt 0ÎÎÎÎ on-M –5 Outp –1ÎÎRRÎÎLL ==ÎÎ 610 k0ΩÎÎ Ω m ÎÎÎÎÎ – –2ÎÎÎÎ m O o –10 ÎNeÎgativÎe LÎimitÎ V ÎÎÎÎÎ – C –3 RL = 2 kΩ VIC –15 –4 ÎÎÎÎRL =ÎÎ 10 ÎÎkΩ ÎÎ –5 –20 –75 –50 –25 0 25 50 75 100 125 –200 –100 0 100 200 TA – Free-Air Temperature – °C VID – Differential Input Voltage – µV Figure 18 Figure 19 OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE vs vs DIFFERENTIAL INPUT VOLTAGE SUPPLY VOLTAGE 15 ÎÎÎÎÎ 16 10 ÎÎVTAC CÎÎ=± 2 =5Îΰ ±C15ÎÎ V Î – V 12 TA = 25°C VOM+ e RL = 10 kΩ g a ge – V 5 put Volt 48 RL = 2 kΩ put Volta 0 ÁÁÁÁ Peak Out 0 Out –5 ÁÎÎRL ÁÎÎ= 60ÁÎÎ0 ΩÁÎÎ um –4 V– O ÁÎÎRRLL ÁÎÎ== 12 kkÁÎÎΩΩ ÁÎÎ Maxim –8 RL = 2 kΩ –10 ÁÎRL ÁÎ= 10ÁÎ kΩÁÎ – RL = 10 kΩ M O –12 V VOM– –15 –16 –400 –200 0 200 400 0 2 4 6 8 10 12 14 16 VID – Differential Input Voltage – µV |VCC±| – Supply Voltage – V Figure 20 Figure 21 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE† vs vs FREQUENCY FREQUENCY V 30 ÁÁÁÁ oltage – V 2350 VCC± = ±15 V RL = 2 kΩ Voltage – 25 ÁÁVCÁÁC± =ÁÁ ±15ÁÁ V ÁÁ ÁÁTRAÁÁL == 22ÁÁ5 k°ΩCÁÁ ut V put utp Out 20 k O 20 ak a e e P k-to-P 15 ak-to- 15 ximum Pea 10 VCTCA± = = 1 ±255 °VC TA = –55°C aximum Pe 10 ÁÁVÁÁCCÁÁ± = ±ÁÁ5 VÁÁ a M – MP) 5 – PP) 5 O(P VO( 0 V 0 10 k 100 k 1 M 10 M 10 k 100 k 1 M 10 M f – Frequency – Hz f – Frequency – Hz Figure 22 Figure 23 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE vs vs FREQUENCY OUTPUT CURREÁNTÁÁÁÁ V 30 Output Voltage – 2205 ÁÁVCCÁÁ± =ÁÁ ±15ÁÁ V ÁÁÁÁRTALÁÁ == 1205ÁÁ °kCΩÁÁ ut Voltage – V 45 ÁÁÁTVRAÁÁÁCL C== ± 21ÁÁÁ 5=0° ±Ck5ΩÁÁÁ V ÁÁÁ k p ea ut 3 P O ÁÁÁ Peak-to- 15 m Peak 2 ÁÁÁÁVÁOMÁ+ m 10 mu VOM– mu ÁÁÁÁÁ axi ÁÁÁ Maxi ÁÁVCCÁ±= Á±5 VÁ – M 1 – 5 |OM P) V P | O( 0 V 0 10 k 100 k 1 M 10 M 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – Hz |IO| – Output Current – mA Figure 24 Figure 25 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS MAXIMUM PEAK OUTPUT VOLTAGE† MAXIMUM PEAK OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE OUTPUT CURRENT ÁÁÁÁÁ 16 5 ÁVCÁC± Á= ±1Á5 VÁ VOM+ RL = 10 kΩ Output Voltage – V 111024 ÁÁÁÁÁÁÁVOMÁÁ+ ÁÁÁÁTRALÁÁ == 21ÁÁ50° kCΩÁÁÁÁ Output Voltage – V 1234 RL = 2 kΩ VCC±= ±5 V k 8 k 0 ea ÁVÁOM–Á ea P P m 6 m –1 ÁÁÁ u u m m xi xi –2 ÁÁVOMÁ– Ma 4 Ma RL = 2 kΩ – – –3 |M M O 2 O –4 |V V RL = 10 kΩ 0 –5 0 5 10 15 20 25 30 35 40 45 50 –75 –50 –25 0 25 50 75 100 125 |IO| – Output Current – mA TA – Free-Air Temperature – °C Figure 26 Figure 27 LARGE-SIGNAL DIFFERENTIAL VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE† AMPLIFICATION vs vs FREE-AIR TEMPERATURE LOAD RESISTANCE 16 RL = 10 kΩ V 250 VO = ±1 V oltage – V 182 ÁÁVÁÁOMÁÁ+ RL = 2 kΩ ation – V/m 200 TA = 25°C VCC± = ±15 V V c Output 4 VCC± = ±15 V Amplifi 150 m Peak 0 Voltage 100 VCC± = ±5 V – MaximuM ––84 ÁÁVÁÁOM–ÁÁ RL = 2 kΩ Differential 50 O –12 – V D RL = 10 kΩ AV –16 0 –75 –50 –25 0 25 50 75 100 125 0.4 1 4 10 40 100 TA – Free-Air Temperature – °C RL – Load Resistance – kΩ Figure 28 Figure 29 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 106 mV VCC± = ±15 V V/ 105 RL = 2 kΩ 0° n – CL = 25 pF atio 104 TA = 25°C 30° c plifi AVD hift Am 103 60° e S oltage 102 90° – Phas V Phase Shift al m enti 101 120°φ r e – Diff 1 150° D V A 0.1 180° 10 100 1 k 10 k 100 k 1 M 10 M f – Frequency – Hz Figure 30 TL054 TL051 AND TL052 LARGE-SIGNAL DIFFERENTIAL LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION† VOLTAGE AMPLIFICATION† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 1000 1000 mV VCC± = ±5 V mV VCC± = ±5 V n – V/ 400 VO = ±2.3 V n – V/ 400 VO = ±2.3 V o o ati ati c c plifi plifi RL = 10 kΩ Am RL = 10 kΩ Am e 100 e 100 g g a a Volt Volt RL = 2 kΩ al RL = 2 kΩ al nti 40 nti 40 e e er er Diff Diff – – D D V V A 10 A 10 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 31 Figure 32 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION† COMMON-MODE REJECTION RATIO vs vs FREE-AIR TEMPERATURE FREQUENCY 1000 100 ÁÁÁÁÁ V VCC± = ±15 V B VCC± = ±5 V n – V/m 400 RL = 10 kΩ ÁVÁO =Á 10 ÁV Á atio – d 8900 TA = 25°C o R cati on 70 mplifi ejecti 60 A R Voltage 100 RL = 2 kΩ n-Mode 4500 al mo nti 40 m 30 e o r C Diffe R – 20 – VD CMR 10 A 10 0 –75 –50 –25 0 25 50 75 100 125 10 100 1 k 10 k 100 k 1 M 10 M TA – Free-Air Temperature – °C f – Frequency – Hz Figure 33 Figure 34 COMMON-MODE REJECTION RATIO COMMON-MODE REJECTION RATIO† vs vs FREQUENCY FREE-AIR TEMPERATURE 100 100 atio – dB 9800 VTAC C=± 2 =5° ±C15 V Ratio – dB 95 VCC± = ±15 V VIC = VICRMin ction R 70 ection 90 eje 60 Rej de R 50 ode 85 o M n-M 40 on- VCC± = ±5 V o m m m 80 m 30 o o C R – C 20 RR – 75 R M M 10 C C 0 70 10 100 1 k 10 k 100 k 1 M 10 M –75 –50 –25 0 25 50 75 100 125 f – Frequency – Hz TA – Free-Air Temperature – °C Figure 35 Figure 36 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE SUPPLY-VOLTAGE REJECTION RATIO† vs vs FREQUENCY FREE-AIR TEMPERATURE 100 110 B VCC± = ±5 V to ±15 V d 40 AVD = 100 – o 106 ati R Ω n ce – 10 ctio dan AVD = 10 Reje 102 pe 4 e m g put I Volta 98 ut 1 y- O pl – AVD = 1 up zo 0.4 VCC±= ±15 V ÁR – SÁR 94 TA = 25°C ÁVÁV SS ro (open loop) ≈ 250 Ω ÁkkÁ 0.1 90 1 k 10 k 100 k 1 M –75 –50 –25 0 25 50 75 100 125 f – Frequency – Hz TA – Free-Air Temperature – °C Figure 37 Figure 38 SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT vs vs SUPPLY VOLTAGE TIME 60 60 VO = 0 VID = 100 mV A TA = 25°C mA ent – m 40 VID = 100 mV rent – 40 urr 20 Cur 20 ut C put uit Outp 0 cuit Out –20 c r rt-Cir –20 ort-Ci –40 o h ÁOS – ShOSÁ–40 VID = –100 mV ÁÁIOS – SIOSÁÁ–60 VID = –100 mV VCC± = ±15 V ÁIIÁ ÁÁ TA = 25°C –60 0 0 2 4 6 8 10 12 14 16 0 10 20 30 40 50 60 |VCC±| – Supply Voltage – V t – Time – s Figure 39 Figure 40 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL051 SHORT-CIRCUIT OUTPUT CURRENT† SUPPLY CURRENT† vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 60 3 VCC± = ±15 V A m – 40 ÎÎÎÎÎ 2.5 Current 20 ÎVÎID =Î 100Î m VÎ VCC± = ±5 V – mA 2 TTAA == –2555°C°C ut nt TA = 125°C utp urre O 0 C 1.5 rcuit VCC± = ±5 V pply – Short-Ci –20 ÎVÎID =Î –10Î0 mÎ V Î VCC± = ±15 V ÁÁICC – SuICCÁÁ 1 ÁS SÁ–40 ÁÁ0.5 ÁIOIOÁ VO = 0 VO = 0 No Load –60 0 –75 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA – Free-Air Temperature – °C |VCC±| – Supply Voltage – V Figure 41 Figure 42 TL052 TL054 SUPPLY CURRENT† SUPPLY CURRENT† vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 5 10 4 8 A TA = 25°C m A Current – 3 TTAA == 1–2555°°CC urrent – m 6 TÎÎA T=A ÎÎ1T =2A 5– °=ÎÎ5C 52°5CÎΰC ÎÎ y C pl y up 2 ppl 4 ÁSÁ u – S C C – ÁCÁC ÁC CÁ II CC ÁÁ 1 ÁIIÁ 2 VO = 0 VO = 0 No Load No Load 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 |VCC±| – Supply Voltage – V |VCC±| – Supply Voltage – V Figure 43 Figure 44 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL052 TL051 SUPPLY CURRENT† SUPPLY CURRENT† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 5 3 2.5 4 nt – mA 2 VVCCCC±± == ±±51 5V V ent – mA 3 VVCCCC±± == ±±155 V V e rr r u ur C C 1.5 y y pl ppl up 2 u ÁSÁ ÁC – SCÁ 1 ÁCC – CCÁ CC II ÁIIÁ ÁÁ1 0.5 VO = 0 VO = 0 No Load No Load 0 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 45 Figure 46 TL054 TL051 SUPPLY CURRENT† SLEW RATE vs vs FREE-AIR TEMPERATURE LOAD RESISTANCE 10 25 ÎÎÎÎÎÎ VCC± = ±15 V SR+ ÎÎÎÎÎÎ 8 ÎÎÎÎÎÎ 20 A VCC± = ±5 V m ÎÎÎÎÎÎ – µs SR– ent 6 – V/ 15 rr e upply Cu 4 Slew Rat 10 S – Á– Á R C C S ÁICICÁ 2 5 VCC± = ±5 V CL = 100 pF ÁÁ VO = 0 TA = 25°C No Load See Figure 1 0 0 –75 –50 –25 0 25 50 75 100 125 0.4 1 4 10 40 100 TA – Free-Air Temperature – °C RL – Load Resistance – kΩ Figure 47 Figure 48 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL052 TL054 SLEW RATE SLEW RATE vs vs LOAD RESISTANCE LOAD RESISTANCE 25 25 SR+ ÎÎ 20 20 SR+ s s µ µ– V/ 15 SR– e – V/ 15 SR– ate Rat R w ew 10 Sle 10 Sl – – R R S S 5 CVCL C=± 1 =0 0± 5p FV 5 CVCL C=± 1 =0 0± 5p FV TA = 25°C TA = 25°C See Figure 1 See Figure 1 0 0 0.4 1 4 10 40 100 0.4 1 4 10 40 100 RL – Load Resistance – kΩ RL – Load Resistance – kΩ Figure 49 Figure 50 TL052 TL051 SLEW RATE SLEW RATE vs vs LOAD RESISTANCE LOAD RESISTANCE 30 25 SR+ SR+ 25 20 SR– SR– µs 20 s Rate – V/ 15 µate – V/ 15 SR – Slew 10 VCC± = ±15 V SR – Slew R 10 VCC± = ±15 V 5 CTAL == 2150°0C pF 5 CTAL == 2150°0C pF See Figure 1 See Figure 1 0 0 0.4 1 4 10 40 100 0.4 1 4 10 40 100 RL – Load Resistance – kΩ RL – Load Resistance – kΩ Figure 51 Figure 52 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL054 TL051 SLEW RATE SLEW RATE† vs vs LOAD RESISTANCE FREE-AIR TEMPERATURE 25 30 SR+ 25 20 SR+ µs SR– µs 20 V/ V/ – 15 – e e at at 15 SR– R R w w Sle 10 Sle R – R – 10 S VCC± = ±5 V S VCC± = ±5 V 5 CTAL == 2150°0C pF 5 RL = 2 kΩ See Figure 1 0 0 0.4 1 4 10 40 100 –75 –50 –25 0 25 50 75 100 125 RL – Load Resistance – kΩ TA – Free-Air Temperature – °C Figure 53 Figure 54 TL052 TL054 SLEW RATE† SLEW RATE† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 25 20 SR+ 20 SR+ 15 s s µ µ SR– V/ V/ – 15 – e SR– e at at R R 10 w w Sle 10 Sle – – R R S VCC± = ±5 V S 5 VCC± = ±5 V 5 RL = 2 kΩ RL = 2 kΩ CL = 100 pF CL = 100 pF See Figure 1 See Figure 1 0 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 55 Figure 56 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL051 TL052 SLEW RATE† SLEW RATE† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 30 25 SR+ SR+ 25 20 s s µV/ 20 µV/ SR– – SR– – 15 e e Rat 15 Rat w w e e Sl Sl 10 – 10 – R R S S VCC± = ±15 V VCC± = ±15 V 5 RL = 2 kΩ 5 RL = 2 kΩ CL = 100 pF CL = 100 pF See Figure 1 See Figure 1 0 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 57 Figure 58 TL054 SLEW RATE† OVERSHOOT FACTOR vs vs FREE-AIR TEMPERATURE LOAD CAPACITANCE 20 50 SR+ SR– 40 15 ÎÎÎÎ % µs – ÎVCCα =Î ±5 VÎ V/ r e – acto 30 w Rat 10 oot F ÎÎVCCα = α15 ÎV e h 20 Sl rs SR – Ove ÎÎÎVIÎÎÎ(PP)ÎÎÎ = ±1ÎÎÎ0 mÎÎÎV 5 VCC± = ±15 V 10 RL = 2 kΩ RL = 2 kΩ ÎÎTAÎÎ = 2ÎÎ5°CÎÎÎÎ See Figure 1 CL = 100 pF ÎÎÎÎÎ See Figure 1 0 0 –75 –50 –25 0 25 50 75 100 125 0 50 100 150 200 250 300 TA – Free-Air Temperature – °C CL – Load Capacitance – pF Figure 59 Figure 60 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL052 AND TL054 TL051 EQUIVALENT INPUT NOISE VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE vs vs FREQUENCY FREQUENCY 100 ÁÁÁÁÁ 100 z Hz VCC± = ±15 V H ÁÁVCÁC± =Á ±15Á V e – nV/ 70 TRSAeSe == F 22ig50°u CΩre 3 ge – nV/ 70 ÁÁÁÁRTSAeSe ÁÁ == F 22ig50ÁÁ°u CΩre ÁÁ3 g a 50 e Volta 4500 se Volt 40 ut Nois 30 put Noi 30 p n nt In ent I 20 ale 20 val uiv qui q E n – E Vn – V 10 10 10 100 1 k 10 k 100 k 10 100 1 k 10 k 100 k f – Frequency – Hz f – Frequency – Hz Figure 61 Figure 62 TL051 TOTAL HARMONIC DISTORTION UNITY-GAIN BANDWIDTH vs vs FREQUENCY SUPPLY VOLTAGE 1 3.2 VCC± = ±15 V % 0.4 AVD = 1 n – VTAO (=R 2M5S°C) = 6 V Hz 3.1 o M rti – nic Disto 00.0.14 ndwidth 3 o a m B – Total Har 0.01 Unity-Gain 2.9 VRIL = = 1 20 kmΩV HD 0.004 – 1 2.8 CL = 25 pF T B TA = 25°C See Figure 4 0.001 100 1 k 10 k 100 k 2.7 0 2 4 6 8 10 12 14 16 f – Frequency – Hz |VCC±| – Supply Voltage – V Figure 63 Figure 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL052 TL054 UNITY-GAIN BANDWIDTH UNITY-GAIN BANDWIDTH vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 3.2 2.9 z 3.1 z 2.8 H H M M – – h h dt dt wi 3 wi 2.7 d d n n a a B B n n ai 2.9 ÁÁÁÁ ai 2.6 ÁÎÁÎÁÎÁÎÁ G G y- ÁVIÁ = 10Á mVÁ y- ÁÎÎVÁÎÎI = 1ÁÎÎ0 mÁÎÎV ÁÎ Unit ÁRLÁ = 2Á kΩÁ Unit ÁÎÎÎRÁÎÎÎL =ÁÎÎÎ 2 kΩÁÎÎÎÁÎÎÎÎ – 2.8 CL = 25 pF – 2.5 CL = 25 pF B1 ÁTAÁ = 2Á5°CÁ B1 ÁÎÎTÁÎÎA = ÁÎÎ25°CÁÎÎÁÎÎÎÎ See Figure 4 See Figure 4 ÁÁÁÁ ÁÎÁÎÁÎÁÎÁÎÎÎ 2.7 2.4 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 |VCC±| – Supply Voltage – V |VCC±| – Supply Voltage – V Figure 65 Figure 66 TL051 TL052 UNITY-GAIN BANDWIDTH† UNITY-GAIN BANDWIDTH† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 4 4 VCC± = ±15 V z z H H M M 3 3 – – h h widt VCC± = ±5 V widt d d n n a a B 2 B 2 n n ai ai G G y- y- VCC± = ±5 V to ±15 V nit nit VI = 10 mV – U1 1 VRIL = = 1 20 kmΩV – U1 1 RCLL == 225 k pΩF B CL = 25 pF B TA = 25°C See Figure 4 See Figure 4 0 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 67 Figure 68 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL051 TL054 UNITY-GAIN BANDWIDTH† PHASE MARGIN vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 4 65° Hz 63° M 3 – h dt wi gin 61° d r n a a M n B 2 se y-Gai VCC± = ±5 V to ±15 V – Pha 59° – Unit1 1 RCVILL = == 1 2205 km pΩVF φm 57° VRIL = = 1 20 kmΩV B STAee = F 2ig5°uCre 4 TCAL == 2255° pCF See Figure 4 0 55° –75 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TA – Free-Air Temperature – °C |VCC±| – Supply Voltage – V Figure 69 Figure 70 TL052 TL054 PHASE MARGIN PHASE MARGIN vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 65° 65° 63° 63° n n rgi 61° rgi 61° a a M M e e s s a a h h P 59° P 59° – – ÁÁÁÁÁ m m φ φ VI = 10 mV ÁVÁI = 1Á0 mÁV Á 57° RL = 2 kΩ 57° ÁRÁL = Á2 kΩÁÁ CL = 25 pF CL = 25 pF TA = 25°C ÁTÁA = Á25°CÁÁ See Figure 4 See Figure 4 ÁÁÁÁÁ 55° 55° 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 |VCC±| – Supply Voltage – V |VCC±| – Supply Voltage – V Figure 71 Figure 72 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL051 TL052 PHASE MARGIN† PHASE MARGIN† vs vs LOAD CAPACITANCE LOAD CAPACITANCE 70° 70° VI = 10 mV VI = 10 mV RL = 2 kΩ RL = 2 kΩ 65° TA = 25°C TA = 25°C See Figure 4 65° See Figure 4 60° n gin VCC± = ±15 V rgi 60° ÎÎVCCα = α15 ÎV r a a See Note A M See Note A e M 55° se s a a h ÎÎÎÎÎ – Phm 50° VCC± = ±5 V – Pm 55° ÎVÎCC±Î = ±5Î V Î φ φ 50° 45° 40° 45° 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 CL – Load Capacitance – pF CL – Load Capacitance – pF Figure 73 Figure 74 TL054 PHASE MARGIN† vs LOAD CAPACITANCE 70° VI = 10 mV RL = 2 kΩ TA = 25°C 65° See Figure 4 n ÎÎÎÎÎ argi 60° ÎVCCα =Î ±15Î V Î M See Note A e s a h – P 55° ÎVÎCCα = ±Î5 VÎ m φ 50° 45° 0 10 20 30 40 50 60 70 80 90 100 CL – Load Capacitance – pF Figure 75 †Values of phase margin below a load capacitance of 25 pF were estimated. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS TL051 TL052 PHASE MARGIN† PHASE MARGIN† vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 65Á° ÁÁÁÁ 65° ÁÁÁÁÁ ÁÁVRIL = Á= 1 20 kÁmΩVÁ ÁÁVRIL = =Á 1 20 kmÁΩV Á 63Á° ÁSCeLe Á= F 2ig5Áu prFe Á4 63° ÁÁCL =Á 25 ÁpF Á ÁÁÁÁÁ VCC± = ±15 V ÁÁSeeÁ FiguÁre 4Á VCC± = ±15 V n gin 61° rgi 61° r a a M se M VCC± = ±5 V ase a h – Phm 59° – Pm 59° VCC± = ±5 V φ φ 57° 57° 55° 55° –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 76 Figure 77 TL054 PHASE MARGIN† vs FREE-AIR TEMPERATURE 65° 63° VCC± = ±15 V n rgi 61° a M e s a h P 59° – m VCC± = ±5 V ÁÁÁÁÁ φ 57° ÁÁVRÁÁIL = = 1 ÁÁ20 kmΩÁÁV ÁÁ CL = 25 pF ÁSÁee FÁigurÁe 4Á 55° –75 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C Figure 78 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER SMALL-SIGNAL LARGE-SIGNAL PULSE RESPONSE PULSE RESPONSE 16 8 12 6 V 8 4 m V ÁÁÁÁÁ Output Voltage – –044 ÁÁÁÁTVSRCACeLLÁÁÁÁe C=== F± 212 iÁÁÁÁ=g50 k° u0±ΩC r1peÁÁÁÁ5F 1 VÁÁÁÁ Output Voltage – –022 ÁÁÁÁTVRCSÁÁÁÁACeLLe C=== F± ÁÁÁÁ212 i=g50 k° u0±ΩC rÁÁÁÁ1pe5F 1 VÁÁÁÁ – – O O V –8 V –4 –12 –6 –16 –8 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 t – Time – µs t – Time – µs Figure 79 Figure 80 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION output characteristics All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance. The TL05x and TL05xA drive higher capacitive loads; however, as the load capacitance increases, the resulting response pole occurs at lower frequencies, causing ringing, peaking, or even oscillation. The value of the load capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the problem. Capacitive loads of 1000 pF, and larger, may be driven if enough resistance is added in series with the output (see Figure 81 and Figure 82). (a) CL = 100 pF, R = 0 (b) CL = 300 pF, R = 0 (c) CL = 350 pF, R = 0 (d) CL = 1000 pF, R = 0 (e) CL = 1000 pF, R = 50 Ω (f) CL = 1000 pF, R = 2 kΩ Figure 81. Effect of Capacitive Loads 15 V – R VO 5 V + –5 V –15 V CL 2 kΩ (see Note A) NOTE A: CL includes fixture capacitance. Figure 82. Test Circuit for Output Characteristics POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION input characteristics The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets easily can exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 83). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input. Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation. VI + VO – VI – – VO + VO VI + (a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER Figure 83. Use of Guard Rings noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input-bias current requirements of the TL05x and TL05xA result in a very low current noise. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ. 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION phase meter The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two input signals V and V . The reference signal V must be the same frequency as V . The TLC3702 comparators A B A B (U1) convert these two input sine waves into ±5-V square waves. Then, R1 and R4 provide level shifting prior to the SN74HC109 dual J-K flip flops. Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of V . B Flip-flop U2A also produces a square wave at one-half the input frequency. The pulse duration of U2A varies from zero to one-half the period, where zero corresponds to zero phase delay between V and V and one-half A B the period corresponds to V lagging V by 360 degrees. B A The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1 and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the 0- to 2.5-V integrator output to a 0- to 3.6-V output range. R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz frequency range. +5 V R2 C2 100 kΩ +5 V 0.016 µF S R6 R7 VA U1A R1 1JC1U2A U3 10 kΩ 10 kΩ +U4A + 100 kΩ 1RK NC 10 kRΩ5 0.016 CµF1 – –U4B VO R9 20 kΩ R3 100 kΩ S NC R8 2J U2B 50 kΩ C1 Gain +5 V 2K R4 100 kΩ R R10 10 kΩ VB Zero U1B –5 V NOTE A: U1 = TLC3702; VCC± = ±5 V U2 = SN74HC109 U3 = TLC4066 U4, U5 = TL05x; VCC± = ±5 V Figure 84. Phase Meter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION precision constant-current source over temperature A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R; therefore, the current to the load simply is 2.5 V divided by R. Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator’s cathode connects to the operational amplifier output, this circuit sources load current. Similarly, if the cathode connects to the inverting input, the circuit sinks current from the load. To minimize output current change with temperature, R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with split-voltage supplies. 150 pF 150 pF U2 U2 +15 V +15 V 100 kΩ 100 kΩ – – U1 U1 + + IO –15 V II –15 V Load R Load V = 0 to 10 V V = 0 to –10 V R (a) SOURCE CURRENT LOAD (b) SINK CURRENT LOAD NOTE A: U1 = 1/2 TL05x U2 = LM385, LT1004, or LT1009 voltage reference 2.5 V I = , R = Low-temperature-coefficient metal-film resistor R Figure 85. Precision Constant-Current Source 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION instrumentation amplifier with adjustable gain/null The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 kΩ, the circuit gain equals 100, while with R1 = 200 kΩ, the circuit gain equals two. The following equation shows the instrumentation amplifier gain as a function of R1: AV(cid:1)1(cid:0)(cid:4)R2R(cid:0)1R3(cid:5) Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5, R6, and R7 controls the CMRR of this application. The following equation shows the output voltages when the input voltage equals zero. This dc error can be nulled by adjusting the offset null potentiometer; however, any change in offset voltage over time or temperature also creates an error. To calculate the error from changes in offset, consider the three offset components in the equation as delta offsets, rather than initial offsets. The improved stability of Texas Instruments enhanced JFETs minimizes the error resulting from change in input offset voltage with time. Assuming V equals zero, V can I O be shown as a function of the offset voltage: VO(cid:1)VIO2(cid:2)(cid:4)1(cid:0)RR31(cid:5) (cid:4)R5R(cid:0)7R7(cid:5) (cid:4)1(cid:0)RR64(cid:5)(cid:0)RR21(cid:4)RR64(cid:5)(cid:3) –VIO1(cid:2)RR31 (cid:4)R5R(cid:0)7R7(cid:5) (cid:4)1(cid:0)RR64(cid:5)(cid:0)RR64(cid:4)1(cid:0)RR21(cid:5)(cid:3)(cid:0)VIO3(cid:4)1(cid:0)RR64(cid:5) VI– + R4 R6 U1A – 10 kΩ 10 kΩ 100 kΩ R2 1200 0tu krΩn 10 MΩ –U2A VO + AV = 2 to 100 10 MΩ 2 kΩ R1 VCC+ R3 100 kΩ 82 kΩ – – R5 R7 U1B U2B Offset Null VI+ + 10 kΩ 10 kΩ + 1 kΩ 0.1 µF 82 kΩ NOTE A: U1 and U2 = TL05xA; VCC± = ±15 V. VCC– Figure 86. Instrumentation Amplifier POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION high input impedance log amplifier The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low temperature coefficient. In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-µA temperature-stable current source that sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and Q2 (see Figure 88). The output voltage is given by the following equation: VO(cid:2)–(cid:3)1(cid:1)RR65(cid:4) kqT(cid:7)(cid:8)(cid:9)In(cid:5)R1 (cid:0)1V(cid:0)I 10–6(cid:6)(cid:10)(cid:11)(cid:7)wanhdereTkis(cid:2)Ke1lv.i3n8te(cid:0)m1p0e–ra2t3u,req(cid:2)1.602(cid:0)10–19, Q1 Q2 R4 2.5 MΩ 2N2484 + 15 V R102 kΩ _U1C _+U1D VO + R1 (see equation above) U1A + C1 VI _ 10 kΩ U_1B R6 R3 150 pF 10 kΩ R5 270 kΩ 10 kΩ –15V IC1 NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference Figure 87. Log Amplifier –0.1 B d – n –0.15 o ati c plifi –0.2 m A e g a –0.25 olt V al nti –0.3 e r e Diff Á– Á–0.35 D ÁVÁ A ÁÁ–0.4 0 1 2 3 4 5 6 7 8 9 10 f – Frequency – Hz Figure 88. Output Voltage vs Input Voltage for Log Amplifier 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION analog thermometer By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through the temperature-sensing diode D1. For this section of the circuit to operate correctly, the TL05x must use split supplies, and R3 must be a metal-film resistor with a low temperature coefficient. The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature. Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains constant. Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F). IC1 + R9 R12 C1 U1B – 10 kΩ 10 kΩ 150 pF R6 R1 – 10 kΩ 100 kΩ U1A +15 V R5 R7 + R3 10 kΩ 5 kΩ 5 kΩ – (see Note B) S1 U2B VO (see Note C) + (see Note D) D1 (see Note A) +15 V –15 V R2 100 kΩ R8 10 kΩ – R10 U2A IC2 + 10 kΩ R4 R11 50 kΩ 10 kΩ NOTES: A. Temperature-sensing diode ≈ (–2 mV/°C) B. Metal-film resistor (low temperature coefficient) C. Switch open for °F and closed for °C D. VO α temperature; 10 mV/°C or 10 mV/°F E. U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference Figure 89. Analog Thermometer POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION voltage-ratio-to-dB converter The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For measuring two input signals of different frequencies, extra filtering should be added after the rectifiers. The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing the logarithmic conversion also requires two well-matched npn transistors. The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-kΩ potentiometer on the input of U3C calibrates the zero-dB reference level. The following equations are used to derive the relationship between the input voltage ratio, expressed in decibels, and the output voltage. V (cid:8)In (cid:5)V (cid:6) – (cid:5)V (cid:6)(cid:10) (cid:3) A(cid:4) A B X dB(cid:1)20 log (cid:1)20(cid:7) (cid:7) V In (10) B (cid:9) (cid:11) X dB(cid:1)8.686 (cid:3)In (cid:5)VA(cid:6) – In (cid:5)VB(cid:6)(cid:4) kT (cid:3) VA (cid:4) kT (cid:3) VB (cid:4) VBE(Q1)(cid:1) q In R(cid:0)IS VBE(Q2)(cid:1) q In R(cid:0)IS (cid:0)VBE(cid:1)VBE(Q1)–VBE(Q2)(cid:1) kqT (cid:3)In (cid:5)VA(cid:6) – In (cid:5)VB(cid:6)(cid:4) X dB(cid:1)8k.T6(cid:2)8q6 (cid:3)VBE(Q1)–VBE(Q2)(cid:4)(cid:1)336 (cid:3)VBE(Q1)–VBE(Q2)(cid:4) at 25°C where –23 –19 k(cid:1)1.38(cid:0)10 , q(cid:1)1.602(cid:0)10 , and T is Kelvin temperature This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain 100 mV/dB. 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION R2 2N2484 Q1 VA + R1 10 kΩ U1A + _ 20 kΩ _U1B + R6 U1C + R7 D1 _ 10 kΩ _U1D + R18 R20 R5 10 kΩ _U3A 10 kΩ 10 kΩ 10 kΩ R16 + 30 kRΩ3 R104 kΩ 16.3 kΩ _U3D VO R9 2N2484 R76 VB + R8 10 kΩ 16.3 kΩ U_2A + 20 kΩ U2B + R13 + R19 _ D2 U_2C 10 kΩ U_+2D R14 Q2 U_3B 10 kΩ R12 10 kΩ R21 15 V 10 kΩ 10 kΩ R10 R11 82 kΩ 30 kΩ 10 kΩ + U3C _ 1 kΩ C1 82 kΩ –15 V NOTE A: U1A through U3D = TL05xA, VCC± = ±15 V. D1 and D2 = 1N914. Figure 90. Voltage Ratio-to-dB Converter 2 1 V – e g a olt V ut 0 p ut O – O V –1 –2 0 1 2 3 4 5 6 7 8 9 10 Ratio – VA/VB Figure 91. Output Voltage vs the Ratio of the Input Voltages for Voltage-to-dB Converter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using MicrosimParts, the model-generation software used with Microsim PSpice. The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the TL05x typical electrical and operating characteristics at T = 25°C. Using this information, output simulations A of the following key parameters can be generated to a tolerance of 20% (in most cases): (cid:0) (cid:0) Maximum positive output voltage swing Unity-gain frequency (cid:0) (cid:0) Maximum negative output voltage swing Common-mode rejection ratio (cid:0) (cid:0) Slew rate Phase margin (cid:0) (cid:0) Quiescent power dissipation DC output resistance (cid:0) (cid:0) Input bias current AC output resistance (cid:0) (cid:0) Open-loop voltage amplification Short-circuit output current limit NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 DLN 3 EGND + VCC+ 92 9 FB RSS ISS + – 90 91 VB RO2 + DLP + – RP + – HLIM VLP VLN IN– 2 10 VC R2 – – + DP J1 J2 – 6 C2 7 IN+ 53 + 3 VLIM 11 12 DC GCM GA – 8 C1 RD1 RD2 60 RO1 VAD + DE – 54 5 VCC– 4 – + VE OUT .SUBCKT TL05x 1 2 3 4 5 RD1 4 11 3.422E3 C1 11 12 3.988E–12 RD2 4 12 3.422E3 C2 6 7 15.00E–12 R01 8 5 125 DC 5 53 DX R02 7 99 125 DE 54 5 DX RP 3 4 11.11E3 DLP 90 91 DX RSS 10 99 666.7E6 DLN 92 90 DX VB 9 0 DC 0 DP 4 3 DX VC 3 53 DC 3 EGND99 0 POLY (2) (3,0) (4,0) 0 .5 .5 VE 54 4 DC 3.7 FB 7 99 POLY (5) VB VC VE VLP VLIM 7 8 DC 0 + VLN 0 2.875E6 –3E6 3E6 3E6 –3E6 VLP 91 0 DC 28 GA 6 0 11 12 292.2E–6 VLN 0 92 DC 28 GCM 0 6 10 99 6.542E–9 .MODEL DX D (IS=800.0E–18) ISS 3 10 DC 300.0E–6 .MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6 HLIM 90 0 VLIM 1K + VTO=–.1) J1 11 2 10 JX .ENDS J2 12 1 10 JX R2 6 9 100.0E3 Figure 92. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates. 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL051ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 051AC & no Sb/Br) TL051ACP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL051ACP & no Sb/Br) TL051CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL051C & no Sb/Br) TL051CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL051C & no Sb/Br) TL051CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL051CP & no Sb/Br) TL051CPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL051CP & no Sb/Br) TL052ACD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 052AC & no Sb/Br) TL052ACDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 052AC & no Sb/Br) TL052ACP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL052ACP (RoHS) TL052ACPE4 ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL052ACP (RoHS) TL052AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 052AI & no Sb/Br) TL052AIDE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 052AI & no Sb/Br) TL052AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 052AI & no Sb/Br) TL052AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 052AI & no Sb/Br) TL052AIP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 TL052AIP (RoHS) TL052CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C & no Sb/Br) TL052CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL052CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C & no Sb/Br) TL052CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C & no Sb/Br) TL052CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL052C & no Sb/Br) TL052CP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TL052CP (RoHS) TL052CPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 T052 & no Sb/Br) TL052ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL052I & no Sb/Br) TL052IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL052I & no Sb/Br) TL052IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL052I & no Sb/Br) TL052IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL052I & no Sb/Br) TL052IP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 TL052IP (RoHS) TL054ACD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054AC & no Sb/Br) TL054ACDE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054AC & no Sb/Br) TL054ACDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054AC & no Sb/Br) TL054ACN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL054ACN & no Sb/Br) TL054AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054AI & no Sb/Br) TL054AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054AI & no Sb/Br) TL054AIDRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054AI & no Sb/Br) TL054CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054C & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TL054CDE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054C & no Sb/Br) TL054CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054C & no Sb/Br) TL054CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL054CN & no Sb/Br) TL054CNE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 TL054CN & no Sb/Br) TL054CNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TL054 & no Sb/Br) TL054ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054I & no Sb/Br) TL054IDE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054I & no Sb/Br) TL054IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054I & no Sb/Br) TL054IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TL054I & no Sb/Br) TL054IN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TL054IN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TL051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL052ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL052AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL052CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL052IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL054ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL054AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL054CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL054CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TL054IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TL051CDR SOIC D 8 2500 340.5 338.1 20.6 TL052ACDR SOIC D 8 2500 340.5 338.1 20.6 TL052AIDR SOIC D 8 2500 340.5 338.1 20.6 TL052CDR SOIC D 8 2500 340.5 338.1 20.6 TL052IDR SOIC D 8 2500 340.5 338.1 20.6 TL054ACDR SOIC D 14 2500 333.2 345.9 28.6 TL054AIDR SOIC D 14 2500 333.2 345.9 28.6 TL054CDR SOIC D 14 2500 333.2 345.9 28.6 TL054CNSR SO NS 14 2000 367.0 367.0 38.0 TL054IDR SOIC D 14 2500 333.2 345.9 28.6 PackMaterials-Page2

None

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated