TJA1082 FlexRay node transceiver Rev. 6 — 28 November 2012 Product data sheet 1. General description The TJA1082 FlexRay node transceiver is compliant with the FlexRay electrical physical layer specification V2.1 Rev. B (see Ref.1). In addition, it incorporates features and parameters included in V3.0.1 (see Ref.2 and Section14). It is primarily intended for communication systems operating at between 2.5 Mbit/s and 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1082 offers an optimized solution for Electronic Control Unit (ECU) applications that do not need enhanced power management and are typically switched by the ignition or activated by a dedicated wake-up line. The TJA1082 provides a differential transmit capability to the network and a differential receive capability to the FlexRay controller. It offers excellent ElectroMagnetic Compatibility (EMC) performance as well as high ElectroStatic Discharge (ESD) protection. The TJA1082 actively monitors system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. 2. Features and benefits 2.1 Optimized for time triggered communication systems  Compliant with Electrical Physical Layer specification 2.1 Rev. B  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Data transfer at 2.5 Mbit/s, 5 Mbit/s and 10 Mbit/s  Supports 60ns minimum bit time at 400 mV differential voltage  Very low ElectroMagnetic Emission (EME) to support unshielded cable  Differential receiver with high common-mode range for excellent ElectroMagnetic Immunity (EMI)  Auto I/O level adaptation to host controller supply voltage V IO  Can be used in 14 V and 42 V powered systems  Instant shut-down interface (via BGE pin) 2.2 Low power management  Very low current consumption in Standby mode  Remote wake-up via a wake-up pattern or dedicated FlexRay data frames on the bus lines

TJA1082 NXP Semiconductors FlexRay node transceiver 2.3 Diagnosis and robustness  Enhanced supply voltage monitoring for V and V CC IO  Two error diagnosis modes: Status register readout via the Serial Peripheral Interface (SPI) Simple error indication via pin ERRN  Overtemperature detection  Short-circuit detection on bus lines  Power-on flag  Clamping diagnosis for pins TXEN and BGE  Bus pins protected against 8 kV ESD pulses (according to IEC61000-4-2 and HBM)  Bus pins protected against transients in automotive environment (according to ISO7637 classC)  Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground  Maximum differential voltage between pins BP or BM and any other pin of 60V  Bus lines remain passive when the transceiver is not powered  No reverse currents from the digital input pins to V or V when the transceiver is not IO CC powered 2.4 FlexRay conformance classes  Bus driver - bus guardian interface  Bus driver logic level adaptation 3. Ordering information Table 1. Ordering info rmation Type number Package Name Description Version TJA1082TT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 2 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 4. Block diagram VCC 14 VCC UNDERVOLTAGE DETECTION TJA1082 VIO 1 VIO UDNEDTEERCVTOIOLNTAGE OVER- TEMPERATURE TXEN TIMEOUT DETECTION 3 TXEN I/O 13 BP 2 TRANSMITTER 12 TXD I/O BM I/O 6 STBN I/O STATE MACHINE 10 ERRN I/O 5 BGE I/O 8 SDO I/O LOW-POWER RECEIVER 9 SCSN I/O SPI 7 BUS ERROR SCLK I/O ACTIVITY NORMAL DETECTION RECEIVER 4 RXD I/O MUX 11 015aaa000 GND Fig 1. Block diagram TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 3 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 5. Pinning information 5.1 Pinning VIO 1 14 VCC TXD 2 13 BP TXEN 3 12 BM RXD 4 TJA1082 11 GND BGE 5 10 ERRN STBN 6 9 SCSN SCLK 7 8 SDO 015aaa001 Fig 2. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Type Description V 1 P supply voltage for V voltage level adaptation IO IO TXD 2 I transmit data input; internal pull-down TXEN 3 I transmitter enable input; when HIGH transmitter disabled; internal pull-up RXD 4 O receive data output BGE 5 I bus guardian enable input; when LOW transmitter disabled; internal pull-down STBN 6 I mode control input; transceiver in Normal mode when HIGH; internal pull-down SCLK 7 I SPI clock signal; internal pull-up SDO 8 O SPI data output SCSN 9 I SPI chip select input; internal pull-up/pull-down ERRN 10 O error diagnosis output and wake-up indication GND 11 P ground BM 12 I/O bus line minus BP 13 I/O bus line plus V 14 P supply voltage (+5 V) CC 6. Functional description 6.1 Power modes The TJA1082 features three power modes: Normal, Standby and Power-off. Normal and Standby modes can be selected via the STBN input (HIGH for Normal mode) once the transceiver has been powered up. See Table3 for a detailed description of pin signaling in the three power modes. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 4 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 3. Pin signallin g in the different power modes Mode STBN UV at UV ERRN RXD SDO Biasing UV-det Trans- Low- V at BP, BM mitter power IO LOW HIGH LOW HIGH V receiver CC Normal HIGH no no error error bus bus high- V / 2 enabled enabled enabled[1] CC flag flag DATA_ DATA_1 impedance set reset 0 or idle (in simple error Standby LOW no no wake wake wake wake GND disabled enabled[2] indication flag flag flag flag mode) or set reset set reset enabled (in LOW no yes[3] wake wake wake wake disabled SPI mode) flag flag flag flag set[4] reset[4] set[4] reset[4] HIGH no yes[3] error error wake wake flag flag flag flag set reset set[4] reset[4] X yes[5] no LOW LOW high- enabled[2] impedance X yes[5] yes[3] LOW LOW disabled Power-off[6] X X[5] yes high- HIGH GND[7] disabled disabled impedance [1] The wake flag is set if a valid wake-up event is detected while switching to Standby mode. [2] The wake flag is set if a valid wake-up event is detected. [3] V > V > V . uvd(VCC) CC th(det)POR [4] Pins ERRN and RXD reflect the state of the wake flag prior to the V undervoltage event. CC [5] The internal signals at pins STBN, BGE and TXD are set LOW; the internal signals at pins TXEN, SCLK and SCSN are set HIGH. [6] V < V at power-up and V < V at power-down (see Figure6 and Figure7). CC th(rec)POR CC th(det)POR [7] Except when V = 0; in this case BP and BM are floating. CC 6.1.1 Normal mode In Normal mode, the transceiver transmits and receives data via the bus lines BP and BM. The transmitter and the normal receiver are enabled, along with the undervoltage detection function. The timing diagram for Normal mode is illustrated in Figure3. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 5 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver TXD BGE TXEN BP BM RXD 015aaa002 Fig 3. Timing diagram in Normal mode Table4 describes the behavior of the transmitter in Normal mode, when the temperature flag (TEMP HIGH) is not set and with no time-out on pin TXEN. Transmitter behavior is illustrated in Figure14. Table 4. Transmitter operation in Normal mode BGE TXEN TXD Bus state Transmitter L X X idle transmitter is disabled X H X idle transmitter is disabled H L H DATA_1 transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW H L L DATA_0 transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH The transmitter is activated during the first LOW level on pin TXD while pin BGE is HIGH and pin TXEN is LOW. In Normal mode, the normal receiver output is connected directly to pin RXD (see Table5). Receiver behavior is illustrated in Figure15. Table 5. Behavior of normal receiver in Normal mode Bus state RXD DATA_0 L DATA_1 H idle H When V and V are within their operating ranges, pin ERRN indicates the status of the IO CC error flag. See Section6.8 for a detailed description of error signalling in Normal mode. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 6 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 6.1.1.1 Bus activity and idle detection In Normal mode, bus activity and bus idle are detected as follows: • Bus activity is detected when the absolute differential voltage on the bus lines is higher than V  for t : i(dif)det(act) det(act)(bus) – If the differential voltage on the bus lines is lower than V after bus activity has IL(dif) been detected, pin RXD switches LOW. – If the differential voltage on the bus lines is higher than V after bus activity has IH(dif) been detected, pin RXD remains HIGH. • Bus idle is detected when the absolute differential voltage on the bus lines is lower than V  for t . This results in pin RXD being switched HIGH or i(dif)det(act) det(idle)(bus) staying HIGH. 6.1.2 Standby mode Standby mode is a low-power mode featuring very low current consumption. In Standby mode, the transceiver is unable to transmit or receive data since both the transmitter and the normal receiver are switched off. The low-power receiver is activated to monitor the bus for wake-up activity, provided an undervoltage has not been detected on pin V . CC The low-power receiver is deactivated if an undervoltage is detected on pin V - with the CC result that the wake flag is not set if a wake-up pattern or dedicated data frame is received. Pins ERRN and RXD indicate the status of the wake flag when V and V are within IO CC their operating ranges. See Table3 for a description of pins ERRN and RXD when an undervoltage is detected on pin V or pin V . IO CC The status register cannot be read via the SPI interface if an undervoltage is detected on pin V . IO The BGE input has no effect in Standby mode. 6.1.3 Power-off mode The transmitter and the two receivers (normal and low-power) are deactivated in Power-off mode. As a result, the wake flag is not set if a wake-up pattern or dedicated data frame is received. If the voltage at V rises above V , the transceiver CC th(rec)POR switches to Standby mode and the digital section is reset. If V subsequently drops CC below V , the transceiver reverts to Power-off mode (see Section6.2). th(det)POR The status register cannot be read via the SPI interface in Power-off mode. 6.1.4 State transitions Figure4 shows the TJA1082 state transition diagram. The timing diagram for the ERRN indication signal during transitions between Normal and Standby modes, when the error flag is set and the wake flag is not set, is illustrated in Figure5 and described in Table6. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 7 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver NORMAL (STBN -> HIGH while STBN -> LOW or UV flags cleared) or UVVCC flag set or (UV flags cleared while UVVIO flag set STBN = HIGH) STANDBY VCC > Vth(rec)POR VCC < Vth(det)POR POWER OFF 015aaa004 Fig 4. State transitions diagram 20 μs STBN td(norm-stb) td(stb-norm) ERRN 015aaa003 Fig 5. State transitions timing (error flag set) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 8 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 6. State transiti ons  indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition UVV UVV wake flag[1] PWON flag[1] STBN VCC level IO CC flag[1] flag[1] Normal to Standby cleared cleared cleared cleared  L V > V CC uvd(VCC)  set cleared cleared cleared H V > V CC uvd(VCC) cleared  set cleared cleared H V > V > V uvd(VCC) CC th(det)POR Standby to Normal cleared cleared 1  cleared 2  cleared  H V > V CC uvd(VCC)  cleared cleared 1  cleared 2  cleared H V > V CC uvd(VCC) cleared  cleared 1  cleared 2  cleared H V > V > V uvd(VCC) CC th(det)POR Standby to Power-off X set X X X  V < V CC th(det)POR Power-off to Standby X set X 1  set X  V > V CC th(rec)POR [1] See Table7 for set and reset conditions of all flags. 6.2 Power-up and power-down behavior 6.2.1 Power-up The TJA1082 has two supply pins: V (+5 V) and V (for the voltage level adaptation). CC IO The ramp up of the different power supplies can vary, depending on the state or value of a number of signals and parameters. The power-up behavior of the TJA1082 is not affected by the sequence in which power is supplied to these pins or by the voltage ramp up. As an example, Figure6 shows one possible power supply ramp-up scenario. The digital section of the TJA1082 is supplied by V . The voltage on pin V ramps up before the CC CC voltage on pin V . As long as the voltage on V remains below the power-on reset IO CC recovery threshold, V , the internal state machine is not active and the transceiver th(rec)POR is totally passive, remaining in Power-off mode. As soon as the voltage crosses the V threshold, the internal state machine starts running, setting the PWON flag and th(rec)POR switching the TJA1082 to Standby mode. This initializes the V and V under-voltage CC IO flags to the set state (since both V and V are actually in undervoltage state just after CC IO power-on). Once both V and V have reached their operating ranges, the under-voltage flags are IO CC reset. The operating mode is then determined by the level on STBN (the TJA1082 switches to Normal mode if STBN is HIGH and remains in Standby mode if STBN is LOW), provided V and V are above their respective undervoltage recovery levels IO CC (V and V ). uvr(VIO) uvr(VCC) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 9 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Power-off Standby Normal Vuvr(VCC) Vth(rec)POR VCC Vuvr(VIO) VIO STBN RXD ERRN 015aaa005 Fig 6. Power-up behavior (example) 6.2.2 Power-down The behavior of the TJA1082 during power-down is illustrated in Figure7. Normal Standby Power-off Vuvd(VCC) Vth(det)POR VCC Vuvd(VIO) VIO STBN RXD ERRN 015aaa006 Fig 7. Power-down behavior (example) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 10 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 6.3 Remote wake-up 6.3.1 Bus wake-up via wake-up pattern A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up pattern consists of at least two consecutive wake-up symbols. A wake-up symbol consists of a DATA_0 phase lasting longer than t , followed by an idle phase lasting det(wake)DATA_0 longer than t , provided both wake-up symbols occur within a time span of det(wake)idle t (see Figure8). The transceiver also wakes up if the idle phases are replaced det(wake)tot by DATA_1 phases. wake-up < tdet(wake)tot Vdif (mV) > tdet(wake)idle > tdet(wake)idle 00 -500 > tdet(wake)DATA_0 > tdet(wake)DATA_0 > tdet(wake)idle > tdet(wake)idle +500 0 -500 > tdet(wake)DATA_0 > tdet(wake)DATA_0 wake-up symbol wake-up symbol wake-up pattern 015aaa007 Fig 8. Bus wake-up timing The wake-up mechanism of the TJA1082 follows the state transition diagram shown in Figure9. See Ref.1 for more details of the wake-up mechanism. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 11 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver power on Wait I' DATA_1 or idle on bus start tdet(wake)idle DATA_0 for longer than tsup(int)wake Initial state tdet(wake)idle expired DATA_0 on bus Wait S' start tdet(wake)Data_0 DATA_1 or idle for longer than tsup(int)wake tdet(wake)tot expired Start state tdet(wake)Data_0 expired tdet(wake)tot expired DATA_1 or idle on bus Wait A' start tdet(wake)idle DATA_0 for longer than tsup(int)wake tdet(wake)tot expired Wait state A tdet(wake)idle expired tdet(wake)tot expired Wait B' DATA_0 on bus start tdet(wake)Data_0 DATA_1 or idle for longer than tsup(int)wake Wait state B tdet(wake)tot expired tdet(wake)Data_0 expired DATA_1 or idle on bus Wait C' start tdet(wake)idle tdet(wake)tot expired DATA_0 for longer than tsup(int)wake Wait state C Wake-up! tdet(idle)wake expired 015aaa008 Fig 9. Wake-up state machine 6.3.2 Bus wake-up via dedicated FlexRay data frame The TJA1082 wake flag is set when a dedicated data frame emulating a valid wake-up pattern, as shown in Figure10, is received. The DATA_0 and DATA_1 phases of the emulated wake-up symbol are interrupted by the Byte Start Sequence (BSS) preceding each byte in the data frame. With a data rate of 10Mbit/s, the interruption has a maximum duration of 130ns and does not prevent the transceiver from recognizing the wake-up pattern in the payload. For longer interruptions at lower data rates (5Mbit/s and 2.5Mbit/s), the wake-up pattern should be used (see Section6.3.1). The wake flag is not set if an invalid wake-up pattern is received. See Ref.1 for more details on invalid wake-up patterns. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 12 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Vdif wake-up 130 ns 870 ns870 ns +1500 0 V −1500 770 870 870 130 130 ns ns ns ns ns 5 μs 5 μs 5 μs 5 μs 015aaa097 The duration of each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and vice versa is about 20 ns. The TJA1082 wake-up flag is set on receipt of the following frame payload: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF Fig 10. Minimum bus pattern for bus wake-up via dedicated FlexRay data frame 6.4 Bus error detection The TJA1082 detects the following bus errors during transmission: • Short-circuit BP to BM at the ECU connector or on the bus • Short-circuit BP to GND at the ECU connector or on the bus • Short-circuit BM to GND at the ECU connector or on the bus • Short-circuit BP to V at the ECU connector or on the bus CC • Short-circuit BM to V at the ECU connector or on the bus CC The bus error flag is not set when a wake-up pattern or a FlexRay Collision Avoidance Symbol (CAS) is being transmitted or received. 6.5 Fail silent behavior Three mechanisms guarantee the ‘fail silent’ behavior of the TJA1082: • The TXEN Clamped flag is set if pin TXEN goes LOW for longer than t in detCL(TXEN) Normal mode; the transmitter is disabled. • The BGE Clamped flag is set if pin BGE goes HIGH for longer than t in detCL(BGE) Normal mode; no action is taken. • If a loss-of-ground occurs at the transceiver, resulting in the TJA1082 switching to Power-off mode, no current flows out of the digital input pins (TXD, TXEN, BGE, STBN, SCLK, SCSN); see Table3 for details of the behavior of the bus pins. 6.6 TJA1082 flags The TJA1082 has 11 status/error flags. These are described in Table7. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 13 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 7. TJA1082 flag s and set/reset conditions Flag name Flag type Flag description Set condition Reset condition[1] Consequence of flag set bus wake status indicates if a wake-up wake-up event on bus transition to Normal RXD  LOW; flag event has occurred in Standby mode[2] mode ERRN  LOW [3] Normal status indicates if the transceiver entering Normal mode leaving Normal mode - mode flag is in Normal mode transmitter status indicates the transmitter transmitter enabled[4] transmitter disabled - enabled flag status BGE status indicates if pin BGE is BGE HIGH for longer BGE LOW[5] - clamped flag clamped than t [5] detCL(BGE) PWON status indicates when the digital V > V transition to Normal - CC th(rec)POR flag section is initialized mode bus error error flag indicates if a bus error has bus error detected[5] no bus error detected or ERRN  LOW [6] been detected positive edge on TXEN[5] TEMP error flag indicates if the max. T > T [5] TXEN = HIGH while ERRN  LOW [6]; vj j(dis)(high) HIGH junction temperature has T < T [5] transmitter disabled vj j(dis)(high) been reached TXEN error flag indicates if pin TXEN is TXEN LOW for longer TXEN = HIGH[5] ERRN  LOW [6]; clamped clamped than t [5] transmitter disabled detCL(TXEN) UVV error flag indicates if there is an V < V for V > V for ERRN  LOW [6]; CC CC uvd(VCC) CC uvr(VCC) undervoltage at pin V longer than t longer than t entering Standby CC det(uv)(VCC) rec(uv)(VCC) mode UVV error flag indicates if there is an V < V for V > V for longer ERRN  LOW [6]; IO IO uvd(VIO) IO uvr(VIO) undervoltage at pin V longer than t than t entering Standby IO det(uv)(VIO) rec(uv)(VIO) mode SPI error error flag indicates if an SPI error SPI error detected[8] falling edge on SCSN ERRN  LOW [7]; has occurred SDO goes to a high impedance state [1] All flags, with the exception of the PWON flag, are reset after a power-on reset. [2] If an undervoltage has not been detected on pin V . CC [3] If STBN = LOW. [4] If BGE = HIGH, the Normal mode flag is set, the TEMP HIGH flag is not set and the TXEN clamped flag is not set. [5] Flag can only be set or reset in Normal mode or on leaving Normal mode. [6] If STBN= HIGH. [7] If STBN= HIGH in SPI mode [8] The SPI error flag is set when: a) more than 16 falling edges occur on pin SCLK while pin SCSN=LOW b) less than 16 falling edges occur on pin SCLK while pin SCSN=LOW. 6.7 TJA1082 status register The TJA1082 contains a 16-bit status register, of which bits S0 to S4 reflect the state of the status flags, bits S5 to S10 reflect the state of the error flags and bit S15 is a parity bit. All flags can be individually read out on pin SDO via a 16-bit SPI interface when the transceiver is configured in SPI mode. The status register bits are described in Table8. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 14 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 8. TJA1082 status register Status Flag name Set condition Reset condition bit S0 bus wake bus wake flag set bus wake flag cleared S1 Normal Normal mode flag set Normal mode flag cleared mode S2 transmitter transmitter enabled flag set transmitter enabled flag cleared enabled S3 BGE BGE clamped flag set BGE clamped flag cleared clamped S4 PWON PWON flag set PWON flag cleared and successful readout[1] S5 bus error bus error flag set bus error flag cleared and successful readout[1] S6 TEMP TEMP HIGH flag set TEMP HIGH flag cleared and successful HIGH readout[1] S7 TXEN TXEN clamped flag set TXEN clamped flag cleared and successful clamped readout[1] S8 UVV UVV flag set UVV flag cleared and successful readout[1] CC CC CC S9 UVV UVV flag set UVV flag cleared and successful readout[1] IO IO IO S10 SPI error SPI error flag set SPI error flag cleared and successful readout[1] S11 reserved always LOW S12 reserved always HIGH S13 reserved always LOW S14 reserved always HIGH S15 parity bit odd parity of status bits even parity of status bits [1] Also cleared during Power-off. 6.8 Error signalling The TJA1082 provides two modes for error indication: • SPI mode (default mode) • Simple error indication mode SPI mode is active on power-up. To switch to simple error indication mode, SCSN has to be held LOW (connected to GND) and SCLK held HIGH (connected to V ) for longer than t (provided a V IO det(L)(SCLK) IO undervoltage has not occurred). When the TJA1082 is in simple error indication mode, a rising edge on SCSN initiates a transition to SPI mode (provided a V undervoltage has not occurred). IO TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 15 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver SPI mode simple error SPI mode SCSN indication mode (V) VIO 0 t SCLK (V) VIO 0 t tdet(L)(SCLK) 015aaa015 Fig 11. Timing diagram for configuration of error indication mode If a V undervoltage condition is detected, it is not possible to switch between SPI mode IO and simple error indication mode. 6.8.1 SPI mode The error flag information in the status register is latched in SPI mode. This means that the status bit is reset once the status register has been completely read (provided the corresponding error flag has been reset). If an error condition is detected in Normal mode, pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes HIGH again once all the error bits (S5-S10) have been reset. 6.8.2 Simple error indication mode If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant error flag has been set. Pin ERRN goes HIGH again when all error conditions have been cleared and all flags have been reset. Error flags are not latched. It is not possible to read-out the status bits in this mode. 6.9 SPI interface The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register when the transceiver is in SPI mode (see Section6.8). While pin SCSN is HIGH, the SDO output is in a high-impedance state. To begin a status register readout, the host must force pin SCSN LOW. This causes the SDO pin to output a LOW level by default. The data at pin SDO is then shifted out on the rising edge of the clock signal on pin SCLK. The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin SDO returned to a high-impedance state once the status register has been read successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock signals on SCLK are ignored while SCSN is HIGH. The timing diagram for the SPI readout is illustrated in Figure12. The SLCK period ranges from 500ns to 100s (10 kbit/s to 2Mbit/s). TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 16 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver If SCSN remains LOW for longer than 16 clock cycles, it recognized as an SPI error. When this happens, the SPI error flag is set and pin SDO goes to a high-impedance state until the next falling edge on pin SCSN. An SPI error is also assumed if fewer than 16 clock cycles are received while SCSN is LOW. If this happens, the SPI error flag is set. All status bits are refreshed once the status register has been successfully read. When the transceiver is in simple error indication mode the SDO output is in a high-impedance state and pin SCSN is in pull-down mode. In SPI mode pin SCSN is in pull-up mode. SPI readout is not possible when the transceiver has detected an undervoltage on V . IO SCSN tSPILEAD TSCLK tSPILAG SCLK 01 02 03 15 16 td(SCSNHL-SDOL) td(SCLKLH-SDODV) td(SCSNLH-SDOZ) SDO Z L S0 S1 S2 S14 S15 Z 015aaa009 Fig 12. SPI readout timing diagram 7. Limiting values Table 9. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit V supply voltage no time limit 0.3 +5.5 V CC V supply voltage on pin V no time limit 0.3 +5.5 V IO IO V voltage on pin ERRN no time limit 0.3 V + 0.3 V ERRN IO V voltage on pin RXD no time limit 0.3 V + 0.3 V RXD IO V voltage on pin SDO no time limit 0.3 V + 0.3 V SDO IO V voltage on pin TXEN no time limit 0.3 +5.5 V TXEN V voltage on pin TXD no time limit 0.3 +5.5 V TXD V voltage on pin STBN no time limit 0.3 +5.5 V STBN V voltage on pin SCSN no time limit 0.3 +5.5 V SCSN V voltage on pin SCLK no time limit 0.3 +5.5 V SCLK V voltage on pin BGE no time limit 0.3 +5.5 V BGE V voltage on pin BP no time limit (with respect to pins BM 60 +60 V BP and GND) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 17 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit V voltage on pin BM no time limit (with respect to pins BP 60 +60 V BM and GND) I input current on pin ERRN no time limit; V =0V 10 10 mA I(ERRN) IO I input current on pin RXD no time limit; V =0V 10 10 mA I(RXD) IO I input current on pin SDO no time limit; V =0V 10 10 mA I(SDO) IO V transient voltage on pins BM and BP [1] 100 - V trt [2] - 75 V [3] 150 - V [4] - 100 V T storage temperature 55 +150 C stg T virtual junction temperature [5] 40 +150 C vj V electrostatic discharge voltage IEC61000-4-2 on pins BP and BM to [6] 8.0 +8.0 kV ESD ground HBM on pins BP and BM to ground [7] 8.0 +8.0 kV HBM on any other pin [7] 4.0 +4.0 kV MM on all pins [8] 200 +200 V CDM on all pins [9] 1000 +1000 V [1] According to ISO7637, test pulse 1, class C; verified by an external test house. [2] According to ISO7637, test pulse 2a, class C; verified by an external test house. [3] According to ISO7637, test pulse 3a, class C; verified by an external test house. [4] According to ISO7637, test pulse 3b, class C; verified by an external test house. [5] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature T is: T = T + TD x R , where R is vj vj amb th(j-a) th(j-a) a fixed value to be used for the calculation of T . The rating for T limits the allowable combinations of power dissipation (P) and vj vj ambient temperature (Tamb). [6] IEC61000-4-2: C = 150 pF; R = 330 . [7] HBM: C = 100 pF; R = 1.5 k. [8] MM: C = 200 pF; L = 0.75 H; R = 10 . [9] CDM: R = 1 . 8. Thermal characteristics Table 10. Thermal cha racteristics Symbol Parameter Conditions Typ Unit R thermal resistance from junction to ambient in free air 130 K/W th(j-a) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 18 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 9. Static characteristics Table 11. Static charac teristics All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Pin V CC I supply current Standby mode with no undervoltage; - 20 30 A CC T  85 C vj Standby mode with no undervoltage; - 20 40 A T 150 C vj Power-off mode; T  85 C - - 30 A vj Power-off mode; T  150 C - - 40 A vj Normal mode; - - 15 mA V =0VorV =V BGE TXEN IO Normal mode; V =V ; - - 35 mA BGE IO V = 0 V; R  45  TXEN bus Normal mode; V =V ; V =0V; - - 15 mA BGE IO TXEN R > 10 M bus V undervoltage detection 4.5 - 4.729 V uvd(VCC) voltage on pin V CC V undervoltage recovery 4.52 - 4.749 V uvr(VCC) voltage on pin V CC V undervoltage hysteresis 20 - 240 mV uvhys(VCC) voltage on pin V CC V power-on reset detection 3.75 - 4.15 V th(det)POR threshold voltage V power-on reset recovery 3.85 - 4.25 V th(rec)POR threshold voltage V power-on reset hysteresis 100 - 500 mV hys(POR) voltage Pin V IO I supply current on pin V Normal mode; V = V ; - - 1000 A IO IO TXEN IO V = V ; R > 10 M BGE IO RXD Normal mode; V = 0 V; - - 1000 A TXEN V = V ; R > 10 M BGE IO RXD Standby mode with no undervoltage - 2.2 7 A Power-off mode; V = 5 V - 3 7 A IO V undervoltage detection 2.6 - 2.779 V uvd(VIO) voltage on pin V IO V undervoltage recovery 2.62 - 2.799 V uvr(VIO) voltage on pin V IO V undervoltage hysteresis 20 - 190 mV uvhys(VIO) voltage on pin V IO Pin SCSN V HIGH-level input voltage 0.7V - 5.5 V IH IO V LOW-level input voltage 0.3 - 0.3V V IL IO TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 19 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit I HIGH-level input current simple error indication mode; 3 - 15 A IH V =0.7V SCSN IO I LOW-level input current SPI mode; V = 0.3V 15 - 3 A IL SCSN IO I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V = V = 0V SCSN CC IO Pin SCLK V HIGH-level input voltage 0.7V - 5.5 V IH IO V LOW-level input voltage 0.3 - 0.3V V IL IO I HIGH-level input current V = V 1 0 +1 A IH SCLK IO I LOW-level input current V = 0.3V 15 - 3 A IL SCLK IO I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V = V = 0V SCLK CC IO Pin STBN V HIGH-level input voltage 0.7V - 5.5 V IH IO V LOW-level input voltage 0.3 - 0.3V V IL IO I HIGH-level input current V = 0.7V 3 - 15 A IH STBN IO I LOW-level input current V = 0 V 1 0 +1 A IL STBN I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V =V = 0 V STBN CC IO Pin TXEN V HIGH-level input voltage 0.7V - V + 0.3 V IH IO IO V LOW-level input voltage 0.3 - 0.3V V IL IO I HIGH-level input current V = V 1 0 +1 A IH TXEN IO I LOW-level input current V = 0.3V 300 - 50 A IL TXEN IO I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V = V = 0V TXEN CC IO Pin BGE V HIGH-level input voltage 0.7V - 5.5 V IH IO V LOW-level input voltage 0.3 - 0.3V V IL IO I HIGH-level input current V = 0.7V 3 - 15 A IH BGE IO I LOW-level input current V = 0 V 1 0 +1 A IL BGE I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V = V = 0V BGE CC IO Pin TXD V HIGH-level input voltage Normal mode 0.7V - V + 0.3 V IH IO IO V LOW-level input voltage Normal mode 0.3 - 0.3V V IL IO I HIGH-level input current V = 0.7V 3 - 15 A IH TXD IO I LOW-level input current V =0V 1 0 +1 A IL TXD I reverse current Power-off mode; to V / V ; 5 0 +5 A r CC IO V = 5 V; V = V = 0V TXD CC IO TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 20 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit C input capacitance with respect to all other pins at ground; [1] - - 10 pF i V = 100 mV; f = 5MHz TXD Pin RXD I HIGH-level output current V = V  0.4 V; V =V 15 - 1.7 mA OH RXD IO IO CC I LOW-level output current V = 0.4 V 2 - 20 mA OL RXD Pin ERRN I HIGH-level output current V =V  0.4 V; V =V 1500 - 100 A OH ERRN IO IO CC I LOW-level output current V = 0.4 V 200 - 1700 A OL ERRN I leakage current Power-off mode; V  V 5 - +5 A L ERRN IO Pin SDO I HIGH-level output current V = V  0.4 V 8 3 0.5 mA OH SDO IO I LOW-level output current V = 0.4 V 0.8 3 9 mA OL SDO I leakage current high-impedance state; 0V<V <V 5 - +5 A L SDO IO Pins BP and BM V idle output voltage on pin Normal mode;V = V ; R =45  0.4V 0.5V 0.6V V o(idle)(BP) TXEN IO bus CC CC CC BP Standby mode with no undervoltage on 0.1 0 +0.1 V pin V CC V idle output voltage on pin Normal mode;V = V ; R =45 0.4V 0.5V 0.6V V o(idle)(BM) TXEN IO bus CC CC CC BM Standby mode with no undervoltage on 0.1 0 +0.1 V pin V CC I idle output current on pin Normal and Standby modes with no 7.5 - +7.5 mA o(idle)BP BP undervoltage; 60 V  V  +60 V BP I idle output current on pin Normal and Standby modes with no 7.5 - +7.5 mA o(idle)BM BM undervoltage; 60 V  V  +60 V BM V differential idle output Normal mode; R = 45  25 0 +25 mV o(idle)(dif) bus voltage V differential HIGH-level Normal mode; 40   R  55 ; 600 1000 1500 mV OH(dif) bus output voltage C =100pF bus V differential LOW-level Normal mode; 40   R  55 ; 1500 1000 600 mV OL(dif) bus output voltage C =100pF bus V differential HIGH-level Normal mode; 10VV  +15 V; 150 225 300 mV IH(dif) BP input voltage 10VV  +15 V BM V differential LOW-level Normal mode; 10VV  +15 V; 300 225 150 mV IL(dif) BP input voltage 10VV  +15 V BM Standby mode with no undervoltage on 400 225 125 mV pin V ; 10VV  +15 V; CC BP 10VV  +15 V BM V  activity detection 150 225 300 mV i(dif)det(act) differential input voltage (absolute value) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 21 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit I  short-circuit output on pin BP; 5VV +60V - - 35 mA O(sc) BP current (absolute value) on pin BM; 5VV +60V - - 35 mA BM on pins BP and BM; V =V ; - - 35 mA BP BM 5VV +60V; BP 5VV +60V BM R input resistance on pin BP R =   10 20 40 k i(BP) bus R input resistance on pin R =   10 20 40 k i(BM) bus BM R differential input R =   20 40 80 k i(dif)(BP-BM) bus resistance between pin BP and pin BM I input leakage current on Power-off mode; V =V =0 V; 5 0 +5 A LI(BP) CC IO pin BP 0 V  V 5V BP loss of ground; V =V =0V; all [1] 1600 - +1600 A BP BM other pins connected to 16V via 0  I input leakage current on Power-off mode; V =V =0 V; 5 0 +5 A LI(BM) CC IO pin BM 0 V  V 5V BM loss of ground; V =V =0V; all [1] 1600 - +1600 A BP BM other pins connected to 16V via 0  V DATA_0 bus Normal mode; R = 45  0.4V 0.5V 0.6V V cm(bus)(DATA_0) bus CC CC CC common-mode voltage V DATA_1 bus Normal mode; R = 45  0.4V 0.5V 0.6V V cm(bus)(DATA_1) bus CC CC CC common-mode voltage V bus common-mode Normal mode; DATA_1  DATA_0; 25 0 +25 mV cm(bus) voltage difference R = 45  bus V active to idle Normal mode; R = 45  300 0 +300 mV cm(act-idle) bus common-mode voltage difference V differential input voltage Normal mode; (V +V )/2=2.5V - - 10 % i(dif)(H-L) BP BM difference between HIGH-level and LOW-level C input capacitance on pin with respect to all other pins at ground; [1] - - 15 pF i(BP) BP V = 100 mV; f = 5 MHz BP C input capacitance on pin with respect to all other pins at ground; [1] - - 15 pF i(BM) BM V = 100 mV; f = 5 MHz BM C differential input with respect to all other pins at ground; [1] - - 5 pF i(dif)(BP-BM) capacitance between pin V = 100 mV; V = 100 mV; BP BM BP and pin BM f = 5MHz Temperature protection T high disable junction 180 - 200 C j(dis)(high) temperature [1] Guaranteed by design. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 22 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 10. Dynamic characteristics Table 12. Dynamic cha racteristics All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Pins BP and BM t delay time from TXD to bus Normal mode [1][2] d(TXD-bus) DATA_0 - - 50 ns DATA_1 - - 50 ns t delay time difference from TXD to bus Normal mode; between [1][2] 4 - +4 ns d(TXD-bus) DATA_0 and DATA_1 t delay time from bus to RXD Normal mode; C = 15 pF; [3] d(bus-RXD) RXD (V +V )/2 = 2.5 V BP BM DATA_0 - - 50 ns DATA_1 - - 50 ns Normal mode; C = 25 pF; [3] RXD (V +V )/2 = 2.5 V BP BM DATA_0 - - 60 ns DATA_1 - - 60 ns t delay time difference from bus to RXD Normal mode; between [3] d(bus-RXD) DATA_0 and DATA_1; (V +V )/2= 2.5 V BP BM C = 15 pF 5 - 5 ns RXD C = 25 pF 6 - 6 ns RXD t delay time from TXEN to bus idle Normal mode; V = 0 V - - 75 ns d(TXEN-busidle) TXD t delay time from TXEN to bus active Normal mode; V = 0 V - - 75 ns d(TXEN-busact) TXD t  delay time difference from TXEN to bus Normal mode; between TXEN [4] 50 ns d(TXEN-bus) (absolute value) to bus active and TXEN to bus idle; V = 0 V TXD t delay time from BGE to bus idle Normal mode; V = 0 V - - 75 ns d(BGE-busidle) TXD t delay time from BGE to bus active Normal mode; V = 0 V - - 75 ns d(BGE-busact) TXD t bus differential rise time DATA_0 to DATA_1; [5] 3.75 - 18.75 ns r(dif)(bus) 20% to 80%; R = 45 ; bus C = 100 pF bus t bus differential fall time DATA_1 to DATA_0; [5] 3.75 - 18.75 ns f(dif)(bus) 80% to 20%; R = 45; bus C = 100 pF bus t difference between differential rise and on bus; 80% to 20% [5] 3 - 3 ns (r-f)(dif) fall time R = 45; C = 100 pF bus bus t bus fall time from idle to active bus idle to DATA_0; [5][6] - - 30 ns f(bus)(idle-act) R = 45 ; C = 100pF; bus bus 30 mV > V > 300 mV dif t bus fall time from active to idle DATA_1 to bus idle; [5][6] - - 30 ns f(bus)(act-idle) R = 45 ; C = 100pF; bus bus 300 mV > V > 30 mV dif TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 23 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 12. Dynamic characteristics …continued All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit t bus rise time from active to idle DATA_0 to bus idle; [5][6] - - 30 ns r(bus)(act-idle) C = 100pF bus 300 mV < V < 30 mV dif Wake-up detection t DATA_0 wake-up detection time Standby mode with no [7] 1 - 4 s det(wake)DATA_0 undervoltage on pin V ; CC 10VV +15V; BP 10VV  +15 V BM t idle wake-up detection time Standby mode with no [7] 1 - 4 s det(wake)idle undervoltage on pin V ; CC 10VV +15V; BP 10VV  +15 V BM t total wake-up detection time Standby mode with no [7] 50 - 115 s det(wake)tot undervoltage on pin V ; CC 10VV +15V; BP 10VV  +15 V BM t wake-up interruption suppression time Standby mode with no [8] 130 - - ns sup(int)wake undervoltage on pin V ; CC 10VV +15V; BP 10VV  +15 V BM Undervoltage t undervoltage detection time on pin V 0 V  V  5.5 V; 2 - 100 s det(uv)(VCC) CC IO V =4.4 V CC t undervoltage recovery time on pin V 0 V  V  5.5 V; 2 - 100 s rec(uv)(VCC) CC IO V =4.85 V CC t undervoltage detection time on pin V V < V < 5.5 V; 5 - 100 s det(uv)(VIO) IO th(det)POR CC V = 2.5 V IO t undervoltage recovery time on pin V V < V < 5.5 V; 5 - 100 s rec(uv)(VIO) IO th(det)POR CC V = 2.9 V IO Activity detection t activity detection time on bus pins Normal mode; [6] 100 - 250 ns det(act)(bus) V : 0 mV  400 mV; dif (V +V )/2 = 2.5 V BP BM t idle detection time on bus pins Normal mode; [6] 100 - 250 ns det(idle)(bus) V : 400 mV  0 mV; dif (V +V )/2 = 2.5 V BP BM t  active to idle detection time difference Normal mode; on bus pins; - - 150 ns det(act-idle) (absolute value) (V +V )/2 = 2.5 V BP BM ERRN signalling t LOW-level detection time on pin SCLK Normal or Standby mode with 95 - 310 s det(L)(SCLK) no undervoltage on pin V IO SPI t SCSN falling edge to SDO LOW-level V < V < 5.5 V; [9] - - 250 ns d(SCSNHL-SDOL) uvd(VIO) IO delay time 4.5V< V < 5.5 V; CC C = 50 pF SDO TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 24 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver Table 12. Dynamic characteristics …continued All parameters are guaranteed for V = 4.5 V to 5.25 V; V = 2.6 V to 5.25V; T = 40 C to +150 C and R = 45  CC IO vj bus unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit t SCLK rising edge to SDO data valid V < V < 5.5 V; [9] - - 200 ns d(SCLKLH-SDODV) uvd(VIO) IO delay time 4.5V< V < 5.5 V; CC C = 50 pF SDO t SCSN rising edge to SDO three-state V < V < 5.5 V; [9] - - 500 ns d(SCSNLH-SDOZ) uvd(VIO) IO delay time 4.5V< V < 5.5 V; CC C = 50 pF SDO T SCLK period V < V < 5.5 V; [9] 0.5 - 100 s SCLK uvd(VIO) IO 4.5V< V < 5.5 V; CC C =50 pF SDO t SPI enable lead time V < V < 5.5 V; [9] 250 - - ns SPILEAD uvd(VIO) IO 4.5V< V < 5.5 V; CC C =50 pF SDO t SPI enable lag time V < V < 5.5 V; [9] 250 - - ns SPILAG uvd(VIO) IO 4.5V< V < 5.5 V; CC C =50 pF SDO RXD t rise time 20% to 80%; C = 15 pF [4] - - 5 ns r RXD 20% to 80%; C = 25 pF [4] - - 9 ns RXD t fall time 80% to20%; C = 15 pF [4] - - 5 ns f RXD 80% to20%; C = 25 pF [4] - - 9 ns RXD t difference between rise and fall time C = 15 pF [4] 4 - 4 ns (r-f) RXD C = 25 pF [4] 7 - 7 ns RXD Bus error flag t normal mode to standby delay time bus error flag set 3 - 10 s d(norm-stb) t standby to normal mode delay time bus error flag set 3 - 10 s d(stb-norm) Miscellaneous t TXEN clamp detection time 4.5 V < V < 5.5 V 1500 - 2600 s detCL(TXEN) CC t BGE clamp detection time 4.5 V < V < 5.5 V 1500 - 2600 s detCL(BGE) CC [1] Rise and fall time (10% to 90%) of tr(TXD) and tf(TXD) = 51 ns. [2] See Figure14. [3] See Figure15. [4] Guaranteed by design. [5] See Figure17. [6] Vdif=VBPVBM. [7] See Figure8. [8] See Figure10. [9] See Figure12. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 25 of 38

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P T N rodu JA1082 td(TXD-bus0) td(TXEN-busact) td(BGE-busact) XP ct d td(TXD-bus1) td(TXEN-busidle) td(BGE-busidle) S a e ta m sh TXD 0.5VIO ic e e o t n d u c t TXEN 0.5VIO o r s BGE 0.5VIO A ll inform Rev. 6 — 28 November 2012 ation provided in this document is subject to legal disclaim Fig 13. DeBtaPi laenddR BXtiMDm+−i33n000g.005 Vd0mm IiVVVOagram td(bus-RXD) td(bus-R−X3D0) mVttdd(ebt(uids−-leR3)X(0bD0u) s m+) V ttdd(ebt(uasc-tR)(XbDus) )+ −3tr0(b umsVact-bu−si3dl0e0) mtf(bVusact-busidle) tr(dif)(bus) tf(dif)(bus) 015aa28a000 1%%0 ers. F le x R a y © N n T X o P B d J 26 of 38 .V. 2012. All rights reserved. e transceiver A1082

TJA1082 NXP Semiconductors FlexRay node transceiver > 100 ns TXD 100 % of VIO 50 % of VIO 0 % of VIO t td(TXD-bus) td(TXD-bus) Vdif(VBP-VBM) (mV) > 600 100 % 80 % 300 0 t −300 20 % < −600 0 % tf(dif)(bus) tr(dif)(bus) 015aaa011 V is the transmitter test signal. dif Fig 14. Transmitter timing diagram Vdif(VBP-VBM) (mV) 22 ns 22 ns 400 300 0 −300 −400 30 ns 30 ns 30 ns td(bus-RXD) RXD td(bus-RXD) 100 % VIO 80 % VIO 50 % VIO 20 % VIO 0 % VIO tf(RXD) tr(RXD) 015aaa012 V is the receiver test signal. dif Fig 15. Normal receiver timing diagram TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 27 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 11. Test information +5 V 100 nF 1 14 VIO VCC 13 BP Rbus Cbus TJA1082 12 BM 4 RXD CRXD 015aaa013 Fig 16. Test circuit for measuring dynamic characteristics +5 V 100 nF 1 14 VIO VCC 13 1 nF BP ISO 7637 Rbus Cbus PULSE TJA1082 12 GENERATOR BM 1 nF 4 RXD 15 pF 015aaa014 The waveforms of the applied transients are in accordance with ISO7637, testpulses1,2a,3a and 3b. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz Fig 17. Test circuit for measuring automotive transients TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 28 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 12. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..7328 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig 18. Package outline SOT402-1 (TSSOP14) TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 29 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 30 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table13 and14 Table 13. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 14. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure19. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 31 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 32 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 14. Appendix 14.1 EPL 3.0.1 requirements implemented in the TJA1082 Table 15. EPL 3.0.1 req uirements implemented EPL 3.0.1 parameter Description - wake-up via dedicated data frames dBusTxDif difference between rise and fall times:  3ns R transmitter output voltage defined for DC bus load of 40  to 55 /100 pF DCLoad - transmission not allowed to start with DATA_1 dBDTx10, dBDTx01 transmitter delay:  75ns dBDTxia, dBDTxai transmitter idle-to-active/active-to-idle transition delay:  75ns dBDTxDM transmitter idle-to-active delay mismatch: 50ns uData0_LP receiver thresholds for detecting DATA_0 in low-power modes: 400 mV (min)/ 100mV (max) dBDRxai idle reaction time: 50 ns to 275ns dBDActivityDetection activity detection time 100 ns to 250 ns dBDRxia activity reaction time: 100 ns to 325 ns uData1  uData0 receiver threshold mismatch:  30 mV dBDRx10, dBDRx01 receiver delay:  75 ns dBusRx0BD, dBusRx1BD minimum bit time: 70 ns C_StarTxD, C_BDTxD maximum input capacitance on pin TXD: 10 pF dBDRxD + dBDRxD sum of RXD rise and fall times (20%/80%):  13 ns with a 15 pF load R15 F15 dBDTxRxai idle loop delay:  325 ns dStarTxActiveMax TXEN timeout: 650 s to 2600s - BD_Off mode defined (TJA1082 Power-off mode) dBDModeChange Reaction time to mode change request 100 s (max) - Short circuit currents: iBP ,iBM BP shorted to BM: < 60 mA; no time limit BMShortMax BPShortMax iBP ,iBM BP/BM shorted to ground: < 60 mA; no time limit GNDShortMax GNDShortMax iBP ,iBM BP/BM shorted to 5 V: < 60 mA; no time limit -5ShortMax -5ShortMax iBP ,iBM BP/BM shorted to 27 V: < 60 mA; no time limit BAT48ShortMax BAT27ShortMax iBP ,iBM BP/BM shorted to 48 V: < 72 mA; no time limit BAT48ShortMax BAT27ShortMax iBP ,iBM BP/BM shorted to 60 V: < 90 mA; for 400 ms (max) BAT60ShortMax BAT60ShortMax - ERRN output signals errors including wake-up status and wake-up source iBP , IBM leakage current on BP/BM in case of loss of GND 1600A (max) LeakGND LeakGND uBDUVV V undervoltage detection threshold: > 4 V CC CC uUV V undervoltage detection threshold: > 2V; detection timeout 1000 ms (max) IO IO dBDRV , dBDRV , dStarRV V /V /V undervoltage recovery time: 10ms (max) CC IO BAT CC IO BAT - Qualification according to AEC-Q100 temperature classes uESDExt 6kV ESD (min) on pins BP and BM according to HBM (100 pF/1500 ) uESDInt 2kV ESD (min) on all other pins according to HBM (100pF/1500 ) uESDIEC 6 kV ESD (min) on pins BP and BM according to IEC 61000-4-2 TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 33 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 15. Abbreviations Table 16. Abbreviations Abbreviation Description CDM Charged Device Model ECU Electronic Control Unit EMC ElectroMagnetic Compatibility EME ElectroMagnetic Emission EMI ElectroMagnetic Immunity ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PWON Power-on 16. References [1] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. B, FlexRay Consortium, Nov 2006 [2] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 3.0.1, FlexRay Consortium [3] AN — Application hint AN10365 - Surface mount reflow soldering description TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 34 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 17. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1082 v.6 20121128 Product data sheet - TJA1082 v.5 Modifications: • Section6.2.1, Section6.8: text revised • Table9: parameter values revised: V , V CC IO • Table12: parameter conditions revised: t r(bus)(act-idle) TJA1082 v.5 20120620 Product data sheet - TJA1082 v.4 TJA1082 v.4 20120613 Product data sheet - TJA1082 v.3 TJA1082 v.3 20110224 Product data sheet - TJA1082 v.2 TJA1082 v.2 20090810 Product data sheet - TJA1082 v.1 TJA1082 v.1 20090701 Preliminary data sheet - - TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 35 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 18.2 Definitions Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, Draft — The document is a draft version only. The content is still under authorized or warranted to be suitable for use in life support, life-critical or internal review and subject to formal approval, which may result in safety-critical systems or equipment, nor in applications where failure or modifications or additions. NXP Semiconductors does not give any malfunction of an NXP Semiconductors product can reasonably be expected representations or warranties as to the accuracy or completeness of to result in personal injury, death or severe property or environmental information included herein and shall have no liability for the consequences of damage. NXP Semiconductors and its suppliers accept no liability for use of such information. inclusion and/or use of NXP Semiconductors products in such equipment or Short data sheet — A short data sheet is an extract from a full data sheet applications and therefore such inclusion and/or use is at the customer's own with the same product type number(s) and title. A short data sheet is intended risk. for quick reference only and should not be relied upon to contain detailed and Applications — Applications that are described herein for any of these full information. For detailed and full information see the relevant full data products are for illustrative purposes only. NXP Semiconductors makes no sheet, which is available on request via the local NXP Semiconductors sales representation or warranty that such applications will be suitable for the office. In case of any inconsistency or conflict with the short data sheet, the specified use without further testing or modification. full data sheet shall prevail. Customers are responsible for the design and operation of their applications Product specification — The information and data provided in a Product and products using NXP Semiconductors products, and NXP Semiconductors data sheet shall define the specification of the product as agreed between accepts no liability for any assistance with applications or customer product NXP Semiconductors and its customer, unless NXP Semiconductors and design. It is customer’s sole responsibility to determine whether the NXP customer have explicitly agreed otherwise in writing. In no event however, Semiconductors product is suitable and fit for the customer’s applications and shall an agreement be valid in which the NXP Semiconductors product is products planned, as well as for the planned application and use of deemed to offer functions and qualities beyond those described in the customer’s third party customer(s). Customers should provide appropriate Product data sheet. design and operating safeguards to minimize the risks associated with their applications and products. 18.3 Disclaimers NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s Limited warranty and liability — Information in this document is believed to third party customer(s). Customer is responsible for doing all necessary be accurate and reliable. However, NXP Semiconductors does not give any testing for the customer’s applications and products using NXP representations or warranties, expressed or implied, as to the accuracy or Semiconductors products in order to avoid a default of the applications and completeness of such information and shall have no liability for the the products or of the application or use by customer’s third party consequences of use of such information. NXP Semiconductors takes no customer(s). NXP does not accept any liability in this respect. responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC60134) will cause permanent In no event shall NXP Semiconductors be liable for any indirect, incidental, damage to the device. Limiting values are stress ratings only and (proper) punitive, special or consequential damages (including - without limitation - lost operation of the device at these or any other conditions above those given in profits, lost savings, business interruption, costs related to the removal or the Recommended operating conditions section (if present) or the replacement of any products or rework charges) whether or not such Characteristics sections of this document is not warranted. Constant or damages are based on tort (including negligence), warranty, breach of repeated exposure to limiting values will permanently and irreversibly affect contract or any other legal theory. the quality and reliability of the device. Notwithstanding any damages that customer might incur for any reason Terms and conditions of commercial sale — NXP Semiconductors whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards products are sold subject to the general terms and conditions of commercial customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual Right to make changes — NXP Semiconductors reserves the right to make agreement is concluded only the terms and conditions of the respective changes to information published in this document, including without agreement shall apply. NXP Semiconductors hereby expressly objects to limitation specifications and product descriptions, at any time and without applying the customer’s general terms and conditions with regard to the notice. This document supersedes and replaces all information supplied prior purchase of NXP Semiconductors products by customer. to the publication hereof. TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 36 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver No offer to sell or license — Nothing in this document may be interpreted or 18.4 Licenses construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. NXP ICs with FlexRay functionality Export control — This document as well as the item(s) described herein This NXP product contains functionality that is compliant with the FlexRay may be subject to export control regulations. Export might require a prior specifications. authorization from competent authorities. These specifications and the material contained in them, as released by the Translations — A non-English (translated) version of a document is for FlexRay Consortium, are for the purpose of information only. The FlexRay reference only. The English version shall prevail in case of any discrepancy Consortium and the companies that have contributed to the specifications between the translated and English versions. shall not be liable for any use of the specifications. The material contained in these specifications is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material contained in the specifications requires a license to such Intellectual Property Rights. These specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. The FlexRay specifications have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications. The word FlexRay and the FlexRay logo are registered trademarks. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 28 November 2012 37 of 38

TJA1082 NXP Semiconductors FlexRay node transceiver 20. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 14 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 14.1 EPL 3.0.1 requirements implemented 2.1 Optimized for time triggered communication in the TJA1082. . . . . . . . . . . . . . . . . . . . . . . . 33 systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2 Low power management . . . . . . . . . . . . . . . . . 1 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3 Diagnosis and robustness . . . . . . . . . . . . . . . . 2 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 FlexRay conformance classes . . . . . . . . . . . . . 2 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 36 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 36 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 Functional description . . . . . . . . . . . . . . . . . . . 4 19 Contact information . . . . . . . . . . . . . . . . . . . . 37 6.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.1 Bus activity and idle detection . . . . . . . . . . . . . 7 6.1.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.3 Power-off mode . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.4 State transitions . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Power-up and power-down behavior . . . . . . . . 9 6.2.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 Bus wake-up via wake-up pattern. . . . . . . . . . 11 6.3.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.4 Bus error detection. . . . . . . . . . . . . . . . . . . . . 13 6.5 Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 13 6.6 TJA1082 flags. . . . . . . . . . . . . . . . . . . . . . . . . 13 6.7 TJA1082 status register . . . . . . . . . . . . . . . . . 14 6.8 Error signalling . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8.1 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8.2 Simple error indication mode . . . . . . . . . . . . . 16 6.9 SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Thermal characteristics . . . . . . . . . . . . . . . . . 18 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 23 11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 28 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 29 13 Soldering of SMD packages . . . . . . . . . . . . . . 30 13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 30 13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 30 13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 30 13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 November 2012 Document identifier: TJA1082

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: TJA1081TS,118 TJA1082TT,112 TJA1082TT,118 TJA1083TTJ TJA1081BTS,118