TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 • 24-Pin Advanced CMOS PLD JTL AND NT PACKAGE (TOP VIEW) • Virtually Zero Standby Power • CLK/I 1 24 VCC Propagation Delay Time: I 2 23 I/O/Q I, I/O to I/O in the Turbo Mode I 3 22 I/O/Q -25C . . . 25 ns Max I 4 21 I/O/Q -30I . . . 30 ns Max I 5 20 I/O/Q I, I/O to I/O in the Zero-Power Mode I 6 19 I/O/Q -25C . . . 35 ns Max I 7 18 I/O/Q -30I . . . 40 ns Max I 8 17 I/O/Q CLK to Q I 9 16 I/O/Q -25C . . . 15 ns Max I 10 15 I/O/Q -30I . . . 20 ns Max I 11 14 I/O/Q • Variable Product Term Distribution Allows GND 12 13 I More Complex Functions to Be Implemented FN PACKAGE • Each Output Is User-Programmable for (TOP VIEW) RPoeglairsittey,r eadn do rO Cuotpmubt iEnnataobrliea lC Oopnetrroaltion, LK/I C CCO/Q O/Q • II C N V I/ I/ Extra Terms Provide Logical Synchronous 4 3 2 1 28 27 26 Set and Asynchronous Reset Capability I 5 25 I/O/Q • I 6 24 I/O/Q Preload Capability on All Registered I 7 23 I/O/Q Outputs Allow for Improved Device Testing NC 8 22 NC • UV Light Erasable Cell Technology Allows I 9 21 I/O/Q for: I 10 20 I/O/Q Reconfigurable Logic I 11 19 I/O/Q Reprogrammable Cells 12 1314 15 16 1718 Full Factory Testing for High I I D C IQ Q Programming Yield N N O/ O/ G • I/ I/ Programmable Design Security Bit NC−No internal connection Prevents Copying of Logic Stored in Device Pin assignments in operating mode • Package Options Include Plastic Dual-In-Line and Clip Carrier [for One-Time-Programmable (OTP) Devices] and Ceramic Dual-In-Line Windowed Package . AVAILABLE OPTIONS PACKAGE TYPE TA CERAMIC WINDOWED PLASTIC PLASTIC RANGE DUAL-IN-LINE DUAL-IN-LINE CHIP CARRIER (JTL) (NT) (FN) 0°C to 75°C TICPAL22V10Z-25CJTL TICPAL22V10Z-25CNT TICPAL22V10Z-25CFN −40°C to 85°C NA TICPAL22V10Z-30INT TICPAL22V10Z-30IFN EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 description The CMOS PLD devices feature variable product terms, flexible outputs, and virtually zero standby power. It combines TI’s EPIC™ (Enhanced Processed Implanted CMOS) process with ultraviolet-light-erasable EPROM technology. Each output has an output logic macrocell (OLM) configuration allowing for user definition of the output type. This device provides reliable, low-power substitutes for numerous high-performance TTL PLDs with gate complexities between 300 and 800 gates. The TICPAL22V10Z has 12 dedicated inputs and 10 user-definable outputs. Individual outputs can be programmed as registered or combinational and inverting or noninverting as shown in the OLM diagram. These ten outputs are enabled through the use of individual product terms The variable product-term distribution on this device removes rigid limitation to a maximum of eight product terms per output. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. The variable allocation of product terms allows for far more complex functions to be implemented in this device than in previously available devices. With features such as the programmable OLMs and the variable product-term distribution, the TICPAL22V10Z offers quick design and development of custom LSI functions. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs can be implemented with this device. Design complexity is enhanced by the addition of synchronous set and asynchronous reset product terms. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0 independently of the clock. The output logic level after set or reset will depend on the polarity selected during programming. Output registers of this device can be preloaded to any desired state during testing, thus allowing for full logical verification during product testing. The TICPAL22V10Z has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating tested under MIL-STD-883C, Method 3015.6. However, care should be exercised in handling these devices, as exposure to ESD may result in a degradation of the device parametric performance. The floating-gate programmable cells allow the devices to be fully programmed and tested before assembly to assure high field programming yield and functionality. They are then erased by ultraviolet light before packaging. The TICPAL22V10Z-25C is characterized for operation from 0°C to 75°C. The TICPAL22V10Z-30I is characterized for operation from −40°C to 85°C. design security The ’PAL22V10Z contains a programmable design security cell. Programming this cell will disable the read verify and programming circuitry protecting the design from being copied. The security cell is usually programmed after the design is finalized and released to production. A secured device will verify as if every location in the device is programmed. Because programming is accomplished by storing an invisible charge instead of opening a metal link, the ’22V10Z cannot be copied by visual inspection. Once a secured device is fully erased, it can be reprogrammed to any desired configuration. • 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 functional block diagram (positive logic) C1 Set & 1S 44 x 132 Reset R 8 1 Output Logic I/O/Q Macrocell EN 10 I/O/Q 22 EN CLK/I 12 I/O/Q EN 14 I/O/Q EN 16 I/O/Q EN 16 I/O/Q 11 22 EN I 14 10 I/O/Q EN 12 I/O/Q EN 10 I/O/Q EN 8 I/O/Q EN 10 10 10 denotes programmable cell inputs • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 et s e R us ers) nost ogi synchro all re O/Q O/Q O/Q O/Q O/Q A(t I/ I/ I/ I/ I/ 3 2 1 0 9 2 2 2 2 1 MACROCELL P = 5808R = 5809 MACROCELL P = 5810R = 5811 MACROCELL P = 5812R = 5813 MACROCELL P = 5814R = 5815 MACROCELL P = 5816R = 5817 0 4 6 3 2 3 8 2 nt 24 e m e cr 20 n I 6 1 2 1 8 ) c i g o 4 l e v i it 0 s o 0 6 0 0 4 2 6 2 6 0 (p 39 44 88 92 145 149 211 215 286 m 2 3 4 5 1 a s gr K/I ber I I I I dia CL FirstCellNum c i g o l • 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 et Ss) s er oust ngi oe O/Q O/Q O/Q O/Q O/Q ynchro all r I/ I/ I/ I/ I/ S(t I 8 7 6 5 4 3 1 1 1 1 1 1 MACROCELL P = 5818R = 5819 MACROCELL P = 5820R = 5821 MACROCELL P = 5822R = 5823 MACROCELL P = 5824R = 5825 MACROCELL P = 5826R = 5827 ell. c er st gi e e r h s t ell i c R) e ( h ntd t en ma Cell Number + Increell is the polarity cell = First e (P) c ber L th mL E 2904 3608 3652 4268 4312 4840 4884 5324 5368 5720 5764 ell NuROC CC 6 7 8 9 10 11 ble MA ah I I I I I I mc mea grade Pronsi I • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 output logic macrocell (OLM) description A great amount of architectural flexibility is provided by the user-configurable macrocell output options. The macrocell consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like a standard TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input. The Q and Q outputs are made available to the output select multiplexer. The asynchronous reset and synchronous set controls are available in all flip-flops. The select multiplexers are controlled by programmable cells. The combination of these programmable cells will determine which macrocell functions are implemented. It is this user control of the architectural structure that provides the generic flexibility of this device. output logic macrocell diagram Output Logic Macrocell MUX 2 3 AR R 1D 0 C1 1 SS 1S 1 0 G 0 3 From Clock Buffer S0 MUX 1 1 G1 S1 AR = asynchronous reset SS = synchronous set • 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 output logic macrocell options (see Figure 1) R R 1D 1D C1 C1 1S 1S S1 = 0 S1 = 0 S0 = 0 S0 = 1 REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT S1 = 1 S1 = 1 S0 = 0 S0 = 1 I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE CELL SELECT FEEDBACK AND OUTPUT CONFIGURATION S1 S0 0 0 Register feedback Registered Active low 0 1 Register feedback Registered Active high 1 0 I/O feedback Combinational Active low 1 1 I/O feedback Combinational Active high 0 = erased cell, 1 = programmed cell S1 and S0 are select-function cells as shown in the output logic macrocell diagram. Figure 1. Resultant Macrocell Feedback and Output Logic After Programming • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7

TICPAL22V10Z-25C ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V +0.5 V I CC Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40 mA O O CC Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or NT package . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: JTL package . . . . . . . . . . . . . . . . . . . . . 300°C Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V Driving TTL −3.2 IOH High-level output current mA Driving CMOS −4 Driving TTL 16 IOL Low-level output current mA Driving CMOS 4 Clock high 10 tw Pulse duration Clock low 10 ns Asynchronous reset 20 Input or feedback 17 tsu Setup time, turbo mode Asynchronous reset inactive 20 ns Synchronous preset inactive 20 Input or feedback 25 tsu Setup time, zero-power mode Asynchronous reset inactive 30 ns Synchronous preset inactive 30 th Hold time Input or feedback 0 ns TA Operating free-air temperature 0 75 °C • 8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITION MIN TYP† MAX UNIT VCC = 4.75 V, IOH = −3.2 mA for TTL 4 4.8 VOH VCC = 4.75 V, IOH = −4 mA for CMOS 3.86 4.7 V VCC = 4.75 V, IOL = 16 mA for TTL 0.25 0.5 VOL V VCC = 4.75 V, IOL = 4 mA for CMOS 0.07 0.4 IOZH VCC = 5.25 V, VO = 2.7 V 0.01 10 μA IOZL VCC = 5.25 V, VO = 0.5 V −0.01 −10 μA IIH VCC = 5.25 V, VI = 5.25 V 0.01 10 μA IIL VCC = 5.25 V, VI = 0.5 V −0.01 −10 μA IO‡ VCC = 5.25 V, VO = 0.5 V −30 −45 −90 mA ICC§ VOCuCtp =u t5s .o2p5e Vn,, VZeI r=o 0-p oorw VeCr Cm,ode 10 100 μA I 6 Ci VI = 2 V, f = 1 MHz pF I/O 10 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3) FROM TO PARAMETER MIN TYP† MAX UNIT (INPUT) (OUTPUT) Without feedback 50 66 fmax¶ MHz With feedback 31.2 55 Turbo mode 16 25 tpd I, I/O O, I/O ns Zero-power mode 21 35 Turbo mode 18 30 tpd Asynchronous Q ns Zero-power mode RESET 23 40 tpd CLK↑ Q 10 15 ns Turbo mode 15 25 ten I, I/O I, Q, I/O ns Zero-power mode 20 35 Turbo mode 15 25 tdis I, I/O I, Q, I/O ns Zero-power mode 17 35 †All typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. §Disabled outputs are tied to GND or VCC. ¶fmax (with feedback) = tsu (cid:2) tpd1(CLK to Q); fmax (without feedback) = tw(high) (cid:2)1 tw(low) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9

TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V +0.5 V I CC Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40 mA O O CC Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or NT package . . . . . . . . . . . . . . . . 260°C Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V Driving TTL −3.2 IOH High-level output current Driving CMOS −4 mA Driving TTL 16 IOL Low-level output current Driving CMOS 4 mA Clock high 12 tw Pulse duration Clock low 12 ns Asynchronous reset 30 Input or feedback 22 tsu Setup time, turbo mode Asynchronous reset inactive 25 ns Synchronous preset inactive 25 Input or feedback 30 tsu Setup time, zero-power mode Asynchronous reset inactive 35 ns Synchronous preset inactive 35 th Hold time Input or feedback 0 ns TA Operating free-air temperature −40 85 °C • 10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITION MIN TYP† MAX UNIT VCC = 4.5 V, IOH = −3.2 mA for TTL 4 4.8 VOH VCC = 4.5 V, IOH = −4 mA for CMOS 3.86 4.7 V VCC = 4.5 V, IOL = 16 mA for TTL 0.25 0.5 VOL V VCC = 4.5 V, IOL = 4 mA for CMOS 0.07 0.4 IOZH VCC = 5.5 V, VO = 2.7 V 0.01 10 μA IOZL VCC = 5.5 V, VO = 0.5 V −0.01 −10 μA IIH VCC = 5.5 V, VI = 5.5 V 0.01 10 μA IIL VCC = 5.5 V, VI = 0.5 V −0.01 −10 μA IO‡ VCC = 5.5 V, VO = 0.5 V −30 −45 −90 mA ICC§ VOCuCtp =u t5s .o5p Ve,n, VZeI r=o 0-p oorw VeCr Cm,ode 10 100 μA I 6 Ci VI = 2 V, f = 1 MHz pF I/O 10 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3) FROM TO PARAMETER MIN TYP† MAX UNIT (INPUT) (OUTPUT) Without feedback 41.6 66 fmax¶ MHz With feedback 23.8 55 Turbo mode 16 30 tpd I, I/O O, I/O ns Zero-power mode 21 40 Turbo mode 18 35 tpd Asynchronous Q ns Zero-power mode RESET 23 45 tpd CLK↑ Q 10 20 ns Turbo mode 15 30 ten I, I/O I, Q, I/O ns Zero-power mode 20 40 Turbo mode 15 30 tdis I, I/O I, Q, I/O ns Zero-power mode 17 40 †All typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation. §Disabled outputs are tied to GND or VCC. ¶fmax (with feedback) = tsu (cid:2) tpd1(CLK to Q); fmax (without feedback) = tw(high) (cid:2)1 tw(low) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 preload procedure for registered outputs (see Notes 2 and 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to setup through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. The output level depends on the polarity selected during programming. Step 1. With V at 5 V and pin 1 at V , raise pin 8 to V . CC IL IHH Step 2. Apply either V or V to the output corresponding to the register to be preloaded. IL IH Step 3. Pulse pin 1, clocking in preload data. Step 4. Remove output voltage, then lower pin 8 to V . Preload can be verified by observing the voltage level IL at the output pin. VIHH Pin 8 VIL tsu td td tw VIH CLK/I VIL VIH VOH Registered I/O Input Output VIL VOL Figure 2. Preload Waveforms NOTES:2. Pin numbers shown are for the JTL and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly. 3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V. programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. • 12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION 5 V (see Note D) S1 300 Ω From Output Test Under Test Point CL 390 Ω (see Note A) LOAD CIRCUIT FOR 3-STATE OUTPUTS 3 V 3 V High-Level CLK 1.5 V 1.5 V 1.5 V Pulse 0 0 tsu th tw 3 V IDnpautat 1.5 V 1.5 V Low-Level 3 V 1.5 V 1.5 V 0 Pulse (see Note B) 0 (see Note B) VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3 V 3 V Input 1.5 V 1.5 V Output 0 Control 1.5 V 1.5 V (low-level tpd tpd enabling) 0 In-Phase VOH ten tdis (see Note B) 1.5 V 1.5 V Output ≈ VOL 3.3 V tpd tpd WSa1v eCfolorsme d1 1.5 V VOL + 0.5 V VOH (see Note C) VOL Out-of-Phase 1.5 V 1.5 V tdis Output ten (see Note D) VOL Waveform 2 VOH S1 Open PRVOOPALTGAAGTEIO WNA DVEELFAOYR TMIMSES (see Note C) 1.5 V V≈O 0H V − 0.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES:A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. All input pulses have the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr = tf = 2 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 3. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 special design features True CMOS Outputs: Each TICPAL22V10Z output is designed with a P-channel pull-up transistor and an N-channel pull-down transistor, a true CMOS output with rail-to-rail output switching. This provides direct interface to CMOS logic, memory, or ASIC devices without the need for a pull-up resistor. The CMOS output has 16-mA drive capability, which makes the TICPAL22V10Z an ideal substitute for bipolar PLDs. The electrical characteristics of this device show the output under both CMOS and TTL conditions. Simultaneous Switching: High-performance CMOS devices often have output glitches on nonswitched outputs when a large number of outputs are switched simultaneously. This glitch is commonly referred to as ”ground bounce” and is most noticeable on outputs held at VOL (low-level output voltage). Ground bounce is caused by the voltage drop across the inductance in the package lead when current is switched (dv α I x di/dt). One solution is to restrict the number of outputs that can switch simultaneously. Another solution is to change the device pinout such that the ground is located on a low-inductance package pin. TI opted for a third option in order to maintain pinout compatibility and eliminate functional constraints. This option controls the output transistor turn-on characteristics and puts a limit on the instantaneous current available to the load, much like the I resistor in a TTL circuit. OS Wake-Up Features: The TICPAL22V10Z employs input signal transition detection techniques to power up the device from the standby-power mode. The transition detector monitors all inputs, I/Os, and feedback paths. Whenever a transition is sensed, the detector activates the power-up mode. The device will remain in the power-up mode until the detector senses that the inputs and outputs have been static for about 40 ns; thereafter, the device returns to the standby mode. Turbo Mode or Zero-Power Mode: When the turbo cell is programmed, the device will be set to the power-up mode. Therefore, the delay associated with its transition detection and power up will be eliminated. This is how the faster propagation delays and shorter setup times are obtained in the turbo mode. The turbo mode and the associated speed increase can be effectively simulated with the turbo cell erased, if a series of adjacent input, I/O, or feedback edges occur with an interval of about 25 ns or less between these adjacent edges. Under these conditions, the TICPAL22V10Z will never have the opportunity to power down due to the frequency of the adjacent edges. Power Up: The TICPAL22V10Z device configuration bits (power mode, and macrocell configuration) are read at the first input transition after a monotonic power up. When completed, the TICPAL22V10Z is in its designed configuration. The use of an initializing device reset is necessary in applications where registered feedback is used to ensure the TICPAL22V10Z is in a known state at the beginning of system operation. Power Dissipation: Power dissipation of the TICPAL22V10Z is defined by three contributing factors, and the total power dissipation is the sum of all three. Standby Power: The product of V and the standby I . The standby current is the reverse current CC CC through the diodes that are reversed biased. This current is very small, and for circuits that remain in static condition for a long time, this low amount of current can become a major performance advantage. Dynamic Power: The product of V and the dynamic current. This dynamic current flows through the CC device only when the transistors are switching from one logic level to the other. The total dynamic current for the TICPAL22V10Z is dependent upon the users’ configuration of the device and the operating frequency. Output loading can be a source of additional power dissipation. Interface Power: The product of I (interface) and V . The total interface power is dependent on the CC CC number of inputs at the TTL V level. The interface power can be eliminated by the addition of a pull-up OH resistor. • 14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 Even though power dissipation is a function of the user’s device configuration and the operating frequency, the TICPAL22V10Z is a lower powered solution than either the quarter-powered or half-powered bipolar devices. The virtually zero standby power feature makes the TICPAL22V10Z the device of choice for low-duty-cycle applications. programming and erasability Programming of the TICPAL22V10Z is achieved through floating-gate avalanche injection techniques. The charge trapped on the floating gate remains after power has been removed, allowing for the nonvolatility of the programmed data. The charge can be removed by exposure to light with wavelengths of less than 400 nm (4000 Å). The recommended erasure wavelength is 253.7 nm (2537 Å), with erasure time of 60 to 90 minutes, using a light source with a power rating of 12000 μW/cm2 placed within 2.5 cm (one inch) of the device. The TICPAL22V10Z is designed for programming endurance of 1000 write/erase cycles with a data retention of ten years. To guarantee maximum data retention, the window on the device should be covered by an opaque label. The fluorescent light in a room can erase a unit in three years or, in the case of a direct sunlight, erasure can be complete in one week. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS NORMALIZED SUPPLY CURRENT OUTPUT CURRENT vs vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE (10-BIT COUNTER) 400 C 1.4 VCC = 5 V °5 120000 TA = 25°C IOL = 2V,TA 1.3 VVVCCCCCC === 445.. 75V5 V V − mA 70 = 5 C 1.2 VVCCCC == 55..255 V V ent 40 VC 1.1 ut Curr 20 −IOH ent at 1 − OutpO 107 pply Curr 0.9 I 4 u S 2 zed 0.8 CL = 50 pF ali fclock = 23.8 MHz m Duty Cycle = 50% or 0.7 0 1 2 3 4 5 N −50 −25 0 25 50 75 100 VO − Output Voltage − V TA − Free-Air Temperature − °C Figure 4 Figure 5 SUPPLY CURRENT vs NORMALIZED PROPAGATION DELAY TIME CLOCK FREQUENCY vs (10-BIT COUNTER) SUPPLY VOLTAGE 100 1.15 VTAC C= =2 55° CV = 5 V CL = 50 pF C CLK to Q and Turbo Mode 80 Duty cycle = 50% VC 1.1 A Turbo Bit on at − m me Zero-Power Mode ent 60 y Ti 1.05 r a ur el C D y n Suppl 40 agatio 1 − p C ro C P I 20 zed 0.95 TA = 25 °C Turbo Bit off mali CR1L == 5300 0p ΩF or R2 = 390 Ω 0 N 0.9 100 1 k 10 k 100 k 1 M 10 M 100 M 4.5 4.75 5 5.25 5.5 fclock − Clock Frequency − Hz VCC − Supply Voltage − V Figure 6 Figure 7 • 16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TICPAL22V10Z-25C, TICPAL22V10Z-30I ™ EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS CHANGE IN NORMALIZED PROPAGATION DELAY TIME PROPAGATION DELAY TIME vs vs FREE-AIR TEMPERATURE LOAD CAPACITANCE C 1.2 30 °25 VCCL C= =5 05 pVF VTAC C= =2 55 °VC = R1 = 300 Ω s R1 = 300 Ω TA R2 = 390 Ω − n 25 R2 = 390 Ω at 1.1 me Time ay Ti 20 y el a D el n pagation D 1 Propagatio 1150 tPHL ro n alized P 0.9 = CLK to Q hange i 5 tPLH m C = Zero-Power Mode r o = Turbo Mode N 0.8 0 −50 −25 0 25 50 75 100 0 100 200 300 400 500 600 700 800 TA − Free-Air Temperature −°C CL − Load Capacitance − pF Figure 8 Figure 9 CHANGE IN PROPAGATION DELAY TIME vs NUMBER OF OUTOUTS SWITCHING 1.5 VCC = 5 V TA = 25 °C ns CL = 50 pF − R1 = 300 Ω e R2 = 390 Ω m Ti Registered Macrocell y 1 a el D on tPHL ati g a p Pro 0.5 tPLH n e i g n a h C 0 1 2 3 4 5 6 7 8 9 10 Number of Outputs Switching Figure 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17

None

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TEXAS: Austin: (512) 250-6769 COLORADO: Anthem (303) 790-4500; Arrow/Schweber CANADA: Calgary: Future (403) 235-5325; Dallas: (214) 917-1264 (303) 799-0258; Hall-Mark (303) 790-1662; Marshall (303) Edmonton: Future (403) 438-2858; Houston: (713) 778-6592 451-8383; Wyle (303) 457-9953. Montreal: Arrow/Schweber (514) 421-7411; Future (514) Midland: (915) 561-7137 CONNECTICUT: Anthem (203) 575-1575; Arrow/Schweber 694-7710; Marshall (514) 694-8142 UTAH: Salt Lake CIty: (801) 466-8972 (203) 265-7741; Hall-Mark (203) 271-2844; Marshall (203) Ottawa: Arrow/Schweber (613) 226-6903; Future (613) WISCONSIN: Waukesha: (414) 798-1001 265-3822. 820-8313. CANADA: Nepean: (613) 726-1970 FLORIDA:Fort Lauderdale:Arrow/Schweber (305) Quebec: Future (418) 897-6666. RStic. hLmauornedn tH: (i5ll1: 4(4) 1363)5 8-88349-92181 492797--84280800;. Halll-Mark (305) 971-9280; Marshall (305) TFourtuornet o(4: 1A6r)r o6w12/S-9c2h0w0e;b Mera (r4sh1a6l)l 6(47106-7) 746598;- 8046. Orlando: Arrow/Schweber (407) 333-9300; Hall-Mark (407) 830-5855; Marshall (407) 767-8585; Zeus (407) 788-9100. Vancouver: Arrow/Schweber (604) 421-2333; Future (604) 294-1166. Tampa: Hall-Mark (813) 541-7440; Marshall (813) 573-1399. TI Regional GEORGIA: Arrow/Schweber (404) 497-1300; Hall-Mark (404) 623-4400; Marshall (404) 923-5750. ILLINOIS: Anthem (708) 884-0200; Arrow/Schweber (708) Technology 250-0500; Hall-Mark (312) 860-3800; Marshall (708) 490-0155; Newark (312)784-5100. INDIANA: Arrow/Schweber (317) 299-2071; Hall-Mark TI Die Processors (317) 872-8875; Marshall (317) 297-0483. Centers IOWA: Arrow/Schweber (319) 395-7230. KANSAS: Arrow/Schweber (913) 541-9542; Hall-Mark Chip Supply (407) 298-7100 (913) 888-4747; Marshall (913) 492-3121. CALIFORNIA: Irvine: (714) 660-8140 MARYLAND: Anthem (301) 995-6640; Arrow/Schweber Elmo Semiconductor (818) 768-7400 Santa Clara: (408) 748-2222 (301) 596-7800; Hall-Mark (301) 988-9800; Marshall (301) Minco Technology Labs (512) 834-2022 622-1118; Zeus (301) 997-1118. GEORGIA: Norcross: (404) 662-7945 MASSACHUSETTS: Anthem (508) 657-5170; ILLINOIS: Arlington Heights: (708) 640-2909 Arrow/Schweber (508) 658-0900; Hall-Mark (508) INDIANA: Indianapolis: (317) 573-6400 667-0902; Marshall (508) 658-0810; Wyle (617) 272-7300; MASSACHUSETTS: Waltham: (617) 895-9196 Zeus (617) 246-8200. MEXICO: Mexico City: 491-70834 MINNESOTA: Minneapolis: (612) 828-9300 TEXAS: Dallas: (214) 917-3881 CANADA: Nepean: (613) 726-1970 Customer Response Center TOLL FREE: (800) 336-5236 OUTSIDE USA: (214) 995-6611 (8:00 a.m. − 5:00 p.m. CST) D0892 ©1992 Texas Instruments Incorporated SRPS007C

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PAL22V10Z-25CJTL ACTIVE CDIP JT 24 15 TBD A42 N / A for Pkg Type 0 to 75 22V10Z -25CJTL (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 Addendum-Page 2

MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN A PINS ** 24 28 DIM 24 13 1.280 1.460 A MAX (32,51) (37,08) B A MIN 1.240 1.440 (31,50) (36,58) 0.300 0.291 B MAX (7,62) (7,39) 1 12 0.070 (1,78) 0.245 0.285 B MIN 0.030 (0,76) (6,22) (7,24) 0.320 (8,13) 0.100 (2,54) MAX 0.015 (0,38) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.100 (2,54) 0.008 (0,20) 4040110/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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