THS7372 www.ti.com SBOS578–AUGUST2011 4-Channel Video Amplifier with One CVBS and Three Full-HD Filters with 6-dB Gain CheckforSamples:THS7372 FEATURES DESCRIPTION 1 • OneSDTVVideoAmplifierforCVBSVideo Fabricated using the revolutionary, complementary 2345 Silicon-Germanium (SiGe) BiCom3X process, the • ThreeFixedFull-HD1080p60Filtersfor THS7372 is a low-power, single-supply, 2.7-V to 5-V, Y’/P’ /P’ ,G’B’R’,orComputerRGBOutputs B R four-channel integrated video buffer. It incorporates • Sixth-OrderLow-PassFilters: one SDTV filter and three fixed Full-HD (also known – SDChannel: –3dBat9.5MHz as True-HD) HDTV filters. All filters feature sixth-order Butterworth characteristics that are useful – FixedFull-HDChannels:–3dBat72MHz as digital-to-analog converter (DAC) reconstruction • VersatileInputBiasing: filters or as analog-to-digital converter (ADC) – DC-Coupledwith300-mVOutputShift anti-aliasingfilters. – AC-CoupledwithSync-TipClamporBias The THS7372 has flexible input coupling capabilities, • Built-in6-dBGain(2V/V) and can be configured for either ac- or dc-coupled inputs. The 300-mV output level shift allows for a full • +2.7-Vto+5-VSingle-SupplyOperation sync dynamic range at the output with 0-V input. • Rail-to-RailOutput: AC-coupled modes include a transparent sync-tip – OutputSwingswithin100mVfromthe clamp for CVBS, Y', and G'B'R' signals. AC-coupled biasing for P' /P' channels can easily be achieved Rails:AllowsACorDCOutputCoupling B R byaddinganexternalresistortoV . – SupportsDrivingTwoVideoLines/Channel S+ The THS7372 is an ideal choice for a wide range of • LowTotalQuiescentCurrent:23.4mAat3.3V video buffer applications. Its rail-to-rail output stage • DisabledSupplyCurrentFunction:0.1μA with 6-dB gain allows for both ac and dc line driving. • LowDifferentialGain/Phase:0.2%/0.35° The ability to drive two lines, or 75-Ω loads, allows for maximum flexibility as a video line driver. The • RoHS-CompliantTSSOP-14Package 23.4-mA total quiescent current at 3.3 V and 0.1 μA (disabled mode) makes it well-suited for systems that APPLICATIONS mustmeetpower-sensitiveEnergyStar®standards. • SetTopBoxOutputVideoBuffering The THS7372 is available in a TSSOP-14 package • PVR/DVDROutputBuffering thatislead-freeandgreen(RoHS-compliant). • BluRay™OutputVideoBuffering THS7372 CVBS Out 75W CVBS 1 CVBS IN CVBS OUT 14 37.4W 2 NC DIS CVBS 13 DCiVsBabSle +2.7+ V5 tVo 3 VS+ GND 12 Encoder Y'/G' 37.4W 45 NFHCD1 IN FHDDIS1 OFHUDT 1110 DFHisDable 75WY'/G' Out SOC/DAC/ P’B/B' 67 FFHHDD23 IINN FFHHDD23 OOUUTT 98 75WP'B/B' Out 37.4W P'R/R' Out 75W P’R/R' 37.4W Single-Supply,DC-Input/DC-OutputCoupledVideoLineDriver 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. BluRayisatrademarkofBlu-rayDiscAssociation(BDA). 2 EnergyStarisaregisteredtrademarkofEnergyStar. 3 MacrovisionisaregisteredtrademarkofMacrovisionCorporation. 4 Allothertrademarksarethepropertyoftheirrespectiveowners. 5 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

THS7372 SBOS578–AUGUST2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. PACKAGE/ORDERINGINFORMATION(1)(2) PACKAGE PACKAGE TRANSPORT ECOSTATUS(2) PRODUCT PACKAGE-LEAD DESIGNATOR MARKING MEDIA,QUANTITY THS7372IPW Rails,90 TSSOP-14 PW THS7372 Pb-Free,Green THS7372IPWR TapeandReel,2000 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. (2) ThesepackagesconformtoLead(Pb)-freeandgreenmanufacturingspecifications.Additionaldetailsincludingspecificmaterialcontent canbeaccessedatwww.ti.com/leadfree. GREEN:TIdefinesGreentomeanLead(Pb)-Freeandinaddition,useslesspackagematerialsthatdonotcontainhalogens,including bromine(Br),orantimony(Sb)above0.1%oftotalproductweight.N/A:NotyetavailableLead(Pb)-Free;forestimatedconversion dates,gotowww.ti.com/leadfree.Pb-FREE:TIdefinesLead(Pb)-FreetomeanRoHScompatible,includingaleadconcentrationthat doesnotexceed0.1%oftotalproductweight,and,ifdesignedtobesoldered,suitableforuseinspecifiedlead-freesoldering processes. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. THS7372 UNIT Supplyvoltage,V toGND 5.5 V S+ Inputvoltage,V –0.4toV V I S+ Outputcurrent,I ±90 mA O Continuouspowerdissipation SeeThermalInformationTable Maximumjunctiontemperature,anycondition(2),T +150 °C J Maximumjunctiontemperature,continuousoperation,long-termreliability(3),T +125 °C J Storagetemperaturerange,T –60to+150 °C STG Humanbodymodel(HBM) 4000 V ESDrating: Chargedevicemodel(CDM) 1000 V Machinemodel(MM) 200 V (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. (2) Theabsolutemaximumjunctiontemperatureunderanyconditionislimitedbytheconstraintsofthesiliconprocess. (3) Theabsolutemaximumjunctiontemperatureforcontinuousoperationislimitedbythepackageconstraints.Operationabovethis temperaturemayresultinreducedreliabilityand/orlifetimeofthedevice. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,V 2.7 5 V S+ Ambienttemperature,T –40 +85 °C A 2 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 ELECTRICAL CHARACTERISTICS: V = +3.3 V S+ AtT =+25°C,R =150ΩtoGND,anddc-coupledinput/output,unlessotherwisenoted. A L THS7372 TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNITS LEVEL(1) ACPERFORMANCE:SD(CVBS)CHANNEL Passbandbandwidth –1dB;V =0.2V and2V 6.6 8.2 10 MHz B O PP PP Small-andlarge-signalbandwidth –3dB;V =0.2V and2V 8 9.5 11 MHz B O PP PP Withrespectto500kHz(2),f=6.75MHz –0.9 0.2 1.2 dB B Attenuation Withrespectto500kHz(2),f=27MHz 42 54 dB B Groupdelay f=100kHz 78 ns C Groupdelayvariation f=5.1MHzwithrespectto100kHz 11 ns C Channel-to-channeldelay 0.3 ns C Differentialgain NTSC/PAL 0.2/0.35 % C Differentialphase NTSC/PAL 0.35/0.5 Degrees C Totalharmonicdistortion f=1MHz,V =1.4V –69 dB C O PP 100kHzto6MHz,non-weighted 70 dB C Signal-to-noiseratio 100kHzto6MHz,unifiedweighting 78 dB C Allchannels,T =+25°C 5.7 6 6.3 dB A A Gain Allchannels,T =–40°Cto+85°C 5.65 6.35 dB B A f=6.75MHz 0.7 Ω C Outputimpedance Disabled 20||3 kΩ||pF C Returnloss f=6.75MHz 47 dB C Crosstalk f=1MHz,SDchanneltoFHDchannels –82 dB C ACPERFORMANCE:FULL-HD(FHD)CHANNELS Passbandbandwidth –1dB;V =0.2V and2V 53 60 66 MHz B O PP PP Small-andlarge-signalbandwidth –3dB;V =0.2V and2V 60 72 83 MHz B O PP PP Withrespectto500kHz(2),f=54MHz –0.5 0.6 2 dB B Attenuation Withrespectto500kHz(2),f=148MHz 33 40 dB B Groupdelay f=100kHz 12 ns C Groupdelayvariation f=54MHzwithrespectto100kHz 4.5 ns C Channel-to-channeldelay 0.3 ns C Totalharmonicdistortion f=20MHz,V =1.4V –54 dB C O PP 100kHzto60MHz,non-weighted 60 dB C Signal-to-noiseratio 100kHzto60MHz,,unifiedweighting 70 dB C Allchannels,T =+25°C 5.7 6 6.3 dB A A Gain Allchannels,T =–40°Cto+85°C 5.65 6.35 dB B A f=60MHz 4 Ω C Outputimpedance Disabled 2||3 kΩ||pF C Returnloss f=60MHz 32 dB C f=6.75MHz,FHDchannelstoSDchannel –68 dB C Crosstalk f=25MHz,FHDtoFHDchannels –54 dB C (1) Testlevels:(A)100%testedat+25°C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulationonly.(C)Typicalvalueonlyforinformation. (2) 3.3-Vsupplyfilterspecificationsareensuredby100%testingat5-Vsupplytogetherwithdesignandcharacterization. Copyright©2011,TexasInstrumentsIncorporated 3

THS7372 SBOS578–AUGUST2011 www.ti.com ELECTRICAL CHARACTERISTICS: V = +3.3 V (continued) S+ AtT =+25°C,R =150ΩtoGND,anddc-coupledinput/output,unlessotherwisenoted. A L THS7372 TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNITS LEVEL(1) DCPERFORMANCE V =0V,SDchannel 200 305 400 mV A IN Biasedoutputvoltage V =0V,FHDchannels 200 300 400 mV A IN Inputvoltagerange DCinput,limitedbyoutput –0.1/1.46 V C V =–0.1V,SDchannel 140 200 μA A IN Sync-tipclampchargecurrent V =–0.1V,FHDchannels 280 400 μA A IN Inputimpedance 800||2 kΩ||pF C OUTPUTCHARACTERISTICS R =150Ωto+1.65V 3.15 V C L R =150ΩtoGND 2.85 3.1 V A L Highoutputvoltageswing R =75Ωto+1.65V 3.1 V C L R =75ΩtoGND 3 V C L R =150Ωto+1.65V(V =–0.2V) 0.06 V C L IN R =150ΩtoGND(V =–0.2V) 0.05 0.12 V A L IN Lowoutputvoltageswing R =75Ωto+1.65V(V =–0.2V) 0.1 V C L IN R =75ΩtoGND(V =–0.2V) 0.05 V C L IN Outputcurrent(sourcing) R =10Ωto+1.65V 80 mA C L Outputcurrent(sinking) R =10Ωto+1.65V 70 mA C L POWERSUPPLY Operatingvoltage 2.6 3.3 5.5 V B V =0V,allchannelson 18.8 23.4 28.5 mA A IN V =0V,SDchannelon,FHDchannelsoff 5.6 6.9 9 mA A IN Totalquiescentcurrent,noload V =0V,SDchanneloff,FHDchannelson 13.2 16.5 19.5 mA A IN V =0V,allchannelsoff,V =3V 0.1 10 μA A IN DISABLE Power-supplyrejectionratio Atdc 52 dB C (PSRR) LOGICCHARACTERISTICS(3) V Disabled 1.6 1.4 V A IH V Enabled 0.75 0.6 V A IL I Appliedvoltage=3.3V 1 μA C IH I Appliedvoltage=0V 1 μA C IL Disabletime 200 ns C Enabletime 250 ns C (3) Thelogicinputpinsdefaulttoalogic'0'conditionwhenleftfloating. 4 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 ELECTRICAL CHARACTERISTICS: V = +5 V S+ AtT =+25°C,R =150ΩtoGND,anddc-coupledinput/output,unlessotherwisenoted. A L THS7372 TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNITS LEVEL(1) ACPERFORMANCE:SD(CVBS)CHANNEL Passbandbandwidth –1dB;V =0.2V and2V 6.6 8.2 10 MHz B O PP PP Small-andlarge-signalbandwidth –3dB;V =0.2V and2V 8 9.5 11 MHz B O PP PP Withrespectto500kHz,f=6.75MHz –0.9 0.25 1.2 dB A Attenuation Withrespectto500kHz,f=27MHz 42 54 dB A Groupdelay f=100kHz 78 ns C Groupdelayvariation f=5.1MHzwithrespectto100kHz 11 ns C Channel-to-channeldelay 0.3 ns C Differentialgain NTSC/PAL 0.2/0.35 % C Differentialphase NTSC/PAL 0.35/0.5 Degrees C Totalharmonicdistortion f=1MHz,V =1.4V –71 dB C O PP 100kHzto6MHz,non-weighted 70 dB C Signal-to-noiseratio 100kHzto6MHz,unifiedweighting 78 dB C Allchannels,T =+25°C 5.7 6 6.3 dB A A Gain Allchannels,T =–40°Cto+85°C 5.65 6.35 dB B A f=6.75MHz 0.7 Ω C Outputimpedance Disabled 20||3 kΩ||pF C Returnloss f=6.75MHz 47 dB C Crosstalk f=1MHz,SDchanneltoFHDchannels –82 dB C ACPERFORMANCE:FULL-HD(FHD)CHANNELS Passbandbandwidth –1dB;V =0.2V and2V 53 60 66 MHz B O PP PP Small-andlarge-signalbandwidth –3dB;V =0.2V and2V 60 72 83 MHz B O PP PP Withrespectto500kHz,f=54MHz –0.5 0.4 2 dB A Attenuation Withrespectto500kHz,f=148MHz 33 40 dB A Groupdelay f=100kHz 12 ns C Groupdelayvariation f=54MHzwithrespectto100kHz 4.5 ns C Channel-to-channeldelay 0.3 ns C Totalharmonicdistortion f=20MHz,V =1.4V –50 dB C O PP 100kHzto60MHz,non-weighted 60 dB C Signal-to-noiseratio 100kHzto60MHz,unifiedweighting 70 dB C Allchannels,T =+25°C 5.7 6 6.3 dB A A Gain Allchannels,T =–40°Cto+85°C 5.65 6.35 dB B A f=60MHz 4 Ω C Outputimpedance Disabled 2||3 kΩ||pF C Returnloss f=60MHz 32 dB C f=6.75MHz,FHDchannelstoSDchannel –68 dB C Crosstalk f=25MHz,FHDchannelstoFHDchannels –54 dB C DCPERFORMANCE V =0V,SDchannel 200 305 400 mV A IN Biasedoutputvoltage V =0V,FHDchannels 200 300 400 mV A IN Inputvoltagerange DCinput,limitedbyoutput –0.1/2.3 V C V =–0.1V,SDchannel 140 200 μA A IN Sync-tipclampchargecurrent V =–0.1V,FHDchannels 280 400 μA A IN Inputimpedance 800||2 kΩ||pF C (1) Testlevels:(A)100%testedat+25°C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulationonly.(C)Typicalvalueonlyforinformation. Copyright©2011,TexasInstrumentsIncorporated 5

THS7372 SBOS578–AUGUST2011 www.ti.com ELECTRICAL CHARACTERISTICS: V = +5 V (continued) S+ AtT =+25°C,R =150ΩtoGND,anddc-coupledinput/output,unlessotherwisenoted. A L THS7372 TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNITS LEVEL(1) OUTPUTCHARACTERISTICS R =150Ωto+2.5V 4.85 V C L R =150ΩtoGND 4.4 4.75 V A L Highoutputvoltageswing R =75Ωto+2.5V 4.7 V C L R =75ΩtoGND 4.5 V C L R =150Ωto+2.5V(V =–0.2V) 0.06 V C L IN R =150ΩtoGND(V =–0.2V) 0.05 0.12 V A L IN Lowoutputvoltageswing R =75Ωto+2.5V(V =–0.2V) 0.1 V C L IN R =75ΩtoGND(V =–0.2V) 0.05 V C L IN Outputcurrent(sourcing) R =10Ωto+2.5V 90 mA C L Outputcurrent(sinking) R =10Ωto+2.5V 85 mA C L POWERSUPPLY Operatingvoltage 2.6 5 5.5 V B V =0V,allchannelson 19.7 24.5 30.2 mA A IN V =0V,SDchannelon,FHDchannelsoff 6 7.2 9.5 mA A IN Totalquiescentcurrent,noload V =0V,SDchanneloff,FHDchannelson 13.7 17.3 20.7 mA A IN V =0V,allchannelsoff,V =3V 1 10 μA A IN DISABLE Power-supplyrejectionratio Atdc 52 dB C (PSRR) LOGICCHARACTERISTICS(2) V Disabled 2.1 1.9 V A IH V Enabled 1.2 1 V A IL I Appliedvoltage=3.3V 1 μA C IH I Appliedvoltage=0V 1 μA C IL Disabletime 150 ns C Enabletime 200 ns C (2) Thelogicinputpinsdefaulttoalogic'0'conditionwhenleftfloating. THERMAL INFORMATION THS7372 THERMALMETRIC(1) PW UNITS 14PINS θ Junction-to-ambientthermalresistance 134.4 JA θ Junction-to-case(top)thermalresistance 52.2 JC(top) θ Junction-to-boardthermalresistance 64.3 JB °C/W ψ Junction-to-topcharacterizationparameter 7.5 JT ψ Junction-to-boardcharacterizationparameter 63.7 JB θ Junction-to-case(bottom)thermalresistance n/a JC(bottom) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 PIN CONFIGURATION PWPACKAGE TSSOP-14 (TOPVIEW) CVBS IN 1 14 CVBS OUT NC 2 13 DISABLE CVBS V 3 12 GND S+ NC 4 11 DISABLE FHD FHD1 IN 5 10 FHD1 OUT FHD2 IN 6 9 FHD2 OUT FHD3 IN 7 8 FHD3 OUT NC=Noconnection. TERMINALFUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CVBSIN 1 I Standard-definitionvideoinputforCVBSsignal;LPF=9.5MHz CVBSOUT 14 O Standard-definitionvideooutputforCVBSsignal;LPF=9.5MHz Disable Disablestandarddefinitionchannel.LogichighdisablestheSDchannelandlogiclowenablesthe 13 I CVBS SDchannel.Thispindefaultstologiclowifleftopen. Disablefullhigh-definitionchannels.LogichighdisablestheFHDchannelsandlogiclowenables DisableFHD 11 I theFHDchannels.Thispindefaultstologiclowifleftopen. FHD1IN 5 I Fullhigh-definitionvideoinput,channel1;LPF=72MHz FHD1OUT 10 O Fullhigh-definitionvideooutput,channel1;LPF=72MHz FHD2IN 6 I Fullhigh-definitionvideoinput,channel2;LPF=72MHz FHD2OUT 9 O Fullhigh-definitionvideooutput,channel2;LPF=72MHz FHD3IN 7 I Fullhigh-definitionvideoinput,channel3;LPF=72MHz FHD3OUT 8 O Fullhigh-definitionvideooutput,channel3;LPF=72MHz GND 12 I Groundpinforallinternalcircuitry NC 2,4 — Nointernalconnection;itisrecommendedtoconnectNCtoGND V 3 I Positivepower-supplypin;connectto+2.7Vupto+5V S+ Copyright©2011,TexasInstrumentsIncorporated 7

THS7372 SBOS578–AUGUST2011 www.ti.com FUNCTIONALBLOCKDIAGRAM +V S g m Level Shift CVBS CVBS 6 dB Input LPF Output Sync-Tip Clamp 800 kW (DC Restore) 6-Pole 9.5 MHz +V S g m Level Shift FHD Channel 1 FHD Channel 1 6 dB Input LPF Output Sync-Tip Clamp 800 kW (DC Restore) 6-Pole 72 MHz +V S g m Level Shift FHD Channel 2 FHD Channel2 6 dB Input LPF Output Sync-Tip Clamp 800 kW (DC Restore) 6-Pole 72 MHz +V S g m Level Shift FHD Channel 3 FHD Channel 3 6 dB Input LPF Output Sync-Tip Clamp 800 kW (DC Restore) 6-Pole 72 MHz +2.7 V to +5 V Disable FHD Disable CVBS 8 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS Table1.TableofGraphs:3.3V,Standard-Definition(SD)Channels TITLE FIGURE Figure1,Figure2,Figure9, SDSmall-SignalGainvsFrequency Figure10,Figure11,Figure12, Figure13 SDPhasevsFrequency Figure3 SDGroupDelayvsFrequency Figure4 SDDifferentialGain Figure5 SDDifferentialPhase Figure6 SDLarge-SignalGainvsFrequency Figure7,Figure8 SDTHDvsFrequency Figure14 SDLarge-SignalPulseResponsevsTime Figure15 SDSmall-SignalPulseResponsevsTime Figure16 SDSlewRatevsOutputVoltage Figure17 SDEnable/DisableResponsevsTime Figure18 Table2.TableofGraphs:3.3V,FullHD(FHD)Channels TITLE FIGURE Figure19,Figure20,Figure25, FHDSmall-SignalGainvsFrequency Figure26,Figure27,Figure28, Figure29 FHDPhasevsFrequency Figure21 FHDGroupDelayvsFrequency Figure22 FHDLarge-SignalGainvsFrequency Figure23,Figure24 FHDTHDvsFrequency Figure30 FHDLarge-SignalPulseResponsevsTime Figure31 FHDSmall-SignalPulseResponsevsTime Figure32 FHDSlewRatevsOutputVoltage Figure33 FHDEnable/DisableResponsevsTime Figure34 FHDCrosstalk Figure35 FHDtoSDCrosstalk Figure36 SDtoFHDCrosstalk Figure37 Copyright©2011,TexasInstrumentsIncorporated 9

THS7372 SBOS578–AUGUST2011 www.ti.com Table3.TableofGraphs:5V,Standard-Definition(SD)Channels TITLE FIGURE Figure38,Figure39,Figure46, SDSmall-SignalGainvsFrequency Figure47,Figure48,Figure49, Figure50 SDPhasevsFrequency Figure40 SDGroupDelayvsFrequency Figure41 SDDifferentialGain Figure42 SDDifferentialPhase Figure43 SDLarge-SignalGainvsFrequency Figure44,Figure45 SDTHDvsFrequency Figure51 SDLarge-SignalPulseResponsevsTime Figure52 SDSmall-SignalPulseResponsevsTime Figure53 SDSlewRatevsOutputVoltage Figure54 SDEnable/DisableResponsevsTime Figure55 Table4.TableofGraphs:5V,FullHD(FHD)Channels TITLE FIGURE Figure56,Figure57,Figure58, FHDSmall-SignalGainvsFrequency Figure59,Figure60,Figure61, Figure62 FHDPhasevsFrequency Figure63 FHDGroupDelayvsFrequency Figure64 FHDLarge-SignalGainvsFrequency Figure65,Figure66 FHDSlewRatevsOutputVoltage Figure67 FHDTHDvsFrequency Figure68 FHDLarge-SignalPulseResponsevsTime Figure69 FHDSmall-SignalPulseResponsevsTime Figure70 FHDEnable/DisableResponsevsTime Figure71 FHDCrosstalk Figure72 FHDtoSDCrosstalk Figure73 SDtoFHDCrosstalk Figure74 10 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 Table5.TableofGraphs:GeneralStandard-Definition(SD)Channels TITLE FIGURE SDOutputImpedancevsFrequency Figure75 SDS22OutputReturnLossvsFrequency Figure76 SDDisabledOutputImpedancevsFrequency Figure77 SDPSRRvsFrequency Figure78 Table6.TableofGraphs:GeneralFullHD(FHD)Channels TITLE FIGURE FHDOutputImpedancevsFrequency Figure79 FHDS22OutputReturnLossvsFrequency Figure80 FHDDisabledOutputImpedancevsFrequency Figure81 FHDPSRRvsFrequency Figure82 Copyright©2011,TexasInstrumentsIncorporated 11

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 RL = 150 W RL = 150 W 0 RL = 75 W 6 RL = 75 W 5.5 −10 5 B) −20 B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V VS+ = 3.3 V Load = RL || 10 pF 3.5 Load = RL || 10 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure1. Figure2. SDPHASEvsFREQUENCY SDGROUPDELAYvsFREQUENCY 45 130 RL = 150 W VS+ = 3.3 V RL = 150 W 0 RL = 75 W 120 Load = RL || 10 pF RL = 75 W −−9405 s) 110 VIDnOCpUu−TtC =Bo iu2ap0sl0 e= dm 0 OV.6Pu5Pt pVuDtC n e (°)−135 elay ( 100 has−180 p D 90 P u o −225 VS+ = 3.3 V Gr 80 −270 Load = RL || 10 pF VOUT = 200 mVPP −315 Input Bias = 0.65 VDC 70 DC−Coupled Output −360 60 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure3. Figure4. SDDIFFERENTIALGAIN SDDIFFERENTIALPHASE 0.05 0.5 V = 3.3 V S+ 0 0.45 -0.05 0.4 Gain (%) -0-.01.51 NTSC °Phase () 0.03.53 PAL ential -0.2 PAL ential 0.02.52 NTSC Differ -0.25 Differ 0.15 -0.3 0.1 -0.35 0.05 V = 3.3 V S+ -0.4 0 1st 2nd 3rd 4th 5th 6th 1st 2nd 3rd 4th 5th 6th Steps Steps Figure5. Figure6. 12 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels (continued) Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDLARGE-SIGNALGAINvsFREQUENCY SDLARGE-SIGNALGAINvsFREQUENCY 10 6.5 VOUT = 200 mVPP 0 VOUT = 2 VPP 6 5.5 −10 VOUT = 200 mVPP B) −20 B) 5 VOUT = 2 VPP d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V 3.5 VS+ = 3.3 V Load = 150 W || 10 pF Load = 150 W || 10 pF −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (MHz) Frequency (MHz) Figure7. Figure8. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 DC−Coupled Output 0 AC−Coupled Output 6 5.5 −10 DC−Coupled Output 5 AC−Coupled Output B) −20 B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V 3.5 VS+ = 3.3 V Load = 150 W || 10 pF Load = 150 W || 10 pF −50 VOUT = 200 mVPP 3 VOUT = 200 mVPP Input Bias = 0.65 VDC Input Bias = 0.65 VDC −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure9. Figure10. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 TA = −40°C 0 TA = 25°C 6 TA = 85°C 5.5 −10 TA = −40°C dB) −20 dB) 5 TTAA == 2855°°CC n ( n ( 4.5 Gai −30 Gai 4 −40 VLoSa+ d= =3 .135 V0 W || 10 pF 3.5 VLoSa+ d= =3 .135 V0 W || 10 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure11. Figure12. Copyright©2011,TexasInstrumentsIncorporated 13

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels (continued) Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDSMALL-SIGNALGAINvsFREQUENCY SDTHDvsFREQUENCY 10 −30 CL = 5 pF VOUT = 0.5 VPP 0 CCLL == 1108 ppFF n (dBc) −40 VVVOOOUUUTTT === 112 . 4VV PPVPPPP −10 ortio −50 VOUT = 2.5 VPP n (dB) −20 nic Dist −60 Gai −30 armo −70 H −40 VLoSa+ d= =3 .135 V0 W || CL Total −80 VInSp+u =t B3i.a3s V = 0.65 VDC −50 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −90 1M 8M −60 100k 1M 10M 100M 1G Frequency (Hz) G002 Frequency (MHz) Figure13. Figure14. SDLARGE-SIGNALPULSERESPONSEvsTIME SDSMALL-SIGNALPULSERESPONSEvsTIME Figure15. Figure16. SDSLEWRATEvsOUTPUTVOLTAGE SDENABLE/DISABLERESPONSEvsTIME 60 VS+ = 3.3 V Positive and Negative Slew Rates 50 s) 40 mV/ ate ( 30 R w e Sl 20 10 0 0.5 1 1.5 2 2.5 Output Voltage (VPP) Figure17. Figure18. 14 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 RL = 150 W 0 RL = 75 W 6 5.5 −10 RL = 150 W B) −20 B) 5 RL = 75 W d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V VS+ = 3.3 V Load = RL || 5 pF 3.5 Load = RL || 5 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 1M 10M 100M 1G 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure19. Figure20. FHDPHASEvsFREQUENCY FHDGROUPDELAYvsFREQUENCY 45 20 RL = 150 W RL = 150 W 0 RL = 75 W 18 RL = 75 W −45 16 −90 s) n e (°)−135 elay ( 14 has−180 p D 12 P u o −225 VS+ = 3.3 V Gr 10 VS+ = 3.3 V −270 Load = RL || 5 pF Load = RL || 5 pF VOUT = 200 mVPP VOUT = 200 mVPP −315 Input Bias = 0.65 VDC 8 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −360 6 1M 10M 100M 1G 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure21. Figure22. FHDLARGE-SIGNALGAINvsFREQUENCY FHDLARGE-SIGNALGAINvsFREQUENCY 10 6.5 0 6 5.5 B) −−2100 VVOOUUTT == 220 V0P mPVPP B) 5 VVOOUUTT == 220 V0P mPVPP d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V 3.5 VS+ = 3.3 V Load = 150 W || 5 pF Load = 150 W || 5 pF −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 1M 10M 100M 1G 1M 10M 100M Frequency (MHz) Frequency (MHz) Figure23. Figure24. Copyright©2011,TexasInstrumentsIncorporated 15

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 0 6 5.5 −10 DC−Coupled Output DC−Coupled Output 5 AC−Coupled Output B) −20 AC−Coupled Output B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 3.3 V 3.5 VS+ = 3.3 V Load = 150 W || 5 pF Load = 150 W || 5 pF −50 VOUT = 200 mVPP 3 VOUT = 200 mVPP Input Bias = 0.65 VDC Input Bias = 0.65 VDC −60 2.5 1M 10M 100M 1G 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure25. Figure26. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 TA = −40°C 0 TA = 25°C 6 TA = 85°C 5.5 −10 TA = −40°C dB) −20 dB) 5 TTAA == 2855°°CC n ( n ( 4.5 Gai −30 Gai 4 −40 VLoSa+ d= =3 .135 V0 W || 5 pF 3.5 VLoSa+ d= =3 .135 V0 W || 5 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 0.65 VDC 3 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −60 2.5 1M 10M 100M 1G 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure27. Figure28. FHDSMALL-SIGNALGAINvsFREQUENCY FHDTHDvsFREQUENCY 10 −30 CL = 5 pF VOUT = 0.5 VPP 0 CCLL == 1108 ppFF n (dBc) −40 VVVOOOUUUTTT === 112 . 4VV PPVPPPP −10 ortio −50 VOUT = 2.5 VPP n (dB) −20 nic Dist −60 Gai −30 armo −70 H −40 VLoSa+ d= =3 .135 V0 W || CL Total −80 VInSp+u =t B3i.a3s V = 0.65 VDC −50 Input Bias = 0.65 VDC DC−Coupled Output DC−Coupled Output −90 1M 10M 60M −60 1M 10M 100M 1G Frequency (Hz) G000 Frequency (MHz) Figure29. Figure30. 16 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDLARGE-SIGNALPULSERESPONSEvsTIME FHDSMALL-SIGNALPULSERESPONSEvsTIME Figure31. Figure32. FHDSLEWRATEvsOUTPUTVOLTAGE FHDENABLE/DISABLERESPONSEvsTIME 350 VS+ = 3.3 V Positive and Negative Slew Rates 300 250 s) me (V/ 200 at w R 150 e Sl 100 50 0 0.5 1 1.5 2 2.5 Output Voltage (VPP) Figure33. Figure34. FHDCROSSTALK FHDTOSDCROSSTALK(1) −30 −30 FHD1 into FHD2 VS+ = 3.3 V FHD1 into SD VS+ = 3.3 V FHD1 into FHD3 FHD2 into SD −40 FHD2 into FHD1 −40 FHD3 into SD FHD2 into FHD3 −50 FHD3 into FHD1 −50 B) FHD3 into FHD2 B) d d k ( k ( al −60 al −60 st st s s o o Cr −70 Cr −70 −80 −80 −90 −90 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure35. Figure36. (1) Measuredatvictim-channeloutputconnectorrelativetoaggressor-channeloutputconnector. Copyright©2011,TexasInstrumentsIncorporated 17

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. SDTOFHDCROSSTALK(2) −40 SD into FHD1 VS+ = 3.3 V SD into FHD2 −50 SD into FHD3 −60 B) d k ( al −70 st s o Cr −80 −90 −100 1M 10M 100M Frequency (Hz) Figure37. (2) Measuredatvictim-channeloutputconnectorrelativetoaggressor-channeloutputconnector. 18 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 RL = 150 W RL = 150 W 0 RL = 75 W 6 RL = 75 W 5.5 −10 5 B) −20 B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 5 V VS+ = 5 V Load = RL || 10 pF 3.5 Load = RL || 10 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 1 VDC 3 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure38. Figure39. SDPHASEvsFREQUENCY SDGROUPDELAYvsFREQUENCY 45 130 RL = 150 W VS+ = 5 V RL = 150 W 0 RL = 75 W 120 Load = RL || 10 pF RL = 75 W −−9405 s) 110 VIDnOCpUu−TtC =Bo iu2ap0sl0 e= dm 1 OV VPuDPtCput n e (°)−135 elay ( 100 has−180 p D 90 P u o −225 VS+ = 5 V Gr 80 −270 Load = RL || 10 pF VOUT = 200 mVPP −315 Input Bias = 1 VDC 70 DC−Coupled Output −360 60 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure40. Figure41. SDDIFFERENTIALGAIN SDDIFFERENTIALPHASE 0.05 0.6 V = 5 V S+ 0 0.5 Gain (%) -0-.00.51 NTSC °Phase () 0.4 PAL al -0.15 al 0.3 nti nti NTSC Differe -0-.02.52 PAL Differe 0.2 0.1 -0.3 V = 5 V S+ -0.35 0 1st 2nd 3rd 4th 5th 6th 1st 2nd 3rd 4th 5th 6th Steps Steps Figure42. Figure43. Copyright©2011,TexasInstrumentsIncorporated 19

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels (continued) Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDLARGE-SIGNALGAINvsFREQUENCY SDLARGE-SIGNALGAINvsFREQUENCY 10 6.5 VOUT = 200 mVPP 0 VOUT = 2 VPP 6 5.5 −10 VOUT = 200 mVPP B) −20 B) 5 VOUT = 2 VPP d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 5 V 3.5 VS+ = 5 V Load = 150 W || 10 pF Load = 150 W || 10 pF −50 Input Bias = 1 VDC 3 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (MHz) Frequency (MHz) Figure44. Figure45. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 DC−Coupled Output 0 AC−Coupled Output 6 5.5 −10 DC−Coupled Output 5 AC−Coupled Output B) −20 B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 5 V 3.5 VS+ = 5 V Load = 150 W || 10 pF Load = 150 W || 10 pF −50 VOUT = 200 mVPP 3 VOUT = 200 mVPP Input Bias = 1 VDC Input Bias = 1 VDC −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure46. Figure47. SDSMALL-SIGNALGAINvsFREQUENCY SDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 TA = −40°C 0 TA = 25°C 6 TA = 85°C 5.5 −10 TA = −40°C dB) −20 dB) 5 TTAA == 2855°°CC n ( n ( 4.5 Gai −30 Gai 4 −40 VLoSa+ d= =5 1V50 W || 10 pF 3.5 VLoSa+ d= =5 1V50 W || 10 pF VOUT = 200 mVPP VOUT = 200 mVPP −50 Input Bias = 1 VDC 3 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output −60 2.5 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure48. Figure49. 20 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels (continued) Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDSMALL-SIGNALGAINvsFREQUENCY SDTHDvsFREQUENCY 10 −30 CL = 5 pF VOUT = 0.5 VPP 0 CCLL == 1108 ppFF n (dBc) −40 VVVOOOUUUTTT === 112 . 4VV PPVPPPP −10 ortio −50 VOUT = 3 VPP n (dB) −20 nic Dist −60 Gai −30 armo −70 H −40 VLoSa+ d= =5 1V50 W || CL Total −80 VInSp+u =t B5i aVs = 1 VDC −50 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output −90 1M 8M −60 100k 1M 10M 100M 1G Frequency (Hz) G003 Frequency (MHz) Figure50. Figure51. SDLARGE-SIGNALPULSERESPONSEvsTIME SDSMALL-SIGNALPULSERESPONSEvsTIME Figure52. Figure53. SDSLEWRATEvsOUTPUTVOLTAGE SDENABLE/DISABLERESPONSEvsTIME 80 VS+ = 5 V Positive and Negative Slew Rates 60 s) mV/ ate ( 40 R w e Sl 20 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Voltage (VPP) Figure54. Figure55. Copyright©2011,TexasInstrumentsIncorporated 21

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 10 6.5 0 6 5.5 −10 DC−Coupled Output DC−Coupled Output 5 AC−Coupled Output B) −20 AC−Coupled Output B) d d n ( n ( 4.5 Gai −30 Gai 4 −40 VS+ = 5 V 3.5 VS+ = 5 V Load = 150 W || 5 pF Load = 150 W || 5 pF −50 VOUT = 200 mVPP 3 VOUT = 200 mVPP Input Bias = 1 VDC Input Bias = 1 VDC −60 2.5 1M 10M 100M 1G 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure56. Figure57. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 10 10 CL = 5 pF RL = 150 W 0 CL = 10 pF 0 RL = 75 W CL = 18 pF −10 −10 B) −20 B) −20 d d n ( n ( Gai −30 Gai −30 −40 −40 VS+ = 5 V VS+ = 5 V Load = RL || 5 pF Load = 150 W || CL VOUT = 200 mVPP −50 Input Bias = 1 VDC −50 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output −60 −60 1M 10M 100M 1G 1M 10M 100M 1G Frequency (MHz) Frequency (Hz) Figure58. Figure59. FHDSMALL-SIGNALGAINvsFREQUENCY FHDSMALL-SIGNALGAINvsFREQUENCY 6.5 10 TA = −40°C 6 0 TA = 25°C TA = 85°C 5.5 RL = 150 W −10 B) 5 RL = 75 W B) −20 d d n ( 4.5 n ( Gai Gai −30 4 3.5 VLoSa+ d= =5 RVL || 5 pF −40 VLoSa+ d= =5 1V50 W || 5 pF VOUT = 200 mVPP VOUT = 200 mVPP 3 Input Bias = 1 VDC −50 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output 2.5 −60 1M 10M 100M 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure60. Figure61. 22 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDSMALL-SIGNALGAINvsFREQUENCY FHDPHASEvsFREQUENCY 6.5 45 RL = 150 W 6 0 RL = 75 W −45 5.5 TA = −40°C −90 Gain (dB) 4.55 TTAA == 2855°°CC Phase (°)−−118305 4 VS+ = 5 V −225 VS+ = 5 V 3.5 Load = 150 W || 5 pF −270 Load = RL || 5 pF VOUT = 200 mVPP VOUT = 200 mVPP 3 Input Bias = 1 VDC −315 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output 2.5 −360 1M 10M 100M 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure62. Figure63. FHDGROUPDELAYvsFREQUENCY FHDLARGE-SIGNALGAINvsFREQUENCY 20 10 RL = 150 W 18 RL = 75 W 0 16 −10 ns) VOUT = 200 mVPP y ( 14 B) −20 VOUT = 2 VPP Dela n (d up 12 Gai −30 o Gr 10 VS+ = 5 V −40 Load = RL || 5 pF VS+ = 5 V VOUT = 200 mVPP Load = 150 W || 5 pF 8 Input Bias = 1 VDC −50 Input Bias = 1 VDC DC−Coupled Output DC−Coupled Output 6 −60 1M 10M 100M 1G 1M 10M 100M 1G Frequency (Hz) Frequency (MHz) Figure64. Figure65. FHDLARGE-SIGNALGAINvsFREQUENCY FHDSLEWRATEvsOUTPUTVOLTAGE 6.5 450 VS+ = 5 V 6 400 Positive and Negative Slew Rates 350 5.5 VOUT = 200 mVPP s) 300 n (dB) 4.55 VOUT = 2 VPP mate (V/ 250 ai R 200 G 4 ew Sl 150 3.5 VLoSa+ d= =5 1V50 W || 5 pF 100 3 Input Bias = 1 VDC 50 DC−Coupled Output 2.5 0 1M 10M 100M 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (MHz) Output Voltage (VPP) Figure66. Figure67. Copyright©2011,TexasInstrumentsIncorporated 23

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDTHDvsFREQUENCY FHDLARGE-SIGNALPULSERESPONSEvsTIME −30 VOUT = 0.5 VPP dBc) −40 VVOOUUTT == 11 .4V PVPPP n ( VOUT = 2 VPP ortio −50 VOUT = 3 VPP st c Di −60 ni o m ar −70 H Total −80 VInSp+u =t B5i aVs = 1 VDC DC−Coupled Output −90 1M 10M 60M Frequency (Hz) G001 Figure68. Figure69. FHDSMALL-SIGNALPULSERESPONSEvsTIME FHDENABLE/DISABLERESPONSEvsTIME Figure70. Figure71. FHDCROSSTALK FHDTOSDCROSSTALK(1) −30 −30 FHD1 into FHD2 VS+ = 5 V FHD1 into SD VS+ = 5 V FHD1 into FHD3 FHD2 into SD −40 FHD2 into FHD1 −40 FHD3 into SD FHD2 into FHD3 −50 FHD3 into FHD1 −50 B) FHD3 into FHD2 B) d d k ( k ( al −60 al −60 st st s s o o Cr −70 Cr −70 −80 −80 −90 −90 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure72. Figure73. (1) Measuredatvictim-channeloutputconnectorrelativetoaggressor-channeloutputconnector. 24 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued) Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. SDTOFHDCROSSTALK(2) −40 SD into FHD1 VS+ = 5 V SD into FHD2 −50 SD into FHD3 −60 B) d k ( al −70 st s o Cr −80 −90 −100 1M 10M 100M Frequency (Hz) Figure74. (2) Measuredatvictim-channeloutputconnectorrelativetoaggressor-channeloutputconnector. Copyright©2011,TexasInstrumentsIncorporated 25

THS7372 SBOS578–AUGUST2011 www.ti.com TYPICAL CHARACTERISTICS: General Standard-Definition (SD) Channels Withload=150Ω||10pF,dc-coupledinputandoutput,unlessotherwisenoted. SDOUTPUTIMPEDANCEvsFREQUENCY SDS22OUTPUTRETURNLOSSvsFREQUENCY 10 −20 VS+ = 3.3 V to 5 V −25 VS+ = 3.3 V to 5 V B) −30 d Wdance () 1 urn Loss ( −−4305 put Impe 0.1 utput Ret −−5405 ut O −55 O 2, 2 −60 S −65 0.01 −70 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure75. Figure76. SDDISABLEDOUTPUTIMPEDANCEvsFREQUENCY SDPSRRvsFREQUENCY 100 70 VS+ = 3.3 V to 5 V VS+ = 3.3 V to 5 V Disable Mode B) 60 d o ( ) ati 50 We (k 10 n R c o edan ejecti 40 p R utput Im 1 Supply 2300 O − er w o 10 P 0.1 0 100k 1M 10M 100M 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure77. Figure78. 26 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 TYPICAL CHARACTERISTICS: General Full HD (FHD) Channels Withload=150Ω||5pF,dc-coupledinputandoutput,unlessotherwisenoted. FHDOUTPUTIMPEDANCEvsFREQUENCY FHDS22OUTPUTRETURNLOSSvsFREQUENCY 10 −20 VS+ = 3.3 V to 5 V −25 VS+ = 3.3 V to 5 V B) −30 d Wdance () 1 urn Loss ( −−4305 put Impe 0.1 utput Ret −−5405 ut O −55 O 2, 2 −60 S −65 0.01 −70 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure79. Figure80. FHDDISABLEDOUTPUTIMPEDANCEvsFREQUENCY FHDPSRRvsFREQUENCY 10 70 VS+ = 3.3 V to 5 V VS+ = 3.3 V to 5 V Disable Mode B) 60 d o ( ) ati 50 Wk R e ( n c o edan 1 ejecti 40 p R utput Im Supply 2300 O − er w o 10 P 0.1 0 100k 1M 10M 100M 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure81. Figure82. Copyright©2011,TexasInstrumentsIncorporated 27

THS7372 SBOS578–AUGUST2011 www.ti.com APPLICATION INFORMATION The THS7372 is targeted for four-channel video output applications that require one standard-definition (SD) video output buffer and three full-high definition (FHD) video output buffers. Although it can be used for numerous other applications, the needs and requirements of the video signal are the most important design parameters of the THS7372. Built on the revolutionary, complementary Silicon Germanium (SiGe) BiCom3X process, the THS7372 incorporates many features not typically found in integrated video parts while consuming verylowpower.TheTHS7372includesthefollowingfeatures: • Single-supply 2.7-V to 5-V operation with low total quiescent current of 23.4 mA at 3.3 V and 24.5mAat5V • Disable mode allows for shutting down individual SD/FHD blocks of amplifiers to save system power in power-sensitiveapplications • Inputconfigurationacceptingdc+levelshift,acsync-tipclamp,orac-bias – AC-biasingisallowedwiththeuseofexternalpull-upresistorstothepositivepowersupply • Sixth-order,low-passfilterforDACreconstructionorADCimagerejection: – 9.5MHzforNTSC,PAL,SECAM,andcompositevideo(CVBS)signals – 72MHzfor1080p60Y’/P’ /P’ orG’B’R’signals B R • Individually-controlled Disable mode shuts down all amplifiers in each SD/FHD block to reduce quiescent currentto0.1μA • Internally-fixed gain of 2-V/V (+6-dB) buffer that can drive two video lines with dc-coupling or traditional ac-coupling • Flow-through configuration using a TSSOP-14 package that complies with the latest lead-free (RoHS-compatible)andgreenmanufacturingrequirements OPERATING VOLTAGE The THS7372 is designed to operate from 2.7 V to 5 V over the –40°C to +85°C temperature range. The impact on performance over the entire temperature range is negligible as a result of the implementation of thin film resistors and high-quality, low-temperature coefficient capacitors. The design of the THS7372 allows operation down to 2.6 V, but it is recommended to use at least a 3-V supply to ensure that no issues arise with headroom or clipping with 100% color-saturated CVBS signals. If only 75% color saturated CVBS is supported, then the output voltage requirements are reduced to 2 V on the output, allowing a 2.7-V supply to be utilized without PP issues. A 0.1-μF to 0.01-μF capacitor should be placed as close as possible to the power-supply pins. Failure to do so mayresultintheTHS7372outputsringingoroscillating.Additionally,alargecapacitor(suchas22μFto100μF) shouldbeplacedonthepower-supplylinetominimizeinterferencewith50-/60-Hzlinefrequencies. INPUT VOLTAGE The THS7372 input range allows for an input signal range from –0.2 V to approximately (V – 1.5 V). However, S+ becauseoftheinternalfixedgainof2V/V(+6dB)andtheinternalinputlevelshiftof150mV(typical),theoutput isgenerallythelimitingfactorfortheallowablelinearinputrange.Forexample,witha5-Vsupply,thelinearinput range is from –0.2 V to 3.5 V. However, because of the gain and level shift, the linear output range limits the allowablelinearinputrangetoapproximately–0.1Vto2.3V. 28 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 INPUT OVERVOLTAGE PROTECTION TheTHS7372isbuiltusingaveryhigh-speed,complementary,bipolar,andCMOSprocess.Theinternaljunction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection diodestothepowersupplies,asshowninFigure83. +V S External Internal Input/Output Circuitry Pin Figure83. InternalESDProtection These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The protectiondiodescantypicallysupport30mAofcontinuouscurrentwhenoverdriven. TYPICAL CONFIGURATION AND VIDEO TERMINOLOGY A typical application circuit using the THS7372 as a video buffer is shown in Figure 84. It shows a DAC or encoder driving the input channels of the THS7372. The SD channel (CVBS IN pin) can be used for NTSC, PAL, or SECAM signals. The other three channels are the component video Y’/P’ /P’ (sometimes labeled Y’U’V’ or B R incorrectly labeled Y’/C’ /C’ ) signals. These signals are typically 480i, 576i, 480p, 576p, 720p, 1080i, or up to B R 1080p60signals. Note that the Y’ term is used for the luma channels throughout this document rather than the more common luminance (Y) term. This usage accounts for the definition of luminance as stipulated by the International Commission on Illumination (CIE). Video departs from true luminance because a nonlinear term, gamma, is added to the true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically createluma(Y’).Thus,luminance(Y)isnotmaintained,providingadifferenceinterminology. THS7372 CVBS Out 75W 75W CVBS 1 CVBS IN CVBS OUT 14 37.4W 2 NC DIS CVBS 13 Disable CVBS +2.7 V to +5 V 3 VS+ GND 12 oder Y'/G' 4 NC DIS FHD 11 DFHisDable 75WY'/G’Out 75W Enc 37.4W 5 FHD1 IN FHD1 OUT 10 C/ DA 6 FHD2 IN FHD2 OUT 9 C/ SO P’B/B' 7 FHD3 IN FHD3 OUT 8 37.4W P' /B’Out B 75W 75W P’ /R' R 37.4W P' /R’Out R 75W 75W Figure84. TypicalFour-ChannelSystemInputsfromDC-CoupledEncoder/DACwith DC-CoupledLineDriving Copyright©2011,TexasInstrumentsIncorporated 29

THS7372 SBOS578–AUGUST2011 www.ti.com R’G’B’ (commonly mislabeled RGB) is also called G’B’R’ (again commonly mislabeled as GBR) in professional video systems. The Society of Motion Picture and Television Engineers (SMPTE) component standard stipulates that the luma information is placed on the first channel, the blue color difference is placed on the second channel, and the red color difference signal is placed on the third channel. This practice is consistent with the Y'/P' /P' nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G') B R also carries the sync information, it makes logical sense that G' be placed first in the system. Because the blue color difference channel (P' ) is next and the red color difference channel (P' ) is last, then it also makes logical B R sense to place the B' signal on the second channel and the R' signal on the third channel, respectfully. Thus, hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels, but this configuration may not always be the case in all systems. INPUT MODE OF OPERATION: DC The inputs to the THS7372 allow for both ac- and dc-coupled inputs. Many DACs or video encoders can be dc-connected to the THS7372. One of the drawbacks to dc-coupling arises when 0 V is applied to the input. Although the input of the THS7372 allows for a 0-V input signal without issue, the output swing of a traditional amplifier cannot yield a 0-V signal, resulting in possible clipping. This limitation is true for any single-supply amplifier because of the characteristics of the output transistors. Neither CMOS nor bipolar transistors can achieve 0 V while sinking current. This transistor characteristic is also the same reason why the highest output voltageisalwayslessthanthepower-supplyvoltagewhensourcingcurrent. This output clipping can reduce the sync amplitudes (both horizontal and vertical sync) on the video signal. A problemoccursifthevideosignalreceiverusesanautomaticgaincontrol(AGC)looptoaccountforlossesinthe transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC circuit can increase the gain too much—resulting in too much luma and/or chroma amplitude gain correction. This correction may result in a picture with an overly bright display with too muchcolorsaturation. Other AGC circuits use the chroma burst amplitude for amplitude control; reduction in the sync signals does not alter the proper gain setting. However, it is good engineering design practice to ensure that saturation/clipping does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation couldpossiblyresultintimingdelaysorotheraberrationsonthesignals. To eliminate saturation or clipping problems, the THS7372 has a 150-mV input level shift feature. This feature takes the input voltage and adds an internal +150-mV shift to the signal. Because the THS7372 also has a gain of 6 dB (2 V/V), the resulting output with a 0-V applied input signal is approximately 300 mV. The THS7372 rail-to-rail output stage can create this output level while connected to a typical video load. This configuration ensures that no saturation or clipping of the sync signals occur. This shift is constant, regardless of the input signal.Forexample,ifa1-Vinputisapplied,theoutputis2.3V. Becausetheinternalgainisfixedat+6dB,thegaindictateswhattheallowablelinearinputvoltagerangecanbe without clipping concerns. For example, if the power supply is set to 3 V, the maximum output is approximately 2.9 V while driving a significant amount of current. Thus, to avoid clipping, the allowable input is ([2.9 V/2] – 0.15 V) = 1.3 V. This range is valid for up to the maximum recommended 5-V power supply that allows approximately a([4.9V/2]– 0.15V)=2.3Vinputrangewhileavoidingclippingontheoutput. 30 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 The input impedance of the THS7372 in this mode of operation is dictated by the internal, 800-kΩ pull-down resistor, as shown in Figure 85. Note that the internal voltage shift does not appear at the input pin; it only shows attheoutputpin. +VS Internal Circuitry Input Pin 800 kW Level Shift Figure85. EquivalentDCInputModeCircuit INPUT MODE OF OPERATION: AC SYNC TIP CLAMP Some video DACs or encoders are not referenced to ground but rather to the positive power supply. The resulting video signals are generally at too great a voltage for a dc-coupled video buffer to function properly. To account for this scenario, the THS7372 incorporates a sync-tip clamp circuit. This function requires a capacitor (nominally 0.1 μF) to be in series with the input. Although the term sync-tip-clamp is used throughout this document,itshouldbenotedthattheTHS7372wouldprobablybebettertermedasadcrestorationcircuitbased onhowthisfunctionisperformed.Thiscircuitisanactiveclampcircuitandnotapassivediodeclampfunction. The input to the THS7372 has an internal control loop that sets the lowest input applied voltage to clamp at ground (0 V). By setting the reference at 0 V, the THS7372 allows a dc-coupled input to also function. Therefore, the sync-tip-clamp (STC) is considered transparent because it does not operate unless the input signal goes below ground. The signal then goes through the same 150-mV level shifter, resulting in an output voltage low levelof300mV.Iftheinputsignaltriestogobelow0V,theTHS7372internalcontrolloopsourcesupto6mAof current to increase the input voltage level on the THS7372 input side of the coupling capacitor. As soon as the voltagegoesabovethe0-Vlevel,theloopstopssourcingcurrentandbecomesveryhighimpedance. One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has overshoot—common in VCR signals, noise, DAC overshoot, or reflections found in poor printed circuit board (PCB) layouts. Ideally, the STC should not react to the overshoot voltage of the input signal. Otherwise, this responsecouldresultinclippingontherestofthevideosignalbecauseitmayraisethebiasvoltagetoomuch. Copyright©2011,TexasInstrumentsIncorporated 31

THS7372 SBOS578–AUGUST2011 www.ti.com To help minimize this input signal overshoot problem, the control loop in the THS7372 has an internal low-pass filter, as shown in Figure 86. This filter reduces the response time of the STC circuit. This delay is a function of how far the voltage is below ground, but in general it is approximately a 400-ns delay for the SD channel filters and approximately a 150-ns delay for the FHD filters. The effect of this filter is to slow down the response of the controlloopsoasnottoclampontheinputovershootvoltagebutrathertheflatportionofthesyncsignal. +VS STC LPF Internal Circuitry +V S g m 0.1mF Input Pin Input 800 kW Level Shift Figure86. EquivalentACSync-Tip-ClampInputCircuit Asaresultofthisdelay,syncmayhaveanapparentvoltageshift.Theamountofshiftdependsontheamountof droop in the signal as dictated by the input capacitor and the STC current flow. Because sync is used primarily for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in most systems. While this feature may not fully eliminate overshoot issues on the input signal, in cases of extreme overshoot and/or ringing, the STC system should help minimize improper clamping levels. As an additional method to help minimize this issue, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the external terminationresistorscanhelpfilterovershootproblems. It should be noted that this STC system is dynamic and does not rely upon timing in any way. It only depends on the voltage that appears at the input pin at any given point in time. The STC filtering helps minimize level shift problems associated with switching noises or very short spikes on the signal line. This architecture helps ensure averyrobustSTCsystem. When the ac STC operation is used, there must also be some finite amount of discharge bias current. As previously described, if the input signal goes below the 0-V clamp level, the internal loop of the THS7372 sources current to increase the voltage appearing at the input pin. As the difference between the signal level and the 0-V reference level increases, the amount of source current increases proportionally—supplying up to 6 mA of current. Thus, the time to re-establish the proper STC voltage can be very fast. If the difference is very small, thenthesourcecurrentisalsoverysmalltoaccountforminorvoltagedroop. However,whathappensiftheinputsignalgoesabovethe0-Vinputlevel?Theproblemisthatthevideosignalis always above this level and must not be altered in any way. Thus, if the sync level of the input signal is above this 0-V level, then the internal discharge (sink) current reduces the ac-coupled bias signal to the proper 0-V level. This discharge current must not be large enough to alter the video signal appreciably or picture quality issues may arise. This effect is often seen by looking at the tilt (droop) of a constant luma signal being applied and the resulting output level. The associated change in luma level from the beginning and end of the video line is the amountoflinetilt(droop). If the discharge current is very small, the amount of tilt is very low, which is a generally a good thing. However, the amount of time for the system to capture the sync signal could be too long. This effect is also termed hum rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The value of the discharge current andtheac-couplingcapacitorcombinetodictatethehumrejectionandtheamountoflinetilt. 32 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 To allow for both dc- and ac-coupling in the same part, the THS7372 incorporates an 800-kΩ resistor to ground. Although a true constant current sink is preferred over a resistor, there can be issues when the voltage is near ground.Thisconfigurationcancausethecurrentsinktransistortosaturateandcausepotentialproblemswiththe signal. The 800-kΩ resistor is large enough to not impact a dc-coupled DAC termination. For discharging an ac-coupled source, Ohm’s Law is used. If the video signal is 1 V, then there is 1 V/800 kΩ = 1.25-μA of discharge current. If more hum rejection is desired or there is a loss of sync occurring, then simply decrease the 0.1-μF input coupling capacitor. A decrease from 0.1 μF to 0.047 μF increases the hum rejection by a factor of 2.1. Alternatively, an external pull-down resistor to ground may be added that decreases the overall resistance andultimatelyincreasesthedischargecurrent. To ensure proper stability of the ac STC control loop, the source impedance must be less than 1 kΩ with the input capacitor in place. Otherwise, there is a possibility of the control loop ringing, which may appear on the output of the THS7372. Because most DACs or encoders use resistors (typically less than 300 Ω) to establish the voltage, meeting the less than 1-kΩ requirement is easily done. However, if the source impedance looking from the THS7372 input perspective is very high, then simply adding a 1-kΩ resistor to GND ensures proper operationoftheTHS7372. INPUT MODE OF OPERATION: AC BIAS Sync-tip clamps work very well for signals that have horizontal and/or vertical syncs associated with them; however, some video signals do not have a sync embedded within the signal. If ac-coupling of these signals is desired, then a dc bias is required to properly set the dc operating point within the THS7372. This function is easily accomplished with the THS7372 by simply adding an external pull-up resistor to the positive power supply, asshowninFigure87. +3.3 V +3.3 V Internal Circuitry C 0.1INmF RPU Input Input Pin 800 kW Level Shift Figure87. AC-BiasInputModeCircuitConfiguration ThedcvoltageappearingattheinputpinisequaltoEquation1: 800 kW V = V DC S 800 kW+ R PU (1) The THS7372 allowable input range is approximately 0 V to (V – 1.5 V), allowing for a very wide input voltage S+ range. As such, the input dc bias point is very flexible, with the output dc bias point being the primary factor. For example, if the output dc bias point is desired to be 1.6 V on a 3.3-V supply, then the input dc bias point should be (1.6 V – 300 mV)/2 = 0.65 V. Thus, the pull-up resistor calculates to approximately 3.3 MΩ, resulting in 0.644 V. If the output dc-bias point is desired to be 1.6 V with a 5-V power supply, then the pull-up resistor calculatestoapproximately5.36MΩ. Keep in mind that the internal 800-kΩ resistor has approximately a ±20% variance. As such, the calculations should take this variance into account. For the 0.644-V example above, using an ideal 3.3-MΩ resistor, the input dcbiasvoltageisapproximately0.644V±0.1V. The value of the output bias voltage is very flexible and is left to each individual design. It is important to ensure that the signal does not clip or saturate the video signal. Thus, it is recommended to ensure the output bias voltage is between 0.9 V and (V – 1 V). For 100% color saturated CVBS or signals with Macrovision®, the S+ CVBS signal can reach up to 1.23 V at the input, or 2.46 V at the output of the THS7372. In contrast, other PP PP signals are typically 1 V or 0.7 V at the input which translate to an output voltage of 2 V or 1.4 V . The PP PP PP PP outputbiasvoltagemustaccountforaworst-casesituation,dependingonthesignalsinvolved. Copyright©2011,TexasInstrumentsIncorporated 33

THS7372 SBOS578–AUGUST2011 www.ti.com One other issue that must be taken into account is the dc-bias point is a function of the power supply. As such, there is an impact on system PSRR. To help reduce this impact, the input capacitor combines with the pull-up resistance to function as a low-pass filter. Additionally, the time to charge the capacitor to the final dc bias point is a function of the pull-up resistor and the input capacitor size. Lastly, the input capacitor forms a high-pass filter with the parallel impedance of the pull-up resistor and the 800-kΩ resistor. In general, it is good to have this high-pass filter at approximately 3 Hz to minimize any potential droop on a P’ or P’ signal. A 0.1-μF input B R capacitorwitha3.3-MΩ pull-upresistorequatestoapproximatelya2.5-Hzhigh-passcornerfrequency. This mode of operation is recommended for use with chroma (C’), P’ , P’ , U’, and V’ signals. This method can B R also be used with sync signals if desired. The benefit of using the STC function over the ac-bias configuration on embedded sync signals is that the STC maintains a constant back-porch voltage as opposed to a back-porch voltage that fluctuates depending on the video content. Because the high-pass corner frequency is a very low 2.5Hz,theimpactonthevideosignalisnegligiblerelativetotheSTCconfiguration. One question may arise over the P’ and P’ channels. For 480i, 576i, 480p, and 576p signals, a sync may or B R may not be present. If no sync exists within the signal, then it is obvious that ac-bias is the preferred method of ac-couplingthesignal. For 720p, 1080i, and 1080p signals, or for the the 480i, 576i, 480p, and 576p signals with sync present on the P’ and P’ channels, the lowest voltage of the sync is –300 mV below the midpoint reference voltage of 0 V. B R TheP’ andP’ signalsallowasignaltobeaslowas –350mVbelowthemidpointreferencevoltageof0V.This B R allowance corresponds to 100% yellow for P’ signal or 100% cyan for P’ signal . Because the P’ and P’ B R B R signal voltage can be lower than the sync voltage, there exists a potential for clipping of the signal for a short periodoftimeifthesignalsdropbelowthesyncvoltage. The THS7372 does include a 150-mV input level shift, or 300 mV at the output, that should mitigate any clipping issues. For example, if a STC is used, then the bottom of the sync is 300 mV at the output. If the signal does go the lowest level, or 50 mV lower than the sync at the input, then the instantaneous output is (–50 mV + 150 mV) ×2=200mVattheoutput. Another potential risk is that if this signal (100% yellow for P’ or 100% cyan for P’ ) exists for several pixels, B R then the STC circuit engages to raise the voltage back to 0 V at the input. This function can cause a 50-mV level shift at the input midway through the active video signal. This effect is undesirable and can cause errors in the decoding of the signal. It is therefore recommended to use ac bias mode for component P’ and P’ signals B R whenac-couplingisdesired. 34 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 OUTPUT MODE OF OPERATION: DC-COUPLED The THS7372 incorporates a rail-to-rail output stage that can be used to drive the line directly without the need for large ac-coupling capacitors. This design offers the best line tilt and field tilt (droop) performance because no ac-coupling occurs. Keep in mind that if the input is ac-coupled, then the resulting tilt as a result of the input ac-coupling continues to be seen on the output, regardless of the output coupling. The 80-mA output current drive capability of the THS7372 is designed to drive two video lines simultaneously—essentially, a 75-Ω load—while keeping the output dynamic range as wide as possible. Figure 88 shows the THS7372 driving two videolineswhilekeepingtheoutputdc-coupled. THS7372 CVBS 1 Out CVBS 2 Out 75W 75W 75W 75W CVBS 1 CVBS IN CVBS OUT 14 37.4W 2 NC DIS CVBS 13 Disable CVBS +2.7+ V5 tVo 3 VS+ GND 12 oder Y'/G' 4 NC DIS FHD 11 DFHisDable 75WY'/G’1Out 75W 75WY'/G’2 Out 75W Enc 37.4W 5 FHD1 IN FHD1 OUT 10 C/ DA 6 FHD2 IN FHD2 OUT 9 C/ SO P’B/B' 7 FHD3 IN FHD3 OUT 8 37.4W P'/B’1Out P'/B’2 Out B B 75W 75W 75W 75W P’ /R' R 37.4W P' /R’1Out P' /R’2 Out R R 75W 75W 75W 75W Figure88. TypicalFour-ChannelSystemwithDC-CoupledLineDrivingandTwoOutputsPerChannel One concern of dc-coupling, however, arises if the line is terminated to ground. If the ac-bias input configuration is used, the output of the THS7372 has a dc bias on the output, such as 1.6 V. With two lines terminated to ground, this configuration allows a dc current path to flow, such as 1.6 V/75-Ω = 21.3 mA. The result of this configuration is a slightly decreased high output voltage swing and an increase in power dissipation of the THS7372. While the THS7372 was designed to operate with a junction temperature of up to +125°C, care must be taken to ensure that the junction temperature does not exceed this level or else long-term reliability could suffer. Using a 5-V supply, this configuration can result in an additional dc power dissipation of (5 V – 1.6 V) × 21.3 mA = 72.5 mW per channel. With a 3.3-V supply, this dissipation reduces to 36.2 mW per channel. The overall low quiescent current of the THS7372 design minimizes potential thermal issues even when using the TSSOP package at high ambient temperatures, but power and thermal analysis should always be examined in any system to ensure that no issues arise. Be sure to use RMS power and not instantaneous power when evaluatingthethermalperformance. Note that the THS7372 can drive the line with dc-coupling regardless of the input mode of operation. The only requirement is to make sure the video line has proper termination in series with the output (typically 75 Ω). This requirement helps isolate capacitive loading effects from the THS7372 output. Failure to isolate capacitive loads may result in instabilities with the output buffer, potentially causing ringing or oscillations to appear. The stray capacitance appearing directly at the THS7372 output pins should be kept below 20 pF for the fixed SD filter channels and below 15 pF for the FHD filter channels. One way to help ensure this condition is satisfied is to makesurethe75-Ω sourceresistorisplacedwithin0.5inches,or12.7mm,oftheTHS7372outputpin.Ifalarge ac-couplingcapacitorisused,thecapacitorshouldbeplacedafterthisresistor. There are many reasons dc-coupling is desirable, including reduced costs, printed circuit board (PCB) area, and no line tilt. A common question is whether or not there are any drawbacks to using dc-coupling. There are some potential issues that must be examined, such as the dc current bias as discussed above. Another potential risk is whether this configuration meets industry standards. EIA/CEA-770 stipulates that the back-porch shall be 0 V ± 1 V as measured at the receiver. With a double-terminated load system, this requirement implies a 0-V ± 2-V level Copyright©2011,TexasInstrumentsIncorporated 35

THS7372 SBOS578–AUGUST2011 www.ti.com at the video amplifier output. The THS7372 can easily meet this requirement without issue. However, in Japan, the EIAJ CP-1203 specification stipulates a 0-V ± 0.1-V level with no signal. This requirement can be met with the THS7372 in shutdown mode, but while active it cannot meet this specification without output ac-coupling. AC-coupling the output essentially ensures that the video signal works with any system and any specification. Formanymodernsystems,however,dc-couplingcansatisfymostneeds. OUTPUT MODE OF OPERATION: AC-COUPLED Averycommonmethodofcouplingthevideosignaltothelineiswithalargecapacitor.Thiscapacitoristypically between 220 μF and 1000 μF, although 470 μF is very typical. The value of this capacitor must be large enough to minimize the line tilt (droop) and/or field tilt associated with ac-coupling as described previously in this document. AC-coupling is performed for several reasons, but the most common is to ensure full interoperability with the receiving video system. This approach ensures that regardless of the reference dc voltage used on the transmittingside,thereceivingsidere-establishesthedcreferencevoltagetoitsownrequirements. In the same way as the dc output mode of operation discussed previously, each line should have a 75-Ω source termination resistor in series with the ac-coupling capacitor. This 75-Ω resistor should be placed next to the THS7372 output to minimize capacitive loading effects. If two lines are to be driven, it is best to have each line use its own capacitor and resistor rather than sharing these components. This configuration helps ensure line-to-line dc isolation and eliminates the potential problems as described previously. Using a single, 1000-μF capacitorfortwolinesispermissible,butthereisachanceforinterferencebetweenthetworeceivers. Lastly, because of the edge rates and frequencies of operation, it is recommended (but not required) to place a 0.1-μF to 0.01-μF capacitor in parallel with the large 220-μF to 1000-μF capacitor. These large value capacitors are most commonly aluminum electrolytic. It is well-known that these capacitors have significantly large equivalent series resistance (ESR), and the impedance at high frequencies is rather large as a result of the associated inductances involved with the leads and construction. The small 0.1-μF to 0.01-μF capacitors help passthesehigh-frequencysignals(greaterthan1MHz)withmuchlowerimpedancethanthelargecapacitors. Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of the chroma signal in a S-Video system is not required to go as low (or as high of a frequency) as the luma channels. Thus,thecapacitorvaluesofthechromaline(s)canbesmaller,suchas0.1μF. Figure 89 shows a typical configuration where the input is ac-coupled and the output is also ac-coupled. AC-coupled inputs are generally required when current-sink DACs are used or the input is connected to an unknownsource,suchaswhentheTHS7372isusedasaninputdevice. +V THS7372 CVBS Out 0.1mF(1) 75W 330mF(2) 75W CVBS 1 CVBS IN CVBS OUT 14 37.4W 2 NC DIS CVBS 13 Disable CVBS +V 0.1mF(1) +2.7+ V5 tVo 3 VS+ GND 12 oder Y'/G' 4 NC DIS FHD 11 DFHisDable 75W 330mF(2) Y'/G’Out 75W Enc 37.4W 5 FHD1 IN FHD1 OUT 10 C/ +V DA 0.1mF(1) 6 FHD2 IN FHD2 OUT 9 C/ SO P’B/B' 7 FHD3 IN FHD3 OUT 8 37.4W P'/B’Out +V 75W 330mF(2) B 75W 0.1mF(1) P’ /R' R 37.4W R R PU PU P' /R’Out 75W 330mF(2) R 75W +2.7 V to +5 V (1) AC-coupledinputisshowninthisexample.DC-couplingisalsoallowedaslongastheDACoutputvoltageiswithintheallowablelinear inputandoutputvoltagerangeoftheTHS7372.Toapplydc-coupling,removethe0.1-μFinputcapacitorsandtheR pull-upresistors. PU (2) Thisexampleshowsanac-coupledoutput.DC-couplingisalsoallowedbysimplyremovingthesecapacitors. Figure89. TypicalACInputSystemDrivingAC-CoupledVideoLines 36 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 LOW-PASS FILTER Each channel of the THS7372 incorporates a sixth-order, low-pass filter. These video reconstruction filters minimize DAC images from being passed onto the video receiver. Depending on the receiver design, failure to eliminate these DAC images can cause picture quality problems because of aliasing of the ADC in the receiver. Another benefit of the filter is to smooth out aberrations in the signal that some DACs can have if the internal filtering is not very good. This benefit helps with picture quality and ensures that the signal meets video bandwidthrequirements. Each filter has an associated Butterworth characteristic. The benefit of the Butterworth response is that the frequency response is flat with a relatively steep initial attenuation at the corner frequency. The problem with this characteristic is that the group delay rises near the corner frequency. Group delay is defined as the change in phase (radians/second) divided by a change in frequency. An increase in group delay corresponds to a time domainpulseresponsethathasovershootandsomepossibleringingassociatedwiththeovershoot. The use of other type of filters, such as elliptic or chebyshev, are not recommended for video applications because of the very large group delay variations near the corner frequency resulting in significant overshoot and ringing. While these filters may help meet the video standard specifications with respect to amplitude attenuation, the group delay is well beyond the standard specifications. Considering this delay with the fact that video can go from a white pixel to a black pixel over and over again, it is easy to see that ringing can occur. Ringing typically causes a display to have ghosting or fuzziness appear on the edges of a sharp transition. On the other hand, a Bessel filter has ideal group delay response, but the rate of attenuation is typically too low for acceptable image rejection.Thus,theButterworthfilterisanacceptablecompromiseforbothattenuationandgroupdelay. The THS7372 SD filter has a nominal corner (–3-dB) frequency at 9.5 MHz and a –1-dB passband typically at 8.2 MHz. This 9.5-MHz filter is ideal for SD NTSC, PAL, and SECAM composite video (CVBS) signals. The 9.5-MHz,–3-dBcornerfrequencywasdesignedtoachieve54dBofattenuationat27MHz—acommonsampling frequency between the DAC/ADC second and third Nyquist zones found in many video systems. This consideration is important because any signal that appears around this frequency can also appear in the basebandasaresultofaliasingeffectsofanADCfoundinareceiver. The THS7372 FHD filters have a nominal corner (–3-dB) frequency at 72 MHz and a –1-dB passband typically at 60 MHz. This 72-MHz filter is ideal for 1080p50 or 1080p60 component video. It is also ideal for oversampling systems where the video DAC upsamples the video signal such as 720p or 1080i upsampled to 148.5 MHz. The benefitisanextremelyflatpassbandresponsealongwithalmostnogroupdelaywithintheHDvideopassband. Keep in mind that images do not stop at the DAC sampling frequency, f (for example, 27 MHz for traditional SD S DACs); they continue around the sampling frequencies of 2x f , 3x f , 4x f , and so on (that is, 54 MHz, 81 MHz, S S S 108MHz,etc.).Becauseofthesemultipleimages,anADCcanfolddownintothebasebandsignal,meaningthat thelow-passfiltermustalsoeliminatethesehigher-orderimages.TheTHS7372filtersareButterworthfiltersand, assuch,donotbounceathigherfrequencies,thusmaintaininggoodattenuationperformance. The filter frequencies were chosen to account for process variations in the THS7372. To ensure the required video frequencies are effectively passed, the filter corner frequency must be high enough to allow component variations. The other consideration is that the attenuation must be large enough to ensure the anti-aliasing/reconstruction filtering is sufficient to meet the system demands. Thus, the selection of the filter frequencies was not arbitrarily selected and is a good compromise that should meet the demands of most systems. BENEFITS OVER PASSIVE FILTERING Twokeybenefitsofusinganintegratedfiltersystem,suchastheTHS7372,overapassivesystemarePCBarea and filter variations. The small TSSOP-14 package for four video channels is much smaller over a passive RLC network, especially a six-pole passive network. Additionally, consider that inductors have at best ±10% tolerances (normally, ±15% to ±20% is common) and capacitors typically have ±10% tolerances. Using a Monte Carlo analysis shows that the filter corner frequency (–3 dB), flatness (–1 dB), Q factor (or peaking), and channel-to-channel delay have wide variations. These variances can lead to potential performance and quality issues in mass-production environments. The THS7372 solves most of these problems with the corner frequency beingessentiallytheonlyvariable. Copyright©2011,TexasInstrumentsIncorporated 37

THS7372 SBOS578–AUGUST2011 www.ti.com Another concern about passive filters is the use of inductors. Inductors are magnetic components, and are therefore susceptible to electromagnetic coupling/interference (EMC/EMI). Some common coupling can occur because of other video channels nearby using inductors for filtering, or it can come from nearby switched-mode power supplies. Some other forms of coupling could be from outside sources with strong EMI radiation and can causefailureinEMCtestingsuchasrequiredforCEcompliance. One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the ambient temperature and the subsequent die temperature changes. To minimize temperature effects, the THS7372 uses low-temperature coefficient resistors and high-quality, low-temperature coefficient capacitors foundintheBiCom3Xprocess.Thesefiltershavebeenspecifiedby design to account for process variations and temperature variations to maintain proper filter characteristics. This approach maintains a low channel-to-channel timedelaythatisrequiredforpropervideosignalperformance. Another benefit of the THS7372 over a passive RLC filter is the input and output impedance. The input impedance presented to the DAC varies significantly, from 35 Ω to over 1.5 kΩ with a passive network, and may cause voltage variations over frequency. The THS7372 input impedance is 800 kΩ, and only the 2-pF input capacitance plus the PCB trace capacitance impact the input impedance. As such, the voltage variation appearing at the DAC output is better controlled with a fixed termination resistor and the high input impedance bufferoftheTHS7372. On the output side of the filter, a passive filter again has a large impedance variation over frequency. The EIA/CEA-770 specifications require the return loss to be at least 25 dB over the video frequency range of usage. For a video system, this requirement implies the source impedance (which includes the source, series resistor, and the filter) must be better than 75 Ω, ±9 Ω. The THS7372 is an operational amplifier that approximates an ideal voltage source, which is desirable because the output impedance is very low and can source and sink current.Toproperlymatchthetransmissionlinecharacteristicimpedanceofavideoline,a75-Ω seriesresistoris placed on the output. To minimize reflections and to maintain a good return loss meeting EIA/CEA specifications, this output impedance must maintain a 75-Ω impedance. A wide impedance variation of a passive filter cannot ensurethislevelofperformance.Ontheotherhand,theTHS7372hasapproximately0.7Ω ofoutputimpedance, or a return loss of 47 dB, at 6.75 MHz for the SD filter and approximately 4 Ω of output impedance, or a return loss of 32 dB, at 60 MHz for the FHD filters. Thus, the system is matched significantly better with a THS7372 comparedtoapassivefilter. One final benefit of the THS7372 over a passive filter is power dissipation. A DAC driving a video line must be able to drive a 37.5-Ω load: the receiver 75-Ω resistor and the 75-Ω impedance matching resistor next to the DAC to maintain the source impedance requirement. This requirement forces the DAC to drive at least 1.25 V P (100% saturation CVBS)/37.5 Ω = 33.3 mA. A DAC is a current-steering element, and this amount of current flows internally to the DAC even if the output is 0 V. Thus, power dissipation in the DAC may be very high, especially when four channels are being driven. Using the THS7372 with a high input impedance and the capability to drive up to two video lines per channel can reduce DAC power dissipation significantly. This outcome is possible because the resistance that the DAC drives can be substantially increased. It is common to set this resistance in a DAC by a current-setting resistor on the DAC itself. Thus, the resistance can be 300 Ω or more, substantially reducing the current drive demands from the DAC and saving significant amounts of power. For example, a 3.3-V, four-channel DAC dissipates 440 mW alone for the steering current capability (four channels × 33.3 mA × 3.3 V) if it must drive a 37.5-Ω load. With a 300-Ω load, the DAC power dissipation as a resultofcurrentsteeringcurrentwouldonlybe55mW(fourchannels×4.16mA ×3.3V). 38 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 EVALUATION MODULE To evaluate the THS7372, an evaluation module (EVM) is available. The THS7372EVM allows for testing the THS7372 in many different configurations. Inputs and outputs include BNC connectors and RCA connectors commonly found in video systems, along with 75-Ω input termination resistors, 75-Ω series source termination resistors, and 75-Ω characteristic impedance traces. Several unpopulated component pads are found on the EVM to allow for different input and output configurations as dictated by the user. This EVM is designed to be usedwithasinglesupplyfrom2.6Vupto5V. The EVM default input configuration sets all channels for dc input coupling. The input signal must be within 0 V to approximately 1.4 V for proper operation. Failure to be within this range saturates and/or clips the output signal. If the input range is beyond this, if the signal voltage is unknown, or if coming from a current sink DAC, thenacinputconfigurationisdesired.ThisoptioniseasilyaccomplishedwiththeEVMbysimplyreplacingtheZ 1 throughZ 0-Ω resistorswith0.1-μFcapacitors. 4 For an ac-coupled input and sync-tip clamp (STC) functionality commonly used for CVBS, component Y' signals, and R'G'B' signals, no other changes are needed. However, if a bias voltage is needed after the input capacitor which is commonly needed for component P' and P' , then a pull-up resistor should be added to the signal on B, R the EVM. This configuration is easily achieved by simply adding a resistor to any of the following resistor pads; RX4 to RX6 for the FHD channels and RX8 for the CVBS channel. A common value to use is 3.3 MΩ. Note that evensignalswithembeddedsynccanalsousebiasmodeifdesired. The EVM default output configuration sets all channels for ac output coupling. The 470-μF and 0.1-μF capacitors work well for most ac-coupled systems. However, if dc-coupled output is desired, then replacing the 0.1-μF capacitors (C24, C26, C28, and/or C30) with 0-Ω resistors works well. Removing the 470-μF capacitors is optional, but removing them from the EVM eliminates a few picofarads of stray capacitance on each signal path whichmaybedesirable. The THS7372 incorporates an easy method to configure the disable modes. The use of JP1 controls the SD channeldisablefeature;JP3controlstheFHDchannelsdisablefeature. Connection of JP1 and JP3 to GND applies 0 V to the disable pins and the THS7372 operates normally. Moving JP1 to +V causes the THS7372 SD channel to be in disable mode, while moving JP3 to +V causes the S S THS7372FHDchannelstobeindisablemode. Figure90showstheTHS7372EVMschematic.Figure92andFigure93illustratethetwolayersoftheEVMPCB, incorporatingstandardhigh-speedlayoutpractices.Table7liststhebillofmaterialsastheboardcomessupplied fromTexasInstruments. Copyright©2011,TexasInstrumentsIncorporated 39

THS7372 SBOS578–AUGUST2011 www.ti.com + + Figure90. THS7372EVMSchematic1 40 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 Figure91. THS7372EVMSchematic2 Copyright©2011,TexasInstrumentsIncorporated 41

THS7372 SBOS578–AUGUST2011 www.ti.com Figure92. THS7372EVMPCBTopLayer Figure93. THS7372EVMPCBBottomLayer 42 Copyright©2011,TexasInstrumentsIncorporated

THS7372 www.ti.com SBOS578–AUGUST2011 THS7372EVM Bill of Materials Table7.THS7372EVMPartsList MANUFACTURER DISTRIBUTOR ITEM REFDES QTY DESCRIPTION SMDSIZE PARTNUMBER PARTNUMBER (DIGI-KEY) 1 FB1,FB2 2 Bead,ferrite,2.5A,330Ω 805 (TDK)MPZ2012S331A 445-1569-1-ND Capacitor,100µF,tantalum,10V,10%,low (DIGI-KEY) 2 C17 1 C (AVX)TPSC107K010R0100 ESR 478-1765-1-ND Capacitor,22µF,tantalum,16V,10%,low (DIGI-KEY) 3 C18 1 C (AVX)TPSC226K016R0375 ESR 478-1767-1-ND C5-C8, 4 C19-C22, 12 Open 0805 — — C31-C34 (DIGI-KEY) 5 C15 1 Capacitor,0.01µF,ceramic,100V,X7R 0805 (AVX)08051C103KAT2A 478-1358-1-ND C1-C4,C10, C12-C14,C16, (DIGI-KEY) 6 17 Capacitor,0.1µF,ceramic,50V,X7R 0805 (AVX)08055C104KAT2A C24,C26,C28, 478-1395-1-ND C30,C35-C38 (DIGI-KEY) 7 C9,C11 2 Capacitor,0.1µF,ceramic,50V,X7R 1206 (AVX)12065C104KAT2A 478-1556-1-ND C23,C25,C27, (PANASONIC) (DIGI-KEY) 8 4 Capacitor,aluminum,470µF,10V,20% F C29 EEE-FP1A471AP PCE4526CT-ND RX1-RX12,R7, 9 16 Open 0603 — — R10,R12,R14 Z1-Z4,R1, (DIGI-KEY) 10 12 Resistor,0Ω 0805 (ROHM)MCR10EZHJ000 R16-R21,R26 RHM0.0ACT-ND R2-R5, (DIGI-KEY) 11 8 Resistor,75Ω,1/8W,1% 0805 (ROHM)MCR10EZHF75.0 R22-R25 RHM75.0CCT-ND (DIGI-KEY) 12 R8 1 Resistor,100Ω,1/8W,1% 0805 (ROHM)MCR10EZHF1000 RHM100CCT-ND (DIGI-KEY) 13 R6,R13 2 Resistor,1kΩ,1/8W,1% 0805 (ROHM)MCR10EZHF1001 RHM1.00KCCT-ND (DIGI-KEY) 14 R9,R11 2 Resistor,100kΩ,1/8W,1% 0805 (ROHM)MCR10EZHF1003 RHM100KCCT-ND (DIGI-KEY) 15 R15 1 Resistor,1kΩ,1/4W,1% 1206 (ROHM)MCR18EZHF1001 RHM1.00KFCT-ND (DIGI-KEY) 16 D1-D8 8 Diode,ultrafast (FAIRCHILD)BAV99 BAV99FSCT-ND Jack,bananareceptance,0.25"diameter 17 J6,J7 2 (SPC)813 (NEWARK)39N867 hole J1-J3,J5, (AMPHENOL) 18 8 Connector,BNC,jack,75Ω (NEWARK)93F7554 J11-J14 31-5329-72RFX 19 J8 1 Connector,SMA,jack,50Ω (AMPHENOL)901-144-8RFX (DIGI-KEY)ARFX1231-ND 20 J4,J15 2 Connector,RCAjack,yellow (CUI)RCJ-044 (DIGI-KEY)CP-1421-ND 21 J9,J10 2 Connector,RCA,jack,R/A (CUI)RCJ-32265 (DIGI-KEY)CP-1446-ND 22 TP1,TP2 2 Testpoint,black (KEYSTONE)5001 (DIGI-KEY)5001K-ND 23 JP1-JP4 4 Header,0.1"CTRS,0.025"squarepins 3pos. (SULLINS)PBC36SAAN (DIGI-KEY)S1011E-36-ND 24 JP1-JP4 4 Shunts (SULLINS)SSC02SYAN (DIGI-KEY)S9002-ND 25 U1 1 IC,THS7372 PW (TI)THS7372IPW — 26 4 Standoff,4-40hex,0.625"length (KEYSTONE)1808 (DIGI-KEY)1808K-ND 27 4 Screw,Phillips,4-40,.250" (BF)PMS4400031PH (DIGI-KEY)H343-ND 28 1 Board,printedcircuit EDGE#6526621REV.A — Copyright©2011,TexasInstrumentsIncorporated 43

THS7372 SBOS578–AUGUST2011 www.ti.com EVALUATIONBOARD/KITIMPORTANTNOTICE TexasInstruments(TI)providestheenclosedproduct(s)underthefollowingconditions: Thisevaluationboard/kitisintendedforuseforENGINEERINGDEVELOPMENT,DEMONSTRATION,OREVALUATIONPURPOSES ONLYandisnotconsideredbyTItobeafinishedend-productfitforgeneralconsumeruse.Personshandlingtheproduct(s)musthave electronicstrainingandobservegoodengineeringpracticestandards.Assuch,thegoodsbeingprovidedarenotintendedtobecomplete intermsofrequireddesign-,marketing-,and/ormanufacturing-relatedprotectiveconsiderations,includingproductsafetyandenvironmental measurestypicallyfoundinendproductsthatincorporatesuchsemiconductorcomponentsorcircuitboards.Thisevaluationboard/kitdoes notfallwithinthescopeoftheEuropeanUniondirectivesregardingelectromagneticcompatibility,restrictedsubstances(RoHS),recycling (WEEE),FCC,CEorUL,andthereforemaynotmeetthetechnicalrequirementsofthesedirectivesorotherrelateddirectives. Shouldthisevaluationboard/kitnotmeetthespecificationsindicatedintheUser’sGuide,theboard/kitmaybereturnedwithin30daysfrom thedateofdeliveryforafullrefund.THEFOREGOINGWARRANTYISTHEEXCLUSIVEWARRANTYMADEBYSELLERTOBUYER ANDISINLIEUOFALLOTHERWARRANTIES,EXPRESSED,IMPLIED,ORSTATUTORY,INCLUDINGANYWARRANTYOF MERCHANTABILITYORFITNESSFORANYPARTICULARPURPOSE. Theuserassumesallresponsibilityandliabilityforproperandsafehandlingofthegoods.Further,theuserindemnifiesTIfromallclaims arisingfromthehandlingoruseofthegoods.Duetotheopenconstructionoftheproduct,itistheuser’sresponsibilitytotakeanyandall appropriateprecautionswithregardtoelectrostaticdischarge. EXCEPTTOTHEEXTENTOFTHEINDEMNITYSETFORTHABOVE,NEITHERPARTYSHALLBELIABLETOTHEOTHERFORANY INDIRECT,SPECIAL,INCIDENTAL,ORCONSEQUENTIALDAMAGES. TIcurrentlydealswithavarietyofcustomersforproducts,andthereforeourarrangementwiththeuserisnotexclusive. TIassumesnoliabilityforapplicationsassistance,customerproductdesign,softwareperformance,orinfringementofpatentsor servicesdescribedherein. PleasereadtheUser’sGuideand,specifically,theWarningsandRestrictionsnoticeintheUser’sGuidepriortohandlingtheproduct.This noticecontainsimportantsafetyinformationabouttemperaturesandvoltages.ForadditionalinformationonTI’senvironmentaland/or safetyprograms,pleasecontacttheTIapplicationengineerorvisitwww.ti.com/esh. NolicenseisgrantedunderanypatentrightorotherintellectualpropertyrightofTIcoveringorrelatingtoanymachine,process,or combinationinwhichsuchTIproductsorservicesmightbeorareused. FCCWarning Thisevaluationboard/kitisintendedforuseforENGINEERINGDEVELOPMENT,DEMONSTRATION,OREVALUATIONPURPOSES ONLYandisnotconsideredbyTItobeafinishedend-productfitforgeneralconsumeruse.Itgenerates,uses,andcanradiateradio frequencyenergyandhasnotbeentestedforcompliancewiththelimitsofcomputingdevicespursuanttopart15ofFCCrules,whichare designedtoprovidereasonableprotectionagainstradiofrequencyinterference.Operationofthisequipmentinotherenvironmentsmay causeinterferencewithradiocommunications,inwhichcasetheuserathisownexpensewillberequiredtotakewhatevermeasuresmay berequiredtocorrectthisinterference. EVMWARNINGSANDRESTRICTIONS ItisimportanttooperatethisEVMwithintheinputvoltagerangeof2.6Vto5.5Vsingle-supplyandtheoutputvoltagerangeof0Vto 5.5V. Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamagetotheEVM.Iftherearequestions concerningtheinputrange,pleasecontactaTIfieldrepresentativepriortoconnectingtheinputpower. Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/orpossiblepermanentdamagetotheEVM. PleaseconsulttheEVMUser'sGuidepriortoconnectinganyloadtotheEVMoutput.Ifthereisuncertaintyastotheloadspecification, pleasecontactaTIfieldrepresentative. Duringnormaloperation,somecircuitcomponentsmayhavecasetemperaturesgreaterthan+85°C.TheEVMisdesignedtooperate properlywithcertaincomponentsabove+85°Caslongastheinputandoutputrangesaremaintained.Thesecomponentsincludebutare notlimitedtolinearregulators,switchingtransistors,passtransistors,andcurrentsenseresistors.Thesetypesofdevicescanbeidentified usingtheEVMschematiclocatedintheEVMUser'sGuide.Whenplacingmeasurementprobesnearthesedevicesduringoperation, pleasebeawarethatthesedevicesmaybeverywarmtothetouch. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2009,TexasInstrumentsIncorporated 44 Copyright©2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS7372IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 THS7372 & no Sb/Br) THS7372IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 THS7372 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS7372IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS7372IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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