Product Sample & Technical Tools & Support & Folder Buy Documents Software Community THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 THS413x High-Speed, Low-Noise, Fully-Differential I/O Amplifiers 1 Features 3 Description • HighPerformance The THS413x device is one in a family of fully- 1 differential input/differential output devices fabricated – 150MHz,–3dBBandwidth(V =±15V) CC using Texas Instruments' state-of-the-art BiComI – 51V/µsSlewRate complementarybipolarprocess. – –100dBThirdHarmonicDistortionat TheTHS413xismadeofatruefully-differentialsignal 250kHz path from input to output. This design leads to an • LowNoise excellent common-mode noise rejection and improvedtotalharmonicdistortion. – 1.3nV/√HzInput-ReferredNoise • Differential-Input/Differential-Output DeviceInformation(1) – BalancedOutputsRejectCommon-Mode PARTNUMBER PACKAGE BODYSIZE(NOM) Noise SOIC(8) 4.90mmx3.91mm – ReducedSecond-HarmonicDistortionDueto THS4130 VSSOP(8) 3.00mmx3.00mm DifferentialOutput HVSSOP(8) 3.00mmx3.00mm • WidePower-SupplyRange SOIC(8) 4.90mmx3.91mm – V =5VSingleSupplyto ±15VDualSupply CC THS4131 VSSOP(8) 3.00mmx3.00mm • ICC(SD)=860µAinShutdownMode(THS4130) HVSSOP(8) 3.00mmx3.00mm (1) For all available packages, see the orderable addendum at 2 Applications theendofthedatasheet. • Single-EndedToDifferentialConversion • DifferentialADCDriver • DifferentialAntialiasing • DifferentialTransmitterAndReceiver • OutputLevelShifter TypicalA/DApplicationCircuit TotalHarmonicDistortionvsFrequency V −20 DD B VOUT= 2 VPP 5 V d −30 − n VIN VOCM + − AINAVDD DVDD c Distortio −−5400 − + AIN AVSS Vref DOIUGTITPAULT armoni −60 VCC= 5 V to±5 V H −70 al −5 V otT −80 − THD −90 VCC =±15 V −100 100 k 1 M 10 M f−Frequency−Hz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................16 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 18 3 Description............................................................. 1 9.1 ApplicationInformation............................................18 4 RevisionHistory..................................................... 2 9.2 TypicalApplication .................................................20 5 DeviceComparisonTables................................... 3 10 PowerSupplyRecommendations..................... 22 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 22 11.1 LayoutGuidelines.................................................22 7 Specifications......................................................... 4 11.2 LayoutExample....................................................23 7.1 AbsoluteMaximumRatings......................................4 11.3 GeneralPowerPADDesignConsiderations.........24 7.2 ESDRatings..............................................................4 12 DeviceandDocumentationSupport................. 26 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................5 12.1 DocumentationSupport .......................................26 7.5 ElectricalCharacteristics...........................................5 12.2 RelatedLinks........................................................26 7.6 DissipationRatings...................................................7 12.3 CommunityResources..........................................26 7.7 TypicalCharacteristics..............................................8 12.4 Trademarks...........................................................26 12.5 ElectrostaticDischargeCaution............................26 8 DetailedDescription............................................ 13 12.6 Glossary................................................................26 8.1 Overview.................................................................13 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................15 Information........................................................... 26 8.3 FeatureDescription.................................................15 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionH(May2011)toRevisionI Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection............................... 1 ChangesfromRevisionG(January2010)toRevisionH Page • ChangedfootnoteAinFigure45......................................................................................................................................... 25 ChangesfromRevisionF(January2006)toRevisionG Page • ChangedDGKpackagespecificationsintheDissipationRatingtable.................................................................................. 7 2 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 5 Device Comparison Tables Table1.AvailableDevicePackages PACKAGEDDEVICES MSOPPowerPAD™ MSOP SMALLOUTLINE EVALUATION T (D) (DGN) SYMBOL (DGK) SYMBOL MODULES A THS4130CD THS4130CDGN AOB THS4130CDGK ATP THS4130EVM 0°Cto+70°C THS4131CD THS4131CDGN AOD THS4131CDGK ATQ THS4131EVM THS4130ID THS4130IDGN AOC THS4130IDGK ASO — –40°Cto+85°C THS4131ID THS4131IDGN AOE THS4131IDGK ASP — Table2.DeviceDescriptionTable DEVICE DESCRIPTION THS412x 100MHz,43V/µs,3.7nV/√Hz THS414x 160MHz,450V/µs,6.5nV/√Hz THS415x 180MHz,850V/µs,9nV/√Hz 6 Pin Configuration and Functions D,DGN,orDGKPackage D,DGN,orDGKPackage 8-PinSOIC,VSSOP,orHVSSOP 8-PinSOIC,VSSOP,orHVSSOP THS4130TopView THS4131TopView V - 1 8 V + V - 1 8 V + IN IN IN IN V 2 7 PD V 2 7 NC OCM OCM V + 3 6 V - V + 3 6 V - CC CC CC CC V + 4 5 V - V + 4 5 V - OUT OUT OUT OUT PinFunctions PIN I/O DESCRIPTION NAME THS4130 THS4131 NC — 7 — Noconnect PD 7 — I Activelowpowerdownpin V 3 3 I/O Positivesupplyvoltagepin CC+ V 6 6 I/O Negativesupplyvoltagepin CC– V 1 1 I Negativeinputpin IN– V 2 2 I Commonmodeinputpin OCM V 4 4 O Positiveoutputpin OUT+ V 5 5 O Negativeoutputpin OUT– V 8 8 I Positiveinputpin IN+ Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Inputvoltage –V +V V I CC CC V toV Supplyvoltage –33 33 V CC– CC+ I (2) Outputcurrent 150 mA O V Differentialinputvoltage –6 6 V ID Continuoustotalpowerdissipation SeeDissipationRatings T (3) Maximumjunctiontemperature 150 °C J T (4) Maximumjunctiontemperature,continuousoperation,long-termreliability 125 °C J C-suffix 0 70 °C T Operatingfree-airtemperature A I-suffix –40 85 °C T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) TheTHS413xmayincorporateaPowerPADontheundersideofthechip.Thisactsasaheatsinkandmustbeconnectedtoathermally dissipativeplaneforproperpowerdissipation.Failuretodosomayresultinexceedingthemaximumjunctiontemperaturewhichcould permanentlydamagethedevice.SeeTItechnicalbriefsSLMA002andSLMA004formoreinformationaboutusingthePowerPAD thermally-enhancedpackage. (3) Theabsolutemaximumtemperatureunderanyconditionislimitedbytheconstraintsofthesiliconprocess. (4) Themaximumjunctiontemperatureforcontinuousoperationislimitedbypackageconstraints.Operationabovethistemperaturemay resultinreducedreliabilityand/orlifetimeofthedevice. 7.2 ESD Ratings VALUE UNIT THS4130:D,DGN,ORDGKPACKAGES Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(1) ±1500 THS4131:D,DGN,ORDGKPACKAGES Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Dualsupply ±2.5 ±15 V toV V cc+ cc– Singlesupply 5 30 C-suffix 0 70 T °C A I-suffix –40 85 4 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 7.4 Thermal Information THS413x THERMALMETRIC(1) D(SOIC) DGN(VSSOP) DGK UNIT (HVSSOP) 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 114.5 55.8 182.5 °C/W θJA R Junction-to-case(top)thermalresistance 60.3 61.6 72.3 °C/W θJC(top) R Junction-to-boardthermalresistance 54.8 34.5 103.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 14 13.8 11.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 54.3 34.4 101.9 °C/W JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 7.5 Electrical Characteristics(1) V =±5V,R =800Ω,andT =+25°C,unlessotherwisenoted. CC L A MA PARAMETER TESTCONDITIONS MIN TYP UNIT X DYNAMICPERFORMANCE Gain=1,R V =5 f 125 CC =390Ω Small-signalbandwidth(–3dB), Gain=1,R single-endedinput,differential V =±5 f 135 CC =390Ω output,V =63mV I PP Gain=1,R V =±15 f 150 CC =390Ω BW MHz Gain=2,R V =5 f 80 CC =750Ω Small-signalbandwidth(–3dB), Gain=2,R single-endedinput,differential V =±5 f 85 CC =750Ω output,V =63mV I PP Gain=2,R V =±15 f 90 CC =750Ω SR Slewrate(2) Gain=1 52 V/µs Settlingtimeto0.1% Stepvoltage=2V,gain=1 78 t ns s Settlingtimeto0.01% Stepvoltage=2V,gain=1 213 DISTORTIONPERFORMANCE f=250kHz –95 V =5 CC f=1MHz –81 Totalharmonicdistortion, differentialinput,differential f=250kHz –96 V =±5 output,gain=1,Rf=390Ω,RL= CC f=1MHz –80 800Ω,V =2V O PP TH f=250kHz –97 V =±15 dBc D CC f=1MHz –80 f=250kHz –91 V =±5 CC f=1MHz –75 V =4V O PP f=250kHz –91 V =±15 CC f=1MHz –75 V =±2.5 97 CC Spurious-freedynamicrange, V =2V V =±5 98 O PP CC SF differentialinput,differential V =±15 99 dB DR output,gain=1,R =390Ω, CC f RL=800Ω,f=250kHz VCC=±5 93 V =4V O PP V =±15 95 CC (1) Thefullrangetemperatureis0°Cto+70°CfortheC-suffix,and–40°Cto+85°CfortheI-suffix. (2) Slewrateismeasuredfromanoutputlevelrangeof25%to75%. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Electrical Characteristics(1) (continued) V =±5V,R =800Ω,andT =+25°C,unlessotherwisenoted. CC L A MA PARAMETER TESTCONDITIONS MIN TYP UNIT X Thirdintermodulationdistortion V =4V,G=1,F1=3MHz,F2=3.5MHz –53 dBc I(PP) Third-orderintercept V =4V,G=1,F1=3MHz,F2=3.5MHz 41.5 dB I(PP) NOISEPERFORMANCE nV/√ V Inputvoltagenoise f=10kHz 1.3 n Hz pA/√ I Inputcurrentnoise f=10kHz 1 n Hz DCPERFORMANCE T =+25°C 71 78 A Open-loopgain dB T =fullrange 69 A T =+25°C 0.2 2 A Inputoffsetvoltage T =fullrange 3 A mV V(O Common-modeinputoffset T =+25°C 0.2 3.5 S) voltage,referredtoVOCM A µV/° Inputoffsetvoltagedrift T =fullrange 4.5 A C I Inputbiascurrent T =fullrange 2 6 µA IB A I Inputoffsetcurrent T =fullrange 100 500 nA OS A nA/° Offsetdrift 2 C INPUTCHARACTERISTICS CM Common-moderejectionratio T =fullrange 80 95 dB RR A –3.7 V Common-modeinputvoltage –4to IC 7to V range 4.5 R 4.3 R Inputresistance Measuredintoeachinputterminal 34 MΩ I C Inputcapacitance,closedloop 4 pF I r Outputresistance Openloop 41 Ω o OUTPUTCHARACTERISTICS 1.2 0.9 T =+25°C to to A 3.8 4.1 V =5V CC 1.3 T =full A to ±4 range 3.7 Outputvoltageswing TA=+25°C ±3.7 V VCC=±5V TA=full ±3.6 range ±10. ±12. T =+25°C A 5 4 V =±15V CC T =full ±10. A range 2 6 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 Electrical Characteristics(1) (continued) V =±5V,R =800Ω,andT =+25°C,unlessotherwisenoted. CC L A MA PARAMETER TESTCONDITIONS MIN TYP UNIT X T =+25°C 25 45 A VCC=5V,RL=7Ω TA=full 20 range T =+25°C 30 55 A IO Outputcurrent VCC=±5V,RL=7Ω TA=full 28 mA range T =+25°C 60 85 A VCC=±15V,RL=7Ω TA=full 65 range POWERSUPPLY Singlesupply 4 33 V C Supplyvoltagerange ±16 V C Splitsupply ±2 .5 T =+25°C 12.3 15 A I Quiescentcurrent VCC=±5V TA=full 16 mA CC range V =±15V T =+25°C 14 CC A T =+25°C 0.86 1.4 A I Quiescentcurrent(shutdown) SCDC)( (THS4130only)(3) V=–5V TA=full 1.5 mA range T =+25°C 73 98 A PS RR Power-supplyrejectionratio(dc) TA=full 70 dB range (3) Fordetailedinformationonthebehaviorofthepower-downcircuit,seethePower-DownModesection. 7.6 Dissipation Ratings POWERRATING(2) PACKAGE θ (1)(°C/W) θ (°C/W) T =+25°C T =+85°C JA JC A A D 97.5 38.3 1.02W 410mW DGN 58.4 4.7 1.71W 685mW DGK 134 72 750mW 300mW (1) ThisdatawastakenusingtheJEDECstandardHigh-KtestPCB. (2) Powerratingisdeterminedwithajunctiontemperatureof+125°C.Thisisthepointwheredistortionstartstosubstantiallyincrease. ThermalmanagementofthefinalPCBshouldstrivetokeepthejunctiontemperatureatorbelow+125°Cforbestperformanceand long-termreliability. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com 7.7 Typical Characteristics 25 3 20 Gain = 10_Rf= 4 kW RVVCIL=C= 6 =830± m05 WVVP,,P 21 GRVCLaCi=n = 8=0± 105, WV,, Rf= 620W VI= 63 mVPP 15 Gain = 5_Rf= 2 kW 0 −dB 10 −dB −−12 Rf= 390W Output 5 Gain = 2_Rf= 750W Output −3 −4 Gain = 1_Rf= 390W 0 −5 −6 −5 −7 −10 −8 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f−Frequency−Hz f−Frequency−Hz Figure1.Small-SignalFrequencyResponse Figure2.Small-SignalFrequencyResponse 2 3 VCC=±15 2 1 CF= 0 pF 1 0 0 −1 VCC= 5 −1 B dB −2 −d −2 utput− −3 Output −−43 CF= 1 pF O −4 −5 −5 −6 Gain = 1, −7 −6 RL= 800W, Rf= 390W, −8 −7 VI= 63 mVPP −9 −8 −10 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f−Frequency−Hz f−Frequency−Hz Figure3.Small-SignalFrequencyResponse(Various Figure4.Small-SignalFrequencyResponse(VariousC ) F Supplies) 5 1 4 GRLai=n 8=0 10,W, CL= 10 pF VO+ 3 VCC=±5 V, −V 0.5 21 VRIf== 6339 0mWVPP, ponse 0 s B −0 Re VO− −d −1 CL= 0 pF ent −0.5 ut si Outp −−32 ranal T 0.5 n −4 Sig 0 −−65 Large −0.5 VI(Diff) −7 −8 −1 100 k 1 M 10 M 100 M 1 G 0 0.1 0.2 0.3 0.4 0.5 0.6 f−Frequency−Hz t−Time−ms Figure5.Small-SignalFrequencyResponse(VariousC ) Figure6.Large-SignalTransientResponse(Differential L In/SingleOut) 8 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 Typical Characteristics (continued) 5 −50 VCC=±15 V −dB −55 RVCfC= =1 ±kW5 ,V 0 atio −60 R n −65 −5 ctio dB eje −70 ut− −10 de R −75 utp VCC=±5 V Mo O n −80 o −15 m m −85 Gain = 1 o −20 RRCfLF=== 38090 p00FWW,,, VCC= 5 V MRR−C −−9950 VI= 0.2 VRMS C −25 −100 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M f−Frequency−Hz f−Frequency−Hz Figure7.Large-SignalFrequencyResponse Figure8.Common-ModeRejectionRatiovsFrequency 15 940 14.5 920 14 urrent−mA 11231..355 VCC=±15 V Ay Current−m 898000 C pl pply 12 VCC=±5 V Sup 860 u − −S 11.5 CC 840 CC 11 I I 820 10.5 10 800 −40 −20 0 20 40 60 80 100 −50 −25 0 25 50 75 100 TA−Free-Air Temperature−°C TA−Free-Air Temperature (Shutdown State)−°C Figure9.SupplyCurrentvsFree-AirTemperature Figure10.SupplyCurrentvsFree-AirTemperature (ShutdownState) 2.4 2.04 2.35 2.02 A m nt− 2.3 −V 2 e e −Input Bias Curr 222..12.255 IIB+ −Output oltagVVO 111...999864 RCVVRCOFFLC==== = 5184 10 5 pV00 FVPW,WP IIB IIB− 2.1 1.92 2.05 1.9 −50 −25 0 25 50 75 100 0 25 50 75 100 125 150 TA−Free-Air Temperature−°C t−Time−ns Figure11.InputBiasCurrentvsFree-AirTemperature Figure12.SettlingTime Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Typical Characteristics (continued) −40 2.5 dB GRfa=in 3 =3 01,W, 2 VO+ atio− −50 RL= 400W 1.5 R pply Rejection −−7600 VCC= 5 V ut oltage−VV 051 GRRCCVIfLFL _==P=== e1 3a801,9k00 p00 =pFW W,F2,, ,V, er Su −80 Outp −5 VTACC= =25±°1C5 V w − −1 Po VCC=−5 V VO − −1.5 R −90 R PS −2 VO− −100 −2.5 10 k 100 k 1 M 10 M 100 M 0 40 80 120 160 200 f−Frequency (Differential Out)−Hz t−Time−nS Figure13.Power-SupplyRejectionRatiovsFrequency Figure14.Large-SignalTransientResponse (DifferentialOut) −20 −30 VO= 2 VPP, Single Ended Input dB −30 VOUT= 2 VPP c −40 RRLf== 389000WW,, Differential Output − B G = 1 on −40 −d −50 onic Distorti −−6500 VCC= 5 V to±5 V c Distortion −−7600 VCC= 5 V m ni ar mo al H −70 Har −80 ot−T −80 ond −90 THD −90 VCC=±15 V Sec −100 VCC=±15V,±5V −100 −110 100k 1M 10M 100 k 1 M 10 M f−Frequency−Hz f−Frequency−Hz Figure15.TotalHarmonicDistortionvsFrequency Figure16.Second-HarmonicDistortionvsFrequency −30 −92 −dBc −−5400 VRRGOLf ==== 1 3 8490 0V0PWWP,,, SDiinffgelree nEtniadle Odu Intppuutt dBc −94 fRRG =Lf = =2= 15 38090 0K0WHW,z, VCC=±5 V n − −96 monic Distortio −−7600 VCC=±5 V onic Distortion −−19080 VCC= 5 V VCC=±15 V ond Har −−9800 VCC=±15 V nd Harm −102 c o e c S e −100 S −104 Single Ended Input Differential Output −110 −106 100 k 1 M 10 M 0 1 2 3 4 5 6 7 f−Frequency−Hz VO−Output Voltage−V Figure17.Second-HarmonicDistortionvsFrequency Figure18.Second-HarmonicDistortionvsOutputVoltage 10 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 Typical Characteristics (continued) −88 −30 VCC=±15 V VO= 4 VPP −90 −40 RL= 800W, c Rf= 390W, VCC=±5 V −dB −92 dBc −50 G = 1 monic Distortion −−−999864 VCC=±5 V nic Distortion− −−7600 VCC=±15 V ond Har −−110020 VCC= 5 V d Harmo −−9800 Sec −104 SDiinffgelree nEtniadle Odu Intppuutt fRR =Lf =5= 0 38090 0K0WHW,z, Thir −100 Single Ended Input G = 1 Differential Output −106 −110 0 1 2 3 4 5 6 7 100 k 1 M 10 M VO−Output Voltage−V f−Frequency−Hz Figure19.Second-HarmonicDistortionvsOutputVoltage Figure20.Third-HarmonicDistortionvsFrequency −30 −88 VO= 2 VPP, −40 RRLf== 389000WW,, −90 VCC=±15 V dBc −50 Gain = 1 dBc −92 − − Third Harmonic Distortion −−−−98760000 SDiinffgeVlreCe CnEtn=iad±le 5Od uV Intppuutt VCC=±15 V Third Harmonic Distortion −−−−−119990086420 VCC= 5V VCfRRGC =Lf == =5= 1±0 380590 0 K0VWHW,z, −100 VCC= 5 V −104 Single Ended Input Differential Output −110 −106 100 k 1 M 10 M 0 1 2 3 4 5 6 7 f−Frequency−Hz VO−Output Voltage−V Figure21.Third-HarmonicDistortionvsFrequency Figure22.Third-HarmonicDistortionvsOutputVoltage −88 10 f = 250 KHz −90 RL= 800W, dBc −92 RGf == 1390W, VCC=±5 V z − H n Distortio −−9964 nV/se− monic −98 VCC= 5 V VCC=±15 V ge Noi Third Har −−110020 −VoltaVn −104 Single Ended Input Differential Output −106 1 0 1 2 3 4 5 6 7 10 100 1 k 10 k 100 k VO−Output Voltage−V f−Frequency−Hz Figure23.Third-HarmonicDistortionvsOutputVoltage Figure24.VoltageNoisevsFrequency Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Typical Characteristics (continued) 7E−12 1000 Rf= 1 k, Hz 56EE−−1122 Vge−m 680000 RGL == 1 800W, VCC=(cid:3)±2.5 V pA/ olta V e− 4E−12 et 400 s s −Current Noi 23EE−−1122 −Input OffS) 2000 VCC=(cid:3)±15 V VCC=(cid:3)±5 V In V(O −200 1E−12 −400 0 −600 1 10 100 1 k 10 k 100 k −12 −9 −6 −3 0 3 6 9 12 f−Frequency−Hz VOCM−Common-Mode Output Voltage−V Figure25.CurrentNoisevsFrequency Figure26.InputOffsetVoltagevsCommon-ModeOutput Voltage 15 100 RGf == 21 k VCC=±15 V VCC=(cid:3)±5 V 10 VOUT+ e−V 5 VOUT+ VCC=±5 V We− 10 g c a n olt da V e ut 0 mp Outp VOUT− VCC=±5 V put i −O −5 Out 1 V − o VOUT− z −10 VCC=±15 V −15 0.1 100 1000 10 k 100 k 100 k 1 M 10 M 100 M 1 G RL−Differential Load Resistance−W f−Frequency−Hz Figure27.OutputVoltagevsDifferentialLoadResistance Figure28.OutputImpedancevsFrequency 12 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 8 Detailed Description 8.1 Overview The THS413x is a fully-differential amplifier. Differential amplifiers are typically differential in/single out, whereas fully-differentialamplifiersaredifferentialin/differentialout. DifferentialAmplifier THS413x Rf Fully differentialAmplifier VCC+ R(g) _ VIN− _ + VO+ _ + VIN+ + VO− R(g) Rf VOCM VCC− Figure29. DifferentialAmplifierVersusaFully-DifferentialAmplifier To understand the THS413x fully-differential amplifiers, the definition for the pin outs of the amplifier are provided. (V )+(V ) Input voltage definition V =(V )-(V )V = I+ I- ID I+ I- IC 2 (1) (V )+(V ) Output voltage definition V =(V )-(V ) V = O+ O- OD O+ O- OC 2 (2) Transfer function V = V ´A OD ID (f) (3) Output commonmode voltage V = V OC OCM (4) Differential Structure Rejects Differential Structure Rejects Coupled Noise at The Input VCC+ Coupled Noise at The Output _ VIN− + VO+ _ VIN+ + VO− Differential Structure Rejects Coupled Noise at The Power Supply VOCM VCC− Figure30. DefinitionoftheFully-DifferentialAmplifier If each output is measured independently, each output is one-half of the input signal when gain is 1. The followingequationsexpressthetransferfunctionforeachoutput: 1 V = V O 2 I (5) Thesecondoutputisequalandoppositeinsign: 1 V =- V O 2 I (6) Fully-differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting amplifier holds true for gain calculations. One advantage of fully-differential amplifiers is that they offer twice as much dynamic range compared to single-ended amplifiers. For example, a 1-V ADC can only support an input PP signal of 1 V . If the output of the amplifier is 2 V , then it is not as practical to feed a 2-V signal into the PP PP PP targetedADC.Usingafully-differentialamplifierenablestheusertobreakdowntheoutputintotwo1-V signals PP withoppositesignsandfeedthemintothedifferentialinputnodesoftheADC.Inpractice,thedesignerhasbeen Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Overview (continued) abletofeeda2-Vpeak-to-peaksignalintoa1-VdifferentialADCwiththehelpofafully-differentialamplifier.The final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. The THS413x fully-differential amplifier offers an improved CMRR andPSRRduetoitssymmetricalinputandoutput.Furthermore,second-harmonicdistortionisimproved.Second harmonicstendtocancelbecauseofthesymmetricaloutput. a VOD= 1−0 = 1 VCC+ +1 _ VIN− + VO+ 0 _ VIN+ + VO− +1 VOCM 0 VCC− b VOD= 0−1 =−1 Figure31. Fully-DifferentialAmplifierWithTwo1-V Signals PP Similartothestandardinvertingamplifierconfiguration,inputimpedanceofafully-differentialamplifierisselected by the input resistor, R . If input impedance is a constraint in design, the designer may choose to implement the (g) differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fully- differentialamplifier.Figure32depictsthegeneralformatofinstrumentationamplifiers. Thegeneraltransferfunctionforthiscircuitis: V R æ 2R2ö OD = f ç1+ ÷ VIN1-VIN2 R(g)è R1 ø (7) THS4012 VIN1 + R(g) Rf _ R2 _ R1 THS413x + R2 _ VIN2 + THS4012 R(g) Rf Figure32. InstrumentationAmplifier 14 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 8.2 Functional Block Diagram VCC+ Output Buffer VIN− x1 VOUT+ C R VIN+ Vcm Error Amplifier + _ C R x1 VOUT− Output Buffer VCC+ 30 kW VCC− 30 kW VCC− VOCM 8.3 Feature Description Figure33andFigure34depictthedifferencesbetweentheoperationoftheTHS413xfully-differentialamplifierin two different modes. Fully-differential amplifiers can work with differential input or can be implemented as single in/differentialout. Rf VCC+ VIN− R(g) − + VO+ Vs VIN+ + − VOCM VO− R(g) VCC− Rf Note: For proper operation, maintain symmetry by setting Rf1 = Rf2 = Rfand R(g)1 = R(g)2 = R(g)⇒A= Rf/R(g) Figure33. AmplifyingDifferentialSignals Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Feature Description (continued) Rf VIN− R(g) VCC+ RECOMMENDED RESISTOR VALUES − + VO+ GAIN R(g)W RfW 1 390 390 VIN+ + − VOCM VO− 25 347042 7250010 R(g) 10 402 4020 Vs VCC− Rf Figure34. SingleInWithDifferentialOut 8.4 Device Functional Modes 8.4.1 Power-DownMode The power-down mode is used when power saving is required. The power-down terminal (PD) found on the THS413x is an active low terminal. If it is left as a no-connect terminal, the device always stays on due to an internal 50 kΩ resistor to V . The threshold voltage for this terminal is approximately 1.4 V above V . This CC CC– means that if the PD terminal is 1.4 V above V , the device is active. If the PD terminal is less than 1.4 V CC– above V , the device is off. For example, if V = –5 V, then the device is on when PD reaches –3.6 V, (–5 V CC– CC– + 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal to V in order to turn the device off. Figure 35 shows the simplified version of the power-down circuit. While in CC– thepower-downstate,theamplifiergoesintoahigh-impedancestate.Theamplifieroutputimpedanceistypically greaterthan1MΩ inthepower-downstate. VCC 50 kW To Internal Bias PD Circuitry Control VCC− Figure35. SimplifiedPower-DownCircuit Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very low while in the power-down state. This is because the feedback resistor (R) and the gain resistor (R ) are still f (g) connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of theamplifier.AnexampleoftheclosedloopoutputimpedanceisshowninFigure36. 16 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 Device Functional Modes (continued) 2200 VCC=(cid:3)±5 V G = 1 Rf= 1 kW PD=VCC− W − e c n a d e p 1200 m ut I p ut O 200 100 k 1 M 10 M 100 M 1 G f−Frequency−Hz Figure36. OutputImpedance(inPower-Down)vsFrequency Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information 9.1.1 ResistorMatching Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keeptheperformanceoptimized. V sets the dc level of the output signals. If no voltage is applied to the V pin, it is set to the midrail voltage OCM OCM internallydefinedas: (V )+(V ) CC+ CC- 2 (8) In the differential mode, the V on the two outputs cancel each other. Therefore, the output in the differential OCM mode is the same as the input in the gain of 1. V has a high bandwidth capability up to the typical operation OCM range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the V OCM pinasabypasscapacitor.TheFunctionalBlockDiagramshowsthesimplifieddiagramoftheTHS413x. 9.1.2 DrivingaCapacitiveLoad Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 37. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance loadingandprovidestheproperlineimpedancematchingatthesourceend. 390W 20W Output 390W THS413x 390W 20W Output 390W Figure37. DrivingaCapacitiveLoad 9.1.3 DataConverters Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 38 shows a typicalconfigurationofafully-differentialamplifierattachedtoadifferentialanalog-to-digitalconverter(ADC). 18 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 Application Information (continued) V DD V CC 5 V VIN + − AVDD DVDD VOCM AIN1 0.1mF − + AIN2AV V SS ref −5 V V − CC Figure38. Fully-DifferentialAmplifierAttachedtoaDifferentialADC Fully-differential amplifiers can operate with a single supply. V defaults to the midrail voltage, V /2. The OCM CC differentialoutputmaybefedintoadataconverter.Thismethodeliminatestheuseofatransformerinthecircuit. If the ADC has a reference voltage output (V ), then it is recommended to connect it directly to the V of the ref OCM amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input terminaloftheamplifiershouldnotexceedthecommon-modeinputvoltagerange. V DD V CC 5 V VIN + − AVDD DVDD VOCM AIN1 0.1mF − + AIN2AV V SS ref Figure39. Fully-DifferentialAmplifierUsingaSingleSupply 9.1.4 Single-SupplyApplications Some single-supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the circuit configuration of Figure 40 is suggested to bring the common-mode input voltage within thespecificationsoftheamplifier. VCC VDD Rf VCC RPU 5 V VIN Rg + − VOUT AVDD DVDD VP VOCM AIN1 THS1206 0.1mF Rg − + VOUT AIN2AVSS Vref RPU VCC Rf Figure40. CircuitWithImprovedCommon-ModeInputVoltage Equation9isusedtocalculateR : PU Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Application Information (continued) V -V R = P CC PU 1 1 (V -V ) +(V -V ) IN P RG OUT P RF (9) 9.2 Typical Application For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 41 presents a methodbywhichthenoisemaybefilteredintheTHS413x. Figure 41 shows a typical application design example for the THS413x device in active low-pass filter topology drivingandADC. R2 C1 VCC R4 + C3 R1 R3 VIN− − + VIN+ Vs C2 THS413x R(t) THS1050 VIN+ + − VIN− VOCM R1 R3 VOCM C3 VIC R4 VCC− + C1 R2 Figure41. AntialiasFiltering 9.2.1 DesignRequirements Table3showsexampledesignparametersandvaluesforthetypicalapplicationdesignexampleinFigure41. Table3.DesignParameters DESIGNPARAMETERS VALUE Supplyvoltage ±2.5Vto±15V Amplifiertopology Voltagefeedback DCcoupledwithoutputcommon Outputcontrol modecontrolcapability 500kHz,Multiplefeedbacklowpass Filterrequirement filter 20 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 9.2.2 DetailedDesignProcedure 9.2.2.1 ActiveAntialiasFiltering Figure41showsamultiple-feedback(MFB)lowpassfilter.Thetransferfunctionforthisfiltercircuitis: æ ö æ Rt ö ç ÷ H (f)=ç K ÷´çç 2R4+Rt ÷÷ WhereK = R2 d ççç-æç f ö÷2 + 1 jf +1÷÷÷ ççè1+ j22pRfR44+RRtCt3÷÷ø R1 è èFSF´fcø QFSF´fc ø (10) 1 2´R2R3C1C2 FSF´fc = andQ= 2p 2´R2R3C1C2 R3C1+R2C1+KR3C1 (11) K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the qualityfactor. Re2+ Im2 FSF= Re2+ Im2 andQ= 2Re (12) where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C,andC2=nCresultsin: 1 2´mn FSF´fc = andQ= 2pRC 2´mn 1+m(1+K) (13) Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select CandcalculateRforthedesiredfc. 9.2.3 ApplicationCurve 5 VCC=±15 V 0 −5 B d − ut −10 utp VCC=±5 V O −15 Gain = 1 −20 RRfL== 389000WW,, VCC= 5 V CF= 0 pF, VI= 0.2 VRMS −25 100 k 1 M 10 M 100 M 1 G f−Frequency−Hz Figure42.Large-SignalFrequencyResponse Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com 10 Power Supply Recommendations The THS413x device was designed to be operated on power supplies ranging from 2.5V to 15V. Single power supplies ranging from 5V to 30V can also be used. TI recommends using power-supply accuracy of 5%, or better. When operated on a board with high-speed digital signals, it is important to provide isolation between digital signal noise and the analog input pins. The THS413x is connected to power supplies through pin 3 (V ) CC+ and pin 6 (V ). Each supply pin should be decoupled to GND as close to the device as possible with a low- CC- inductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method of reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are advised. To avoid undesirable signal transients, the THS413x device should not be powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs whenanADCisusedintheapplication. 11 Layout 11.1 Layout Guidelines To achieve the levels of high-frequency performance of the THS413x device, follow proper printed-circuit board (PCB) high-frequency design techniques. A general set of guidelines is given below. In addition, a THS413x deviceevaluationboardisavailabletouseasaguideforlayoutorforevaluatingthedeviceperformance. • Ground planes—It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, thegroundplanecanberemovedtominimizethestraycapacitance. • Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. Inaddition,the0.1-µFcapacitorshouldbeplacedascloseaspossibletothesupplyterminal.Asthisdistance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strivefordistancesoflessthan0.1inchesbetweenthedevicepowerterminalsandtheceramiccapacitors. • Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to theprinted-circuitboardarethebestimplementation. • Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance attheinputoftheamplifier. • Surface-mount passive components—Using surface-mount passive components is recommended for high- frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept asshortaspossible. 22 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 11.2 Layout Example THS413x Symmetrical Symmetrical Input Paths RG RF Output Paths Figure43. THS413xEVMTopLayer Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com Layout Example (continued) Separate Vcc+ and Vcc- planes Vcc+ Vcc- Figure44. THS413xEVMLayer3 11.3 General PowerPAD Design Considerations The THS413x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted (see Figure 45a and Figure 45b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see Figure 45c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from thethermalpad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heatcanbeconductedawayfromthepackageintoeitheragroundplaneorotherheatdissipatingdevice. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surfacemountwiththepreviouslyawkwardmechanicalmethodsofheatsinking. More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, (PowerPAD Thermally-Enhanced Package, SLMA002). This document can be found on the TI website (www.ti.com) by searching on the key word PowerPAD. The document can also beorderedthroughyourlocalTIsalesoffice.RefertoSLMA002whenordering. 24 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 www.ti.com SLOS318I–MAY2000–REVISEDAUGUST2015 General PowerPAD Design Considerations (continued) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from V toV .Typically,thethermalpadisconnectedtothegroundplanebecausethisplanetendstophysicallybe CC– CC+ thelargestandisabletodissipatethemostamountofheat. Figure45. ViewsofThermally-EnhancedDGNPackage Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:THS4130 THS4131

THS4130,THS4131 SLOS318I–MAY2000–REVISEDAUGUST2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation EVMUser'sGuideforHigh-SpeedFully-DifferentialAmplifier,SLOU101 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY THS4130 Clickhere Clickhere Clickhere Clickhere Clickhere THS4131 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:THS4130 THS4131

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4130CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 4130C & no Sb/Br) THS4130CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 4130C & no Sb/Br) THS4130CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM 0 to 70 ATP & no Sb/Br) THS4130CDGN ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM 0 to 70 AOB PowerPAD & no Sb/Br) CU NIPDAUAG THS4130CDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM 0 to 70 AOB PowerPAD & no Sb/Br) CU NIPDAUAG THS4130CDGNRG4 ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOB PowerPAD & no Sb/Br) THS4130ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4130I & no Sb/Br) THS4130IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 85 ASO & no Sb/Br) THS4130IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS Call TI Level-1-260C-UNLIM -40 to 85 ASO & no Sb/Br) THS4130IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 85 ASO & no Sb/Br) THS4130IDGN ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 AOC PowerPAD & no Sb/Br) CU NIPDAUAG THS4130IDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 AOC PowerPAD & no Sb/Br) CU NIPDAUAG THS4130IDGNRG4 ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOC PowerPAD & no Sb/Br) THS4130IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4130I & no Sb/Br) THS4130IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4130I & no Sb/Br) THS4131CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 4131C & no Sb/Br) THS4131CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 4131C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4131CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM 0 to 70 ATQ & no Sb/Br) THS4131CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS Call TI Level-1-260C-UNLIM 0 to 70 ATQ & no Sb/Br) THS4131CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM 0 to 70 ATQ & no Sb/Br) THS4131CDGN ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM 0 to 70 AOD PowerPAD & no Sb/Br) CU NIPDAUAG THS4131CDGNG4 ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOD PowerPAD & no Sb/Br) THS4131CDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM 0 to 70 AOD PowerPAD & no Sb/Br) CU NIPDAUAG THS4131CDGNRG4 ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOD PowerPAD & no Sb/Br) THS4131CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 4131C & no Sb/Br) THS4131ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4131I & no Sb/Br) THS4131IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4131I & no Sb/Br) THS4131IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 85 ASP & no Sb/Br) THS4131IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS Call TI Level-1-260C-UNLIM -40 to 85 ASP & no Sb/Br) THS4131IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ASP & no Sb/Br) THS4131IDGN ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 AOE PowerPAD & no Sb/Br) CU NIPDAUAG THS4131IDGNG4 ACTIVE MSOP- DGN 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOE PowerPAD & no Sb/Br) THS4131IDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 AOE PowerPAD & no Sb/Br) CU NIPDAUAG THS4131IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 4131I & no Sb/Br) (1) The marketing status values are defined as follows: Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS4130CDGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Power PAD THS4130IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4130IDGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Power PAD THS4130IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4131CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4131CDGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Power PAD THS4131CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4131IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4131IDGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Power PAD THS4131IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS4130CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 THS4130IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4130IDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 THS4130IDR SOIC D 8 2500 350.0 350.0 43.0 THS4131CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4131CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 THS4131CDR SOIC D 8 2500 350.0 350.0 43.0 THS4131IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4131IDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 THS4131IDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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