(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 (cid:1) High Speed THS4061 THS4062 JG, D AND DGN PACKAGE D AND DGN PACKAGE − 180 MHz Bandwidth (G = 1, −3 dB) (TOP VIEW) (TOP VIEW) − 400 V/µs Slew Rate − 40-ns Settling Time (0.1%) NULL 1 8 NULL 1OUT 1 8 VCC+ (cid:1) High Output Drive, IO = 115 mA (typ) IN− 2 7 VCC+ 1IN− 2 7 2OUT (cid:1) Excellent Video Performance IN+ 3 6 OUT 1IN+ 3 6 2IN− − 75 MHz 0.1 dB Bandwidth (G = 1) VCC− 4 5 NC −VCC 4 5 2IN+ − 0.02% Differential Gain − 0.02° Differential Phase NC − No internal connection (cid:1) Very Low Distortion − THD = −72 dBc at f = 1 MHz (cid:1) Cross-Section View Showing Wide Range of Power Supplies PowerPAD Option (DGN) − V = ±5 V to ±15 V CC (cid:1) Available in Standard SOIC, MSOP THS4061 PowerPAD, JG, or FK Package FK PACKAGE (cid:1) (TOP VIEW) Evaluation Module Available L L L L C U C U C description N N N N N 3 2 1 20 19 The THS4061 and THS4062 are general- NC 4 18 NC purpose, single/dual, high-speed voltage feed- back amplifiers ideal for a wide range of IN− 5 17 VCC+ applications including video, communication, and NC 6 16 NC imaging. The devices offer very good ac IN+ 7 15 OUT performance with 180-MHz bandwidth, 400-V/µs slew rate, and 40-ns settling time (0.1% ). The NC 8 14 NC THS4061/2 are stable at all gains for both 9 10 11 12 13 ianmveprltifiniegrs a hnadv neo an inhvigehrt ionugt pcuotn fdigriuvrea tcioanpsa.b Tilihtye soef NC V CC− NC NC NC 115 mA and draw only 7.8 mA supply current per channel. Excellent professional video results can be obtained with the low differential gain/phase errors of 0.02%/0.02° and wide 0.1 db flatness to VI + 75 Ω 75 MHz. For applications requiring low distortion, THS4061 75 Ω VO the THS4061/2 is ideally suited with total _ 75 Ω harmonic distortion of −72 dBc at f = 1 MHz. 2 kΩ 2 kΩ LINE DRIVER (G = 2) CAUTION: The THS4061 and THS4062 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. (cid:16)(cid:22)(cid:24)(cid:18)(cid:25)(cid:26)(cid:1)(cid:14)(cid:24)(cid:27) (cid:18)(cid:19)(cid:1)(cid:19) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$(- Copyright  1998 − 2003, Texas Instruments Incorporated (cid:16)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $.( $(!"% (cid:31)(cid:30) (cid:1)(/#% (cid:14)(cid:29)%$!’"((cid:29)$% (cid:24)(cid:29) )!(cid:31),’&$% &(cid:31)")+(cid:28)#(cid:29)$ $(cid:31) (cid:12)(cid:14)(cid:20)(cid:11)(cid:16)(cid:22)(cid:21)(cid:11)3(cid:10)434(cid:8) #++ )#!#"($(!% #!( $(%$(, %$#(cid:29),#!, 0#!!#(cid:29)$1- (cid:16)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( ’(cid:29)+(%% (cid:31)$.(!0(cid:28)%( (cid:29)(cid:31)$(,- (cid:24)(cid:29) #++ (cid:31)$.(! )!(cid:31),’&$%(cid:8) )!(cid:31),’&$(cid:28)(cid:31)(cid:29) $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 RELATED DEVICES DEVICE DESCRIPTION THS4011/2 290-MHz Low Distortion High-Speed Amplifiers THS4031/2 100-MHz Low Noise High Speed-Amplifiers THS4061/2 180-MHz High-Speed Amplifiers AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC NUMBER OF PLASTIC CERAMIC CHIP MSOP EVALUATION TA CHANNELS SMALL MSOP† DIP CARRIER SYMBOL MODULES OUTLINE† (DGN) (JG) (FK) (D) 00°CC ttoo 1 THS4061CD THS4061CDGN — — TIABS THS4061EVM 70°C 2 THS4062CD THS4062CDGN — — TIABM THS4062EVM −−4400°CC ttoo 1 THS4061ID THS4061IDGN — — TIABT — 85°C 2 THS4062ID THS4062IDGN — — TIABN — −55°C to 1 — — THS4061MJG THS4061MFK — — 125°C †The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR). functional block diagram Null 1 2 IN− − 8 6 OUT 3 IN+ + Figure 1. THS4061 − Single Channel VCC 1IN− 2 − 8 1 1OUT 3 1IN+ + 6 2IN− − 7 2OUT 5 2IN+ + 4 −VCC Figure 2. THS4062 − Dual Channel 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, V + to V − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V CC CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V I CC Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA O Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V IO Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package . . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D 740 mW 6 mW/°C 475 mW 385 mW — DGN‡ 2.14 W 17.1 mW/°C 1.37 W 1.11 W — JG 1057 mW 8.4 mW/°C 627 mW 546 mW 210 mW FK 1375 mW 11 mW/°C 880 mW 715 mW 275 mW ‡The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently damage the device. recommended operating conditions MIN NOM MAX UNIT Dual supply ±4.5 ±16 SSuuppppllyy vvoollttaaggee,, VVCCCC++ aanndd VVCCCC−− VV Single supply 9 32 C-suffix 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA I-suffix −40 85 °CC M-suffix −55 125 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) A CC L dynamic performance THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX VCC = ±5 V Gain = 1 180 MHz DDyynnaammiicc ppeerrffoorrmmaannccee ssmmaallll--ssiiggnnaall VCC = ±15 V 50 bbaannddwwiiddtthh ((−−33 ddBB)) GGaaiinn == −−11 MMHHzz BBWW VCC = ±5 V 50 VCC = ±15 V 75 BBaannddwwiiddtthh ffoorr 00..11 ddBB ffllaattnneessss GGaaiinn == 11 MMHHzz VCC = ±5 V 20 VCC = ±15 V 400 SSRR SSlleeww rraattee GGaaiinn == −−11 VV//µss VCC = ±5 V 350 VCC = ±15 V, 5-V step (0 V to 5 V) 40 SSeettttlliinngg ttiimmee ttoo 00..11%% GGaaiinn == −−11 nnss VCC = ±5 V, VO = −2.5 V to 2.5 V, 40 ttss VCC = ±15 V, 5-V step (0 V to 5 V) 140 SSeettttlliinngg ttiimmee ttoo 00..0011%% GGaaiinn == −−11 nnss VCC = ±5 V, VO = −2.5 V to 2.5 V, 150 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix noise/distortion performance THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX THD Total harmonic distortion f = 1 MHz −72 dBc Vn Input voltage noise f = 10 kHz, VCC = ±5 V or ±15 V 14.5 nV/√Hz In Input current noise f = 10 kHz, VCC = ±5 V or ±15 V 1.6 pA/√Hz 0.02 VCC = ±15 V % DDiiffffeerreennttiiaall ggaaiinn eerrrroorr GGaaiinn == 22,, NNTTSSCC,, 4400 IIRREE mmoodduullaattiioonn 0.02 VCC = ±5 V % VCC = ±15 V 0.02° DDiiffffeerreennttiiaall pphhaassee eerrrroorr GGaaiinn == 22,, NNTTSSCC,, 4400 IIRREE mmoodduullaattiioonn VCC = ±5 V 0.06° Channel-to-channel crosstalk (THS4062 only) VCC = ±5 V or ±15 V, f = 1 MHz 65 dB †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix dc performance THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX TA = 25°C 5 15 VVCCCC == ±±1155 VV,, VVOO == ±±1100 VV,, RRLL == 11 kkΩΩ VV//mmVV TA = full range 4 OOppeenn lloooopp ggaaiinn TA = 25°C 2.5 8 VVCCCC == ±±55 VV,, VVOO == ±±22..55 VV,, RRLL == 11 kkΩΩ VV//mmVV TA = full range 2 Input offset voltage VCC = ±5 V or ±15 V 2.5 8 mV VVOOSS Offset drift VCC = ±5 V or ±15 V TTAA == ffuullll rraannggee 15 µV/°C IIB Input bias current VCC = ±5 V or ±15 V TA = full range 3 6 µA IOS Input offset current VCC = ±5 V or ±15 V TA = full range 75 250 nA Offset current drift TA = full range 0.3 nA/°C †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued) A CC L input characteristics THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX VCC = ±15 V ±13.8 ±14.1 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee VCC = ±5 V ±3.8 ±4.3 VV VCC = ±15 V, VICR = ±12 V 70 110 CCMMRRRR CCoommmmoonn mmooddee rreejjeeccttiioonn rraattiioo VCC = ±5 V, VICR = ±2.5 V TTAA == ffuullll rraannggee 70 95 ddBB RI Input resistance 1 MΩ Ci Input capacitance 2 pF †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix output characteristics THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX VCC = ±15 V RL = 250 Ω ±11.5 ±12.5 VV VCC = ±5 V RL = 150 Ω ±3.2 ±3.5 VVOO OOuuttppuutt vvoollttaaggee sswwiinngg VCC = ±15 V ±13 ±13.5 VCC = ±5 V RRLL == 11 kkΩΩ ±3.5 ±3.7 VV VCC = ±15 V 80 115 IIOO OOuuttppuutt ccuurrrreenntt VCC = ±5 V RRLL == 2200 ΩΩ 50 75 mmAA ISC Short-circuit current VCC = ±15 V 150 mA RO Output resistance Open loop 12 Ω †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix power supply THS4061C/I, PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† THS4062C/I UUNNIITT MIN TYP MAX Dual supply ±4.5 ±16.5 VVCCCC SSuuppppllyy vvoollttaaggee ooppeerraattiinngg rraannggee VV Single supply 9 33 VCC = ±15 V 7.8 10.5 IICCCC QQuuiieesscceenntt ccuurrrreenntt ((ppeerr aammpplliiffiieerr)) VCC = ±5 V TTAA == ffuullll rraannggee 7.3 10 mmAA TA = 25°C 70 78 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo VVCCCC == ±±55 VV oorr ±±1155 VV ddBB TA = full range 68 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) A CC L dynamic performance THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX Unity-gain bandwidth Closed loop, RL = 1 kΩ VCC = ±15 V *140 180 MHz VCC = ±15 V 180 GGaaiinn == 11 MMHHzz DDyynnaammiicc ppeerrffoorrmmaannccee ssmmaallll--ssiiggnnaall VCC = ±5 V 180 BBWW bbaannddwwiiddtthh ((−−33 ddBB)) VCC = ±15 V 50 GGaaiinn == −−11 MMHHzz VCC = ±5 V 50 VCC = ±15 V 75 BBaannddwwiiddtthh ffoorr 00..11 ddBB ffllaattnneessss GGaaiinn == 11 MMHHzz VCC = ±5 V 20 SR Slew rate VCC = ±15 V RL = 1 kΩ *400 500 V/µs VCC = ±15 V, 5-V step (0 V to 5 V) 40 SSeettttlliinngg ttiimmee ttoo 00..11%% GGaaiinn == −−11 nnss VCC = ±5 V, VO = −2.5 V to 2.5 V, 40 ttss VCC = ±15 V, 5-V step (0 V to 5 V) 140 SSeettttlliinngg ttiimmee ttoo 00..0011%% GGaaiinn == −−11 nnss VCC = ±5 V, VO = −2.5 V to 2.5 V, 150 †Full range = −55°C to 125°C for M suffix *This parameter is not tested. noise/distortion performance THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX THD Total harmonic distortion f = 1 MHz −72 dBc Vn Input voltage noise f = 10 kHz, VCC = ±5 V or ±15 V 14.5 nV/√Hz In Input current noise f = 10 kHz, VCC = ±5 V or ±15 V 1.6 pA/√Hz VCC = ±15 V 0.02 DDiiffffeerreennttiiaall ggaaiinn eerrrroorr GGaaiinn == 22,, NNTTSSCC,, 4400 IIRREE MMoodduullaattiioonn %% VCC = ±5 V 0.02 VCC = ±15 V 0.02° DDiiffffeerreennttiiaall pphhaassee eerrrroorr GGaaiinn == 22,, NNTTSSCC,, 4400 IIRREE MMoodduullaattiioonn VCC = ±5 V 0.06° †Full range = −55°C to 125°C for M suffix dc performance THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V, VO = ±10 V, RL = 1 kΩ 5 9 OOppeenn lloooopp ggaaiinn VCC = ±5 V, VO = ±2.5 V, RL = 1 kΩ TTAA == ffuullll rraannggee 2.5 6 VV//mmVV TA = 25°C 2.5 8 mV IInnppuutt ooffffsseett vvoollttaaggee VVCCCC == ±±55 VV oorr ±±1155 VV RRLL == 11 kkΩΩ VVIIOO TA = full range 9 mV Offset drift VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 15 µV/°C IIB Input bias current VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 3 6 µA IIO Input offset current VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 75 250 nA Offset current drift VCC = ±5 V or ±15 V RL = 1 kΩ TA = full range 0.3 nA/°C †Full range = −55°C to 125°C for M suffix 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 electrical characteristics at T = full range, V = ±15 V, R = 1 kΩ (unless otherwise noted) A CC L (continued) input characteristics THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V ±13.8 ±14.1 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee VCC = ±5 V ±3.8 ±4.3 VV VCC = ±15 V, VICR = ±12 V 70 86 CCMMRRRR CCoommmmoonn mmooddee rreejjeeccttiioonn rraattiioo ddBB VCC = ±5 V, VICR = ±2.5 V 80 90 RI Input resistance 1 MΩ Ci Input capacitance 2 pF †Full range = −55°C to 125°C for M suffix output characteristics THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V RL = 250 Ω ±12 ±13.1 VV VCC = ±5 V RL = 150 Ω ±3.2 ±3.5 VVOO OOuuttppuutt vvoollttaaggee sswwiinngg VCC = ±15 V ±13 ±13.5 VCC = ±5 V RRLL == 11 kkΩΩ ±3.5 ±3.7 VV VCC = ±15 V 70 115 IIOO OOuuttppuutt ccuurrrreenntt VCC = ±5 V RRLL == 2200 ΩΩ 50 75 mmAA ISC Short-circuit current VCC = ±15 V TA = 25°C 150 mA RO Output resistance Open loop 12 Ω †Full range = −55°C to 125°C for M suffix power supply THS4061M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX Dual supply ±4.5 ±16.5 VVCCCC SSuuppppllyy vvoollttaaggee ooppeerraattiinngg rraannggee VV Single supply 9 33 VCC = ±15 V 7.8 9 VCC = ±5 V TTAA == 2255°°CC 7.3 8.5 IICCCC QQuuiieesscceenntt ccuurrrreenntt VCC = ±15 V 11 mmAA VCC = ±5 V TTAA == ffuullll rraannggee 10.5 TA = 25°C 76 80 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo VVCCCC == ±±55 VV oorr ±±1155 VV ddBB TA = full range 74 78 †Full range = −55°C to 125°C for M suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS FIGURE IIB Input bias current vs Free-air temperature 3 VIO Input offset voltage vs Free-air temperature 4 Open-loop gain vs Frequency 5 Phase vs Frequency 5 Differential gain vs Number of loads 6, 8 Differential phase vs Number of loads 7, 9 Closed-loop gain vs Frequency 10, 11 Output amplitude vs Frequency 12, 13 CMRR Common-mode rejection ratio vs Frequency 14 vs Frequency 15 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo vs Free-air temperature 16 VO(PP) Output voltage swing vs Supply voltage 17 ICC Supply current vs Free-air temperature 18 Env Noise spectral density vs Frequency 19 THD Total harmonic distortion vs Frequency 20, 21 Crosstalk vs Frequency 22, 23 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS INPUT BIAS CURRENT INPUT OFFSET VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 4 0 VCC = ±15 V, ±5 V −0.5 VCC = ±5 V A V µ 3.5 m − − −1 urrent oltage −1.5 C V as 3 et put Bi ut Offs −2 VCC = ±15 V n p − IB 2.5 − In −2.5 II O VI −3 2 −3.5 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 3 Figure 4 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 90 VCC = ±15 V 80 0° VCC = ±5 V 70 B d 60 −45° − n Phase Gai 50 se p a o h o 40 −90° P L n- e p 30 O 20 −135° 10 0 −180° 1k 10k 100k 1M 10M 100M 1G f − Frequency − Hz Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS DIFFERENTIAL GAIN DIFFERENTIAL PHASE vs vs NUMBER OF LOADS NUMBER OF LOADS 0.14% 0.7° Gain = 2 Gain = 2 RF = 680 Ω RF = 680 Ω 0.12% 40 IRE − NTSC 0.6 40 IRE − NTSC Worst Case ±100 IRE Ramp Worst Case ±100 IRE Ramp 0.1% 0.5° e s Gain 0.08% Pha 0.4° VCPhCa =se±5 Differential 0.06% VCC =±V5CGCa =in±15 Differential 0.3° VCPCh a=s±e15 Gain 0.04% 0.2° 0.02% 0.1° 0% 0° 1 2 3 4 1 2 3 4 Number of 150 Ω Loads Number of 150 Ω Loads Figure 6 Figure 7 DIFFERENTIAL GAIN DIFFERENTIAL PHASE vs vs NUMBER OF LOADS NUMBER OF LOADS 0.2% 1° Gain = 2 Gain = 2 0.18% RF = 680 Ω 0.9° RF = 680 Ω 40 IRE − PAL 40 IRE − PAL 0.16% Worst Case ±100 IRE Ramp 0.8° Worst Case ±100 IRE Ramp 0.14% 0.7° VCC =±15 se Gain 0.12% Gain Pha 0.6° Differential 00.0.18%% VCGCa i=n±5 Differential 00..54°° VCC =±5 0.06% 0.3° Phase VCC =±15 0.04% 0.2° Phase 0.02% 0.1° 0% 0° 1 2 3 4 1 2 3 4 Number of 150 Ω Loads Number of 150 Ω Loads Figure 8 Figure 9 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS CLOSED-LOOP GAIN CLOSED-LOOP GAIN vs vs FREQUENCY FREQUENCY 2 5 VCC = ±15 V 0 0 Gain − dB −−24 VCC = ±5 V Gain − dB −5 Closed-Loop −−86 Closed-Loop −10 −10 VCC = ±15 V, ±5 V −15 Gain = 1 Gain = −1 −12 RF = 270 Ω RF = 510 Ω RL = 150 Ω RL = 150 Ω −14 −20 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz Figure 10 Figure 11 OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs FREQUENCY FREQUENCY 4 2 2 RF = 1 kΩ 0 RF = 510 Ω B B mplitude − d −02 RF R= F2 7=0 2 Ω00 Ω mplitude − d −−24 RF = 3 kΩ A A Output −4 Output −6 −6 −8 Gain = 1 Gain = −1 RL = 150 Ω RL = 150 Ω −8 −10 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz Figure 12 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO vs vs FREQUENCY FREQUENCY 120 −80 B VCC = ±15 V, ±5 V d B − d −70 o 100 − Rati atio −60 n R o 80 n ecti ctio −50 ej e R ej de 60 y R −40 Mo ppl on- Su −30 m 40 r m we Co Po −20 − − R 20 R R R −10 M S C P VCC = ±15 V, ±5 V 0 0 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M f − Frequency − Hz f − Frequency − Hz Figure 14 Figure 15 POWER SUPPLY REJECTION RATIO OUTPUT VOLTAGE SWING vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 90 30 dB 88 atio − 86 g − V 25 n R VCC = −15 V win RL = 1 kΩ o 84 S 20 Rejecti 82 oltage RL = 150 Ω y V 15 Suppl 80 utput wer 78 VCC = 15 V − O 10 R − Po 76 VO(PP) 5 R S 74 P 72 0 −40 −20 0 20 40 60 80 100 ±4 ±6 ±8 ±10 ±12 ±14 ±16 TA − Free-Air Temperature − °C VCC − Supply Voltage − V Figure 16 Figure 17 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT NOISE SPECTRAL DENSITY vs vs FREE-AIR TEMPERATURE FREQUENCY 10 180 TA = 25°C z 160 9 H A nV/ 140 rent − m 8 VCC = ±15 V nsity − 120 y Cur 7 VCC = ±5 V al De 100 uppl pectr 80 S S − 6 e 60 C s C oi I − N 40 5 v n E 20 4 0 −40 −20 0 20 40 60 80 100 10 100 1k 10k 100k TA − Free-Air Temperature − °C f − Frequency − Hz Figure 18 Figure 19 TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY −40 −40 Gain = 2 Gain = 2 dB −50 VRCL C= =1 5±01 5Ω V dB −50 VRCL C= =1 5±05 ΩV − − n n ortio −60 ortio −60 st st c Di −70 2nd Harmonic c Di −70 2nd Harmonic ni ni o o m m ar −80 ar −80 H H al 3rd Harmonic al 3rd Harmonic Tot −90 Tot −90 − − D D H H T −100 T −100 −110 −110 100k 1M 10M 100k 1M 10M f − Frequency − Hz f − Frequency − Hz Figure 20 Figure 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY 0 0 G = 2, G = 2, −10 RF = 300 (cid:1), −10 RF = 300 (cid:1), RL = 100 (cid:1)(cid:2) RL = 100 (cid:1)(cid:2) −20 VO = 200 mVPP, −20 VO = 200 mVPP, VS = (cid:1)15 V VS = (cid:1)5 V −30 See Figure 24 −30 See Figure 24 c c B B d −40 d −40 − − k k al −50 al −50 CH B to A st st Cros −60 CH B to A Cros −60 CH A to B −70 −70 CH A to B −80 −80 −90 −90 −100 −100 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G f − Frequency − Hz f − Frequency − Hz Figure 22 Figure 23 300 (cid:1) 300 (cid:1) − THS4062 A VIN + 100 (cid:1) 49.9 (cid:1) 300 (cid:1) 300 (cid:1) 50 (cid:1) Load − THS4062 Measured B 49.9 (cid:1) + 49.9 (cid:1) Figure 24. Test Circuits 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 APPLICATION INFORMATION theory of operation The THS406x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f s of T several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 25. (7) VCC+ (6) OUT IN− (2) IN+ (3) (4) VCC− NULL (1) NULL (8) Figure 25. THS4061 Simplified Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 APPLICATION INFORMATION offset nulling The THS4061 has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8 and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in Figure 26. VCC+ 0.1 µF + THS4061 _ 10 kΩ 0.1 µF VCC− Figure 26. Offset Nulling Schematic optimizing unity gain response Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 270 Ω should be used as shown in Figure 27. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + THS406x Output _ 270 Ω Figure 27. Noninverting, Unity Gain Schematic 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 28. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 510 Ω 510 Ω _ Input 20 Ω THS406x Output + CLOAD Figure 28. Driving a Capacitive Load circuit layout considerations In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below. In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device performance. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9) (cid:7)(cid:10)(cid:5)(cid:11)(cid:12)(cid:2)(cid:13) (cid:2)(cid:14)(cid:15)(cid:2)(cid:11)(cid:3)(cid:16)(cid:17)(cid:17)(cid:18) (cid:19)(cid:12)(cid:16)(cid:20)(cid:14)(cid:21)(cid:14)(cid:17)(cid:22)(cid:3) (cid:23) SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003 APPLICATION INFORMATION circuit layout considerations (continued) (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. evaluation board An evaluation board is available for the THS4061 (literature number SLOP226) and THS4062 (literaure number SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 29. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the THS4061 EVM User’s Manual (literature number SLOU038) or the THS4062 EVM User’s Manual (literature number SLOU040) VCC+ + C2 C3 6.8 µF 0.1 µF R4 1 kΩ NULL IN+ + R5 49.9 Ω R3 THS4061 OUT 49.9 Ω _ NULL R2 C1 1 kΩ C4 + 6.8 µF 0.1 µF IN− R1 VCC− 49.9 Ω Figure 29. THS4061 Evaluation Board Schematic 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9960101Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9960101Q2A THS4061MFKB 5962-9960101QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9960101QPA THS4061M THS4061CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4061C & no Sb/Br) THS4061CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4061C & no Sb/Br) THS4061CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABS & no Sb/Br) THS4061CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABS & no Sb/Br) THS4061CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4061C & no Sb/Br) THS4061ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4061I & no Sb/Br) THS4061IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4061I & no Sb/Br) THS4061IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT & no Sb/Br) THS4061IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4061I & no Sb/Br) THS4061IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4061I & no Sb/Br) THS4061MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9960101Q2A THS4061MFKB THS4061MJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 THS4061MJG THS4061MJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9960101QPA THS4061M THS4062CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4062C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4062CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4062C & no Sb/Br) THS4062CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ABM & no Sb/Br) THS4062CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4062C & no Sb/Br) THS4062CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4062C & no Sb/Br) THS4062ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4062I & no Sb/Br) THS4062IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4062I & no Sb/Br) THS4062IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABN & no Sb/Br) THS4062IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABN & no Sb/Br) THS4062IDGNRG4 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4061, THS4061M : •Catalog: THS4061 •Military: THS4061M NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS4061CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4061CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4061IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4061IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4062CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4062IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS4061CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4061CDR SOIC D 8 2500 350.0 350.0 43.0 THS4061IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4061IDR SOIC D 8 2500 350.0 350.0 43.0 THS4062CDR SOIC D 8 2500 350.0 350.0 43.0 THS4062IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated