(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) SLOS238D − MAY 1999 − REVISED AUGUST 2008 (cid:9)(cid:5)(cid:10)(cid:11)(cid:2)(cid:12) (cid:2)(cid:13)(cid:14)(cid:2)(cid:10)(cid:3)(cid:15)(cid:16)(cid:16)(cid:17) (cid:18)(cid:11)(cid:15)(cid:19)(cid:13)(cid:20)(cid:13)(cid:16)(cid:21)(cid:3) FEATURES THS4051 D, DGN, AND JG PACKAGES (cid:1) (TOP VIEW) High Speed: − 70 MHz Bandwidth (G = 1, −3 dB) NULL 1 8 NULL − 240 V/µs Slew Rate IN− 2 7 VCC+ − 60-ns Settling Time (0.1%) IN+ 3 6 OUT (cid:1) High Output Drive, IO = 100 mA (typ) VCC− 4 5 NC (cid:1) Excellent Video Performance: − 0.1 dB Bandwidth of 30 MHz (G = 1) NC − No internal connection − 0.01% Differential Gain − 0.01° Differential Phase THS4052 D AND DGN† PACKAGES (cid:1) Very Low Distortion: (TOP VIEW) − THD = −82 dBc (f = 1 MHz, R = 150 Ω) L − THD = −89 dBc (f = 1 MHz, RL = 1 kΩ) 1OUT 1 8 VCC+ (cid:1) 1IN− 2 7 2OUT Wide Range of Power Supplies: − V = ±5 V to ±15 V 1IN+ 3 6 2IN− CC (cid:1) −VCC 4 5 2IN+ Available in Standard SOIC, MSOP PowerPAD, JG, or FK Packages (cid:1) Evaluation Module Available Cross Section View Showing DESCRIPTION PowerPAD Option (DGN) The THS4051 and THS4052 are general-purpose, †This device is in the Product Preview stage of development. single/dual, high-speed voltage feedback amplifiers ideal Please contact your local TI sales office for availability. for a wide range of applications including video, communication, and imaging. The devices offer very good THS4051 ac performance with 70-MHz bandwidth, 240-V/µs slew FK PACKAGE (TOP VIEW) rate, and 60-ns settling time (0.1%). The THS4051/2 are stable at all gains for both inverting and non- L L L L inverting configurations. These amplifiers have a high C U C U C N N N N N output drive capability of 100 mA and draw only 8.5-mA supply current per channel. Excellent professional video 3 2 1 20 19 results can be obtained with the low differential gain/phase NC 4 18 NC errors of 0.01%/ 0.01° and wide 0.1-dB flatness to 30 MHz. IN− 5 17 VCC+ For applications requiring low distortion, the THS4051/2 is ideally suited with total harmonic distortion of −82 dBc at NC 6 16 NC 1 MHz. IN+ 7 15 OUT NC 8 14 NC RELATED DEVICES 9 10 11 12 13 DEVICE DESCRIPTION C −C C C THS4011/2 290-MHz Low Distortion High-Speed Amplifiers N V CCN N N THS4031/2 100-MHz Low Noise High-Speed Amplifiers THS4081/2 175-MHz Low Power High-Speed Amplifiers Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. SMBus is a trademark of Intel Corp. All other trademarks are the property of their respective owners. (cid:15)(cid:21)(cid:22)(cid:17)(cid:23)(cid:24)(cid:1)(cid:13)(cid:22)(cid:25) (cid:17)(cid:18)(cid:1)(cid:18) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ (cid:15)(cid:30)(cid:29)*%$"# Copyright  1999−2008, Texas Instruments Incorporated $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:1)&-!# (cid:13)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:15)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)(1) Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V I CC Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA O Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V IO Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . 300°C Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE θθJJAA θθJJCC TTAA == 2255°CC PPAACCKKAAGGEE (°C/W) (°C/W) POWER RATING D 167‡ 38.3 740 mW DGN§ 58.4 4.7 2.14 W JG 119 28 1050 mW FK 87.7 20 1375 mW ‡This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W. §This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC. For further information, refer to Application Information section of this data sheet. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Dual supply ±4.5 ±16 SSuuppppllyy vvoollttaaggee,, VVCCCC++ aanndd VVCCCC−− VV Single supply 9 32 C-suffix 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA I-suffix −40 85 °CC M-suffix −55 125 2

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 AVAILABLE OPTIONS(1) PACKAGED DEVICES NUMBER PLASTIC PLASTIC MSOP† EVALUATION TA OF SMALL (DGN) CERAMIC DIP CHIP MMOODDUULLEE CCHHAANNNNEELLSS OOUUTTLLIINNEE†† ((JJGG)) CCAARRRRIIEERR (D) DEVICE SYMBOL (FK) 1 THS4051CD THS4051CDGN ACQ — — THS4051EVM 00°°CC ttoo 7700°°CC 2 THS4052CD THS4052CDGN‡ ACE — — THS4052EVM 1 THS4051ID THS4051IDGN ACR — — — −−4400°°CC ttoo 8855°°CC 2 THS4052ID THS4052IDGN‡ ACF — — — −55°C to 125°C 1 — — — THS4051MJG THS4051MFK — (1)For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. †The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4051CDGN). ‡This device is in the Product Preview stage of development. Please contact your local TI sales office for availability. FUNCTIONAL BLOCK DIAGRAM VCC 1IN− 1OUT 1IN+ Null 2IN− 2OUT 1 2 2IN+ IN− 8 6 OUT 3 IN+ −VCC Figure 1. THS4051 − Single Channel Figure 2. THS4052 − Dual Channel T HARMONIC DISTORTION OT AL vs FREQUENCY −40 VCC = ± 15 V c B Gain = 2 d n - −50 VO(PP) = 2 V o storti −60 c Di RL = 150 Ω ni −70 o m ar al H −80 Tot RL = 1 kΩ D - −90 H T −100 100k 1M 10M 20M f - Frequency - Hz 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS AT T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise A CC L noted) dynamic performance THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V 70 GGaaiinn == 11 MMHHzz DDyynnaammiicc ppeerrffoorrmmaannccee ssmmaallll--ssiiggnnaall bbaannddwwiiddtthh VCC = ±5 V 70 ((−−33 ddBB)) VCC = ±15 V 38 GGaaiinn == 22 MMHHzz VCC = ±5 V 38 BBWW VCC = ±15 V 30 BBaannddwwiiddtthh ffoorr 00..11 ddBB ffllaattnneessss GGaaiinn == 11 MMHHzz VCC = ±5 V 30 VO(pp) = 20 V, VCC = ±15 V 3.8 FFuullll ppoowweerr bbaannddwwiiddtthh§§ MMHHzz VO(pp) = 5 V, VCC = ±5 V 12.7 VCC = ±15 V, 20-V step, Gain = 5 240 SSRR SSlleeww rraattee‡‡ VV//µss VCC = ±5 V, 5-V step Gain = −1 200 VCC = ±15 V, 5-V step 60 SSeettttlliinngg ttiimmee ttoo 00..11%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 60 ttss VCC = ±15 V, 5-V step 130 SSeettttlliinngg ttiimmee ttoo 00..0011%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 140 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix ‡Slew rate is measured from an output level range of 25% to 75%. §Full power bandwidth = slew rate/2 πVO(Peak). noise/distortion performance THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX RL = 150 Ω −82 VVOO((pppp)) == 22 VV,, VVCCCC == ±±1155 VV RL = 1 kΩ −89 TTHHDD TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn ddBBcc ff == 11 MMHHzz,, GGaaiinn == 22 RL = 150 Ω −78 VVCCCC == ±±55 VV RL = 1 kΩ −87 Vn Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 14 nV/√Hz In Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 0.9 pA/√Hz GGaaiinn == 22,, NNTTSSCC,, VCC = ±15 V 0.01% DDiiffffeerreennttiiaall ggaaiinn eerrrroorr 40 IRE modulation, ±100 IRE ramp VCC = ±5 V 0.01% GGaaiinn == 22,, NNTTSSCC,, VCC = ±15 V 0.01° DDiiffffeerreennttiiaall pphhaassee eerrrroorr 40 IRE modulation, ±100 IRE ramp VCC = ±5 V 0.03° Channel-to-channel crosstalk VCC = ±5 V or ±15 V, f = 1 MHz −57 dB (THS4052 only) †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix. 4

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued) A CC L dc performance THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX TA = 25°C 5 9 VVCCCC == ±±1155 VV,, RRLL == 11 kkΩΩ VVOO == ±±1100 VV VV//mmVV TA = full range 3 OOppeenn lloooopp ggaaiinn TA = 25°C 2.5 6 VVCCCC == ±±55 VV,, RRLL == 225500 ΩΩ VVOO == ±±22..55 VV VV//mmVV TA = full range 2 TA = 25°C 2.5 10 VVOOSS IInnppuutt ooffffsseett vvoollttaaggee VVCCCC == ±±55 VV oorr ±±1155 VV mmVV TA = full range 12 Offset voltage drift VCC = ±5 V or ±15 V TA = full range 15 µV/°C TA = 25°C 2.5 6 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV µAA TA = full range 8 TA = 25°C 35 250 IIOOSS IInnppuutt ooffffsseett ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV nnAA TA = full range 400 Offset current drift TA = full range 0.3 nA/°C †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix input characteristics THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V ±13.8 ±14.3 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee VCC = ±5 V ±3.8 ±4.3 VV VCC = ±15 V, VICR = ±12 V 70 100 CCMMRRRR CCoommmmoonn mmooddee rreejjeeccttiioonn rraattiioo VCC = ±5 V, VICR = ±2.5 V TTAA == ffuullll rraannggee 70 100 ddBB ri Input resistance 1 MΩ Ci Input capacitance 1.5 pF †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix output characteristics THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V RL = 250 Ω ±11.5 ±13 VV VCC = ±5 V RL = 150 Ω ±3.2 ±3.5 VVOO OOuuttppuutt vvoollttaaggee sswwiinngg VCC = ±15 V ±13 ±13.6 VCC = ±5 V RRLL == 11 kkΩΩ ±3.5 ±3.8 VV VCC = ±15 V 80 100 IIOO OOuuttppuutt ccuurrrreenntt‡‡ VCC = ±5 V RRLL == 2200 ΩΩ 50 75 mmAA ISC Short-circuit current‡ VCC = ±15 V 150 mA RO Output resistance Open loop 13 W †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix ‡Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued) A CC L power supply THS405xC, THS405xI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX Dual supply ±4.5 ±16.5 VVCCCC SSuuppppllyy vvoollttaaggee ooppeerraattiinngg rraannggee VV Single supply 9 33 TA = 25°C 8.5 10.5 VVCCCC == ±±1155 VV TA = full range 11.5 IICCCC SSuuppppllyy ccuurrrreenntt ((ppeerr aammpplliiffiieerr)) TA = 25°C 7.5 9.5 mmAA VVCCCC == ±±55 VV TA = full range 10.5 TA = 25°C 70 84 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo VVCCCC == ±±55 VV oorr ±±1155 VV ddBB TA = full range 68 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix ELECTRICAL CHARACTERISTICS AT T = FULL RANGE, V = ±15 V, R = 1 KΩ (UNLESS A CC L OTHERWISE NOTED) dynamic performance THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX Unity gain bandwidth VCC = ±15 V, Closed loop RL = 1 kΩ 50§ 70 MHz VCC = ±15 V 70 GGaaiinn == 11 DDyynnaammiicc ppeerrffoorrmmaannccee ssmmaallll--ssiiggnnaall bbaannddwwiiddtthh ((−−33 VCC = ±5 V 70 MMHHzz ddBB)) VCC = ±15 V 38 GGaaiinn == 22 BBWW VCC = ±5 V 38 VCC = ±15 V 30 BBaannddwwiiddtthh ffoorr 00..11 ddBB ffllaattnneessss GGaaiinn == 11 MMHHzz VCC = ±5 V 30 VO(pp) = 20 V, VCC = ±15 V 3.8 FFuullll ppoowweerr bbaannddwwiiddtthh‡‡ MMHHzz VO(pp) = 5 V, VCC = ±5 V 12.7 VCC = ±15 V, RL = 1 kΩ 240§ 300 SSRR SSlleeww rraattee VV//µss VCC = ±5 V, 5-V step Gain = −1 200 VCC = ±15 V, 5-V step 60 SSeettttlliinngg ttiimmee ttoo 00..11%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 60 ttss VCC = ±15 V, 5-V step 130 SSeettttlliinngg ttiimmee ttoo 00..0011%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 140 †Full range = −55°C to 125°C for the THS4051M. ‡Full power bandwidth = slew rate/2 πVO(Peak). §This parameter is not tested. 6

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at T = full range, V = ±15 V, R = 1 kΩ (unless otherwise noted) A CC L noise/distortion performance THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX RL = 150 Ω −82 VVOO((pppp)) == 22 VV,, VVCCCC == ±±1155 VV RL = 1 kΩ −89 TTHHDD TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn ff == 11 MMHHzz,, GGaaiinn == 22,, ddBBcc TTAA == 2255°°CC VVCCCC == ±±55 VV RRLL == 115 k0Ω Ω −−7887 Vn Input voltage noise VTAC C= 2=5 ±°5C V or ±15 V, f = 10 kHz, RL = 150 Ω 14 nV/√Hz In Input current noise VTAC C= 2=5 ±°5C V or ±15 V, f = 10 kHz, RL = 150 Ω 0.9 pA/√Hz Gain = 2, NTSC, VCC = ±15 V 0.01% DDiiffffeerreennttiiaall ggaaiinn eerrrroorr 4400 IIRREE mmoodduullaattiioonn,, ±±110000 IIRREE rraammpp,, TA = 25°C, RL = 150 Ω VCC = ±5 V 0.01% Gain = 2, NTSC, VCC = ±15 V 0.01° DDiiffffeerreennttiiaall pphhaassee eerrrroorr 4400 IIRREE mmoodduullaattiioonn,, ±±110000 IIRREE rraammpp,, TA = 25°C, RL = 150 Ω VCC = ±5 V 0.03° †Full range = −55°C to 125°C for the THS4051M. dc performance THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX TA = 25°C 5 9 VVCCCC == ±±1155 VV,, VVOO == ±±1100 VV VV//mmVV TA = full range 3 OOppeenn lloooopp ggaaiinn TA = 25°C 2.5 6 VVCCCC == ±±55 VV,, VVOO == ±±22..55 VV VV//mmVV TA = full range 2 TA = 25°C 2.5 10 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee VVCCCC == ±±55 VV oorr ±±1155 VV mmVV TA = full range 13 Offset voltage drift VCC = ±5 V or ±15 V TA = full range 15 µV/°C TA = 25°C 2.5 6 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV µAA TA = full range 8 TA = 25°C 35 250 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV nnAA TA = full range 400 Offset current drift TA = full range 0.3 nA/°C †Full range = −55°C to 125°C for the THS4051M. input characteristics THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V ±13.8 ±14.3 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee VCC = ±5 V ±3.8 ±4.3 VV VCC = ±15 V, VICR = ±12 V 70 100 CCMMRRRR CCoommmmoonn mmooddee rreejjeeccttiioonn rraattiioo VCC = ±5 V, VICR = ±2.5 V TTAA == ffuullll rraannggee 70 100 ddBB ri Input resistance 1 MΩ Ci Input capacitance 1.5 pF †Full range = −55°C to 125°C for the THS4051M. 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at T = full range, V = ±15 V, R = 1 kΩ (unless otherwise noted) A CC L (continued) output characteristics THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX VCC = ±15 V RL = 250 Ω ±12 ±13 VV VCC = ±5 V RL = 150 Ω ±3.2 ±3.5 VVOO OOuuttppuutt vvoollttaaggee sswwiinngg VCC = ±15 V ±13 ±13.6 VCC = ±5 V RRLL == 11 kkΩΩ ±3.5 ±3.8 VV VCC = ±15 V, 80 100 TA = 25°C IO Output current‡ VCC = ±15 V, RL = 20 Ω 70 mA TA = full range VCC = ±5 V 50 75 ISC Short-circuit current‡ VCC = ±15 V 150 mA RO Output resistance Open loop 13 W †Full range = −55°C to 125°C for the THS4051M. ‡Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. power supply THS4051M PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP MAX Dual supply ±4.5 ±16.5 VVCCCC SSuuppppllyy vvoollttaaggee ooppeerraattiinngg rraannggee VV Single supply 9 33 TA = 25°C 8.5 10.5 VVCCCC == ±±1155 VV TA = full range 11.5 IICCCC SSuuppppllyy ccuurrrreenntt ((ppeerr aammpplliiffiieerr)) TA = 25°C 7.5 9.5 mmAA VVCCCC == ±±55 VV TA = full range 10.5 PSRR Power supply rejection ratio VCC = ±5 V or ±15 V TA = full range 70 84 dB †Full range = −55°C to 125°C for the THS4051M. 8

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT VOLTAGE vs vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SUPPLY VOLTAGE 0.0 2.8 14 VCC = ± 5 V & ± 15 V TA=25°C V− Input Offset Voltage − mVIO−−−−−−322110......050505 VCVCC C= ±= ±5 V15 V IµInput Bias Current −AIB 22222.....34567 - Output Voltage -VVO 1102468 RRLL = = 1 1 k5Ω0 Ω −3.5 2.2 2 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 5 7 9 11 13 15 TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C ±VCC - Supply Voltage - V Figure 3 Figure 4 Figure 5 COMMON-MODE INPUT VOLTAGE OUTPUT VOLTAGE SUPPLY CURRENT vs vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE V 15 14 11 ± TA=25°C 13.5 − e 13 10 - Common-Mode Input VoltagR11579 - Output Voltage -VVO124311...5552343 VRVRCLCL C =C= =1=1 k±k±Ω Ω 155 V V VRVRCLC LC= C = =2 = 51± 05± 01 Ω5 5Ω VV I− Supply Current − mACC 6789 TA=85°C TA=25°CTA=−40°C C VI 3 2.5 5 5 7 9 11 13 15 −40 −20 0 20 40 60 80 100 5 7 9 11 13 15 ±VCC - Supply Voltage - V TA − Free-Air Temperature − (cid:2)C ± VCC - Supply Voltage - V Figure 6 Figure 7 Figure 8 POWER-SUPPLY REJECTION VOLTAGE & CURRENT NOISE RATIO CMRR vs vs vs FREQUENCY FREQUENCY FREQUENCY nV/− Voltage Noise −VHznI− Current Noise −pA/Hz1n010010001 IN VTAC C= 2=5 ±° C15 VV aNnd ± 5V RR - Power Supply Rejection Ratio - dB −−−−−−−−87654321000000000 VCC = ±15 V −&V ±C5C V +VCC R − Common-Mode Rejection Ratio − dB −−−−−−−−3456789200000000 VRVCIF(P C=P =1) ±=k1 Ω25 VV or ±5 V S R 0.10 P −90 CM−100 10 100 1k 10k 100k 100k 1M 10M 100M 10k 100k 1M 10M 100M f - Frequency - Hz f - Frequency - Hz f − Frequency − Hz Figure 9 Figure 10 Figure 11 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS CROSSTALK OPEN LOOP GAIN AND vs PHASE RESPONSE FREQUENCY vs −20 VCC = ± 15 V FREQUENCY −30 GRFa in= =3 .26 kΩ 100 VCC = ± 5 V & ±15 V 30 RL = 150 Ω 80 0 −40 Crosstalk − dB −−5600 oop Gain − dB 4600 Gain G−−a63i00n Phase L en 20 −90 −70 Op Phase 0 −120 −80 100k 1M 10M 100M f − Frequency − Hz −20 −150 Figure 12 1k 10k 100k 1M 10M 100M f - Frequency - Hz Figure 13 T HARMONIC DISTORTION DISTORTION DISTORTION OT AL vs vs vs FREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE on - dBc −−5400 VGVCOaiC(nP ==P )±2 = 1 25 VV c −−−565500 VRGf =CL = C1= 5 M=1 H±kΩ z15 V c −−−565500 VRGf =CL = C1= 5 M=1 5H±0 z 1Ω5 V armonic Distorti −−7600 RL = 150 Ω Distortion − dB −−−677605 2nd Harmonic Distortion − dB −−−677605 2Hnadrmonic al H −80 3rd Harmonic Tot RL = 1 kΩ −80 −80 D - −90 −85 3rd Harmonic −85 H T −100 −90 −90 100k 1M 10M 20M 0 5 10 15 20 0 5 10 15 20 f - Frequency - Hz VO − Output Voltage − V VO − Output Voltage − V Figure 14 Figure 15 Figure 16 DISTORTION DISTORTION DISTORTION vs vs vs FREQUENCY FREQUENCY FREQUENCY −40 −40 −40 VCC = ± 15 V VCC = ± 5 V VCC = ± 15 V RL = 1 kΩ RL = 1 kΩ RL = 150 Ω −50 G = 2 −50 G = 2 −50 G = 2 VO(PP) = 2 V VO(PP) = 2 V VO(PP) = 2 V c c c B B B d −60 d −60 d −60 − − − n n n o o o orti −70 orti −70 orti −70 Dist 2nd Harmonic Dist 2nd Harmonic Dist 2nd Harmonic −80 −80 −80 3rd Harmonic 3rd Harmonic −90 −90 −90 3rd Harmonic −100 −100 −100 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 17 Figure 18 Figure 19 10

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS DISTORTION OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY −40 VCC = ± 5 V 2 2 RL = 150 Ω −50 GVO =( P2P) = 2 V 1 RF = 750 Ω 1 RF = 750 Ω Distortion − dBc −−6700 2nd Harmonic Amplitude − dB −−021 RF = 620 Ω Amplitude − dB −−021 RF = 620 Ω −80 3rd Harmonic Output −−43 VCC = ± 15 V RF = 0 Ω Output −−43 VCC = ± 5 V RF = 0 Ω −90 Gain = 1 Gain = 1 −5 RL = 150 Ω −5 RL = 150 Ω −100 −6 VO(PP) = 62 mV −6 VO(PP) = 62 mV 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M f − Frequency − Hz f - Frequency - Hz f - Frequency - Hz Figure 20 Figure 21 Figure 22 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 0.4 0.4 8 VCC = ± 15 V VCC = ± 5 V 0.3 Gain = 1 0.3 Gain = −1 7 mplitude − dB−000...120 RVOL (=P P15) 0= Ω62 mV RF = 750 Ω mplitude − dB−000...120 RVOL (=P P15) 0= Ω62 mV RF = 750 Ω mplitude − dB 456 RF = 2.7 kΩ RF = 3.6 kΩ Output A−−00..21 RF = 620 Ω Output A−−00..21 RF = 620 Ω Output A 23 VCC = ±15 V RF = 1 kΩ RF = 0 Ω Gain = 2 −−00..43 −−00..43 RF = 0 Ω 01 RVOL (=P P15) 0= Ω125 mV 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 23 Figure 24 Figure 25 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 8 6.4 6.4 VCC = ±15 V RF = 3.6 kΩ VCC = ±5 V 7 RF = 3.6 kΩ 6.3 GRLa in= =1 520 Ω 6.3 GRLa in= =1 520 Ω B 6 B 6.2 VO(PP) = 125 mV B 6.2 VO(PP) = 125 mV d d d − − − plitude 45 RF = 2.7 kΩ plitude 66..01 plitude 66..01 RF = 3.6 kΩ m m m ut A 3 RF = 1 kΩ ut A 5.9 ut A 5.9 utp utp RF = 2.7 kΩ utp RF = 2.7 kΩ O 2 VCC = ±5 V O 5.8 O 5.8 Gain = 2 1 RL = 150 Ω 5.7 5.7 VO(PP) = 125 mV RF = 1 kΩ RF = 1 kΩ 0 5.6 5.6 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 26 Figure 27 Figure 28 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 8 2 2 CL= 10 pF 7 1 RF = 5.6 kΩ 1 RF = 5.6 kΩ B 6 B 0 B 0 d d d − − − ude 5 RL = 1 kΩ ude −1 RF = 3.9 kΩ ude −1 RF = 3.9 kΩ ut Amplit 34 RL = 150 Ω ut Amplit −−32 RF = 1 kΩ ut Amplit −−32 RF = 1 kΩ p p p Out 2 VCC = ±15 V Out −4 VCC = ± 15 V Out −4 VCC = ± 5 V Gain = 2 Gain = −1 Gain = −1 1 RL = 2.7 k Ω −5 RL = 150 Ω −5 RL = 150 Ω VO(PP) = 125 mV VO(PP) = 62 mV VO(PP) = 62 mV 0 −6 −6 100k 1M 10M 100M 100k 1M 10M 100M 100k 1M 10M 100M f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 29 Figure 30 Figure 31 OUTPUT AMPLITUDE SETTING TIME DIFFERENTIAL GAIN vs vs vs FREQUENCY OUTPUT STEP NUMBER OF 150-Ω LOADS 10 180 0.12 Gain = 2 V 5 VO(PP)=2.25 V 160 V0.C01C% = ± 5 V 0.10 4W0o IrRstE C-NaTseS C± 1M0o0d IuRlaEt ioRnamp B put Voltage - d −−1005 VO(PP)=0.4 V g Time − ns 111024000 V0.C01C% = ± 15 V ntial Gain − % 00..0068 VCC =± 15 V - OutP) −15 VO(PP)=125 mV Settlin 80 V0.C1%C = ± 15 V Differe 0.04 VO(P −−2250 VGRCFa iCn= ==2 .±27 1kΩ5 V 4600 V0.C1%C = ± 5 V 0.02 VCC =± 5 V RL = 150 Ω RF = 360 Ω −30 20 0 100k 1M 10M 100M 1 2 3 4 5 1 2 3 4 f - Frequency - Hz VO - Output Step Voltage - V Number of 150-Ω Loads Figure 32 Figure 33 Figure 34 DIFFERENTIAL GAIN DIFFERENTIAL PHASE DIFFERENTIAL PHASE vs vs vs NUMBER OF 150-Ω LOADS NUMBER OF 150-Ω LOADS NUMBER OF 150-Ω LOADS 0.2 0.5° 0.6° Gain = 2 Gain = 2 Gain = 2 40 IRE-PAL Modulation RF = 1 kΩ 40 IRE-PAL Modulation 0.16 Worst Case ±100 IRE Ramp 0.4° 40 IRE-NTSC Modulation 0.5° Worst Case ±100 IRE Ramp Worst Case ±100 IRE Ramp % ain − 0.12 Phase 0.3° Phase 0.4° VCC =± 15 V Differential G 0.08 VCC =± 15 VVCC =± 5 V Differential 0.2° VCC =± 15 VVCC =± 5 V Differential 00..32°° VCC =± 5 V 0.04 0.1° 0.1° 0 0° 0° 1 2 3 4 1 2 3 4 1 2 3 4 Number of 150-Ω Loads Number of 150-Ω Loads Number of 150-Ω Loads Figure 35 Figure 36 Figure 37 12

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS 1-V STEP RESPONSE 5-V STEP RESPONSE 1-V STEP RESPONSE 0.6 3 0.6 VCC = ± 5 V VCC = ± 15 V 0.4 Gain = 2 2 0.4 Gain = 2 RF = 2.7 kΩ RF = 2.7 kΩ − V RL = 150 Ω − V − V RL = 150 Ω e 0.2 e 1 e 0.2 g g g a a a olt olt olt ut V−0.0 ut V 0 ut V−0.0 p p p ut ut ut − O−0.2 − O −1 VCC = ± 5 V − O−0.2 O O Gain = −1 O V −0.4 V −2 RF = 3.9 kΩ V −0.4 RL = 150 Ω −0.6 −3 −0.6 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 t - Time - ns t - Time - ns t - Time - ns Figure 38 Figure 39 Figure 40 20-V STEP RESPONSE 15 VCC = ± 15 V 10 Gain = 5 RF = 2.7 kΩ − V RL = 150 & 1 kΩ e 5 g a olt ut V 0 p ut O −5 − O V −10 −15 0 100 200 300 400 500 t - Time - ns Figure 41 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION THEORY OF OPERATION bipolar process with NPN and PNP transistors possessing f s of several GHz. This results in an exceptionally high T The THS405x is a high-speed operational amplifier performance amplifier that has a wide bandwidth, high configured in a voltage feedback architecture. It is built slew rate, fast settling time, and low distortion. A simplified using a 30-V, dielectrically isolated, complementary schematic is shown in Figure 42. (7) VCC+ (6) OUT IN− (2) IN+ (3) (4) VCC− NULL (1) NULL (8) Figure 42. THS405x Simplified Schematic NOISE CALCULATIONS AND NOISE FIGURE Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ratio (SNR) is very important. The noise model for the THS405x is shown in Figure 43. This model includes all of the noise sources as follows: • e = Amplifier internal voltage noise (nV/√Hz) n • IN+ = Noninverting current noise (pA/√Hz) • IN− = Inverting current noise (pA/√Hz) • e = Thermal voltage noise associated with each resistor (e = 4 kTR ) Rx Rx x 14

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) eRs en RS eni IN+ IN− Figure 43. Noise Model The total equivalent input noise density (e ) is calculated by using the following equation: ni (cid:7) (cid:2) (cid:3)2 (cid:2) (cid:2) (cid:3)(cid:3)2 (cid:2) (cid:3) (cid:2) (cid:3)2 e (cid:1) e (cid:4) IN(cid:4)(cid:5)R (cid:4) IN–(cid:5) R (cid:6)R (cid:4)4kTR (cid:4)4kT R (cid:6)R ni n S F G s F G Where: k = Boltzmann’s constant = 1.380658 × 10−23 T = Temperature in degrees Kelvin (273 +°C) R || R = Parallel resistance of R and R F G F G To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the overall amplifier ni gain (A ). V (cid:2) (cid:3) R e (cid:1)e A (cid:1) e 1(cid:4) F (noninvertingcase) no ni V ni R G As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel resistance term. This leads G to the general conclusion that the most dominant noise sources are the source resistor (R ) and the internal amplifier noise S voltage (e ). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest n noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits Applications Report (literature number SLVA043). 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. (cid:9) (cid:11) (cid:8) e 2 (cid:8) NF (cid:1) 10log(cid:8) ni (cid:8) (cid:2) (cid:3)2 (cid:10) (cid:12) e Rs Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: (cid:9) (cid:13) (cid:15)(cid:11) (cid:2) (cid:3)2 (cid:2) (cid:3)2 (cid:8) (cid:8) (cid:8)(cid:8) (cid:14) en (cid:4) IN(cid:4)(cid:5)RS (cid:16)(cid:8)(cid:8) (cid:8) (cid:8) NF (cid:1) 10log(cid:8)1(cid:4) (cid:8) (cid:8) 4kTRS (cid:8) (cid:10) (cid:12) Figure 44 shows the noise figure graph for the THS405x. NOISE FIGURE vs SOURCE RESISTANCE 40 f = 10 kHz 35 TA = 25°C 30 B) d 25 e ( gur 20 Fi e s 15 oi N 10 5 0 10 100 1k 10k 100k Source Resistance - Ω Figure 44. Noise Figure vs Source Resistance 16

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION DRIVING A CAPACITIVE LOAD Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 45. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 1 kΩ 1 kΩ _ Input 20 Ω THS405x Output + CLOAD Figure 45. Driving a Capacitive Load OFFSET NULLING The THS405x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4051. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 46. VCC+ 0.1 µF + THS4051 _ 10 kΩ 0.1 µF VCC− Figure 46. Offset Nulling Schematic 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION OFFSET VOLTAGE The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times the OO IO IB corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG (cid:1)IIB− − VO + RS − + (cid:1)IIB+ VIO (cid:2) (cid:3) (cid:2) (cid:3) R R VOO(cid:1)VIO 1(cid:4)RF (cid:17)IIB(cid:4)RS 1(cid:4)RF (cid:17)IIB(cid:18)RF G G Figure 47. Output Offset Voltage Model OPTIMIZING UNITY GAIN RESPONSE Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 620 Ω should be used as shown in Figure 48. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + THS405x Output _ 620 Ω Figure 48. Noninverting, Unity Gain Schematic 18

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL CONFIGURATIONS When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 49). RG RF − + VI R1 C1 f (cid:1) –3dB Figure 49. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C VI R1 R2 C2 RG Figure 50. 2-Pole Low-Pass Sallen-Key Filter 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION CIRCUIT LAYOUT CONSIDERATIONS To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation board is available to use as a guide for layout or for evaluating the device performance. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. GENERAL POWERPAD DESIGN CONSIDERATIONS The THS405x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 51(a) and Figure 51(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 51(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. 20

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 51. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils)  Figure 52. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS405xDGN IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS405xDGN package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the THS405xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches (or 76.2 mm × 76.2 mm), then the expected thermal coefficient, θ , is about 58.4°C/W. For comparison, the non-PowerPAD version of the JA THS405x IC (SOIC) is shown. For a given θ , the maximum power dissipation is shown in Figure 53 and is calculated JA by the following formula: (cid:2) (cid:3) T –T P (cid:1) MAX A D (cid:1) JA Where: P = Maximum power dissipation of THS405x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A θJA = θJC + θCA θ = Thermal coefficient from junction to case JC θ = Thermal coefficient from case to ambient air (°C/W) CA MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 3.5 DθJGAN = P 5a8c.k4a°Cge/W TJ = 150°C 2 oz. Trace And Copper Pad 3 With Solder W − DGN Package on 2.5 θJA = 158°C/W ati SOIC Package 2 oz. Trace And ssip 2 HθJigAh =-K 9 8T°eCs/tW PCB CWoitphpoeurt PSaodlder Di r e w o 1.5 P m u m 1 xi a M 0.5 SOIC Package Low-K Test PCB θJA = 167°C/W 0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and PCB size = 3”×3” Figure 53. Maximum Power Dissipation vs Free-Air Temperature More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 22

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially devices with multiple amplifiers. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 54 to Figure 57 show this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result. When using V = ±5 V, there is generally not a heat problem, even CC with SOIC packages. But, when using V = ±15 V, the SOIC package is severely limited in the amount of heat it can CC dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases and the heat dissipation JA capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4052), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier outputs are identical. THS4051 THS4051 MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS A 128000 VTjC C= 1=5 ±0 °5C V MCuarxriemnut mLi mOuitt Lpiunte A 1000 TTAJ == 15500°C°C VCC = ± 15 V m TA = 50°C m nt − 160 nt − CMuarxreimntu Lmim Oiut tLpiunte e e DGN Package urr 140 urr θJA = 58.4°C/W C C ut 120 Package With ut utp θJA < = 120°C/W utp S O 100 S O 100 M M m R 80 θSJOA- 8= P1a6c7k°Cag/We m R SO-8 Package u u m 60 Low-K Test PCB m θJA = 98°C/W axi axi High-K Test PCB − M 40 − M SO-8 Package I||O 20 Safe OApreearating I||O LθoJwA- K= T16e7s°t CP/CWB Safe OApreearating 0 10 0 1 2 3 4 5 0 3 6 9 12 15 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 54 Figure 55 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) THS4052 THS4052 MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 200 1000 Package With Maximum Output VCC = ± 15 V Maximum Output A 180 θJA ≤ 60°C/W Current Limit Line A TJ = 150°C Current Limit Line nt − m 160 nt − m TBAo t=h 5C0h°aCnnels e e urr 140 urr 100 C C ut 120 ut p p ut ut S O 100 SO-8 Package S O M M um R 80 LθoJwA- K= T16e7s°t CP/CWB um R 10 SθOJA-8 = P 9a8c°kCa/gWe m 60 m High-K Test PCB xi Safe Operating Area xi I− Ma||O 4200 HSiθgOJhA--8K = P T9ae8cs°kCt aP/gWCeB VTTBAJCo tC =h= 5=C10 5±h°0 aC5°nC Vnels I− Ma||O θSDJaAGfe N =O P5pa8ec.r4ka°atCign/eWg Area LθSoJOwA-- 8K= PT1a6ec7sk°t CaPg/CWeB 0 1 0 1 2 3 4 5 0 3 6 9 12 15 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 56 Figure 57 24

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8) www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION EVALUATION BOARD An evaluation board is available for the THS4051 (literature number SLOP220) and THS4052 (literature number SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 58. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the THS4051 EVM User’s Guide or the THS4052 EVM User’s Guide. To order the evaluation board, contact your local TI sales office or distributor. VCC+ + C2 C5 6.8 µF 0.1 µF R4 2 kΩ NULL IN+ + R5 49.9 Ω R3 THS4051 OUT 49.9 Ω _ NULL R2 C1 2 kΩ C4 + 6.8 µF 0.1 µF IN− R1 VCC− 49.9 Ω Figure 58. THS4051 Evaluation Board Schematic 25

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9959901Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9959901Q2A THS4051MFKB 5962-9959901QPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9959901QPA THS4051M THS4051CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4051C & no Sb/Br) THS4051CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACQ & no Sb/Br) THS4051CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACQ & no Sb/Br) THS4051CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4051C & no Sb/Br) THS4051ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4051I & no Sb/Br) THS4051IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4051I & no Sb/Br) THS4051IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACR & no Sb/Br) THS4051IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACR & no Sb/Br) THS4051IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4051I & no Sb/Br) THS4051IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4051I & no Sb/Br) THS4051MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9959901Q2A THS4051MFKB THS4051MJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 THS4051MJG THS4051MJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9959901QPA THS4051M THS4052CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4052C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4052CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACE & no Sb/Br) THS4052CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACE & no Sb/Br) THS4052CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4052C & no Sb/Br) THS4052ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4052I & no Sb/Br) THS4052IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACF & no Sb/Br) THS4052IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACF & no Sb/Br) THS4052IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4052I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4051, THS4051M : •Catalog: THS4051 •Military: THS4051M NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS4051CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4051IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4051IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4052CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4052CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4052IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4052IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS4051CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4051CDR SOIC D 8 2500 350.0 350.0 43.0 THS4051IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4051IDR SOIC D 8 2500 350.0 350.0 43.0 THS4052CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4052CDR SOIC D 8 2500 350.0 350.0 43.0 THS4052IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4052IDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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