(cid:25)(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 (cid:1) C-Stable Amplifiers Drive Any Capacitive THS4041 D AND DGN PACKAGE Load (TOP VIEW) (cid:1) High Speed − 165 MHz Bandwidth (−3 dB); C = 0 pF NULL 1 8 NULL L − 100 MHz Bandwidth (−3 dB); CL = 100 pF IN− 2 7 VCC+ − 35 MHz Bandwidth (−3 dB); C = 1000 pF IN+ 3 6 OUT L − 400 V/µs Slew Rate VCC− 4 5 NC (cid:1) Unity Gain Stable NC − No internal connection (cid:1) High Output Drive, I = 100 mA (typ) O (cid:1) THS4042 Very Low Distortion D AND DGN PACKAGE − THD = −75 dBc (f = 1 MHz, RL = 150 Ω) (TOP VIEW) − THD = −89 dBc (f = 1 MHz, R = 1 kΩ) L (cid:1) Wide Range of Power Supplies 1OUT 1 8 VCC+ − V = ±5 V to ±15 V 1IN− 2 7 2OUT CC (cid:1) 1IN+ 3 6 2IN− Available in Standard SOIC or MSOP PowerPAD Package VCC− 4 5 2IN+ (cid:1) Evaluation Module Available description Cross Section View Showing PowerPAD Option (DGN) The THS4041 and THS4042 are single/dual, high-speed voltage feedback amplifiers capable of driving any capacitive load. This makes them OUTPUT AMPLITUDE ideal for a wide range of applications including vs driving video lines or buffering ADCs. The devices FREQUENCY feature high 165-MHz bandwidth and 400-V/µsec 10 slew rate. The THS4041/2 are stable at all gains 8 CCLL == 01.010 µ0 FpF CCLL == 01 0p0F pF for both inverting and noninverting configurations. 6 B For video applications, the THS4041/2 offer d 4 − excellent video performance with 0.01% differen- de 2 u tial gain error and 0.01° differential phase error. plit 0 m T2fr0ho-emΩs e±lo 5aaVmd tpaoln i±fdi1e o5rspV e.craante dorfifv peo uwpe rt os u1p0p0li emsA ra inngtoin ag Output A −−−264 VGRCFai Cn= ==2 01±01 5Ω V RELATED DEVICES −8 RL = 150 Ω VO(PP)=62 mV RELATED DEVICES −10 100k 1M 10M 100M 1G DEVICE DESCRIPTION f − Frequency − Hz THS4011/2 290-MHz Low Distortion High-Speed Amplifier THS4031/2 100-MHz Low Noise High-Speed Amplifier THS4081/2 175-MHz Low Power High-Speed Amplifiers CAUTION: The THS4041 and THS4042 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Insruments Incorporated. (cid:21)(cid:24)(cid:26)(cid:22)(cid:27)(cid:14)(cid:1)(cid:19)(cid:26)(cid:28) (cid:22)(cid:15)(cid:1)(cid:15) (cid:29)(cid:30)(cid:31)!"#$%(cid:29)!(cid:30) (cid:29)& ’("")(cid:30)% $& !(cid:31) *(+,(cid:29)’$%(cid:29)!(cid:30) -$%). Copyright  2000, Texas Instruments Incorporated (cid:21)"!-(’%& ’!(cid:30)(cid:31)!"# %! &*)’(cid:29)(cid:31)(cid:29)’$%(cid:29)!(cid:30)& *)" %/) %)"#& !(cid:31) (cid:1))0$& (cid:19)(cid:30)&%"(#)(cid:30)%& &%$(cid:30)-$"- 1$""$(cid:30)%2. (cid:21)"!-(’%(cid:29)!(cid:30) *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 AVAILABLE OPTIONS PACKAGED DEVICES NUMBER OF MSOP EVALUATION TA CHANNELS SMAPLLL AOSUTTICLINE† PMLSAOSTPI†C SYMBOL MODULE (D) (DGN) 1 THS4041CD THS4041CDGN ACO THS4041EVM 00°°CC ttoo 7700°°CC 2 THS4042CD THS4042CDGN ACC THS4042EVM 1 THS4041D THS4041IDGN ACP — −−4400°°CC ttoo 8855°°CC 2 THS4042ID THS4042IDGN ACD — †The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4041CDGNR). functional block diagram VCC 8 Null 2 1IN− 1 1OUT IN− 2 1 8 1IN+ 3 6 OUT 3 IN+ 2IN− 6 7 2OUT 5 Figure 2. THS4041 − Single Channel 2IN+ 4 VCC− Figure 1. THS4042 − Dual Channel absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V I CC Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA O Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V IO Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 DISSIPATION RATING TABLE θθJJAA θθJJCC TTAA == 2255°CC PPAACCKKAAGGEE (°C/W) (°C/W) POWER RATING D 167† 38.3 740 mW DGN‡ 58.4 4.7 2.14 W †This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC proposed High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W. ‡This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC. For further information, refer to Application Information section of this data sheet. recommended operating conditions MIN NOM MAX UNIT Dual supply ±4.5 ±16 SSuuppppllyy vvoollttaaggee,, VVCCCC++ aanndd VVCCCC−− VV Single supply 9 32 C-suffix 0 70 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree,, TTAA °°CC I-suffix −40 85 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) A CC L dynamic performance PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VCC = ±15 V Rf = 200 Ω 165 GGaaiinn == 11 MMHHzz DDyynnaammiicc ppeerrffoorrmmaannccee ssmmaallll--ssiiggnnaall bbaannddwwiiddtthh VCC = ±5 V Rf = 200 Ω 150 ((−−33 ddBB)) VCC = ±15 V Rf = 1.3 kΩ 60 GGaaiinn == 22 MMHHzz VCC = ±5 V Rf = 1.3 kΩ 60 BBWW VCC = ±15 V Rf = 200 Ω 45 BBaannddwwiiddtthh ffoorr 00..11 ddBB ffllaattnneessss GGaaiinn == 11 MMHHzz VCC = ±5 V Rf = 200 Ω 45 VO(pp) = 20 V, VCC = ±15 V 6.3 FFuullll ppoowweerr bbaannddwwiiddtthh§§ MMHHzz VO(pp) = 5 V, VCC = ±5 V 20 VCC = ±15 V, 20-V step, Gain = 5 400 SSRR SSlleeww rraattee‡‡ VV//µss VCC = ±5 V, 5-V step, Gain = −1 325 VCC = ±15 V, 5-V step 120 SSeettttlliinngg ttiimmee ttoo 00..11%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 120 ttss VCC = ±15 V, 5-V step 250 SSeettttlliinngg ttiimmee ttoo 00..0011%% GGaaiinn == −−11 nnss VCC = ±5 V, 2-V step 280 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix ‡Slew rate is measured from an output level range of 25% to 75%. §Full power bandwidth = slew rate / 2 π VO(Peak). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued) A CC L noise/distortion performance PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT RL = 150 Ω −75 VVOO((pppp)) == 22 VV,, VVCCCC == ±±1155 VV RL = 1 kΩ −89 TTHHDD TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn ddBBcc ff == 11 MMHHzz,, GGaaiinn == 22 RL = 150 Ω −75 VVCCCC == ±±55 VV RL = 1 kΩ −86 Vn Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 14 nV/√Hz In Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 0.9 pA/√Hz GGaaiinn == 22,, NNTTSSCC,, VCC = ±15 V 0.01% DDiiffffeerreennttiiaall ggaaiinn eerrrroorr 40 IRE modulation, ±100 IRE ramp VCC = ±5 V 0.01% GGaaiinn == 22,, NNTTSSCC,, VCC = ±15 V 0.01° DDiiffffeerreennttiiaall pphhaassee eerrrroorr 40 IRE modulation, ±100 IRE ramp VCC = ±5 V 0.02° Channel-to-channel crosstalk (THS4042 only) VCC = ±5 V or ±15 V, f = 1 MHz Gain = 2 −64 dB †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix dc performance PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VVCCCC == ±±1155 VV,, VVOO == ±±1100 VV,, TA = 25°C 74 80 RL = 1 k Ω TA = full range 69 OOppeenn lloooopp ggaaiinn ddBB VVCCCC == ±±55 VV,, VVOO == ±±22..55 VV,, TA = 25°C 69 76 RL = 250 Ω TA = full range 66 TA = 25°C 2.5 10 VVOOSS IInnppuutt ooffffsseett vvoollttaaggee VVCCCC == ±±55 VV oorr ±±1155 VV mmVV TA = full range 13 Offset voltage drift VCC = ±5 V or ±15 V TA = full range 10 µV/°C TA = 25°C 2.5 6 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV µAA TA = full range 8 TA = 25°C 35 250 IIOOSS IInnppuutt ooffffsseett ccuurrrreenntt VVCCCC == ±±55 VV oorr ±±1155 VV nnAA TA = full range 400 Offset current drift TA = full range 0.3 nA/°C †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix input characteristics PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VCC = ±15 V ±13.8 ±14.3 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee VCC = ±5 V ±3.8 ±4.3 VV VCC = ±15 V, VICR = ±12 V 70 90 CCMMRRRR CCoommmmoonn mmooddee rreejjeeccttiioonn rraattiioo VCC = ±5 V, VICR = ±2.5 V TTAA == ffuullll rraannggee 80 100 ddBB ri Input resistance 1 MΩ Ci Input capacitance 1.5 pF †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued) A CC L output characteristics PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VCC = ±15 V RL = 250 Ω ±11.5 ±13 VV VCC = ±5 V RL = 150 Ω ±3.2 ±3.5 VVOO OOuuttppuutt vvoollttaaggee sswwiinngg VCC = ±15 V ±13 ±13.6 VCC = ±5 V RRLL == 11 kkΩΩ ±3.5 ±3.8 VV VCC = ±15 V 80 100 IIOO OOuuttppuutt ccuurrrreenntt‡‡ VCC = ±5 V RRLL == 2200 ΩΩ 50 65 mmAA ISC Short-circuit current‡ VCC = ±15 V 150 mA RO Output resistance Open loop 13 Ω †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix ‡Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. power supply PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT Dual supply ±4.5 ±16.5 VVCCCC SSuuppppllyy vvoollttaaggee ooppeerraattiinngg rraannggee VV Single supply 9 33 TA = 25°C 8 9.5 VVCCCC == ±±1155 VV TA = full range 11 IICCCC SSuuppppllyy ccuurrrreenntt ((ppeerr aammpplliiffiieerr)) TA = 25°C 7 8.5 mmAA VVCCCC == ±±55 VV TA = full range 10 TA = 25°C 75 84 PPSSRRRR PPoowweerr ssuuppppllyy rreejjeeccttiioonn rraattiioo VVCCCC == ±±55 VV oorr ±±1155 VV ddBB TA = full range 70 †Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS OPEN LOOP GAIN AND OUTPUT AMPLITUDE OUTPUT AMPLITUDE PHASE RESPONSE vs vs vs FREQUENCY FREQUENCY FREQUENCY 100 0 2 0.4 VCC = ±15 V and ±5 V 1 0.3 Open Loop Gain − dB 86420000 Phase Gain −−−−639102000Phase − Degrees Output Amplitude − dB −−−−01234 VGCaiCn == 1±15 V RL = 150 ΩRL = 1 kΩ Output Amplitude − dB −−−00000.....21012 VCC = ±15 VRL = 1R50L Ω= 1 kΩ 0 −150 −5 RVOF == 200.20 VΩrms −0.3 GRVOFai n== =20 0.120 VΩrms −20 −180 −6 −0.4 1k 10k 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f - Frequency - Hz Figure 3 Figure 4 Figure 5 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 10 10 2 CL = 1000 pF CL = 0 pF 8 CL = 0.1 µF CL = 100 pF 8 1 RL = 1 kΩ 6 6 B B B 0 − d 4 − d 4 CL = 0.01 µF − d RL = 150 Ω ude 2 ude 2 CL = 10 pF ude −1 plit 0 plit 0 plit −2 m m m Output A −−−264 VGRCFai Cn= ==2 01±01 5Ω V Output A −−−246 VGRCFai Cn= ==2 01±01 5Ω V Output A −−34 VGCaiCn == 1±5 V −8 RVOL (=P 1P5)=06 Ω2 mV −8 RVOL (=P 1P5)=06 Ω2 mV −5 RVOF == 200.20 VΩrms −10 −10 −6 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 6 Figure 7 Figure 8 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 0.4 10 10 0.3 RL = 1 kΩ 8 CCLL == 01.010 µ0 FpF CCLL == 01 0p0F pF 8 6 6 B 0.2 B B − d − d 4 − d 4 CL = 0.01 µF ude 0.1 ude 2 ude 2 CL = 10 pF plit −0.0 plit 0 plit 0 m m m Output A −−00..12 VGCaiCn == 1±5 VRL = 150 Ω Output A −−−246 VGRCFai Cn= ==2 01±05 ΩV Output A −−−624 VGRCFai Cn= ==2 01±05 ΩV −0.3 RF = 200 Ω −8 RL = 150 Ω −8 RL = 150 Ω VO = 0.2 Vrms VO(PP)=62 mV VO(PP)=62 mV −0.4 −10 −10 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 9 Figure 10 Figure 11 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 8 16 16 CL = 0.1 µF RF = 1.3 kΩ 7 14 RL = 150 Ω 14 RL = 1 kΩ 12 VO(PP) = 125 mV 12 dB 6 dB 10 CL = 1000 pF dB 10 CL = 0.01 µF de − 5 RL = 150 Ω de − 8 de − 8 CL = 100 pF plitu 4 plitu 6 CL = 10 pF plitu 6 m m m Output A 321 VGRVCOFai C n== ==10 ..2±341 kV5Ωr Vms Output A −4202 VGCaiCn == 2±15 V Output A −4202 VGRRVCOFLa i C(n==P ==1P1 5 .)2±3 0=1 k 5Ω1Ω 2V5 mV 0 −4 −4 100k 1M 10M 100M 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 12 Figure 13 Figure 14 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 2 16 16 CL = 0.1 µF VCC = ±5 V 1 14 Gain = 2 14 RL = 1 kΩ 12 RF = 1.3 kΩ 12 ude − dB −01 RL = 150 Ω ude − dB 108 RVCOLL ( =P= 1P15)0=001 0Ω2 5p FmV ude − dB 108 CL = 0.01 µF CL = 100 pF plit −2 plit 6 plit 6 m m m ut A −3 ut A 4 CL = 10 pF ut A 4 Outp −4 VCC = ±5 V Outp 2 Outp 2 VGCaiCn == 2±5 V −5 GRVOFai n== =10 ..234 kVΩrms −02 −02 RRVOFL (==P 1P15.)3 0= k Ω1Ω25 mV −6 −4 −4 100k 1M 10M 100M 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 15 Figure 16 Figure 17 OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 2 10 10 CL = 0.1 µF VCC = ±15 V 1 RL = 1 kΩ 8 Gain = −1 8 6 RF = 2 kΩ 6 de − dB −01 RL = 150 Ω de − dB 42 RVOL (=P 1P5)=06 Ω2 mV de − dB 24 CL = 0.01 µF CL = 100 pF plitu −2 plitu 0 CL = 1000 pF plitu 0 m m m Output A −−34 VCC = ±15 V Output A −−24 CL = 10 pF Output A −−24 VGCaiCn == −±115 V −5 GRVOFai n== =20 .−k2Ω1 Vrms −−68 −−68 RRVOFL (==P 1P25 )k=0Ω6 Ω2 mV −6 −10 −10 100k 1M 10M 100M 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 18 Figure 19 Figure 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE OUTPUT AMPLITUDE OUTPUT AMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY 2 10 10 CL = 0.1 µF VCC = ±5 V 1 RL = 1 kΩ 68 GRFai n= =2 −kΩ1 68 B 0 B RL = 150 Ω B CL = 0.01 µF de − d −1 RL = 150 Ω de − d 24 VO(PP)=62 mV de − d 24 CL = 100 pF plitu −2 plitu 0 CL = 1000 pF plitu 0 m m m Output A −−34 VCC = ±5 V Output A −−24 CL = 10 pF Output A −−24 VGCaiCn == −±51 V −5 GRVOFai n== =20 .−k2Ω1 Vrms −−68 −−68 RRVOFL (==P 1P25 )k=0Ω6 Ω2 mV −6 −10 −10 100k 1M 10M 100M 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 21 Figure 22 Figure 23 OUTPUT OVERSHOOT OUTPUT OVERSHOOT TOTAL HARMONIC DISTORTION vs vs vs CAPACITIVE LOAD CAPACITIVE LOAD FREQUENCY 60 50 −40 VCC = ±15 V & ±5 V VCC = ±15 V & ±5 V B VCC = ±15 V − % 5400 GRRFLa i n== =12 50100 ΩΩ 1 V Step − % 40 GRRFLa i n== =12 5 −k0Ω1 Ω 1 V Step ortion − d −50 GVOai(np p=) 2= 2 V oot oot 30 Dist −60 Output Oversh 321000 5 V Step Output Oversh 2100 5 V Step D − Total Harmonic −−−987000 RL = 150 Ω RL = 1 kΩ H T 0 0 −100 1 10 100 1k 10k 1 10 100 1k 10k 100k 1M 10M 20M Capacitive Load − pF Capacitive Load − pF f − Frequency − Hz Figure 24 Figure 25 Figure 26 DISTORTION DISTORTION DISTORTION vs vs vs FREQUENCY FREQUENCY FREQUENCY −40 −40 −40 VCC = ±15 V VCC = ±15 V VCC = ±5 V Gain = 2 Gain = 2 Gain = 2 −50 RL = 150 Ω −50 RL = 1 kΩ −50 RL = 150 Ω VO(pp) = 2 V VO(pp) = 2 V VO(pp) = 2 V B −60 B −60 B −60 − d 2nd Harmonic − d 2nd Harmonic − d 2nd Harmonic n n n o −70 o −70 o −70 orti orti orti st st st Di −80 Di −80 3rd Harmonic Di −80 −90 3rd Harmonic −90 −90 3rd Harmonic −100 −100 −100 100k 1M 10M 20M 100k 1M 10M 20M 100k 1M 10M 20M f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 27 Figure 28 Figure 29 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS DISTORTION DISTORTION DISTORTION vs vs vs FREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE −40 −40 −50 VCC = ±5 V VCC = ±15 V VCC = ±15 V Gain = 2 Gain = 5 Gain = 5 −50 RL = 1 kΩ −50 RL = 150 Ω −60 RL = 1 kΩ VO(pp) = 2 V f = 1 MHz f = 1 MHz 2nd Harmonic B −60 B) 2nd Harmonic B) Distortion − d −−7800 2nd Harmonic Distortion (d −−7600 3rd Harmonic Distortion (d −−7800 3rd Harmonic −80 −90 −90 3rd Harmonic −100 −90 −100 100k 1M 10M 20M 0 5 10 15 20 0 5 10 15 20 f − Frequency − Hz VO − Output Voltage − V VO − Output Voltage − V Figure 30 Figure 31 Figure 32 DIFFERENTIAL GAIN DIFFERENTIAL PHASE DIFFERENTIAL GAIN vs vs vs NUMBER OF 150-Ω LOADS NUMBER OF 150-Ω LOADS NUMBER OF 150-Ω LOADS 0.5 0.4° 0.6 Gain = 2 Gain = 2 Gain = 2 RF = 1.3 kΩ 0.35° RF = 1.3 kΩ RF = 1.3 kΩ 0.4 40 IRE-NTSC Modulation 40 IRE-NTSC Modulation 0.5 40 IRE-PAL Modulation % Worst Case ±100 IRE Ramp 0.3° Worst Case ±100 IRE Ramp % Worst Case ±100 IRE Ramp Gain − 0.3 Phase0.25° Gain − 0.4 ntial VCC =±15 V ntial 0.2° ntial 0.3 VCC =±15 V Differe 0.2 Differe0.15° Differe 0.2 0.1° 0.1 VCC =±5 V 0.05° VCC =±5 V 0.1 VCC =±5 V VCC =±15 V 0 0° 0 1 2 3 1 2 3 1 2 3 Number of 150-Ω Loads Number of 150-Ω Loads Number of 150-Ω Loads Figure 33 Figure 34 Figure 35 CLOSED-LOOP DIFFERENTIAL PHASE OUTPUT IMPEDANCE PSRR vs vs vs NUMBER OF 150-Ω LOADS FREQUENCY FREQUENCY Differential Phase 000...000123...555234°°°°°° GR4W0Fao i Irn=Rs t=E1 C .-23Pa AksΩeL ±M1o0d0u IlaRtEio nRamp Ω− Output Impedance − 101001 VGRCFai Cn= ==1 2±k5Ω V & ±15 V er Supply Rejection Ratio − dB 567834000000 +VVCCCC = &± 1−5V CV C& R±e5s Vponses 0.00.51°° VCC =±5 V VCC =±15 V ZO R − Pow 2100 R 0° 0.1 PS 0 1 2 3 100k 1M 10M 100M 1G 100k 1M 10M 100M Number of 150-Ω Loads f − Frequency − Hz f − Frequency − Hz Figure 36 Figure 37 Figure 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS CMRR CROSSTALK VOLTAGE & CURRENT NOISE vs vs vs FREQUENCY FREQUENCY FREQUENCY B 90 −20 1k − d VCC = ±15 V & ±5 V VCC = ±15 V & ±5 V VCC = ±15 V & ±5 V ommon Mode Rejection Ratio 45673280000000 RVIF(p =p )1 = k Ω2 V Crosstalk − dB −−−−−7654300000 GRRFLa i n== =12 5.270 kΩΩ nV/− Voltage Noise −Hzn− Current Noise −pA/Hzn101001 IN TA = 25°C VN R − C 10 −80 V I R M C 0 −90 0.10 100k 1M 10M 100M 100k 1M 10M 100M 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz Figure 39 Figure 40 Figure 41 SLEW RATE SETTING TIME INPUT OFFSET VOLTAGE vs vs vs FREE-AIR TEMPERATURE OUTPUT STEP FREE-AIR TEMPERATURE 500 300 0.0 RL = 150 Ω VCC = ±5 V 280 0.01% µSR − Slew Rate − V/s 443325050500000 VVCOC(VVP CO=P C()±P =1=P 5 2)± 0V=5 V5V V Settling Time − ns 221111222086424600000000 GRFai n= =V03 .6C−101%C Ω = ±15 V & ±V05.C0 V1C% = ±15 V V− Input Offset Voltage − mVIO−−−−0112....5050 VCC = ±15 V VCC = ±5 V 200 100 −2.5 −40 −20 0 20 40 60 80 100 1 2 3 4 5 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C VO − Output Step Voltage − V TA − Free-Air Temperature − °C Figure 42 Figure 43 Figure 44 INPUT BIAS CURRENT COMMON-MODE INPUT VOLTAGE OUTPUT VOLTAGE vs vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE SUPPLY VOLTAGE 2.55 V 15 14 VCC = ±5 V & ±15 V ± TA = 25°C TA = 25°C − A 2.50 e 13 12 µ− Input Bias Current − 222...443505 mmon-Mode Input Voltag 1719 - Output Voltage -VO 1086 RL = R1 Lk Ω= 150 Ω o V IIB2.30 - CR 5 4 C 2.25 VI 3 2 −40 −20 0 20 40 60 80 100 5 7 9 11 13 15 5 7 9 11 13 15 TA − Free-Air Temperature − °C ±VCC − Supply Voltage − V ±VCC − Supply Voltage − V Figure 45 Figure 46 Figure 47 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE SUPPLY CURRENT 1-V FALLING EDGE vs vs RESPONSE FREE-AIR TEMPERATURE SUPPLY VOLTAGE 15 10 CL = 0.01 µF VCC = ±15 V Gain = 1 13 RF = 200 Ω - Output Voltage -VVO 11975 VRCL C= =1 k±Ω15 V VRCL C=VR =2CL5 ± C0=1 5Ω=1 Vk±Ω5 V − Supply Current − mACC 9876 TTTAAA === −82554°°0CC°C V− Output Voltage − VO(0.5 V / Div) CCRCLLLL = === 1 1115000000 pΩ0 pF pFF 3 I VCC = ±15 V RL = 150 Ω 1 5 0 50 100 150 200 250 300 −40 −T20A − Fr0ee-Ai2r0 Temp4e0ratu6r0e − °C80 100 5 ± 7VCC − S9upply V1o1ltage −1 V3 15 t − Time − ns Figure 48 Figure 49 Figure 50 1-V FALLING EDGE 5-V FALLING EDGE 5-V FALLING EDGE RESPONSE RESPONSE RESPONSE CL = 0.01 µF VCC = ±5 V VCC = ±15 V VCC = ±5 V Gain = 1 RF = 200 Ω Gain = 1 Gain = 1 e − V RL = 150 Ω e − V RRFL == 125000 ΩΩ e − V RRFL == 125000 ΩΩ g g g − Output Volta(0.5 V / Div) CCLL == 110000 0p FpF − Output Volta(1 V/Div) CL = 1000 pF − Output Volta(1 V/Div) CL = 1000 pF O O O V V CL = 100 pF V CL = 100 pF CL = 10 pF CL = 10 pF CL = 10 pF 0 50 100 150 200 250 300 350 0 50 100 150 200 250 0 50 100 150 200 250 t − Time − ns t − Time − ns t − Time − ns Figure 51 Figure 52 Figure 53 5-V AND 1-V STEP 5-V AND 1-V STEP CAPACITIVE LOAD RESPONSE RESPONSE RESPONSE 4 4 4 5−V Step 5−V Step Gain = −1 3 3 3 V 2 V 2 V 2 − − − e e e ag 1 1−V Step ag 1 1−V Step ag 1 VCC = ±15 V Output Volt −01 VGCaiCn == −±115 V Output Volt −01 VGCaiCn == −±51 V Output Volt −01 RCLL == 01.5001 ΩµF − − − VO −2 RF = 2 kΩ VO −2 RF = 2 kΩ VO −2 RL = 150 Ω RL = 150 Ω −3 CL = 1000 pF −3 CL = 1000 pF −3 Gain = 1 −4 −4 −4 0 100 200 300 400 0 100 200 300 400 500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t − Time − ns t − Time − ns t − Time − µs Figure 54 Figure 55 Figure 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 TYPICAL CHARACTERISTICS CAPACITIVE LOAD 1-VOLT STEP RESPONSE 1-VOLT STEP RESPONSE RESPONSE 4 0.8 0.6 3 Gain = −1 0.6 VGCaiCn == 1±15 V 0.4 VGCaiCn == 1±5 V V 2 V 0.4 RF = 200 Ω V RF = 200 Ω e − e − RL = 150 Ω e − 0.2 RL = 150 Ω ag 1 VCC = ±5 V ag 0.2 ag put Volt 0 RCLL == 01.5001 ΩµF put Volt 0.0 put Volt 0.0 − Out −1 − Out −0.2 − Out −0.2 VO −2 VO −0.4 VO −0.4 −3 −0.6 Gain = 1 −4 −0.8 −0.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 0 100 200 300 400 t − Time − µs t − Time − ns t − Time − ns Figure 57 Figure 58 Figure 59 20-VOLT STEP RESPONSE 5-V STEP RESPONSE 15 3 VCC = ±5 V 10 2 VCC = ±15 V Gain = 1 − V Gain = 5 − V RF = 200 Ω age 5 RF = 1.3 kΩ age 1 RL = 150 Ω ut Volt 0 RL = 150 Ω ut Volt 0 p p ut ut − O −5 − O −1 O O V V −10 −2 −15 −3 0 200 400 600 800 1000 0 100 200 300 400 500 t − Time − ns t − Time − ns Figure 60 Figure 61 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION theory of operation The THS404x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f s of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high T slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 62. (7) VCC+ (6) OUT IN− (2) IN+ (3) (4) VCC− NULL (1) NULL (8) Figure 62. THS4041 Simplified Schematic noise calculations and noise figure Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ration (SNR) is very important. The noise model for the THS404x is shown in Figure 63. This model includes all of the noise sources as follows: • e = Amplifier internal voltage noise (nV/√Hz) n • IN+ = Noninverting current noise (pA/√Hz) • IN− = Inverting current noise (pA/√Hz) • e = Thermal voltage noise associated with each resistor (e = 4 kTR ) Rx Rx x POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) eRs en RS Noiseless eni + _ eno IN+ eRf RF IN− eRg RG Figure 63. Noise Model The total equivalent input noise density (e ) is calculated by using the following equation: ni (cid:7) (cid:2) (cid:3)2 (cid:2) (cid:3)2 (cid:2) (cid:2) (cid:3)(cid:3)2 (cid:2) (cid:3) e (cid:1) e (cid:4) IN(cid:4)(cid:5)R (cid:4) IN–(cid:5) R (cid:6)R (cid:4)4kTR (cid:4)4kT R (cid:6)R ni n S F G s F G Where: k = Boltzmann’s constant = 1.380658 × 10−23 T = Temperature in degrees Kelvin (273 +°C) R || R = Parallel resistance of R and R F G F G To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the ni overall amplifier gain (A ). V (cid:2) (cid:3) R e (cid:1)e A (cid:1) e 1(cid:4) F (noninvertingcase) no ni V ni R G As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel G resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares S n method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits Applications Report (literature number SLVA043). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. (cid:9) (cid:11) NF (cid:1) 10log(cid:8)(cid:8) eni2 (cid:8)(cid:8) (cid:10)(cid:2) (cid:3)2(cid:12) e Rs Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: (cid:9) (cid:13) (cid:15)(cid:11) (cid:2) (cid:3)2 (cid:8) (cid:2) (cid:3)2(cid:8) (cid:8)(cid:8) (cid:14) en (cid:4) IN(cid:4)(cid:5)RS (cid:16)(cid:8)(cid:8) (cid:8) (cid:8) NF (cid:1) 10log(cid:8)1(cid:4) (cid:8) (cid:8) 4kTRS (cid:8) (cid:10) (cid:12) Figure 64 shows the noise figure graph for the THS404x. NOISE FIGURE vs SOURCE RESISTANCE 40 f = 10 kHz 35 TA = 25°C 30 B) d 25 e ( gur 20 Fi e s 15 oi N 10 5 0 10 100 1k 10k 100k Source Resistance − Ω Figure 64. Noise Figure vs Source Resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS404x has been internally compensated to maximize its bandwidth and slew rate performance. Typically when the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin, leading to high frequency ringing or oscillations. However, the THS404x has added internal circuitry that senses a capacitive load and adds extra compensation to the internal dominant pole. As the capacitive load increases, the amplifier remains stable. But, it is not uncommon to see a small amount of peaking in the frequency response. There are typically two ways to compensate for this. The first is to simply increase the gain of the amplifier. This helps by increasing the phase margin to keep peaking minimized. The second is to place an isolation resistor in series with the output of the amplifier, as shown in Figure 65. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. For more information about driving capacitive loads, refer to the Output Resistance and Capacitance section of the Parasitic Capacitance in Op Amp Circuits Application Report (literature number: SLOA013). 1.3 kΩ 1.3 kΩ _ Input 20 Ω THS404x Output + CLOAD Figure 65. Driving a Capacitive Load for Extra Stability offset nulling The THS404x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4041. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 66. VCC+ 0.1 µF + THS4041 _ 10 kΩ 0.1 µF VCC− Figure 66. Offset Nulling Schematic 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION offset voltage The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB− RG + − VI VO + RS (cid:2) IIB+ (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) (cid:2) (cid:3) R R VOO(cid:1)VIO 1(cid:4) RF (cid:17)IIB(cid:4)RS 1(cid:4) RF (cid:17)IIB–RF G G Figure 67. Output Offset Voltage Model optimizing unity gain response Internal frequency compensation of the THS404x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 200 Ω should be used as shown in Figure 68. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + THS404x Output _ 200 Ω Figure 68. Noninverting, Unity Gain Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high frequency performance of the THS404x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS404x evaluation board is available to use as a guide for layout or for evaluating the device performance. (cid:1) Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. (cid:1) Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. (cid:1) Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. (cid:1) Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. (cid:1) Surface-mount passive components − Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. general PowerPAD design considerations The THS404x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 69(a) and Figure 69(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 69(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 69. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils) Figure 70. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 70. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS404xDGN IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS404xDGN package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the THS404xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The actual thermal performance achieved with the THS404xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches, then the expected thermal coefficient, θ , is about 58.4(cid:2)C/W. For comparison, the non-PowerPAD version of JA the THS404x IC (SOIC) is shown. For a given θ , the maximum power dissipation is shown in Figure 71 and JA is calculated by the following formula: (cid:2) (cid:3) T –T P (cid:1) MAX A D (cid:1) JA Where: P = Maximum power dissipation of THS404x IC (watts) D T = Absolute maximum junction temperature (150°C) MAX T = Free-ambient air temperature (°C) A θJA = θJC + θCA θ = Thermal coefficient from junction to case (°C/W) JC θ = Thermal coefficient from case to ambient air (°C/W) CA MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 3.5 DGN Package TJ = 150°C θJA = 58.4°C/W 2 oz. Trace And Copper Pad 3 W With Solder on − 2.5 DθJGAN = P 1a5c8k°aCg/eW ati SOIC Package 2 oz. Trace And ssip 2 HθJigAh =-K 9 8T°eCs/tW PCB CWoitphpoeurt PSaodlder Di r e w o 1.5 P m u m 1 xi a M 0.5 SOIC Package Low-K Test PCB θJA = 167°C/W 0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and PCB size = 3”×3” Figure 71. Maximum Power Dissipation vs Free-Air Temperature More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially mutiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 72 to Figure 75 show this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result. When using V = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using V CC CC = ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases and the JA heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4042), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical. THS4041 THS4041 MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT vs vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS A 128000 VTjC C= 1=5 ±05° CV MCuarxriemnut mLi mOuit tLpiunte A 1000 TTAJ == 15500°C°C VCC = ±15 V − m TA = 50°C − m Maximum Output nt 160 nt Current Limit Line Curre 140 Curre θDJAG N = P5a8c.4k°aCg/eW utput 120 θJPAa c<k =a g1e2 0W°Cith/W utput S O 100 S O 100 M M m R 80 θSJOA- 8= P1a6c7k°Cag/We m R SO-8 Package u u m 60 Low-K Test PCB m θJA = 98°C/W axi axi High-K Test PCB − M 40 − M SO-8 Package I||O 20 Safe OApreearating I||O LθoJwA- K= 1Te67s°t CP/CWB Safe OApreearating 0 10 0 1 2 3 4 5 0 3 6 9 12 15 | VO | − RMS Output Voltage − V | VO | − RMS Output Voltage − V Figure 72 Figure 73 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:25) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) THS4042 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 200 Package With Maximum Output A 180 θJA ≤ 60°C/W Current Limit Line m − nt 160 e r ur 140 C put 120 ut O S 100 SO-8 Package M m R 80 θJA = 167°C/W u Low-K Test PCB m 60 xi Safe Operating Area a I− M||O 2400 HSiθgJOhA--8K = P T9ae8cs°ktC aP/gWCeB VTTAJC C == =510 5±°05C° VC Both Channels 0 0 1 2 3 4 5 | VO | − RMS Output Voltage − V Figure 74 THS4042 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 1000 VCC = ±15 V Maximum Output A TJ = 150°C Current Limit Line − m TA = 50°C nt Both Channels e r r u 100 C ut p ut O S M R SO-8 Package um 10 θJA = 98°C/W m High-K Test PCB xi Ma DGN Package SO-8 Package − |O θJA = 58.4°C/W θJA = 167°C/W I| Safe Operating Area Low-K Test PCB 1 0 3 6 9 12 15 | VO | − RMS Output Voltage − V Figure 75 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:25) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8) (cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:13) (cid:14)(cid:11)(cid:3)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18) (cid:2)(cid:19)(cid:20)(cid:2)(cid:11)(cid:3)(cid:21)(cid:18)(cid:18)(cid:22) (cid:15)(cid:12)(cid:21)(cid:17)(cid:19)(cid:23)(cid:19)(cid:18)(cid:24)(cid:3) SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 APPLICATION INFORMATION evaluation board An evaluation board is available for the THS4041 (literature number SLOP219) and THS4042 (literature number SLOP233). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 76. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the THS4041 EVM User’s Guide or the THS4042 EVM User’s Guide. To order the evaluation board, contact your local TI sales office or distributor. VCC+ + C2 C3 6.8 µF 0.1 µF R4 1.3 kΩ NULL IN+ + R5 49.9 Ω R3 THS4041 OUT 49.9 Ω _ NULL R2 C1 1.3 kΩ C4 + 6.8 µF 0.1 µF IN− R1 VCC− 49.9 Ω Figure 76. THS4041 Evaluation Board POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4041CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4041C & no Sb/Br) THS4041CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACO & no Sb/Br) THS4041CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4041C & no Sb/Br) THS4041ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4041I & no Sb/Br) THS4041IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACP & no Sb/Br) THS4042CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4042C & no Sb/Br) THS4042CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4042C & no Sb/Br) THS4042CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM ACC & no Sb/Br) THS4042CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM ACC & no Sb/Br) THS4042ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4042I & no Sb/Br) THS4042IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM ACD & no Sb/Br) THS4042IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM ACD & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4041 : •Automotive: THS4041-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS4041CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4041CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4041IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4042CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4042IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS4041CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4041CDR SOIC D 8 2500 350.0 350.0 43.0 THS4041IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4042CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4042IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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