Not Recommended for New Designs (cid:5)(cid:1)(cid:3) (cid:5)(cid:4)(cid:9)(cid:1)(cid:2) (cid:5)(cid:6)(cid:8)(cid:1)(cid:3) (cid:5)(cid:6)(cid:7)(cid:1)(cid:3) THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER FEATURES DESCRIPTION 1 • Unity-GainBandwidth:1.8GHz The THS3201 is a wideband, high-speed 23 • HighSlewRate:6700V/m s(G=2V/V, current-feedback amplifier, designed to operate over R =100Ω,10-VStep) a wide supply range of ±3.3 V to ±7.5 V for today's L highperformanceapplications. • IMD :–78dBcat20MHz:(G=10V/V, 3 R =100Ω,2-V Envelope) The wide supply range, combined with low distortion L PP and high slew rate, makes the THS3201 ideally • NoiseFigure:11dB(G=10V/V,R =28Ω, G suited for arbitrary waveform driver applications. The RF=255Ω) distortion performance also enables driving • Input-ReferredNoise(f>10MHz) high-resolution and high-sampling rate analog-to-digitalconverters(ADCs). – VoltageNoise:1.65nV/√Hz – NoninvertingCurrentNoise:13.4pA/√Hz Its high voltage operation capabilities make the THS3201 especially suitable for many test, – InvertingCurrentNoise:20pA/√Hz measurement, and ATE applications where lower • OutputDrive:100mA voltage devices do not offer enough voltage swing • Power-SupplyVoltageRange:±3.3Vto±7.5V capability. Output rise and fall times are nearly independent of step size (to first-order APPLICATIONS approximation), making the THS3201 ideal for • TestandMeasurement buffering small to large step pulses with excellent linearityinhighdynamicsystems. • ATE • High-Resolution,High-SamplingRateADC The THS3201 is offered in a 5-pin SOT-23, 8-pin SOIC, and an 8-pin MSOP with PowerPAD™ Drivers packages. • High-Resolution,High-SamplingRateDAC OutputBuffers RELATEDDEVICESANDDESCRIPTIONS DEVICE DESCRIPTION THS3202 ±7.5-V,2-GHzDualLowDistortionCFBAmplifier THS3001 ±15-V,420-MHzLowDistortionCFBAmplifier THS3061/2 ±15-V,300-MHzLowDistortionCFBAmplifier THS3122 ±15-V,DualCFBAmplifierWith350mADrive OPA695 ±5-V,1.7-GHzLowDistortionCFBAmplifier Low-Noise, Low-Distortion, Wideband Application Circuit NONINVERTING SMALL SIGNAL FREQUENCY RESPONSE 50 W Source +7.5 V 8 7 50 W RF = 768 W + 49.9 W dB 6 VI 49.9 W THS3201 ain - 5 _ 50 W ng G 4 verti 3 n -7.5 V Noni 2 GRLa i=n 1=0 20. W , 1 VO = 0.2 VPP. 768 W 768 W VS = ±7.5 V 0 100 k 1 M 10 M 100 M 1 G 10 G NOTE: Power supply decoupling capacitors not shown f - Frequency - Hz 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ABSOLUTE MAXIMUM RATINGS Overoperatingfree-airtemperaturerangeunlessotherwisenoted.(1) UNIT VS Supplyvoltage 16.5V VI Inputvoltage ±VS IO Outputcurrent 175mA VID Differentialinputvoltage ±3V Continuouspowerdissipation SeeDissipationRatingTable TJ Maximumjunctiontemperature(2) +150°C TJ Maximumjunctiontemperature,continuousoperation,longtermreliability(3) +125°C TA Operatingfree-airtemperaturerange –40°Cto+85°C TSTG Storagetemperaturerange –65°Cto+150°C HBM 3000V ESDratings CDM 1500V MM 100V (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. (2) Theabsolutemaximumratingsunderanyconditionislimitedbytheconstraintsofthesiliconprocess.Stressesabovetheseratingsmay causepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmaydegradedevicereliability.Theseare stressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthosespecifiedisnotimplied. (3) Themaximumjunctiontemperatureforcontinuousoperationislimitedbypackageconstraints.Operationabovethistemperaturemay resultinreducedreliabilityand/orlifetimeofthedevice. PACKAGE DISSIPATION RATINGS(1) POWERRATING(3) q q (2) PACKAGE JC JA (TJ=+125°C) (°C/W) (°C/W) TA≤+25°C TA=+85°C DBV(5) 55 255.4 391mW 156mW D(8) 38.3 97.5 1.02W 410mW DGN(8)(1) 4.7 58.4 1.71W 685mW DGK(8pin) 54.2 260 385mW 154mW (1) TheTHS3201mayincorporateaPowerPAD™ontheundersideofthechip.Thisactsasaheatsink andmustbeconnectedtoathermallydissipativeplaneforproperpowerdissipation.Failuretodoso mayresultinexceedingthemaximumjunctiontemperaturewhichcouldpermanentlydamagethe device.SeeTItechnicalbriefsSLMA002andSLMA004formoreinformationaboututilizingthe PowerPADthermallyenhancedpackage. (2) ThisdatawastakenusingtheJEDECstandardHigh-KtestPCB. (3) Powerratingisdeterminedwithajunctiontemperatureof+125°C.Thisisthepointwheredistortion startstosubstantiallyincrease.ThermalmanagementofthefinalPCBshouldstrivetokeepthe junctiontemperatureatorbelow+125°Cforbestperformanceandlongtermreliability. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Dualsupply ±3.3 ±7.5 Supplyvoltage V Singlesupply 6.6 15 T Operatingfree-airtemperaturerange –40 +85 °C A 2 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 PACKAGE/ORDERINGINFORMATION(1) PARTNUMBER PACKAGETYPE PACKAGEMARKING TRANSPORTMEDIA,QUANTITY THS3201D Rails,75 SOIC-8 — THS3201DR TapeandReel,2500 THS3201DBVT TapeandReel,250 SOT-23 BEO THS3201DBVR TapeandReel,3000 THS3201DGN Rails,80 MSOP-8-PP BEN THS3201DGNR TapeandReel,2500 THS3201DGK Rails,80 MSOP-8 BGP THS3201DGKR TapeandReel,2500 (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. PIN ASSIGNMENTS DBVPACKAGE D,DGN,DGKPACKAGES SOT23-5 SOIC-8,MSOP-8 (TOPVIEW) (TOPVIEW) VOUT 1 5 VS+ NC 1 8 NC V V VS- 2 VIINN+- 23 76 VOS+UT- IN+ 3 4 IN- VS- 4 5 NC NC = No internal connection. See Note A. A. If a PowerPAD is used, it is electrically isolatedfromtheactivecircuitry. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: V = ±7.5 V S AtR =768Ω,R =100Ω,andG=+2,unlessotherwisenoted. F L THS3201 TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS MIN/ 0°Cto –40°Cto +25°C +25°C UNITS TYP/ +70°C +85°C MAX ACPERFORMANCE G=+1,RF=1.2kΩ 1.8 GHz Small-signalbandwidth,–3dB G=+2,RF=768Ω 850 Typ (VO=200mVPP) G=+5,RF=619Ω 565 MHz G=+10,RF=487Ω 520 Bandwidthfor0.1dBflatness G=+2,VO=200mVpp 380 MHz Typ Large-signalbandwidth G=+2,VO=2Vpp 880 MHz Typ Slewrate G=+2,VO=5-Vstep,Rise/Fall 5400/4000 V/m s Typ G=+2,VO=10-Vstep,Rise/Fall 9800/6700 Riseandfalltime G=+2,VO=4-Vstep,Rise/Fall 0.7/0.9 ns Typ Settlingtimeto0.1% 20 G=–2,VO=2-Vstep ns Typ Settlingtimeto0.01% 60 Harmonicdistortion 2nd-orderharmonic G=+5,f=10MHz, RL=100Ω –64 dBc Typ 3rd-orderharmonic VO=2Vpp RL=100Ω –73 dBc Typ Third-orderintermodulationdistortion(IMD3) GVO=(en+v1el0op,ef)c==220VpMpHz,Δf=1MHz, –78 dBc Typ Noisefigure G=+10,fc=100MHz,RF=255Ω, 11 dB Typ RG=28 Inputvoltagenoise f>10MHz 1.65 nV/√Hz Typ Inputcurrentnoise(noninverting) 13.4 pA/√Hz Typ f>10MHz Inputcurrentnoise(inverting) 20 pA/√Hz Typ NTSC 0.008% Typ Differentialgain G=+2,RL=150Ω, PAL 0.004% Typ RF=768Ω NTSC 0.007° Typ Differentialphase PAL 0.011° Typ DCPERFORMANCE Open-looptransimpedancegain VO=±1V,RL=1kΩ 300 200 140 120 kΩ Min Inputoffsetvoltage ±0.7 ±3 ±3.8 ±4 mV Max Averageoffsetvoltagedrift ±10 ±13 m V/°C Typ Inputbiascurrent(inverting) ±13 ±60 ±80 ±85 m A Max VCM=0V Averagebiascurrentdrift(–) ±300 ±400 nA/°C Typ Inputbiascurrent(noninverting) ±14 ±35 ±45 ±50 m A Max Averagebiascurrentdrift(+) ±300 ±400 nA/°C Typ 4 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS: V = ±7.5 V (continued) S AtR =768Ω,R =100Ω,andG=+2,unlessotherwisenoted. F L THS3201 TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS MIN/ 0°Cto –40°Cto +25°C +25°C UNITS TYP/ +70°C +85°C MAX INPUT Common-modeinputrange ±5.1 ±5 ±5 ±5 V Min Common-moderejectionratio VCM=±3.75V 71 60 58 58 dB Min Invertinginputimpedance,Zin Openloop 16 Ω Typ Noninverting 780 kΩ Typ Inputresistance Inverting 11 Ω Typ Inputcapacitance Noninverting 1 pF Typ OUTPUT RL=1kΩ ±6 ±5.9 ±5.8 ±5.8 V Min Voltageoutputswing RL=100Ω ±5.8 ±5.7 ±5.5 ±5.5 V Min Currentoutput,sourcing 115 105 100 100 mA Min RL=20Ω Currentoutput,sinking 100 85 80 80 mA Min Closed-loopoutputimpedance G=+1,f=1MHz 0.01 Ω Typ POWERSUPPLY Minimumoperatingvoltage Absoluteminimum ±3.3 ±3.3 ±3.3 V Min Maximumoperatingvoltage Absolutemaximum ±8.25 ±8.25 ±8.25 V Max Maximumquiescentcurrent 14 18 21 21 mA Max Power-supplyrejection(+PSRR) VS+=7Vto8V 69 63 60 60 dB Min Power-supplyrejection(–PSRR) VS–=–7Vto–8V 65 58 55 55 dB Min Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: V = ±5 V S AtR =715Ω,R =100Ω,andG=+2,unlessotherwisenoted. F L THS3201 TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS MIN/ 0°Cto –40°Cto +25°C +25°C UNITS TYP/ +70°C +85°C MAX ACPERFORMANCE G=+1,RF=1.2kΩ 1.3 GHz Small-signalbandwidth,–3dB G=+2,RF=715Ω 725 Typ (VO=200mVPP) G=+5,RF=576Ω 540 MHz G=+10,RF=464Ω 480 Bandwidthfor0.1dBflatness G=+2,VO=200mVPP 170 MHz Typ Large-signalbandwidth G=+2,VO=2VPP 900 MHz Typ Slewrate G=+2,VO=5-Vstep,Rise/Fall 5200/4000 V/m s Typ Riseandfalltime G=+2,VO=4-Vstep,Rise/Fall 0.7/0.9 ns Typ Settlingtimeto0.1% 20 ns Typ G=–2,VO=2-Vstep Settlingtimeto0.01% 60 ns Typ Harmonicdistortion 2nd-orderharmonic G=+5,f=10MHz, RL=100Ω –69 dBc Typ 3rd-orderharmonic VO=2Vpp RL=100Ω –75 dBc Typ Third-orderintermodulationdistortion(IMD3) GVO=(en+v1el0op,ef)c==220VPMPHz,Δf=1MHz, –81 dBc Typ Noisefigure G=+10,fc=100MHz,RF=255Ω, 11 dB Typ RG=28 Inputvoltagenoise f>10MHz 1.65 nV/√Hz Typ Inputcurrentnoise(noninverting) 13.4 pA/√Hz Typ f>10MHz Inputcurrentnoise(inverting) 20 pA/√Hz Typ NTSC 0.006% Typ Differentialgain G=+2,RL=150Ω, PAL 0.004% Typ RF=768Ω NTSC 0.03° Typ Differentialphase PAL 0.04° Typ DCPERFORMANCE Open-looptransimpedancegain VO=+1V,RL=1kΩ 300 200 140 120 kΩ Min Inputoffsetvoltage ±0.7 ±3 ±3.8 ±4 mV Max Averageoffsetvoltagedrift ±10 ±13 ±V/°C Typ Inputbiascurrent(inverting) ±13 ±60 ±80 ±85 m A Max VCM=0V Averagebiascurrentdrift(–) ±300 ±400 nA/°C Typ Inputbiascurrent(noninverting) ±14 ±35 ±45 ±50 m A Max Averagebiascurrentdrift(+) ±300 ±400 nA/°C Typ 6 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 ELECTRICAL CHARACTERISTICS: V = ±5 V (continued) S AtR =715Ω,R =100Ω,andG=+2,unlessotherwisenoted. F L THS3201 TYP OVERTEMPERATURE PARAMETER TESTCONDITIONS MIN/ 0°Cto –40°Cto +25°C +25°C UNITS TYP/ +70°C +85°C MAX INPUT Common-modeinputrange ±2.6 ±2.5 ±2.5 ±2.5 V Min Common-moderejectionratio VCM=±2.5V 71 60 58 58 dB Min Invertinginputimpedance,ZIN Openloop 17.5 Ω Typ Noninverting 780 kΩ Typ Inputresistance Inverting 11 Ω Typ Inputcapacitance Noninverting 1 pF Typ OUTPUT RL=1kΩ ±3.65 ±3.5 ±3.45 ±3.4 Voltageoutputswing V Min RL=100Ω ±3.45 ±3.33 ±3.25 ±3.2 Currentoutput,sourcing 115 105 100 100 mA Min RL=20Ω Currentoutput,sinking 100 85 80 80 mA Min Closed-loopoutputimpedance G=+1,f=1MHz 0.01 Ω Typ POWERSUPPLY Minimumoperatingvoltage Absoluteminimum ±3.3 ±3.3 ±3.3 V Min Maximumoperatingvoltage Absolutemaximum ±8.25 ±8.25 ±8.25 V Max Maximumquiescentcurrent 14 16.8 19 20 mA Max Power-supplyrejection(+PSRR) VS+=4.5Vto5.5V 69 63 60 60 dB Min Power-supplyrejection(–PSRR) VS–=–4.5Vto–5.5V 65 58 55 55 dB Min Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (V = ±7.5 V) S FIGURE Noninvertingsmall-signalfrequencyresponse 1,2 Invertingsmall-signalfrequencyresponse 3 Noninvertinglarge-signalfrequencyresponse 4 Invertinglarge-signalfrequencyresponse 5 0.1dBgainflatnessfrequencyresponse 6 Capacitiveloadfrequencyresponse 7 Recommendedswitchingresistance vsCapacitiveLoad 8 2ndharmonicdistortion vsFrequency 9 3rdharmonicdistortion vsFrequency 10 2ndharmonicdistortion,G=2 vsOutputvoltage 11 3rdharmonicdistortion,G=2 vsOutputvoltage 12 2ndharmonicdistortion,G=5 vsOutputvoltage 13 3rdharmonicdistortion,G=5 vsOutputvoltage 14 2ndharmonicdistortion,G=10 vsOutputvoltage 15 3rdharmonicdistortion,G=10 vsOutputvoltage 16 Third-orderintermodulationdistortion(IMD ) vsFrequency 17 3 S-Parameter vsFrequency 18,19 Inputvoltageandcurrentnoise vsFrequency 20 Noisefigure vsFrequency 21 Transimpedance vsFrequency 22 Inputoffsetvoltage vsCaseTemperature 23 Inputbiasandoffsetcurrent vsCaseTemperature 24 Slewrate vsOutputvoltagestep 25 Settlingtime 26,27 Quiescentcurrent vsSupplyvoltage 28 Outputvoltage vsLoadresistance 29 Rejectionratio vsFrequency 30 Noninvertingsmall-signaltransientresponse 31 Invertinglarge-signaltransientresponse 32 Overdriverecoverytime 33 Differentialgain vsNumberofloads 34 Differentialphase vsNumberofloads 35 Closed-loopoutputimpedance vsFrequency 36 8 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 Table of Graphs (V = ±5 V) S FIGURE Noninvertingsmall-signalfrequencyresponse 37 Invertingsmall-signalfrequencyresponse 38 0.1dBgainflatnessfrequencyresponse 39 2ndharmonicdistortion vsFrequency 40 3rdharmonicdistortion vsFrequency 41 2ndharmonicdistortion,G=2 vsOutputvoltage 42 3rdharmonicdistortion,G=2 vsOutputvoltage 43 2ndharmonicdistortion,G=5 vsOutputvoltage 44 3rdharmonicdistortion,G=5 vsOutputvoltage 45 2ndharmonicdistortion,G=10 vsOutputvoltage 46 3rdharmonicdistortion,G=10 vsOutputvoltage 47 Third-orderintermodulationdistortion(IMD ) vsFrequency 48 3 S-Parameter vsFrequency 49,50 Slewrate vsOutputvoltagestep 51 Noninvertingsmall-signaltransientresponse 52 Invertinglarge-signaltransientresponse 53 Overdriverecoverytime 54 Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com V = ±7.5 V Graphs S NONINVERTINGSMALL-SIGNAL NONINVERTINGSMALL-SIGNAL INVERTINGSMALL-SIGNAL FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 8 24 24 7 RF = 7R6F8 =W 619 W 2202 G = 10, RF = 487 W 2202 G = -10, RF = 499 W Noninverting Gain - dB 23456 GRLa i=n 1=0R 20F. W=, 1 kW Noninverting Gain - dB 11111024682468 RVVOSL === 1±0G07.2 0.=5G V1W V,P=G, RP 5 .=F, R2=, F 1R .=2F 6k=1W 97 6W8 W Noninverting Gain - dB 11111024682468 RVVOSL === 1±007.20.GG5 VW =V=P, P--5.2,, RRFF == 554796 WW 1 VO = 0.2 VPP. 0 0 VS = ±7.5 V -2 -2 G = -1, RF = 619 W 0 -4 -4 100 k 1 M 10 M 100 M 1 G 10 G 100 k 1 M 10 M 100 M 1 G 10 G 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure1. Figure2. Figure3. INVERTINGLARGE-SIGNAL INVERTINGLARGE-SIGNAL 0.1dBGAINFLATNESS FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 16 16 6.4 14 G =-5, RF = 576 W 1124 G =-5, RF = 549 W 6.3 GRRFLa i==n 17=06 208, WW ,, Inverting Gain - dB 1102468 RL = 1G0 0= W2,, RF = 715 W Inverting Gain - dB 1002468 RVVOSL ===G 1± 2=07 V0.-51P W ,PV .R,F = 576 W Noninverting Gain - dB 5566....89126 VVOS == ±07.2.5 V VPP, 2 VO = 2 VPP. -2 5.7 VS = ±7.5 V 0 -4 5.6 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure4. Figure5. Figure6. RECOMMENDEDR 2ndHARMONICDISTORTION ISO CAPACITIVELOAD vs vs FREQUENCYRESPONSE CAPACITIVELOAD FREQUENCY 16 R(ISO) = 30 W , CL = 22 pF 60 Gain = 5, -40 G = 10 Gain - dB 11102468 GRRVSFLa i===n 1±6=071 50.95 WWV RC(LI S=O 5) 0= p2F0 W , Wended -RISO 345000 RRVSFL === 1±601709.5 W WV, monic Distortion - dBc ---765000 RGRRFG =F= =5 = 61 1459949WWW,, RG= 54.9W Vs =±7.5V 4 R(ISO) = 15 W , mm 20 Har -80 Vout= 2VPP 02 CRL(I SC=O L1) =0= 0 42 7p0 F pWF, Reco 10 _+ RISO CL 2nd Order -90 GRF == 2 768W, RG= 768WRL= 100W -2 0 -100 0 100 200 300 400 500 10 100 1 10 100 f - Frequency - MHz CL - Capacitive Load - pF f - Frequency - MHz Figure7. Figure8. Figure9. 10 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 V = ±7.5 V Graphs (continued) S 2ndHARMONICDISTORTION 3rdHARMONICDISTORTION 3rdHARMONICDISTORTION G=2 G=2 vs vs vs FREQUENCY OUTPUTVOLTAGE OUTPUTVOLTAGE -60 -30 -30 3rd Order Harmonic Distortion - dBc -------99887765050505 GRF == 2 GR76F =8= 1W 40, 9R9GW=,GR R7F =G6= 85 =6W 1594.VVRW9osL,W uR==tG ±1=70 =2.05 V1VWP54PW 2nd Order Harmonic Distortion - dBc -1------09876540000000 VGRRsFL = === 2 ±717601.8065MVWWH, zRG8M= H7z684MWHz 2M6H342zMMH1HMzzHz 3rd Order Harmonic Distortion - dBc -1------09876540000000 3VGRR2sFL M= === H2 ±z71760.805VWW1, 6RMGHz=8 M76H8zW4MHz 624MMH1HMzzHz -100 -110 -110 1 10 100 0 1 2 3 4 5 6 0 1 2 3 4 5 6 f - Frequency - MHz Vout-Output Voltage - VPP Vout-Output Voltage - VPP Figure10. Figure11. Figure12. 2ndHARMONICDISTORTION 3rdHARMONICDISTORTION 2ndORDERHARMONICDISTORTION G=5 G=5 G=10 vs vs vs OUTPUTVOLTAGE OUTPUTVOLTAGE OUTPUTVOLTAGE -30 -30 -30 monic Distortion - dBc ----76540000 VGRRsFL = === 5 ±61710.905VWW, RG= 154W 32MHz 64MHz monic Distortion - dBc ----76540000 VGRRsFL = === 5 ±61740.905VWW, RG= 154W 32MHz64MHz monic Distortion - dBc ----76540000 VRRsFL === ±41790.905VWW,,G R =G 1=0 54.9W 32MHz 64MHz 2nd Order Har -1--098000 16MHz 8MHz4MHz 2MHz1MHz 3rd Order Har -1--098000 16MHz8MHz 4MHz 2MHz1MHz 2nd Order Har -1--098000 16MHz 8MHz 4MHz 2MHz 1MHz -110 -110 -110 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Vout-Output Voltage - VPP Vout-Output Voltage - VPP Vout-Output Voltage - VPP Figure13. Figure14. Figure15. 3rdORDERHARMONICDISTORTION 3rdORDERINTERMODULATION G=10 DISTORTION S-PARAMETER vs vs vs OUTPUTVOLTAGE FREQUENCY FREQUENCY -30 -40 0 3rd Order Harmonic Distortion - dBc -1------09876540000000 VGRRsFL = === 1 ±410790.905VWW,1 6RMGH=z8 5M4H.9zW4MH3z2MH2zMH6z41MMHHzz d Order Intermodulation Distortion - dBc -----9758600000 VVRsoL u==tGR ±1F=270 .02=5WV V7P6P8W, RGRGRGF1F50=== 74 6691899WWW, ,R RGG== 5 145.94WW S-Parameter - dB ----86420000 VGCSS a=2 i=n 20 ±= p7 F+.51 0V 5S0o RuWGrceS151+R-0 FW 5S5001 CW 2W -110 3r -100 -100 0 1 2 3 4 5 6 10 20 30 40 50 60 70 80 90 100 1 M 10 M 100 M 1 G 10 G Vout-Output Voltage - VPP f - Frequency - MHz f - Frequency - Hz Figure16. Figure17. Figure18. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com V = ±7.5 V Graphs (continued) S INPUTVOLTAGEAND S-PARAMETER CURRENTNOISE NOISEFIGURE vs vs vs FREQUENCY FREQUENCY FREQUENCY 0 50 4 14 VGCS a= i=n 3 ±=.37 +.p51F 0V pAHz 45 VTAS == 2±57°.C5 V and ±5 V 3.5 Hz 13 -20 y - 40 3 nV/ 12 S-Parameter - dB-1---08640000 SS1212 5S0o RuWGrce 5+R-0F W 5S5001 CW 2W Input Current Noise DensitI-n 112233050505100 k 1 M NCVounINnrnroiveniensvretet1 i Nrn0Ctigo nuMigsrreent 100 M0012...555 Voltage Noise Density - V-n Noise Figure - dB 11067891 GRRVSGFa i ==n= ±2=257 8+5. 51W W0V & ±5 V 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz 0 50 100 150 200 250 300 350 400 f - Frequency - Hz f - Frequency - MHz Figure19. Figure20. Figure21. TRANSIMPEDANCE INPUTOFFSETVOLTAGE INPUTBIASANDOFFSETCURRENT vs vs vs FREQUENCY CASETEMPERATURE CASETEMPERATURE 120 3 17 7 VS = ±5 and ±7.5V VS = ±7.5 V 100 2.5 A 16 6 A WTransimpedance Gain -dB 24680000 1_+0 W _+ Gain(cid:1)(cid:1)VIIBO - Input Offset Voltage - mVVOS 01..5512 VS = ±V7.S5 =V ±5 V m- Input Bias Currents -IIB 1111112345 IOS IIB- IIB+ 12345 mI- Input Offset Currents -OS 0 0 10 0 100 k 1 M 10 M 100 M 1 G -40-30-20-10 0 102030405060708090 -40-30-20-10 0 10 2030 4050 60708090 f - Frequency - Hz TC - Case Temperature - °C TC - Case Temperature - °C Figure22. Figure23. Figure24. SLEWRATE vs OUTPUTVOLTAGE SETTLINGTIME SETTLINGTIME 10000 1.5 3 9000 Rising Edge 2.5 Rising Edge 1 2 8000 mSR- V/s- Slew Rate± 46357000000000000000 SR+ SR- - Output Voltage - VVO-00..550 FallGRRfVi=nSLFa g1 i=== n EM 1=±5dH077 g-06.z2e5 W WV - Output Voltage - VVO--1001-....5515501 GRRfV=SLFa 1 i===n M 1=±5H077 -06.z25 W WV 2000 -1 -2 Falling Edge 1000 -2.5 0 -1.5 -3 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 0 2.5 5 7.5 10 12.5 Vout-Output Voltage - Vstep t - Time - ns t - Time - ns Figure25. Figure26. Figure27. 12 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 V = ±7.5 V Graphs (continued) S QUIESCENTCURRENT OUTPUTVOLTAGE REJECTIONRATIO vs vs vs SUPPLYVOLTAGE LOADRESISTANCE FREQUENCY 20 7 80 18 TA = 85°C 56 70 VS = ±7.5 V 16 4 Quiescent Current - mA 11102468 TA =T A2 5=° C-40°C - Output Voltage - VVO ----43210123 VTAS == -±470. 5to V 85°C Rejection Ratios - dB 2345600000 PSRR+ CMRR 4 -5 10 2 -6 0 -7 0 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 10 100 1000 100 k 1 M 10 M 100 M VS - Supply Voltage - ±V RL - Load Resistance - W f - Frequency - Hz Figure28. Figure29. Figure30. NONINVERTINGSMALL-SIGNAL INVERTINGLARGE-SIGNAL TRANSIENTRESPONSE TRANSIENTRESPONSE OVERDRIVERECOVERYTIME 0.3 6 10 5 - Output Voltage - VVO-000...1120 GRRVSLFa i===n 71±=1O07 I250.nu5 pWtW puVutt - Output Voltage - VVO ---321012345 GRRVSLFa i===n 51=±407 I-90.n55 pWW uVt - Output Voltage - VVO--4202468 GRVSF = == 2 ±7,678.5 WV, --0123421 - Input Voltage - VVI -6 -3 -0.2 -4 Output -5 -8 -4 -0.3 -6 -10 -5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.2 0.4 0.6 0.8 1 t - Time - m s t - Time - m s t - Time - m s Figure31. Figure32. Figure33. DIFFERENTIALGAIN DIFFERENTIALPHASE CLOSED-LOOPOUTPUTIMPEDANCE vs vs vs NUMBEROFLOADS NUMBEROFLOADS FREQUENCY 0.030 0.040 1000 Gain = 2 Gain = 2 Gain = 2 Differential Gain - % 0000....000011220505 RV4W0SFo Ir==Rs t±7E C67 -8.a 5N s WVeT S±C10 a0n IdR PEa RlamNPTpASLC °Differential Phase - 000000......000000112233050505 RV4W0SFo Ir==Rs t±E7 C76 -.8a 5N s kVeTW S±C10 a0n IdRP PAEaL RlNamTSpC Wd-Loop Output Impedance - 1001.0101 RRVSFL === 1±701705.5 W WV e 0.005 0.005 Clos 0.01 0 0 0.001 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 100 k 1 M 10 M 1 M 1 G Number of Loads - 150 W Number of Loads - 150 W f - Frequency - Hz Figure34. Figure35. Figure36. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com V = ±5 V Graphs S NONINVERTINGSMALL-SIGNAL INVERTINGSMALL-SIGNAL 0.1dBGAINFLATNESS FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 24 24 6.4 2202 G = 10, RF = 464 W 2202 G = -10, RF = 499 W 6.3 GRFa i=n 7=1 25, W , Noninverting Gain - dB 11111024682468 RVVOSL === 1±0G05.2 0 =VG V1W ,P=G, RP 5 .=F, R2=, F 1R .=2F 5k=7W 67 1W5 W Inverting Gain - dB 11111024682468 RVVOSL === G1±005. 2=0 GV V-W 2=P,, P -R5.,F R =F 5 =7 65 4W9 W Noninverting Gain - dB 5566....89126 RVVOSL === 1±005.20 V VW P,P, 0 0 5.7 -2 -2 G =-1, RF = 576 W -4 -4 5.6 100 k 1 M 10 M 100 M 1 G 10 G 100 k 1 M 10 M 100 M 1 G 10 G 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure37. Figure38. Figure39. 2ndORDERHARMONICDISTORTION 2ndHARMONICDISTORTION 3rdORDERHARMONICDISTORTION G=2 vs vs vs FREQUENCY FREQUENCY OUTPUTVOLTAGE -40 -60 -30 G = 10 Vs =±5V 2nd Order Harmonic Distortion - dBc -----9876500000 RGRFG == =5 51RGR74F6F3 ==WW= 2 , 476145WW,, RRGG== 5711.51VVRWWsoL u==t ±1=50 2V0VWPP 3rd Order Harmonic Distortion - dBc -------99887765050505 GRGRF =F == 2= 17 401654WW, ,R RGGGR== F 7= 51= 515 5.1W76WWVVR,osL R u==tG ±1=5=0 2V 01V4WP3PW 2nd Order Harmonic Distortion - dBc -1------09876540000000 GRR3FL2 =M == 2H 71z101506MWWH, zRG =8 M71H5zW644MMHHzz2MH1zMHz -100 -100 -110 1 10 100 1 10 100 0 1 2 3 4 5 6 f - Frequency - MHz f - Frequency - MHz Vout-Output Voltage - VPP Figure40. Figure41. Figure42. 3rdORDERHARMONIC 2ndORDERHARMONIC 3rdORDERHARMONIC DISTORTION,G=2 DISTORTION,G=5 DISTORTION,G=5 vs vs vs OUTPUTVOLTAGE OUTPUTVOLTAGE OUTPUTVOLTAGE -30 -30 -30 monic Distortion - dBc ----76540000 VGRR3sFL2 = M=== 2H ±71z510V50WW, RG= 715W64MHz 1MHz monic Distortion - dBc ----76540000 32VGRRMsFL =H === z5 ±51570V60WW, RG= 143W 64MHz monic Distortion - dBc ----76540000 VGRR3sFL =2 =M== 5 H±515z70V60WW, RG= 143W 64MHz1MHz 3rd Order Har -1--098000 16MHz8MHz 4MHz 2MHz 2nd Order Har -1--098000 16MHz 8MHz 4MHz 2MH1zMHz 3rd Order Har -1--098000 16MHz8MHz 4MHz 2MHz -110 -110 -110 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Vout-Output Voltage - VPP Vout-Output Voltage - VPP Vout-Output Voltage - VPP Figure43. Figure44. Figure45. 14 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 V = ±5 V Graphs (continued) S 2ndORDERHARMONIC 3rdORDERHARMONIC 3rdORDERINTERMODULATION DISTORTION,G=10 DISTORTION,G=10 DISTORTION vs vs vs OUTPUTVOLTAGE OUTPUTVOLTAGE FREQUENCY -30 -30 -50 2nd Order Harmonic Distortion - dBc -1------09876540000000 VRRsFL === ±41560V401,6WWGM, H=R zG10= 581M.H1zW 342MMHHzz2M64H1MzMHHzz 3rd Order Harmonic Distortion - dBc -1------09876540000000 VGRRsFL = 3=== 21 M±410560HV40zWW,1 6RMGH=z 581M.1HzW 4M6H4zMHz2M1HMzHz d Order Intermodulation Distortion - dBc ---------998776586505500505 VVRsoL u==t ±1=50 V02WVPPGRRFG10==GR 45F2614.=1 W7W1,5W,GRR RFG5G=== 51 7746135WWW, -110 -110 3r -100 0 1 2 3 4 5 6 0 1 2 3 4 5 6 10 20 30 40 50 60 70 80 90 100 Vout-Output Voltage - VPP Vout-Output Voltage - VPP f - Frequency - MHz Figure46. Figure47. Figure48. S-PARAMETER S-PARAMETER SLEWRATE vs vs vs FREQUENCY FREQUENCY OUTPUTVOLTAGE 0 0 6000 VS = ±5 V VS = ±5 V Gain = +10 Gain = +10 C = 0 pF -20 C = 3.3 pF 5000 -20 S-Parameter - dB --6400 SS1212 RG RFS12 C S-Parameter - dB --6400 SS1212 RG RF S12C mR- V/s- Slew Rate± 234000000000 SSRR+- -80 +- 50 W -80 +- 50 W S 1000 50 W 50 W 50 W 50 W 50 W 50 W Source Source -100 -100 0 1 M 10 M 100 M 1 G 10 G 1 M 10 M 100 M 1 G 10 G 1 2 3 4 5 f - Frequency - Hz f - Frequency - Hz Vout-Output Voltage - Vstep Figure49. Figure50. Figure51. NONINVERTINGSMALL-SIGNAL INVERTINGLARGE-SIGNAL TRANSIENTRESPONSE TRANSIENTRESPONSE OVERDRIVERECOVERYTIME 0.3 3 6 3 2.5 G = 2, 0.2 Output 2 GRLa i=n 1=0 -05 W 4 RVSF == ±7155 V W , 2 - Output Voltage - VVO--000...2110 GRRVSLFa i===n 71±=105 I25n0 V p WWut - Output Voltage - VVO--1001--....55215501 RVSF == 5I±On45pu9 uVt pWtut - Output Voltage - VVO--4202 --0121 - Input Voltage - VVI -2.5 -0.3 -3 -6 -3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.2 0.4 0.6 0.8 1 t - Time - m s t - Time -m s t - Time - m s Figure52. Figure53. Figure54. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com APPLICATION INFORMATION WIDEBAND, NONINVERTING OPERATION Table1.RecommendedResistorValuesfor OptimumFrequencyResponse The THS3201 is a unity-gain stable, 1.8-GHz current-feedback operational amplifier, designed to THS3201RFforACWhenRLOAD=100Ω operatefroma±3.3-Vto±7.5-Vpowersupply. Gain SupplyVoltage R R G F (V/V) (V) (Ω) (Ω) Figure 55 shows the THS3201 in a noninverting gain ±7.5 — 1.2k of 2-V/V configuration typically used to generate the 1 ±5 — 1.2k performance curves. Most of the curves were characterized using signal sources with 50-Ω source ±7.5 768 768 2 impedance, and with measurement equipment ±5 715 715 presenting a 50-Ω load impedance. The 49.9-Ω shunt ±7.5 154.9 619 resistor at the V terminal in Figure 55 matches the 5 I ±5 143 576 sourceimpedanceofthetestgenerator. ±7.5 54.9 487 10 7.5 V +VS ±5 51.1 464 ±7.5 619 619 + –1 ±5 576 576 50 W Source 100 pF 0.1 mF 6.8 mF –2 ±7.5and±5 287 576 + –5 ±7.5and±5 110 549 VI 49.9 W 49.9 W _THS3201 –10 ±7.5and±5 49.9 499 50 W RF WIDEBAND, INVERTING GAIN OPERATION 768 W 768 W RG Figure 56 shows the THS3201 in a typical inverting 0.1 mF 6.8 mF gain configuration where the input and output 100 pF + impedances and signal gain from Figure 55 are retainedinaninvertingcircuitconfiguration. -VS -7.5 V 7.5 V+VS Figure55.Wideband,Noninverting GainConfiguration + 100 pF 0.1 mF 6.8 mF Unlike voltage-feedback amplifiers, current-feedback + amplifiers are highly dependent on the feedback 49.9 W THS3201 resistor R for maximum performance and stability. _ F Table 1 shows the optimal gain setting resistors R 50 W F and RG at different gains to give maximum bandwidth 50 W Source RG RF with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense VI 287 W 576 W of added peaking in the frequency response, by using RM 0.1 mF 6.8 mF 60.4 W even lower values for R . Conversely, increasing R F F 100 pF + decreasesthebandwidth,butstabilityisimproved. -7.5 V -VS Figure56.Wideband,InvertingGain Configuration 16 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 SINGLE-SUPPLY OPERATION 768 W 768 W The THS3201 has the capability to operate from a single supply voltage ranging from 6.6 V to 15 V. ±7.5 V 75 W 75-W Transmission Line VO(1) When operating from a single power supply, care - THS3201 mustbetakento ensure the input signal and amplifier VI + are biased appropriately to allow for the maximum ±7.5 V 75 W output voltage swing. The circuits shown in Figure 57 75 W n Lines demonstrate methods to configure an amplifier in a 75 W VO(n) mannerconduciveforsingle-supplyoperation. +VS 75 W 50 W Source + 49.9 W Figure58.VideoDistributionAmplifier VI RT 49.9 W _THS3201 Application 50 W +V2S RF ADC DRIVER APPLICATION 768 W The THS3201 can be used as a high-performance RG 768 W ADC driver in applications like radio receiver IF stages, and test and measurement devices. All +VS high-performance ADCs have differential inputs. The 2 RF THS3201 can be used in conjunction with a transformer as a drive amplifier in these applications. 576 W Figure 59 and Figure 60 show two different VS 50 W Source approaches. RG _ 49.9 W In Figure 59, a transformer is used after the amplifier VI 287 W THS3201 to convert the signal to differential. The advantage of 60.4 W RT + this approach is fewer components are required. 50 W R and R are required for impedance matching +VS +VS OUT T 2 2 thetransformer. Figure57.DC-CoupledSingle-SupplyOperation VS+ 0.1 mF VIDEO HDTV DRIVERS RG RF The exceptional bandwidth and slew rate of the THS3201 matches the demands for professional video and HDTV. Most commercial HDTV standards ROUT 1:n 24.9 W THS3201 requires a video passband of 30-MHz. To ensure VIN RT 47pF ADC high signal quality with minimal degradation of 24.9 W performance, a 0.1-dB gain flatness should be at VS- CM 47pF least 7x the passband frequency to minimize group delay variations—requiring 210-MHz 0.1-dB 0.1 mF frequency flatness from the amplifier. High slew rates 0.1 mF ensure there is minimal distortion of the video signal. Component video and RGB video signals require fast Figure59.DifferentialADCDriverCircuit1 transition times and fast settling times to keep a high signal quality. The THS8135, for example, is a In Figure 60, a transformer is used before two 240-MSPS video digital-to-analog converter (DAC) amplifiers to convert the signal to differential. The two and has a transition time approaching 4 ns. The amplifiers then amplify the differential signal. The THS3201 is a perfect candidate for interfacing the advantage to this approach is each amplifier is outputofsuchhigh-performancevideocomponents. required to drive half the voltage as before. R is T usedtoimpedancematchthetransformer. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com Typically, a low value resistor in the range of 10 Ω to VS+ 100 Ω provides the required isolation. Together, the R and C form a real pole in the s-plane located at the 0.1 mF frequency: RG RF fP(cid:1)2(cid:1)1RC Placing this pole at about 10x the highest frequency 24.9 W VIN 1:n THS3201 of interest ensures it has no impact on the signal. 47pF Since the resistor is typically a small value, it is very RT ADC bad practice to place the pole at (or very near) 24.9 W CM frequencies of interest. At the pole frequency, the RG THS3201 amplifiersseesaloadwithamagnitudeof: 47pF RF (cid:1)2xR If R is only 10 Ω, the amplifier is very heavily loaded 0.1 mF VS- above the pole frequency, and generates excessive distortion. 0.1 mF DAC DRIVER APPLICATION Figure60.DifferentialADCDriverCircuit2 The THS3201 can be used as a high-performance DACoutputdriverinapplicationslikeradiotransmitter It is almost universally recommended to use a stages and arbitrary waveform generators. All resistor and capacitor between the op amp output high-performance DACs have differential current andtheADCinputasshowninbothfigures. outputs. Two THS3201s can be used as a differential This resistor-capacitor (RC) combination has multiple drive amplifier in these applications, as shown in functions: Figure61. • ThecapacitorisalocalchargereservoirforADC R on the DAC output is used to convert the output PU • TheresistorisolatestheamplifierfromtheADC current to voltage. The 24.9-Ω resistor and 47-pF • Inconjunction,theyformalow-passnoisefilter capacitor between each DAC output and the op amp input is used to reduce the images generated at During the sampling phase, current is required to multiples of the sampling rate. The values shown chargetheADCinputsamplingcapacitors.Byplacing form a pole at 136 MHz. R sets the output OUT external capacitors directly at the input pins, most of impedanceofeachamplifier. the current is drawn from them. They are seen as a very low impedance source. They can be thought of VS+ as serving much the same purpose as a power-supply bypass capacitor to supply transient 00..11 mFmF current, with the amplifier then providing the bulk AVDD charge. RG RF Ttoyp1ic0a0llyp,Fa lporwo-vviadleuse cthaeparceitqouririnedthetrarannsigeentofc1h0arpgFe RPU 24.9 W THS3201 ROUT VOUT1 reservoir. IOUT1 DAC 47pF The capacitance and the switching action of the ADC 24.9 W is one of the worst loading scenarios that a IOUT2 ROUT high-speed amplifier encounters. The resistor 47pF THS3201 VOUT2 provides a simple means of isolating the associated RPU RG RF phase shift from the feedback network and maintainingthephasemarginoftheamplifier. AVDD VS- 0.1 mF Figure61.DifferentialDACDriverCircuit 18 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 PRINTED CIRCUIT BOARD LAYOUT with a low parasitic capacitance shunting the TECHNIQUES FOR OPTIMAL external resistors, excessively high resistor values PERFORMANCE can create significant time constants that can degrade performance. Good axial metal-film or Achieving optimum performance with high frequency surface-mount resistors have approximately amplifier-like devices in the THS3201 requires careful 0.2pF in shunt with the resistor. For resistor attention to board layout parasitic and external values >2.0kΩ this parasitic capacitance can add componenttypes. a pole and/or a zero that can affect circuit Recommendationsthatoptimizeperformanceinclude: operation. Keep resistor values as low as • Minimize parasitic capacitance to any power or possible, consistent with load driving considerations. ground plane for the negative input and output pins by voiding the area directly below these pins • Connections to other wideband devices on the and connecting traces and the feedback path. board may be made with short direct traces or Parasitic capacitance on the output and negative through onboard transmission lines. For short input pins can cause instability. To reduce connections, consider the trace and the input to unwanted capacitance, a window around the the next device as a lumped capacitive load. signal I/O pins should be opened in all of the Relatively wide traces (50mils to 100 mils) should ground and power planes around those pins and be used, preferably with ground and power planes the feedback path. Otherwise, ground and power opened up around them. Estimate the total planes should be unbroken elsewhere on the capacitive load and determine if isolation resistors board. on the outputs are necessary. Low parasitic • Minimize the distance (<0.25") from the capacitive loads (< 4 pF) may not need an RS power-supply pins to high frequency 0.1-m F and since the THS3201 is nominally compensated to operatewith a 2-pF parasitic load. Higher parasitic 100 pF decoupling capacitors. At the device pins, capacitive loads without an R are allowed as the the ground and power-plane layout should not be S signal gain increases (increasing the unloaded in close proximity to the signal I/O pins. Avoid phase margin). If a long trace is required, and the narrow power and ground traces to minimize 6-dB signal loss intrinsic to a doubly-terminated inductance between the pins and the decoupling transmission line is acceptable, implement a capacitors. The power-supply connections should matched impedance transmission line using always be decoupled with these capacitors. Larger (6.8 m F or more) tantalum decoupling microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout capacitors, effective at lower frequency, should techniques). also be used on the main supply pins. These may be placed somewhat farther from the device and • A 50-Ω environment is not necessary onboard, may be shared among several devices in the and in fact, a higher impedance environment same area of the printed circuit board (PCB). The improves distortion as shown in the distortion primary goal is to minimize the impedance seen in versus load plots. With a characteristic board the differential-current return paths. For driving trace impedance based on board material and differential loads with the THS3201, adding a trace dimensions, a matching series resistor into capacitor between the power-supply pins the trace from the output of the THS3201 is used improves 2nd order harmonic distortion as well as a terminating shunt resistor at the input performance. This also minimizes the current loop ofthedestinationdevice. formedbythedifferentialdrive. Remember also that the terminating impedance is • Careful selection and placement of external the parallel combination of the shunt resistor and components preserve the high-frequency the input impedance of the destination device: this performance of the THS3201. Resistors should be total effective impedance should be set to match a very low reactance type. Surface-mount the trace impedance. If the 6-dB attenuation of a resistors work best and allow a tighter overall doubly-terminated transmission line is layout. Again, keep their leads and PCB trace un-acceptable, a long trace can be length as short as possible. Never use wirebound series-terminated at the source end only. Treat type resistors in a high frequency application. the trace as a capacitive load in this case. This Since the output pin and inverting input pins are does not preserve signal integrity as well as a themostsensitivetoparasitic capacitance, always doubly-terminated line. If the input impedance of position the feedback and series output resistors, the destination device is low, there is some signal if any, as close as possible to the inverting input attenuation due to the voltage divider formed by pins and output pins. Other network components, theseriesoutputintotheterminatingimpedance. such as input termination resistors, should be space placed close to the gain-setting resistors. Even space Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com • Socketing a high-speed part like the THS3201 is not recommended. The additional lead length and 0.205 pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic 0.060 0.017 network which can make it almost impossible to achieve a smooth, stable frequency response. Pin 1 0.013 Best results are obtained by soldering the THS3201partsdirectlyontotheboard. 0.030 0.075 0.025 0.094 PowerPAD DESIGN CONSIDERATIONS The THS3201 is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which 0.035 0.040 0.010 the die is mounted [see Figure 62(a) and vias Figure 62(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the Top View undersideofthe package [see Figure 62(c)]. Because Figure63.DGNPowerPADPCBEtchand this thermal pad has direct thermal contact with the ViaPattern die, excellent thermal performance can be achieved by providing a good thermal path away from the thermalpad. PowerPAD PCB LAYOUT CONSIDERATIONS The PowerPAD package allows for both assembly and thermal management in one manufacturing 1. Prepare the PCB with a top side etch pattern as operation. During the surface-mount solder operation shown in Figure 63. There should be etch for the (when the leads are being soldered), the thermal pad leadsaswellasetchforthethermalpad. canalsobesolderedtoacopperareaunderneath the 2. Place five holes in the area of the thermal pad. package. Through the use of thermal paths within this These holes should be 10 mils in diameter. Keep copper area, heat can be conducted away from the them small so that solder wicking through the package into either a ground plane or other heat holesisnotaproblemduringreflow. dissipatingdevice. 3. Additional vias may be placed anywhere along The PowerPAD package represents a breakthrough the thermal plane outside of the thermal pad in combining the small area and ease of assembly of area. This helps dissipate the heat generated by surface-mount with the, heretofore, awkward the THS3201 IC. These additional vias may be mechanicalmethodsofheatsinking. larger than the 10-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be DIE solderedsothatwickingisnotaproblem. Side View (a) Thermal 4. Connectallholestotheinternalgroundplane. Pad 5. When connecting these holes to the ground DIE plane, do not use the typical web or spoke via End View (b) connection methodology. Web connections have Bottom View (c) a high thermal resistance connection that is Figure62.ViewsofThermally-EnhancedPackage useful for slowing the heat transfer during soldering operations. This makes the soldering of Although there are many ways to properly heatsink vias that have plane connections easier. In this the PowerPAD package, the following steps illustrate application, however, low thermal resistance is therecommendedapproach. desired for the most efficient heat transfer. Therefore, the holes under the THS3201 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumferenceoftheplated-throughhole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from 20 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 being pulled away from the thermal pad area For systems where heat dissipation is more critical, duringthereflowprocess. the THS3201 is offered in an 8-pin MSOP with 7. Apply solder paste to the exposed thermal pad PowerPAD and also available in the SOIC-8 areaandalloftheICterminals. PowerPAD package, offering even better thermal performance. The thermal coefficients for the 8. With these preparatory steps in place, the IC is PowerPAD packages are substantially improved over simply placed in position and run through the the traditional SOIC. Maximum power dissipation solder reflow operation as any standard levels are depicted in the graph for the available surface-mount component. This results in a part packages. The data for the PowerPAD packages thatisproperlyinstalled. assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in POWER DISSIPATION AND THERMAL the PowerPAD application note number SLMA002. CONSIDERATIONS The following graph also illustrates the effect of not To maintain maximum output capabilities, the soldering the PowerPAD to a PCB. The thermal THS3201 does not incorporate automatic thermal impedance increases substantially which may cause shutoff protection. The designer must take care to serious heat and performance issues. Be sure to ensure that the design does not violate the absolute always solder the PowerPAD to the PCB for optimum maximum junction temperature of the device. Failure performance. may result if the absolute maximum junction 4.0 tpeemrfpoermraatunrcee, ofde+si1g5n0°Cforisaexmceaexdimedu.mFojurncbteiosnt n - W 3.5 TJ = 125°C temperature of +125°C. Between +125°C and o +150°C, damage does not occur, but the pati 3.0 q JA = 58.4°C/W pTehrefotrhmearmncael cohfathraecatemripstliifciesrobfetghiensdetovidceegarareded.ictated ower Dissi 22..05 q JA = 98°C/W P by the package and the PCB. Maximum power m 1.5 u dissipation for a given package can be calculated m xi 1.0 usingthefollowingformula. Ma T -T - D 0.5 P = Max A P q JA = 158°C/W DMax q 0.0 -40 -20 0 20 40 60 80 100 JA TA - Free-Air Temperature - °C Where: • P isthemaximumpowerdissipationinthe Results are With No Air Flow and PCB Size = 3”x3” amDMpalxifier(W) q JA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN) • TMaxistheabsolutemaximumjunction qq JJAA == 19588°C°C/W/W f ofor r8 8-P-Pinin S MOSICO HPi gwh/P Toewste rPPCaBd (wD/)o Solder temperature(°C) • T istheambienttemperature(°C) Figure64.MaximumPowerDissipation A vsAmbientTemperature • q =q +q JA JC CA • q isthethermalcoefficientfromthesilicon JC junctionstothecase(°C/W) When determining whether or not the device satisfies • q isthethermalcoefficientfromthecasetothe the maximum power dissipation requirement, it is CA important to not only consider quiescent power ambientair(°C/W) dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com DESIGN TOOLS PD J9* EvaluationFixture,SpiceModels,and ApplicationsSupport C8* R5 Texas Instruments is committed to providing its customers with the highest quality of applications Vs+ 768 W support. To support this goal an evaluation board has 7 8 R3 U1 been developed for the THS3201 operational J1 2 _ R6 amplifier. The board is easy to use, allowing for Vin- 768 W 3 + 6 J4 straightforward evaluation of the device. The 0 W R2 49.9 W R7 Vout evaluation board can be ordered through the Texas 4 1 Not Populated Instruments web site at www.ti.com, or through your Vs- J8* local Texas Instruments sales representative. The PD Ref schematic diagram, board layers, and bill of materials J2 oftheevaluationboardsareprovidedbelow. Vin+ C7* 49.9 W R4 *Does Not Apply to the THS3201 J6 GND TP1 J7 J5 VS- VS- VS+ VS+ FB1 FB2 + C1 C6 C5 C4 C3 C2 + 22 mF 0.1 mF 100 pF 100 pF 0.1 mF 22 mF Figure65.THS3201EVMCircuitConfiguration 22 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 Figure66.THS3201EVMBoardLayout Figure68.THS3201EVMBoardLayout (TopLayer) (ThirdLayer,Power) Figure67.THS3201EVMBoardLayout Figure69.THS3201EVMBoardLayout (SecondLayer,Ground) (BottomLayer) Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com Table2.BillofMaterials(1) THS3201DGNEVM PCB MANUFACTURER'S ITEM DESCRIPTION SMDSIZE REFDES QUANTITY PARTNUMBER 1 Bead,ferrite,3A,80Ω 1206 FB1,FB2 2 (Steward)HI1206N800R-00 2 Cap,22m F,tanatalum,25V,10% D C1,C2 2 (AVX)TAJD226K025R 3 Cap,100pF,ceramic,5%,150V AQ12 C4,C5 2 (AVX)AQ12EM101JAJME 4 Cap,0.1m F,ceramic,X7R,50V 0805 C3,C6 2 (AVX)08055C104KAT2A 6 Open 0805 R7 1 7 Resistor,49.9Ω,1/8W,1% 0805 R6 1 (Phycomp)9C08052A49R9FKHFT 9 Resistor,768Ω,1/8W,1% 0805 R3,R5 2 (Phycomp)9C08052A7680FKHFT 10 Open 1206 C7,C8 2 11 Resistor,0Ω,1/4W,1% 1206 R2 1 (KOA)RK73Z2BLTD 12 Resistor,49.9Ω,1/4W,1% 1206 R4 1 (Phycomp)9C12063A49R9FKRFT 13 Testpoint,black TP1 1 (Keystone)5001 14 Open J8,J9 2 15 Jack,BananaReceptance,0.25”dia.hole J5,J6,J7 3 (HHSmith)101 16 Connector,edge,SMAPCBjack J1,J2,J4 3 (Johnson)142-0701-801 17 Standoff,4-40hex,0.625”length 4 (Keystone)1804 18 Screw,Phillips,4-40,.250” 4 SHR-0440-016-SN 19 IC,THS3201 U1 1 (TI)THS3201DGN 20 Board,printedcircuit 1 (TI)Edge#6447972Rev.A (1) ThecomponentsshownintheBOMwereusedintestbyTI. blankspace Computer simulation of circuit performance using ADDITIONAL REFERENCE MATERIAL SPICE is often useful when analyzing the • PowerPAD Made Easy, application brief performance of analog circuits and systems. This is (SLMA004) particularly true for video and R -amplifier circuits F • PowerPAD Thermally Enhanced Package, where parasitic capacitance and inductance can have technicalbrief(SLMA002) a major effect on circuit performance. A SPICE model for the THS3201 family of devices is available • Voltage Feedback vs Current-Feedback Amplifiers throughtheTexasInstrumentsweb site (www.ti.com). (SLVA051) The Product Information Center (PIC) is available for • Current-Feedback Analysis and Compensation design assistance and detailed product information. (SLOA021) These models do a good job of predicting • Current-Feedback Amplifiers: Review, Stability, small-signal ac and transient performance under a andApplication(SBOA081) wide variety of operating conditions. They are not • Effect of Parasitic Capacitance in Op Amp Circuits intended to model the distortion characteristics of the (SLOA013) amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and isnotmodelediscontainedinthemodelfileitself. 24 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 www.ti.com............................................................................................................................................................. SLOS416C–JUNE2003–REVISEDJUNE2009 EVMWARNINGSANDRESTRICTIONS ItisimportanttooperatethisEVMwithintheinputvoltageandtheoutputvoltagerangesasspecifiedinthetablebelow. InputRange,V 6.6V(±3.3V)to16.5V(±8.25V) S InputRange,V NOTTOEXCEED:Power-SupplyVoltageApplied I OutputRange,V NOTTOEXCEED:Power-SupplyVoltageApplied O Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamagetotheEVM.Iftherearequestions concerningtheinputrange,pleasecontactaTIfieldrepresentativepriortoconnectingtheinputpower. Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/orpossiblepermanentdamagetotheEVM. PleaseconsulttheEVMUser'sGuidepriortoconnectinganyloadtotheEVMoutput.Ifthereisuncertaintyastotheloadspecification, pleasecontactaTIfieldrepresentative. Duringnormaloperation,somecircuitcomponentsmayhavecasetemperaturesgreaterthan+125°C.TheEVMisdesignedtooperate properlywithcertaincomponentsabove+125°Caslongastheinputandoutputrangesaremaintained.Thesecomponentsincludebutare notlimitedtolinearregulators,switchingtransistors,passtransistors,andcurrentsenseresistors.Thesetypesofdevicescanbeidentified usingtheEVMschematiclocatedintheEVMUser'sGuide.Whenplacingmeasurementprobesnearthesedevicesduringoperation, pleasebeawarethatthesedevicesmaybeverywarmtothetouch. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright2008,TexasInstrumentsIncorporated Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):THS3201

Not Recommended for New Designs THS3201 SLOS416C–JUNE2003–REVISEDJUNE2009............................................................................................................................................................. www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(March2008)toRevisionC .................................................................................................. Page • Changed5-VStepto10-VStepinsecondbulletofFeatureslist......................................................................................... 1 • DeletedleadtemperaturerowfromAbsoluteMaximumRatingstable................................................................................. 2 ChangesfromRevisionA(January,2004)toRevisionB .............................................................................................. Page • Updateddocumentformat..................................................................................................................................................... 1 • UpdatedFeatures,Applications,andDescriptionsections................................................................................................... 1 • UpdatedPackage/OrderingInformation................................................................................................................................ 3 • Changed±7.5-Vslewratetypicalvalues............................................................................................................................... 4 • Changed±7.5-Vriseandfalltimetypicalvalues................................................................................................................... 4 • Changed±7.5-V2nd-orderharmonictypicalvalues.............................................................................................................. 4 • Changed±7.5-V3rd-orderharmonictypicalvalues.............................................................................................................. 4 • Deleted±7.5-V3rd-orderintermodulationdistortionspecifications....................................................................................... 4 • Changed±5-Vslewratetypicalvalues.................................................................................................................................. 6 • Changed±5-Vriseandfalltimetypicalvalues...................................................................................................................... 6 • Changed±5-V2nd-orderharmonictypicalvalues................................................................................................................. 6 • Changed±5-V3rd-orderharmonictypicalvalues................................................................................................................. 6 • Deleted±5-V3rd-orderintermodulationdistortionspecifications.......................................................................................... 6 • AddedFigure9throughFigure17;updatedFigure25......................................................................................................... 8 • AddedFigure40throughFigure48;addedFigure51.......................................................................................................... 9 • DeletedPowerSupplysection............................................................................................................................................. 19 • UpdatedfirstparagraphinPrintedCircuitBoardLayoutsection......................................................................................... 19 26 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3201

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS3201D NRND SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3201 & no Sb/Br) THS3201DBVT NRND SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BEO & no Sb/Br) THS3201DBVTG4 NRND SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BEO & no Sb/Br) THS3201DG4 NRND SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3201 & no Sb/Br) THS3201DGK NRND VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 BGP & no Sb/Br) THS3201DGN NRND HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BEN & no Sb/Br) THS3201DGNG4 NRND HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BEN & no Sb/Br) THS3201DGNR NRND HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BEN & no Sb/Br) THS3201DR NRND SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3201 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS3201 : •Enhanced Product: THS3201-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS3201DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 THS3201DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS3201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS3201DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 THS3201DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS3201DR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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