THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS CheckforSamples:THS3110THS3111 FEATURES DESCRIPTION 1 • LowNoise The THS3110 and THS3111 are low-noise, 23 – 2-pA/√HzNoninvertingCurrentNoise high-voltage, current-feedback amplifiers designed to operateoverawidesupplyrangeof±5Vto ±15Vfor – 10-pA/√HzInvertingCurrentNoise today'shighperformanceapplications. – 3-nV/√HzVoltageNoise The THS3110 features a power-down pin (PD) that • HighOutputCurrentDrive:260mA puts the amplifier in low-power standby mode, and • HighSlewRate:1300V/μs lowersthequiescentcurrentfrom4.8mAto270μA. – (R =100Ω,V =8V ) L O PP These amplifiers provide well-regulated ac • WideBandwidth:90MHz(G=2,RL=100Ω) performance characteristics. The unity-gain • WideSupplyRange:±5Vto±15V bandwidth of 100 MHz allows for good distortion characteristics below 10 MHz. Coupled with a high • Power-DownFeature:(THS3110Only) 1300-V/μs slew rate, the THS3110 and THS3111 amplifiers allow for high output voltage swings at high APPLICATIONS frequencies. • VideoDistribution The THS3110 and THS3111 are offered in the • PowerFETDriver SOIC-8 (D) and the MSOP-8 (DGN) packages with • PinDriver PowerPAD™. • CapacitiveLoadDriver space space DIFFERENTIAL GAIN DIFFERENTIAL PHASE vs vs NUMBER OF LOADS NUMBER OF LOADS 0.3 0.4 VIDEO DISTRIBUTION AMPLIFIER APPLICATION Gain = 2, Gain = 2, Differential Gain − %00..0012..5512 RV4W0SFo Ir==Rs tE±1 C1 k−5aW sNV,eT, S±P1CA0 La0n IdR EP ARLa,mp NTSC (cid:1)Differential Phase −000...000123...555123 RV4W0SFo Ir==Rs tE±1 C1 k−5aW sNV,eT, PS±A1CL0 a0n IdR EP ARNLaT,mSCp VI 1 kW 75 W 1+−1 −k51W 5V V 7n5 77-LW55in WWTersansmission Line75 VWVOO((n1)) 0.05 0.05 0 0 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 75 W Number of 150 W Loads Number of 150 W Loads 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. TOP VIEW D, DGN TOP VIEW D, DGN THS3110 THS3111 REF 1 8 PD NC 1 8 NC VIN− 2 7 VS+ VIN− 2 7 VS+ VIN+ 3 6 VOUT VIN+ 3 6 VOUT VS− 4 5 NC VS− 4 5 NC NC = No Internal Connection NC= No Internal Connection NOTE: The device with the power-down option defaults to the ON state if no signal is applied to the PD pin. Additionally, the REF pin functional range is from VS-to (VS+-4 V). AVAILABLEOPTIONS(1) PACKAGEDDEVICE T A PLASTICSMALLOUTLINESOIC(D) PLASTICMSOP(DGN) (2) SYMBOL THS3110CD THS3110CDGN 0°Cto+70°C BJB THS3110CDR THS3110CDGNR THS3110ID THS3110IDGN –40°Cto+85°C BIR THS3110IDR THS3110IDGNR THS3111CD THS3111CDGN 0°Cto+70°C BJA THS3111CDR THS3111CDGNR THS3111ID THS3111IDGN –40°Cto+85°C BIS THS3111IDR THS3111IDGNR (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) ThePowerPADiselectricallyisolatedfromallotherpins. DISSIPATION RATINGS TABLE POWERRATING PACKAGE θJC(°C/W) θJA(°C/W) TJ=+125°C T =+25°C T =+85°C A A D-8(1) 38.3 95 1.05W 421mW DGN-8(2) 4.7 58.4 1.71W 685mW (1) ThesedataweretakenusingtheJEDECstandardlow-KtestPCB.FortheJEDECproposedhigh-KtestPCB,theθ is95°C/Wwith JA powerratingatT =+25°Cof1.05W. A (2) Thesedataweretakenusing2oz.traceandcopperpadthatissoldereddirectlytoa3inch×3inch(76,2mm×76,2mm)PCB.For furtherinformation,refertotheApplicationInformationsectionofthisdatasheet. 2 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Dualsupply ±5 ±15 Supplyvoltage V Singlesupply 10 30 Commercial 0 +70 Operatingfree-airtemperature,T A Industrial –40 +85 °C Operatingjunctiontemperature,continuousoperatingtemperature,T –40 +125 J Normalstoragetemperature,T –40 +85 STG ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperature,unlessotherwisenoted. UNIT Supplyvoltage,V toV 33V S– S+ Inputvoltage,V ±V I S Differentialinputvoltage,V ±4V ID Outputcurrent,I (2) 300mA O Continuouspowerdissipation SeeDissipationRatingsTable Maximumjunctiontemperature,T (3) +150°C J Maximumjunctiontemperature,continuousoperation,longtermreliability,T (4) +125°C J Commercial 0°Cto+70°C Operatingfree-airtemperature,T A Industrial –40°Cto+85°C Storagetemperature,T –65°Cto+125°C stg ESDratings: HBM 900 CDM 1500 MM 200 (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) TheTHS3110andTHS3111mayincorporateaPowerPADontheundersideofthechip.Thisfeatureactsasaheatsinkandmustbe connectedtoathermallydissipatingplaneforproperpowerdissipation.Failuretodosomayresultinexceedingthemaximumjunction temperaturewhichcouldpermanentlydamagethedevice.SeeTITechnicalBriefSLMA002formoreinformationaboututilizingthe PowerPAD™thermally-enhancedpackage. (3) Theabsolutemaximumtemperatureunderanyconditionislimitedbytheconstraintsofthesiliconprocess. (4) Themaximumjunctiontemperatureforcontinuousoperationislimitedbypackageconstraints.Operationabovethistemperaturemay resultinreducedreliabilityand/orlifetimeofthedevice. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS V =±15V,R =1kΩ,R =100Ω,andG=2,unlessotherwisenoted. S F L TYP OVERTEMPERATURE MIN/TYP/ PARAMETER TESTCONDITIONS +25°C +25°C 0°Cto –40°Cto UNIT MAX +70°C +85°C ACPERFORMANCE G=1,RF=1.5kΩ,VO=200mVPP 100 G=2,RF=1kΩ,VO=200mVPP 90 Small-signalbandwidth,–3dB G=5,RF=806Ω,VO=200mVPP 87 MHz TYP G=10,RF=604Ω,VO=200mVPP 66 0.1-dBbandwidthflatness G=2,RF=1.15kΩ,VO=200mVPP 45 Large-signalbandwidth G=5,RF=806Ω,VO=4VPP 95 G=1,VO=4-Vstep,RF=1.5kΩ 800 Slewrate(25%to75%level) V/μs TYP G=2,VO=8-Vstep,RF=1kΩ 1300 RecommendedmaximumSRfor Slewrate repetitivesignals(1) 900 V/μs MAX Riseandfalltime G=–5,VO=10-Vstep,RF=806Ω 8 ns TYP Settlingtimeto0.1% G=–2,VO=2VPPstep 27 ns TYP Settlingtimeto0.01% G=–2,VO=2VPPstep 250 Harmonicdistortion RL=100Ω 52 2ndharmonicdistortion G=2, RF=1kΩ, RL=1kΩ 53 dBc TYP 3rdharmonicdistortion Vf=O1=02MVHPPz, RL=100Ω 48 RL=1kΩ 68 Inputvoltagenoise f>20kHz 3 nV/√Hz TYP Noninvertinginputcurrentnoise f>20kHz 2 pA/√Hz TYP Invertinginputcurrentnoise f>20kHz 10 pA/√Hz TYP NTSC 0.011% Differentialgain G=2, PAL 0.013% RL=150Ω, TYP Differentialphase RF=1kΩ NTSC 0.029° PAL 0.033° DCPERFORMANCE Transimpedance VO=±3.75V,gain=1 1 0.75 0.5 0.5 MΩ MIN Inputoffsetvoltage 3 10 12 12 mV MAX VCM=0V Averageoffsetvoltagedrift ±10 ±10 μV/°C TYP Noninvertinginputbiascurrent 1 4 6 6 μA MAX VCM=0V Averagebiascurrentdrift ±10 ±10 nA/°C TYP Invertinginputbiascurrent 1.5 15 20 20 μA MAX VCM=0V Averagebiascurrentdrift ±10 ±10 nA/°C TYP Inputoffsetcurrent 2.5 15 20 20 μA MAX VCM=0V Averageoffsetcurrentdrift ±30 ±30 nA/°C TYP INPUTCHARACTERISTICS Inputcommon-modevoltagerange ±13.3 ±13 ±12.5 ±12.5 V MIN Common-moderejectionratio VCM=±12.5V 68 62 60 60 dB MIN Noninvertinginputresistance 41 MΩ TYP Noninvertinginputcapacitance 0.4 pF TYP OUTPUTCHARACTERISTICS RL=1kΩ ±13.5 ±13 ±12.5 ±12.5 Outputvoltageswing V MIN RL=100Ω ±13.4 ±12.5 ±12 ±12 Outputcurrent(sourcing) RL=25Ω 260 200 175 175 mA MIN Outputcurrent(sinking) RL=25Ω 260 200 175 175 mA MIN Outputimpedance f=1MHz,closedloop 0.15 Ω TYP (1) Formoreinformation,seetheApplicationInformationsectionofthisdatasheet. 4 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 ELECTRICAL CHARACTERISTICS (continued) V =±15V,R =1kΩ,R =100Ω,andG=2,unlessotherwisenoted. S F L TYP OVERTEMPERATURE MIN/TYP/ PARAMETER TESTCONDITIONS +25°C +25°C 0°Cto –40°Cto UNIT MAX +70°C +85°C POWERSUPPLY Specifiedoperatingvoltage ±15 ±16 ±16 ±16 V MAX Maximumquiescentcurrent 4.8 6.5 7.5 7.5 mA MAX Minimumquiescentcurrent 4.8 3.8 2.5 2.5 mA MIN Power-supplyrejection(+PSRR) VS+=15.5Vto14.5V,VS–=15V 75 65 60 60 dB MIN Power-supplyrejection(–PSRR) VS+=15V,VS–=–15.5Vto–14.5V 69 60 55 55 dB MIN POWER-DOWNCHARACTERISTICS(THS3110Only) REFvoltagerange(2) VS+–4 V MAX VS– V MIN PD≤ Enable V MIN REF+0.8 Power-downvoltagelevel(2) PD≥REF Disable V MAX +2 Power-downquiescentcurrent PD≥REF+2V 270 450 500 500 μA MAX VPD=0V,REF=0V, 11 PDpinbiascurrent μA TYP VPD=3.3V,REF=0V 11 Turn-ontimedelay 90%offinalvalue 4 μs TYP Turn-offtimedelay 10%offinalvalue 6 Inputimpedance 3.4||1.7 kΩ||pF TYP (2) Fordetailedinformationonthebehaviorofthepower-downcircuit,seetheSavingPowerwithPower-DownFunctionalityand Power-DownReferencePinOperationsectionsintheApplicationInformationsectionofthisdatasheet. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS V =±5V,R =1.15Ω,R =100Ω,andG=2,unlessotherwisenoted. S F L TYP OVERTEMPERATURE MIN/TYP/ PARAMETER TESTCONDITIONS +25°C +25°C 0°Cto –40°Cto UNIT MAX +70°C +85°C ACPERFORMANCE G=1,RF=1.5kΩ,VO=200mVPP 85 G=2,RF=1.15kΩ,VO=200mVPP 78 Small-signalbandwidth,–3dB G=5,RF=806Ω,VO=200mVPP 80 MHz TYP G=10,RF=604Ω,VO=200mVPP 60 0.1-dBbandwidthflatness G=2,RF=1.15kΩ,VO=200mVPP 15 Large-signalbandwidth G=5,RF=806Ω,VO=4VPP 80 G=1,VO=4-Vstep,RF=1.5kΩ 640 Slewrate(25%to75%level) V/μs TYP G=2,VO=4-Vstep,RF=1kΩ 700 RecommendedmaximumSRfor Slewrate repetitivesignals(1) 900 V/μs MAX Riseandfalltime G=–5,VO=5-Vstep,RF=806Ω 7 ns TYP Settlingtimeto0.1% G=–2,VO=2VPPstep 20 ns TYP Settlingtimeto0.01% G=–2,VO=2VPPstep 200 Harmonicdistortion RL=100Ω 55 2ndharmonicdistortion G=2, RF=1kΩ, RL=1kΩ 56 dBc TYP 3rdharmonicdistortion Vf=O1=02MVHPPz, RL=100Ω 45 RL=1kΩ 62 Inputvoltagenoise f>20kHz 3 nV/√Hz TYP Noninvertinginputcurrentnoise f>20kHz 2 pA/√Hz TYP Invertinginputcurrentnoise f>20kHz 10 pA/√Hz TYP NTSC 0.011% Differentialgain G=2, PAL 0.015% RL=150Ω, TYP Differentialphase RF=1kΩ NTSC 0.020° PAL 0.033° DCPERFORMANCE Transimpedance VO=±1.25V,gain=1 1 0.75 0.5 0.5 MΩ MIN Inputoffsetvoltage 6 10 12 12 mV MAX VCM=0V Averageoffsetvoltagedrift ±10 ±10 μV/°C TYP Noninvertinginputbiascurrent 1 4 6 6 μA MAX VCM=0V Averagebiascurrentdrift ±10 ±10 nA/°C TYP Invertinginputbiascurrent 1 8 10 10 μA MAX VCM=0V Averagebiascurrentdrift ±10 ±10 nA/°C TYP Inputoffsetcurrent 1 6 8 8 μA MAX VCM=0V Averageoffsetcurrentdrift ±20 ±20 nA/°C TYP INPUTCHARACTERISTICS Inputcommon-modevoltagerange ±3.2 ±2.9 ±2.8 ±2.8 V MIN Common-moderejectionratio VCM=±2.5V 65 62 58 58 dB MIN Noninvertinginputresistance 35 MΩ TYP Noninvertinginputcapacitance 0.5 pF TYP OUTPUTCHARACTERISTICS RL=1kΩ ±4 ±3.8 ±3.6 ±3.6 Outputvoltageswing V MIN RL=100Ω ±3.8 ±3.7 ±3.5 ±3.5 Outputcurrent(sourcing) RL=10Ω 220 150 125 125 mA MIN Outputcurrent(sinking) RL=10Ω 220 150 125 125 mA MIN Outputimpedance f=1MHz,closedloop 0.15 Ω TYP (1) Formoreinformation,seetheApplicationInformationsectionofthisdatasheet. 6 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 ELECTRICAL CHARACTERISTICS (continued) V =±5V,R =1.15Ω,R =100Ω,andG=2,unlessotherwisenoted. S F L TYP OVERTEMPERATURE MIN/TYP/ PARAMETER TESTCONDITIONS +25°C +25°C 0°Cto –40°Cto UNIT MAX +70°C +85°C POWERSUPPLY Specifiedoperatingvoltage ±5 ±4.5 ±4.5 ±4.5 V MIN Maximumquiescentcurrent 4 6 7 7 mA MAX Minimumquiescentcurrent 4 3.2 2 2 mA MIN Power-supplyrejection(+PSRR) VS+=5.5Vto4.5V,VS–=5V 71 62 57 57 dB MIN Power-supplyrejection(–PSRR) VS+=5V,VS–=–5.5Vto–4.5V 66 57 52 52 dB MIN POWER-DOWNCHARACTERISTICS(THS3110Only) REFvoltagerange(2) VS+–4 V MAX VS– V MIN PD≤REF Enable V MIN +0.8 Power-downvoltagelevel(2) PD≥REF Disable V MAX +2 Power-downquiescentcurrent PD≥REF+2V 200 450 500 500 μA MAX VPD=0V,REF=0V, 11 PDpinbiascurrent μA TYP VPD=3.3V,REF=0V 11 Turn-ontimedelay 90%offinalvalue 4 μs TYP Turn-offtimedelay 10%offinalvalue 6 Inputimpedance 3.4||1.7 kΩ||pF TYP (2) Fordetailedinformationonthebehaviorofthepower-downcircuit,seethePower-DownandPower-downReferencesectionsinthe ApplicationInformationsectionofthisdatasheet. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE ±15-VGraphs Noninvertingsmall-signalgainfrequencyresponse 1,2 Invertingsmall-signalgainfrequencyresponse 3 0.1-dBflatness 4 Noninvertinglarge-signalgainfrequencyresponse 5 Invertinglarge-signalgainfrequencyresponse 6 Frequencyresponsecapacitiveload 7 RecommendedR vsCapacitiveload 8 ISO 2ndharmonicdistortion vsFrequency 9 3rdharmonicdistortion vsFrequency 10 Harmonicdistortion vsOutputvoltageswing 11,12 Slewrate vsOutputvoltagestep 13,14,15,16 Noise vsFrequency 17 Settlingtime 18,19 Quiescentcurrent vsSupplyvoltage 20 Outputvoltage vsLoadresistance 21 Inputbiasandoffsetcurrent vsCasetemperature 22 Inputoffsetvoltage vsCasetemperature 23 Transimpedance vsFrequency 24 Rejectionratio vsFrequency 25 Noninvertingsmall-signaltransientresponse 26 Invertinglargesignaltransientresponse 27 Overdriverecoverytime 28 Differentialgain vsNumberofloads 29 Differentialphase vsNumberofloads 30 Closedloopoutputimpedance vsFrequency 31 Power-downquiescentcurrent vsSupplyvoltage 32 Turn-onandturn-offtimedelay 33 ±5-VGraphs Noninvertingsmall-signalgainfrequencyresponse 34 Invertingsmall-signalgainfrequencyresponse 35 0.1-dBflatness 36 Noninvertinglarge-signalgainfrequencyresponse 37 Invertinglarge-signalgainfrequencyresponse 38 Slewrate vsOutputvoltagestep 39,40,41,42 2ndharmonicdistortion vsFrequency 43 3rdharmonicdistortion vsFrequency 44 Harmonicdistortion vsOutputvoltageswing 45,46 Noninvertingsmall-signaltransientresponse 47 Invertingsmall-signaltransientresponse 48 Overdriverecoverytime 49 Rejectionratio vsFrequency 50 8 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS (±15 V) space NONINVERTINGSMALL-SIGNAL NONINVERTINGSMALL-SIGNAL INVERTINGSMALL-SIGNAL FREQUENCYRESPONSE FREQUENCYRESPONSE FREQUENCYRESPONSE 9 24 24 8 RF = 649 W 2202 G = 10, RF = 604 W 2202 G = -10, RF = 649 W RVVOSL === 1±001.205 VWVP,P, 7 18 18 Noninverting Gain - dB 123456 GRVVOSLaR i=R=nF= F1=±=0 01 .=12205 ., 1 1VWV.55P, Pkk,WW Noninverting Gain - dB -11112024602468 RVVGGOSLG = === = =5 21± 0,1 ,01.R ,2R05 RF FVW VF= P= , =P8 ,1 01.61.5 5W kkWW Inverting Gain - dB -11112024602468 GGG == = -- 2-15,, ,RR RFFF == = 11 9. 1k0 W9k WW 0 -4 -4 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 1 M 10 M 100 M 1 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure1. Figure2. Figure3. NONINVERTINGLARGE-SIGNAL INVERTINGLARGE-SIGNAL 0.1-dBFLATNESS FREQUENCYRESPONSE FREQUENCYRESPONSE 6.4 16 16 6.3 GRFa i=n =1. 125, kW , 14 G = 5, RF = 806 W 1124 G = -5, RF = 806 W RVVOSL === 1±201 V05P WVP,, Noninverting Gain - dB 5566....89126 RVVOSL === 1±001.205 VWVP,P, Noninverting Gain - dB 1102468 G = 2, RF = 1 kW Inverting Gain - dB 1002468 G =-1, RF = 1 kW RL = 100 W , 5.7 2 VO = 4 VPP, -2 5.6 0 VS = ±15 V -4 100 k 1 M 10 M 100 M 1 M 10 M 100 M 1 G 1 M 10 M 100 M 1 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure4. Figure5. Figure6. RECOMMENDEDR 2ndHARMONICDISTORTION ISO FREQUENCYRESPONSE vs vs CAPACITIVELOAD CAPACITIVELOAD FREQUENCY 16 60 -30 Signal Gain - dB 11102402468 GRVSLa i==n 1±=01 RC505,(L RIWV S=(OI SR1)ROC C(0=I()SLI L Sp5= O =OF=4 )3 ) .1 =499=07 . 2W20 5p8 4WpF .WF9 W, CL‘ = 22 pF WRecommended R-ISO 1234500000 GRVSLa i==n 1±=01 505, WV, 2nd Harmonic Destortion - dBc ------987654000000 G =G 2 ,= R 5F, =R F1 =k W80GR6 L W=VRV = OSL- 2 1 ===, k R1±2W0F1 ,V 05=P WVP1,, kW -2 0 -100 10 M 100 M 200 M 10 100 100 k 1 M 10 M 100 M Capacitive Load - MHz CL - Capacitive Load - pF f - Frequency - Hz Figure7. Figure8. Figure9. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (±15 V) (continued) space 3rdHARMONICDISTORTION HARMONICDISTORTION HARMONICDISTORTION vs vs vs FREQUENCY OUTPUTVOLTAGESWING OUTPUTVOLTAGESWING -30 -70 -40 VO = 2 VPP, HD3 2nd Harmonic Destortion - dBc ------987654000000 GRRVF SLG= == = 2= 1,1± 5 01k,05 WR WVF, = 806 W GRRFL = == - 211, kkWW , Harmonic Distortion - dBc -----9988750505 HD2 GRRfV=SFLa 1 i===n M 1±=1H01 k205zW,W V,, Harmonic Distortion - dBc -----6655450505 HD3 HD2 GRRfV =SFLa i8===n M1±=101 Hk205W,z WV,, -100 -100 -70 100 k 1 M 10 M 100 M 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 f - Frequency - Hz VO - Output Voltage Swing - VPP VO - Output Voltage Swing - VPP Figure10. Figure11. Figure12. SLEWRATE SLEWRATE SLEWRATE vs vs vs OUTPUTVOLTAGESTEP OUTPUTVOLTAGESTEP OUTPUTVOLTAGESTEP 1000 1400 1400 msV/ 800 GRRVSLFa i===n 1±=101. 5105 kWVW FalRlise msV/ 11020000 GRRVSLFa i===n 11±=. 1 5k15W k VW Fall msV/ 11020000 GRRVSLFa i===n1 1±=0 1k 02W5 W V Fall Rise Rate - 600 Rate - 800 Rise Rate - 800 w w w Sle 400 Sle 600 Sle 600 SR - SR - 400 SR - 400 200 200 200 0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 7 8 9 10 VO - Output Voltage -VPP VO - Output Voltage -VPP VO - Output Voltage -VPP Figure13. Figure14. Figure15. SLEWRATE NOISE vs vs OUTPUTVOLTAGESTEP FREQUENCY SETTLINGTIME 1600 100 1.5 Gain = 2 Fall Rising Edge msSR - Slew Rate - V/ 111468024000000000000 RRVSLF ===1 1± k1kWW5 V Rise V- Voltage Noise - nV/Hzn- Current Noise -IpA/Hzn10 In+ Vn In- - Output Voltage - VVO-00-..51501 GRRVSLFaF i=a==nl l1=±1in01. 1g-052 kEWVWdge 200 0 1 -1.5 0 1 2 3 4 5 6 7 8 9 10 10 100 1 k 10 k 100 k 0 2 4 6 8 10 12 14 16 18 VO - Output Voltage -VPP f - Frequency - Hz t - Time - ns Figure16. Figure17. Figure18. 10 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS (±15 V) (continued) space QUIESCENTCURRENT OUTPUTVOLTAGE vs vs SETTLINGTIME SUPPLYVOLTAGE LOADRESISTANCE 3 6 16 2.5 Rising Edge TA = 85 °C 1124 2 A 5 10 - Output Voltage - VVO--1001-....5515501 GRRVSLFa i===n 1=±101. 1-052 kWVW - Quiescent Current - mQ 234 TTAA == 2-54 0° C°C - Output Voltage - VVO ----864202468 VTAS == -±4105° tVo 85°C -2 I 1 -10 Falling Edge -12 -2.5 -14 -3 0 -16 0 2 4 6 8 10 12 14 16 18 20 2 3 4 5 6 7 8 9 1011 12131415 10 100 1000 t - Time - ns VS - Supply Voltage - ±V RL - Load Resistance - W Figure19. Figure20. Figure21. INPUTBIASAND OFFSETCURRENT INPUTOFFSETVOLTAGE TRANSIMPEDANCE vs vs vs CASETEMPERATURE CASETEMPERATURE FREQUENCY 3.5 4 110 VS = ±15 V 100 3 3.5 V =±15 V and±5 V m- Input Bias Current -AIIBm- Input Offset Current -AIOS012...55512 IIIOIBIBS-+ - Input Offset Voltage - mVVOS 012...555123 VS = ±5 V VS = ±15 V -Transimpedance GaindB 9876543200000000 S 10 0 0 0 -40-30-20-10 0 1020304050607080 90 -40-30-20-10 0 102030405060708090 0.1 1 10 100 1000 TC - Case Temperature - °C TC - Case Temperature - °C Frequency-MHz Figure22. Figure23. Figure24. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (±15 V) (continued) space REJECTIONRATIO vs NONINVERTINGSMALL-SIGNAL INVERTINGLARGE-SIGNAL FREQUENCY TRANSIENTRESPONSE TRANSIENTRESPONSE 70 0.2 6 VS = ±15 V 5 Gain = -5, 60 CMRR 0.15 Output 4 RRLF == 190009 WW ,, Rejection Ratio - dB 23450000 PSRR- PSRR+ - Output Voltage - VVO-0-0.0.000..51510 GRLa i=Inn p1=u0 2t0, W , - Output Voltage - VVO ---3210123 VISn p=u ±t15 V 10 -0.15 RVSF == ±11 k5W V, --54 Output 0 -0.2 -6 100 k 1 M 10 M 100 M 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 f - Frequency - Hz t - Time - ns t - Time - ns Figure25. Figure26. Figure27. DIFFERENTIALGAIN DIFFERENTIALPHASE vs vs OVERDRIVERECOVERYTIME NUMBEROFLOADS NUMBEROFLOADS 20 5 0.3 0.4 Gain = 4, Gain = 2, Gain = 2, 15 RRLF == 160801 WW ,, 0.25 RVSF == ±11 k5W V,, 0.35 RV40SF I==R E±11 k-5 WN V,T,SC and PAL, - Output Voltage - VVO-1-105005 VS = ±15 V -022.5.5- Input Voltage - VVI Differential Gain - % 0.001..512 4W0o IrRstE C -a NsTe S±PC1A0 aL0n IdR PEA RL,amp NTSC (cid:1)Differential Phase - 00..00012...55123 Worst Case P±A1L00 IRE RNaTmSCp -15 0.05 0.05 -20 -5 0 0.2 0.4 0.6 0.8 1 0 0 t - Time - m s 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Number of 150 W Loads Number of 150 W Loads Figure28. Figure29. Figure30. 12 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS (±15 V) (continued) space CLOSED-LOOPOUTPUT POWER-DOWNQUIESCENT IMPEDANCE CURRENT vs vs TURN-ONANDTURN-OFF FREQUENCY SUPPLYVOLTAGE TIMEDELAY 100 350 1.5 WZ- Closed-Loop Output Impedance -O0.001.1101 GRRVSFFa i===n ±1=101 k205W, WV,, mAPowerdown Quiescent Current - 112230505050000000 TA T=A 2 =5 °8C5°C TA = -40°C − Output Voltage Level − VVO−00..5015 0 0PGVRV.1oISOLa w = i=u=n 0et 0 p1.±=r.2du011 5ot0 5 V,wV 0WVdno.c 3 latPanugd0les ±.e45 V0.5 0.6 0.7−01234561PowerDown Pulse − V 100 k 1 M 10 M 100 M 1 G 3 5 7 9 11 13 15 f - Frequency - Hz VS - Supply Voltage - ±V t − Time − ms Figure31. Figure32. Figure33. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (±5 V) space NONINVERTINGSMALL-SIGNAL INVERTINGSMALL-SIGNAL FREQUENCYRESPONSE FREQUENCYRESPONSE 0.1-dBFLATNESS 24 24 6.4 Noninverting Gain − dB 111112202468022468 GGG =G = =1 = 052 ,,1, RR,R RFFF F === = 681 001.146.55 WW kkWW RVVOSL === 1±005.20 V VW P,P, Inverting Gain - dB 111112202468022468 GGG G= = = - = 1-- 205-,1,, R,RR RFFF F === = 169 .1401 99 kk WWWW RVVOSL === 1±005.20 V VW P,P, Noninverting Gain - dB 55666.....689123 GRRVVOSFLa i===n= 1±=1005. .1220 5V, VW kP,WP,, 0 0 5.7 −2 -2 −4 -4 5.6 1 M 10 M 100 M 1 G 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M f − Frequency − Hz f - Frequency - Hz f - Frequency - Hz Figure34. Figure35. Figure36. SLEWRATE NONINVERTINGLARGE-SIGNAL INVERTINGLARGE-SIGNAL vs FREQUENCYRESPONSE FREQUENCYRESPONSE OUTPUTVOLTAGESTEP 16 16 800 14 G = 5, RF = 806 W 14 G = -5, RF = 909 W 700 GRLa i=n 1=0 10 W Fall 12 RF = 1.5 kW Noninverting Gain - dB 1102468 G = 2, RF = 1.15 kW Inverting Gain - dB 102468 VRVGOSL = ===- 1 1±2205 ,V0 RVP WFP, ,= 1 kW msSR - Slew Rate - V/ 234560000000000 VS = ±5 V Rise VO = 4 VPP, 0 2 RVSL == 1±050 V W , -2 100 0 -4 0 1 M 10 M 100 M 1 G 1 10 M 100 M 1 G 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 f - Frequency - Hz f - Frequency - Hz VO - Output Voltage -VPP Figure37. Figure38. Figure39. SLEWRATE SLEWRATE SLEWRATE vs vs vs OUTPUTVOLTAGESTEP OUTPUTVOLTAGESTEP OUTPUTVOLTAGESTEP 800 800 800 Gain = 1 Gain = 2 Fall Gain = 2 Rise msw Rate - V/ 456700000000 RRVSLF === 1±1 5.k5 W VkW Rise Fall msw Rate - V/ 456700000000 RRVSLF === 1±105 k0 WV W Rise msw Rate - V/ 456700000000 RRVSLF === 1±1 5 kk WWV Fall SR - Sle 230000 SR - Sle 230000 SR - Sle 230000 100 100 100 0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 0 1 2 3 4 5 6 VO - Output Voltage -VPP VO - Output Voltage -VPP VO - Output Voltage -VPP Figure40. Figure41. Figure42. 14 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS (±5 V) (continued) space 2ndHARMONICDISTORTION 3rdHARMONICDISTORTION HARMONICDISTORTION vs vs vs FREQUENCY FREQUENCY OUTPUTVOLTAGESWING -30 -30 -65 VO = 2 VPP, Destortion - dBc ---654000 G =G 2 ,= R 5F, R= F6 8=1 6 W81 W Destortion - dBc ---654000 RVGRSLF = === 5 1±6,0580 1V W W, stortion - dBc ---877050 HD3 HD2 2nd Harmonic ---987000 GRL = = - 21, VRVkRWOSLF , ==== 1±2105 Vk0 VWP WP,, 2nd Harmonic ---987000 GRL = = - 21GR, kRF W= F= , 2 =6, 811 k WW Harmonic Di ---998505 GRRfV=SFLa 1 i===n M 1±=1H05. 120 z5V, W k,W -100 -100 -100 100 k 1 M 10 M 100 M 100 k 1 M 10 M 100 M 0 1 2 3 4 5 6 7 f - Frequency - Hz f - Frequency - Hz VO - Output Voltage Swing - VPP Figure43. Figure44. Figure45. HARMONICDISTORTION vs NONINVERTINGSMALL-SIGNAL INVERTINGLARGE-SIGNAL OUTPUTVOLTAGESWING TRANSIENTRESPONSE TRANSIENTRESPONSE -40 0.2 3 2.5 Gain = -5, HD3 0.15 Output 2 RL = 100 W , Harmonic Distortion - dBc ----87650000 HD2 GRRfV=SFLa 8 i===n M 1±=1H05 k20 zWV, W , - Output Voltage - VVO--00-0..0.0100..551510 GRRVSLFa i===nI n11±=p0.5 12u0 5Vt WkW - Output Voltage - VVO---21001--.....555215501 RVSFIn ==pO u±9ut05tp9 Vu Wt, -90 -0.2 -3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 VO - Output Voltage Swing - VPP t - Time - ns t - Time - ns Figure46. Figure47. Figure48. REJECTIONRATIO vs OVERDRIVERECOVERYTIME FREQUENCY 5 1.25 70 Gain = 4, VS = ±5 V 4 RL = 100 W , 1 60 3 RF = 909 W , 0.75 CMRR - Output Voltage - V --21012 VS = ±5 V --00000..25..5255- Input Voltage - V ejection Ratio - dB 23450000 PSRR+ VO VI R -3 -0.75 10 PSRR- -4 -1 -5 -1.25 0 0 0.2 0.4 0.6 0.8 1 100 k 1 M 10 M 100 M t - Time - m s f - Frequency - Hz Figure49. Figure50. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com APPLICATION INFORMATION MAXIMUM SLEW RATE FOR REPETITIVE 15 V SIGNALS +VS The THS3110 and THS3111 are recommended for + high slew rate pulsed applications where the internal 50 W Source 0.1 m F 6.8 m F nodes of the amplifier have time to stabilize between pulses. It is recommended to have at least 20-ns VI + 49.9 W delaybetweenpulses. 49.9 W T_HS3110 50 W LOAD The THS3110 and THS3111 are not recommended RF for applications with repetitive signals (sine, square, 1 kW sawtooth, or other) that exceed 900 V/μs. Using the 1 kW RG part in these applications results in excessive current 0.1 m F 6.8 m F draw from the power supply and possible device + damage. -VS Forapplicationswithhighslewrate,repetitivesignals, -15 V theTHS3091andTHS3095(single),orTHS3092 and THS3096(dual)arerecommended. Figure51. Wideband,NoninvertingGain Configuration WIDEBAND, NONINVERTING OPERATION The THS3110 and THS3111 are unity-gain stable, Current-feedback amplifiers are highly dependent on 100-MHz, current-feedback operational amplifiers, the feedback resistor R for maximum performance F designed to operate from a ±5-V to ±15-V power and stability. Table 1 shows the optimal gain setting supply. resistors R and R at different gains to give F G maximum bandwidth with minimal peaking in the Figure 51 shows the THS3111 in a noninverting gain frequency response. Higher bandwidths can be of 2-V/V configuration typically used to generate the achieved, at the expense of added peaking in the performance curves. Most of the curves were frequency response, by using even lower values for characterized using signal sources with 50-Ω source R . Conversely, increasing R decreases the impedance, and with measurement equipment F F bandwidth,butstabilityisimproved. presentinga50-Ωloadimpedance. Table1.RecommendedResistorValuesfor OptimumFrequencyResponse THS3110ANDTHS3111R ANDR VALUESFORMINIMALPEAKINGWITHR =100Ω F G L GAIN(V/V) SUPPLYVOLTAGE(V) R (Ω) R (Ω) G F ±15 — 1.5k 1 ±5 — 1.5k ±15 1k 1k 2 ±5 1.15k 1.15k ±15 200 806 5 ±5 200 806 ±15 66.5 604 10 ±5 66.5 604 ±15 1k 1k –1 ±5 1k 1k –2 ±15and±5 549 1.1k –5 ±15and±5 182 909 –10 ±15and±5 64.9 649 16 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 WIDEBAND, INVERTING OPERATION +VS Figure 52 shows the THS3111 in a typical inverting 50 W Source gain configuration where the input and output impedances and signal gain from Figure 51 are VI + 49.9 W retainedinaninvertingcircuitconfiguration. RT 49.9 W T_HS3110 50 W LOAD 15 V+VS +VS RF 2 + RG 1 kW 0.1 m F 6.8 m F 1 kW + +VS 49.9 W 2 THS3110 RF _ 50 W LOAD 1.1 kW 50 W Source RG RF 50 W Source VS RG _ VI R556M4.29 WW 1.1 kW 0.1 m F 6.8 m F V5I6.2 W R5T49 W T+HS3110 49.95 W0 W LOAD + +VS +VS -15 V -VS 2 2 Figure53. DC-Coupled,Single-SupplyOperation Figure52. Wideband,InvertingGain Configuration VideoDistribution The wide bandwidth, high slew rate, and high output SINGLE-SUPPLY OPERATION drive current of the THS3110 and THS3111 match The THS3110 and THS3111 have the capability to the demands for video distribution for delivering video operate from a single-supply voltage ranging from signals down multiple cables. To ensure high signal 10 V to 30 V. When operating from a single power quality with minimal degradation of performance, a supply, biasing the input and output at mid-supply 0.1-dB gain flatness should be at least 7x the allows for the maximum output voltage swing. The passband frequency to minimize group delay circuits shown in Figure 53 shows inverting and variations from the amplifier. A high slew rate noninverting amplifiers configured for single supply minimizes distortion of the video signal, and supports operations. component video and RGB video signals that require fast transition times and fast settling times for high signalquality. 1 kW 1 kW 15 V 75 W 75-W Transmission Line VO(1) - VI + -15 V 75 W n Lines 75 W 75 W VO(n) 75 W Figure54. VideoDistributionAmplifier Application Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com DrivingCapacitiveLoads frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at Applications such as FET drivers and line drivers can high frequency. Use a ferrite chip with similar be highly capacitive and cause stability problems for impedance to R , 20 Ω to 50 Ω, at 100 MHz and high-speedamplifiers. ISO lowimpedanceatdc. Figure 55 through Figure 61 show recommended methods for driving capacitive loads. The basic idea 806 W is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load VS from the amplifier feedback path. See Figure 55 for 200 W _ Ferrite Bead recommendedresistorvaluesversuscapacitiveload. + 60 Gain = 5, -VS 1 m F 100 W LOAD 50 RVSL == 1±0105 WV, VS 49.9 W W - O 40 S RI d de 30 en Figure57. FerriteBeadtoIsolateCapacitiveLoad m m 20 o c e R Figure 58 shows another method used to maintain 10 the low frequency load independence of the amplifier while isolating the phase shift caused by the 0 10 100 capacitance at high frequency. At low frequency, CL - Capacitive Load - pF feedback is mainly from the load side of R . At high ISO frequency, the feedback is mainly via the 27-pF Figure55. RecommendedR vsCapacitive capacitor. The resistor R in series with the negative ISO IN Load input is used to stabilize the amplifier and should be equal to the recommended value of R at unity gain. F Placing a small series resistor, RISO, between the Replacing RIN with a ferrite of similar impedance at amplifier output and the capacitive load, as shown in about 100 MHz as shown in Figure 59 gives similar Figure 56, is an easy way of isolating the load results with reduced dc offset and low frequency capacitance. noise. (See the Additional Reference Material section for expanding the usability of current-feedback amplifiers.) 806 W VS RF 200 W _ 5.11 W 100 W LOAD 806 W 27 pF + RISO RIN 49.9- VW S 1 m F RG 750 W _VS 5.11 W 100 W LOAD VS 200 W + -VS 1 m F 49.9 W VS Figure56. ResistortoIsolateCapacitiveLoad Using a ferrite chip in place of R , as shown in ISO Figure 57, is another approach of isolating the output Figure58. FeedbackTechniquewithInput of the amplifier. The ferrite impedance characteristic ResistorforCapacitiveLoad versus frequency is useful to maintain the low 18 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 Figure 61 shows a push-pull FET driver circuit typical RF of ultrasound applications with isolation resistors to 806 W isolatethegatecapacitancefromtheamplifier. 27 pF FIN VS VS VS RG FB _ 5.11 W 100 W LOAD + 5.11 W 200 W _ + -VS 1 m F -VS 49.9 W VS 301 W 66.5 W 301 W Figure59. FeedbackTechniquewithInputFerrite BeadforCapacitiveLoad VS _ 5.11 W Figure 60 shows how to use two amplifiers in parallel + to double the output drive current to larger capacitive loads. This technique is used when more output -VS -VS current is needed to charge and discharge the load Figure61. PowerFETDriveCircuit fasterlikewhendrivinglargeFETtransistors. 806 W SAVING POWER WITH POWER-DOWN FUNCTIONALITY AND SETTING VS 200 W THRESHOLD LEVELS WITH THE _ 5.11 W REFERENCE PIN + 24.9 W The THS3110 features a power-down pin (PD) which -VS lowers the quiescent current from 4.8 mA down to 806 W 270μA,idealforreducingsystempower. VS VS 1 nF The power-down pin of the amplifier defaults to the 200 W REF pin voltage in the absence of an applied voltage, _ 5.11 W putting the amplifier in the normal on mode of + operation. To turn off the amplifier in an effort to 24.9 W conserve power, the power-down pin can be driven -VS towards the positive rail. The threshold voltages for power-on and power-down are relative to the supply Figure60. ParallelAmplifiersforHigherOutput rails and are given in the specification tables. Below Drive the Enable Threshold Voltage, the device is on. Above the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is notspecified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied totheoutputs. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com Figure 62 shows the total system output impedance POWER-DOWN REFERENCE PIN which includes the amplifier output impedance in OPERATION parallel with the feedback plus gain resistors, which In addition to the power-down pin, the THS3110 cumulate to 1870 Ω. Figure 51 shows this circuit features a reference pin (REF) which allows the user configurationforreference. to control the enable or disable power-down voltage levels applied to the PD pin. In most split-supply 2000 applications, the reference pin is connected to W 1800 ground. In either case, the user needs to be aware of ce - 1600 voltage-level thresholds that apply to the power-down n da 1400 pin. The tables below show examples and illustrate e mp 1200 the relationship between the reference voltage and put I 1000 thepower-downthresholds.Inthetable,thethreshold n Out 800 levelsarederivedbythefollowingequations: w PD≤ REF+0.8Vforenable o 600 d wer 400 Gain = 2 PD≥ REF+2.0Vfordisable Po 200 RVSF == ±11 k5W V and ±5 V wheretheusablerangeattheREFpinis 0 100 k 1 M 10 M 100 M 1 G VS–≤VREF≤(VS+– 4V). f - Frequency - Hz The recommended mode of operation is to tie the REF pin to midrail, thus setting the enable/disable Figure62. Power-DownOutputImpedancevs thresholds to V + 0.8 V and V + 2 V Frequency midrail midrail respectively. As with most current feedback amplifiers, the internal POWER-DOWNTHRESHOLDVOLTAGELEVELS architecture places some limitations on the system SUPPLY REFERENCEPIN ENABLE DISABLE when in power-down mode. Most notably is the fact VOLTAGE(V) VOLTAGE(V) LEVEL(V) LEVEL(V) thattheamplifieractuallyturnsONifthereisa±0.7V ±15,±5 0.0 0.8 2.0 or greater difference between the two input nodes ±15 2.0 2.8 4 (V+ and V–) of the amplifier. If this difference exceeds ±0.7 V, the output of the amplifier creates an ±15 –2.0 –1.2 0 output voltage equal to approximately [(V+ – V–) – ±5 1.0 1.8 3 0.7 V] × Gain. Also, if a voltage is applied to the ±5 –1.0 –0.2 1 output while in power-down mode, the V– node +30 15 15.8 17 voltage is equal to V × R /(R + R ). For low O(applied) G F G +10 5.0 5.8 7 gain configurations and a large applied voltage at the output, the amplifier may actually turn ON due to the Note that if the REF pin is left unterminated, it floats aforementionedbehavior. to the positive rail and falls outside of the The time delays associated with turning the device on recommended operating range given above (VS–≤ and off are specified as the time it takes for the VREF ≤VS+–4V). As a result, it no longer serves as amplifier to reach either 10% or 90% of the final a reliable reference for the PD pin and the output voltage. The time delays are in the order of enable/disable thresholds given above no longer microsecondsbecausetheamplifiermovesinandout apply. If the PD pin is also left unterminated, it also ofthelinearmodeofoperationinthesetransitions. floats to the positive rail and the device is disabled. If balanced, split supplies are used (±V ) and the REF S andPDpinsaregrounded,thedeviceisenabled. 20 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 PRINTED-CIRCUIT BOARD LAYOUT • Connections to other wideband devices on the TECHNIQUES FOR OPTIMAL board may be made with short direct traces or PERFORMANCE through onboard transmission lines. For short connections, consider the trace and the input to Achieving optimum performance with a the next device as a lumped capacitive load. high-frequency amplifier, such as the THS3110 and Relatively wide traces [0.05 inch (1,3 mm) to 0.1 THS3111, requires careful attention to board layout inch (2,54 mm)] should be used, preferably with parasitic and external component types. ground and power planes opened up around Recommendationsthatoptimizeperformanceinclude: them. Estimate the total capacitive load and • Minimize parasitic capacitance to any ac ground determine if isolation resistors on the outputs are for all of the signal I/O pins. Parasitic capacitance necessary. Low parasitic capacitive loads (< 4 pF) on the output and input pins can cause instability. may not need an R since the THS3110 and S To reduce unwanted capacitance, a window THS3111 are nominally compensated to operate around the signal I/O pins should be opened in all with a 2-pF parasitic load. Higher parasitic of the ground and power planes around those capacitive loads without an R are allowed as the S pins. Otherwise, ground and power planes should signal gain increases (increasing the unloaded beunbrokenelsewhereontheboard. phase margin). If a long trace is required, and the • Minimize the distance [< 0.25 inch (6,35 mm)] 6-dB signal loss intrinsic to a doubly-terminated from the power-supply pins to high frequency transmission line is acceptable, implement a 0.1-μF and 100-pF decoupling capacitors. At the matched impedance transmission line using device pins, the ground and power plane layout microstrip or stripline techniques (consult an ECL should not be in close proximity to the signal I/O design handbook for microstrip and stripline layout pins. Avoid narrow power and ground traces to techniques). A 50-Ω environment is not necessary minimize inductance between the pins and the onboard, and in fact, a higher impedance decoupling capacitors. The power-supply environment improves distortion as shown in the connections should always be decoupled with distortion versus load plots. With a characteristic these capacitors. Larger (6.8 μF or more) board trace impedance based on board material tantalum decoupling capacitors, effective at lower and trace dimensions, a matching series resistor frequency, should also be used on the main into the trace from the output of the supply pins. These may be placed somewhat THS3110/THS3111 is used as well as a farther from the device and may be shared among terminating shunt resistor at the input of the severaldevicesinthesameareaofthePCboard. destination device. Remember also that the • Careful selection and placement of external terminating impedance is the parallel combination components preserve the high-frequency of the shunt resistor and the input impedance of performance of the THS3110 and THS3111. the destination device: this total effective Resistors should be a very low reactance type. impedance should be set to match the trace Surface-mount resistors work best and allow a impedance. If the 6-dB attenuation of a tighter overall layout. Again, keep their leads and doubly-terminated transmission line is PC board trace length as short as possible. Never unacceptable, a long trace can be use wirewound-type resistors in a high-frequency series-terminated at the source end only. Treat application. Because the output pin and inverting the trace as a capacitive load in this case. This input pins are the most sensitive to parasitic does not preserve signal integrity as well as a capacitance, always position the feedback and doubly-terminated line. If the input impedance of series output resistors, if any, as close as possible the destination device is low, there is some signal to the inverting input pins and output pins. Other attenuation due to the voltage divider formed by network components, such as input termination theseriesoutputintotheterminatingimpedance. resistors, should be placed close to the • Socketingahigh-speedpartliketheTHS3110and gain-setting resistors. Even with a low parasitic THS3111 is not recommended. The additional capacitance shunting the external resistors, lead length and pin-to-pin capacitance introduced excessively high resistor values can create by the socket can create an extremely significant time constants that can degrade troublesome parasitic network which can make it performance. Good axial metal-film or almost impossible to achieve a smooth, stable surface-mount resistors have approximately 0.2 frequency response. Best results are obtained by pF in shunt with the resistor. For resistor values soldering the THS3110/THS3111 parts directly greater than 2.0 kΩ, this parasitic capacitance can ontotheboard. add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com PowerPAD DESIGN CONSIDERATIONS PowerPAD LAYOUT CONSIDERATIONS The THS3110 and THS3111 are available in a 1. PCB with a top side etch pattern as shown in thermally-enhanced PowerPAD family of packages. Figure 64. There should be etch for the leads as These packages are constructed using a downset wellasetchforthethermalpad. leadframe upon which the die is mounted (see Figure 63a and Figure 63b). This arrangement results 0.205 in the lead frame being exposed as a thermal pad on (5,21) the underside of the package (see Figure 63c). 0.060 Because this thermal pad has direct thermal contact (1,52) 0.017 (0,432) with the die, excellent thermal performance can be 0.013 achieved by providing a good thermal path away from (0,33) the thermal pad. Note that devices such as the THS311x have no electrical connection between the 0.075 0.094 (2,39) PowerPADandthedie. (1,91) 0.025 0.030 (0,64) The PowerPAD package allows for both assembly (0,76) and thermal management in one manufacturing operation. During the surface-mount solder operation 0.010 0.040 (0,254) (1,01) (when the leads are being soldered), the thermal pad 0.035 vias (0,89) canalsobesolderedtoacopperareaunderneaththe package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat Dimensionsareininches(mm). dissipatingdevice. Figure64. DGNPowerPADPCBEtchand ViaPattern The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of 2. Place five holes in the area of the thermal pad. surface mount with the, heretofore, awkward These holes should be 0.01 inch (0,254 mm) in mechanicalmethodsofheatsinking. diameter. Keep them small so that solder wicking throughtheholesisnotaproblemduringreflow. 3. Additional vias may be placed anywhere along DIE the thermal plane outside of the thermal pad Side View (a) Thermal area. This helps dissipate the heat generated by Pad the THS3110/THS3111 IC. These additional vias DIE may be larger than the 0.01-inch (0,254 mm) diameter vias directly under the thermal pad. End View (b) Bottom View (c) They can be larger because they are not in the thermal pad area to be soldered so that wicking Figure63. ViewsofThermalEnhancedPackage isnotaproblem. 4. Connect all holes to the internal ground plane. Although there are many ways to properly heatsink Note that the PowerPAD is electrically isolated the PowerPAD package, the following steps illustrate from the silicon and all leads. Connecting the therecommendedapproach. PowerPAD to any potential voltage such as V , S– is acceptable as there is no electrical connection space tothesilicon. space 5. When connecting these holes to the ground space plane, do not use the typical web or spoke via connection methodology. Web connections have space a high thermal resistance connection that is useful for slowing the heat transfer during space soldering operations. This makes the soldering of space vias that have plane connections easier. In this application, however, low thermal resistance is space desired for the most efficient heat transfer. space Therefore, the holes under the THS3110/THS3111 PowerPAD package should space make their connection to the internal ground space plane with a complete connection around the 22 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 entirecircumferenceoftheplated-throughhole. Maximum power dissipation levels are depicted in 6. The top-side solder mask should leave the Figure65fortheavailablepackages.Thedataforthe terminals of the package and the thermal pad PowerPAD packages assume a board layout that area with its five holes exposed. The bottom-side follows the PowerPAD layout guidelines referenced solder mask should cover the five holes of the above and detailed in the PowerPAD application note thermal pad area. This prevents solder from (literature number SLMA002). Figure 65 also being pulled away from the thermal pad area illustrates the effect of not soldering the PowerPAD to duringthereflowprocess. a PCB. The thermal impedance increases substantially which may cause serious heat and 7. Apply solder paste to the exposed thermal pad performance issues. Be sure to always solder the areaandalloftheICterminals. PowerPADtothePCBforoptimumperformance. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard T = 125°C J surface-mount component. This results in a part thatisproperlyinstalled. POWER DISSIPATION AND THERMAL CONSIDERATIONS The THS3110 and THS3111 incorporate automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately +160°C. When the junction temperature reduces to approximately +140°C, the amplifier turns on again. But, for maximum performance and reliability, the designer must take T -Free-Air Temperature-°C A care to ensure that the design does not exceed a junction temperature of +125°C. Between +125°C ResultsarewithnoairflowandPCBsize=3in×3in(7,62mm× and +150°C, damage does not occur, but the 7,62mm);θ =58.4°C/WforMSOP-8withPowerPAD(DGN);θ JA JA performance of the amplifier begins to degrade and =95°C/WforSOIC-8High-KTestPCB(D);θJA=158°C/Wfor long term reliability suffers. The thermal MSOP-8withPowerPAD,withoutsolder. characteristics of the device are dictated by the Figure65. MaximumPowerDistribution package and the PC board. Maximum power vsAmbientTemperature dissipation for a given package can be calculated usingthefollowingformula. When determining whether or not the device satisfies T -T P = Max A the maximum power dissipation requirement, it is DMax q JA (1) important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often Where: times, this is difficult to quantify because the signal • P isthemaximumpowerdissipationinthe pattern is inconsistent, but an estimate of the RMS DMax amplifier(W) power dissipation can provide visibility into a possible • T istheabsolutemaximumjunction problem. Max temperature(°C) • T istheambienttemperature(°C) DESIGN TOOLS A • θ =θ +θ JA JC CA EvaluationFixtures,SpiceModels,and • θ isthethermalcoefficientfromthesilicon JC ApplicationSupport junctionstothecase(°C/W) • θ isthethermalcoefficientfromthecaseto Texas Instruments is committed to providing its CA ambientair(°C/W) customers with the highest quality of applications support. To support this goal an evaluation board has For systems where heat dissipation is more critical, been developed for the THS3110 and THS3111 the THS3110 and THS3111 are offered in an operational amplifiers. The board is easy to use, MSOP-8 with PowerPAD package offering even allowing for straightforward evaluation of the device. better thermal performance. The thermal coefficient The evaluation board can be ordered through the for the PowerPAD packages are substantially Texas Instruments web site, www.ti.com, or through improvedoverthetraditionalSOIC. yourlocalTexasInstrumentssalesrepresentative. Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS3111 is available through the Texas Instruments web site (www.ti.com). The product information center (PIC) is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is containedinthemodelfileitself. J2 GND TP2 J1 J7 VS+ VS− VS+ FB1 FB2 VS− Figure67. THS3110EVMBoardLayout C5 C3 +C1 C2 + C4 C6 (TopLayer) PD NOTE: The Edge number for the THS3111 is J7 R5 Z1 6445587. R6 R4 0 TP1 Vs+ R8B R3 7 J5 2_ 8 R8A Vin− 3+ 6 J6 R1 4 1 R7A R7B Z2 Vout Vs− J4 Vin+ REF R2 J8 1 Figure66. THS3110EVMCircuitConfiguration Figure68. THS3110EVMBoardLayout (BottomLayer) 24 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 www.ti.com........................................................................................................................................ SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009 Table2.BillofMaterials THS3110DGNandTHS3111DGNEVM REFERENCE PCB MANUFACTURER'S ITEM DESCRIPTION SMDSIZE DESIGNATOR QTY PARTNUMBER(1) 1 Bead,ferrite,3A,80Ω 1206 FB1,FB2 2 (Steward)HI1206N800R-00 Capacitor6.8μF,tantalum, 2 D C1,C2 2 (AVX)TAJD685K035R 35V,10% 3 Open 0805 R5,Z1 2 Capacitor0.1μF,ceramic,X7R,50 4 0805 C3,C4 2 (AVX)08055C104KAT2A V Capacitor100pF,ceramic,NPO, 5 0805 C5,C6 2 (AVX)08051A101JAT2A 100V 6 Resistor,0Ω,1/8W,1% 0805 R6(2) 1 (Phycomp)9C08052A0R00JLHFT 7 Resistor,750Ω,1/8W,1% 0805 R3,R4 2 (Phycomp)9C08052A7500FKHFT 8 Open 1206 R7A,Z2 2 9 Resistor,49.9Ω,1/4W,1% 1206 R2,R8A 2 (Phycomp)9C12063A49R9FKRFT 10 Resistor,53.6Ω,1/4W,1% 1206 R1 1 (Phycomp)9C12063A53R6FKRFT 11 Open 2512 R7B,R8B 2 12 Header,0.1"(2,54mm)CTRS, 3Pos. JP1(2) 1 (Sullins)PZC36SAAN 0.025"(6,35mm)SQpins 13 Shunts JP1(2) 1 (Sullins)SSC02SYAN Jack,bananareceptance, 14 J1,J2,J3 3 (SPC)813 0.25"(6,35mm)dia.hole 15 Testpoint,red J7(2),J8(2),TP1 3 (Keystone)5000 16 Testpoint,black TP2 1 (Keystone)5001 17 Connector,SMAPCBjack J4,J5,J6 3 (Amphenol)901-144-8RFX Standoff,4-40hex, 18 4 (Keystone)1808 0.625"(15,875mm)length Screw,Phillips,4-40, 19 4 SHR-0440-016-SN 0.250"(6,35mm) 20 IC,THS3110 U1 1 (TI)THS3110DGN 21 Board,printed-circuit(THS3110) 1 (TI)EDGE#6445586 22 IC,THS3111 U1 1 (TI)THS3111DGN 23 Board,printed-circuit(THS3111) 1 (TI)EDGE#6445587 (1) Manufacturerpartnumbersareusedfortestpurposesonly. (2) AppliestotheTHS3110DGNEVMonly. ADDITIONAL REFERENCE MATERIAL • PowerPADMadeEasy,applicationbrief(SLMA004) • PowerPADThermally-EnhancedPackage,technicalbrief(SLMA002) • VoltageFeedbackvsCurrentFeedbackAmplifiers,(SLVA051) • CurrentFeedbackAnalysisandCompensation(SLOA021) • CurrentFeedbackAmplifiers:Review,Stability,andApplication(SBOA081) • EffectofParasiticCapacitanceinOpAmpCircuits(SLOA013) • Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications Journalwww.ti.com/sc/analogapps). Copyright©2003–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):THS3110THS3111

THS3110 THS3111 SLOS422E–SEPTEMBER2003–REVISEDOCTOBER2009........................................................................................................................................ www.ti.com REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(May2008)toRevisionE ...................................................................................................... Page • ChangedPower-DownCharacteristics,Power-downquiescentcurrenttestconditionsofV =±15VElectrical S Characteristics ...................................................................................................................................................................... 5 • ChangedPower-DownCharacteristics,PDpinbiascurrentparameterofV =±15VElectricalCharacteristics ............... 5 S • ChangedPower-DownCharacteristics,Power-downquiescentcurrenttestconditionsofV =±5VElectrical S Characteristics ...................................................................................................................................................................... 7 • ChangedPower-DownCharacteristics,PDpinbiascurrentparameterofV =±5VElectricalCharacteristics ................. 7 S • AddedcaptiontitletoFigure56 .......................................................................................................................................... 18 • AddedcaptiontitletoFigure57 .......................................................................................................................................... 18 • AddedcaptiontitletoFigure58 .......................................................................................................................................... 18 • AddedcaptiontitletoFigure59 .......................................................................................................................................... 19 • AddedcaptiontitletoFigure60 .......................................................................................................................................... 19 • ChangedthefirstsentenceofthesecondparagraphofSavingPowerwithPower-DownFunctionalitysection .............. 19 ChangesfromRevisionC(February,2007)toRevisionD ............................................................................................ Page • ChangedV =±15VTransimpedancespecificationsfrom1.5MΩ(typ)to1MΩ(typ);1MΩ(at+25°C)to0.75MΩ; S 0.7MΩ(overtemperature)to0.5MΩ .................................................................................................................................. 4 • ChangedV =±15VInputoffsetvoltagespecificationsfrom1.5mV(typ)to3mV(typ);6mV(at+25°C)to10mV; S 8mV(overtemperature)to12mV ....................................................................................................................................... 4 • ChangedV =±15V+PSRRspecificationsfrom83dBto75dB(typ);from75dBto65dB(at+25°C);from70dB S (overtemperature)to60dB.................................................................................................................................................. 5 • ChangedV =±15V–PSRRspecificationsfrom78dBto69dB(typ);from70dBto60dB(at+25°C);from66dB S (overtemperature)to55dB.................................................................................................................................................. 5 • ChangedV =±5VTransimpedancespecificationsfrom1.6MΩ(typ)to1MΩ(typ);1MΩ(at+25°C)to0.75MΩ; S 0.7MΩ(overtemperature)to0.5MΩ .................................................................................................................................. 6 • ChangedV =±5VInputoffsetvoltagespecificationsfrom3mV(typ)to6mV(typ);6mV(at+25°C)to10mV;8 S mV(overtemperature)to12mV .......................................................................................................................................... 6 • ChangedV =±5V+PSRRspecificationsfrom80dBto71dB(typ);from72dBto62dB(at+25°C);from67dB S (overtemperature)to57dB.................................................................................................................................................. 7 • ChangedV =±5V–PSRRspecificationsfrom75dBto66dB(typ);from67dBto57dB(at+25°C);from62dB S (overtemperature)to52dB.................................................................................................................................................. 7 • CorrectedTypicalCharacteristicfigurenumberingerrorsfrompreviousversion ................................................................ 9 • Updated±15VTransimpedancevsFrequencycharacteristicgraph ................................................................................. 11 26 SubmitDocumentationFeedback Copyright©2003–2009,TexasInstrumentsIncorporated ProductFolderLink(s):THS3110THS3111

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS3110ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3110I & no Sb/Br) THS3110IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIR & no Sb/Br) THS3110IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIR & no Sb/Br) THS3110IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3110I & no Sb/Br) THS3110IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3110I & no Sb/Br) THS3111CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 3111C & no Sb/Br) THS3111CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 3111C & no Sb/Br) THS3111ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3111I & no Sb/Br) THS3111IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3111I & no Sb/Br) THS3111IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIS & no Sb/Br) THS3111IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIS & no Sb/Br) THS3111IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 3111I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS3110IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS3110IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS3111IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS3111IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS3110IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 THS3110IDR SOIC D 8 2500 350.0 350.0 43.0 THS3111IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 THS3111IDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 2.15 1.95 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.846 TYPICAL 1.646 4225480/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.846) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (2.15) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225480/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.846) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (2.15) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.06 X 2.40 0.125 1.846 X 2.15 (SHOWN) 0.15 1.69 X 1.96 0.175 1.56 X 1.82 4225480/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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