(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:8)(cid:9)(cid:8)(cid:10) (cid:11)(cid:12)(cid:13)(cid:12)(cid:7) (cid:14)(cid:12)(cid:13)(cid:3)(cid:15)(cid:16)(cid:11)(cid:13)(cid:17)(cid:18)(cid:19)(cid:4)(cid:20)(cid:21) (cid:17)(cid:22)(cid:17)(cid:20)(cid:16)(cid:23)(cid:3)(cid:18)(cid:16)(cid:3)(cid:14)(cid:19)(cid:23)(cid:19)(cid:18)(cid:17)(cid:20) (cid:15)(cid:16)(cid:22)(cid:24)(cid:21)(cid:25)(cid:18)(cid:21)(cid:25)(cid:12) (cid:26)(cid:19)(cid:18)(cid:27) (cid:19)(cid:22)(cid:18)(cid:21)(cid:25)(cid:22)(cid:17)(cid:20) (cid:25)(cid:21)(cid:28)(cid:21)(cid:25)(cid:21)(cid:22)(cid:15)(cid:21) (cid:17)(cid:22)(cid:14) (cid:13)(cid:23)(cid:17) FEATURES DESCRIPTION (cid:1) 14-Bit Resolution The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 (cid:1) 1, 3, and 8 MSPS Speed Grades Available MSPS, single supply analog-to-digital converters (ADCs) (cid:1) Differential Nonlinearity (DNL) ±0.6 LSB Typ with an internal reference, differential inputs, programmable input gain, and an on-chip (cid:1) Integral Nonlinearity (INL) ±1.5 LSB Typ sample-and-hold amplifier. (cid:1) Internal Reference Implemented with a CMOS process, the device has (cid:1) Differential Inputs outstanding price/performance and power/speed ratios. (cid:1) The THS1401, THS1403, and THS1408 are designed for Programmable Gain Amplifier (cid:1) µP-Compatible Parallel Interface use with 3.3-V systems, and with a high-speed µP- compatible parallel interface, making them the first choice (cid:1) Timing Compatible With TMS320C6000 DSP for solutions based on high-performance DSPs such as (cid:1) 3.3-V Single Supply the TI TMS320C6000 series. (cid:1) Power-Down Mode The THS1401, THS1403, and THS1408 are available in a (cid:1) TQFP-48 package in standard commercial and industrial Monolithic CMOS Design temperature ranges. The THS1401, THS1403, and THS1408 are also available in a PQFP-48 package in APPLICATIONS automotive temperature range, and the THS1408 is (cid:1) xDSL Front Ends available in a PQFP-48 package in military temperature (cid:1) Communication range. (cid:1) Industrial Control (cid:1) Instrumentation (cid:1) Automotive VBG REF+ REF REF− 1.5 V BG IN+ 14 15 PGA 14-Bit Buffer D[13:0] + OV bit 0..7 dB ADC IN− 6 A[1:0] CLK CONTROL CS LOGIC WR OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:13)(cid:25)(cid:16)(cid:14)(cid:30)(cid:15)(cid:18)(cid:19)(cid:16)(cid:22) (cid:14)(cid:17)(cid:18)(cid:17) (cid:5)(cid:31)!"#$%(cid:6)(cid:5)"(cid:31) (cid:5)& ’(##)(cid:31)(cid:6) %& "! *(+,(cid:5)’%(cid:6)(cid:5)"(cid:31) -%(cid:6)). (cid:13)#"-(’(cid:6)& Copyright  1999−2005, Texas Instruments Incorporated ’"(cid:31)!"#$ (cid:6)" &*)’(cid:5)!(cid:5)’%(cid:6)(cid:5)"(cid:31)& *)# (cid:6)/) (cid:6))#$& "! (cid:18))0%& (cid:19)(cid:31)&(cid:6)#($)(cid:31)(cid:6)& &(cid:6)%(cid:31)-%#- 1%##%(cid:31)(cid:6)2. (cid:16)(cid:31) *#"-(’(cid:6)& ’"$*,(cid:5)%(cid:31)(cid:6) (cid:6)" (cid:11)(cid:19)(cid:20)(cid:3)(cid:13)(cid:25)(cid:28)(cid:3)(cid:9)(cid:10)4(cid:9)4(cid:7) %,, *%#%$)(cid:6))#& %#) (cid:6))&(cid:6))- ((cid:31),)&& (cid:13)#"-(’(cid:6)(cid:5)"(cid:31) *#"’)&&(cid:5)(cid:31)3 -")& (cid:31)"(cid:6) (cid:31))’)&&%#(cid:5),2 (cid:5)(cid:31)’,(-) (cid:6))&(cid:6)(cid:5)(cid:31)3 "! %,, *%#%$)(cid:6))#&. "(cid:6)/)#1(cid:5)&) (cid:31)"(cid:6))-. (cid:16)(cid:31) %,, "(cid:6)/)# *#"-(’(cid:6)&(cid:7) *#"-(’(cid:6)(cid:5)"(cid:31) *#"’)&&(cid:5)(cid:31)3 -")& (cid:31)"(cid:6) (cid:31))’)&&%#(cid:5),2 (cid:5)(cid:31)’,(-) (cid:6))&(cid:6)(cid:5)(cid:31)3 "! %,, *%#%$)(cid:6))#&. www.ti.com

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted.(1) Supply voltage, (AV to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V DD Supply voltage, (DV to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V DD Reference input voltage range, VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to AVDD + 0.3 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to AV + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to DVDD + 0.3 V Operating free-air temperature range, T : C-suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Q-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. A[1:0] 40, 41 I Address input AGND 7,8, 44, 45, 46 Analog ground AVDD 2, 43, 47 Analog power supply CLK 32 I Clock input CML 4 Reference midpoint. This pin requires a 0.1-µF capacitor to AGND. CS 37 I Chip select input. Active low. DGND 9, 15, 25, 33, 34 Digital ground DVDD 14, 20, 26, 30, 31, 42 Digital power supply D[13:0] 11, 12, 13, 16, 17, 18, I/O Data inputs/outputs 19, 21, 22, 23, 24, 27, 28, 29 NC 38, 39 No connection; do not use. Reserved. IN+ 48 I Positive differential analog input IN− 1 I Negative differential analog input OE 35 I Output enable. Active low. OV 10 O Out-of-range output REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND. REF− 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND. VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND. WR 36 I Write signal. Active low. 2

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PFB AND PHP PACKAGE (TOP VIEW) DD D D D D DN N N D D N+ AV AG AG AG AV DV A0 A1 NC NC CS I 4847 46 45 4443 42 41 40 39 38 37 IN− 1 36 WR AVDD 2 35 OE VBG 3 34 DGND CML 4 33 DGND REF+ 5 32 CLK REF− 6 31 DVDD AGND 7 30 DVDD AGND 8 29 D0 DGND 9 28 D1 OV 10 27 D2 D13 11 26 DVDD D12 12 25 DGND 1314 15 16 1718 19 20 21 22 23 24 1 DD 0 9 8 7 D 6 5 4 3 D1 VDGN D1 D D DVD D D D D D D D NC − No internal connection AVAILABLE OPTIONS PACKAGED DEVICE TA TQFP PQFP (Power Pad) (PFB) (PHP) THS1401CPFB, 0°C to 70°C THS1403CPFB, — THS1408CPFB THS1401IPFB, −40°C to 85°C THS1403IPFB, — THS1408IPFB THS1401QPHP, −40°C to 125°C — THS1403QPHP, THS1408QPHP −55°C to 125°C — THS1408MPHP 3

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 THERMAL CHARACTERISTICS(1) TYP UNIT PFB package 85.9 TThheerrmmaall rreessiissttaannccee,, jjuunnccttiioonn--ttoo--aammbbiieenntt,, ΘΘJJAA °°CC//WW PHP package 28.8 PFB package 19.6 TThheerrmmaall rreessiissttaannccee,, jjuunnccttiioonn--ttoo--ccaassee,, ΘΘJJCC °°CC//WW PHP package 0.79 (1)Thermal resistance is modeled data, is not production tested, and is given for informational purposes only. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage, AVDD, DVDD 3 3.3 3.6 V High level digital input, VIH 2 3.3 V Low level digital input, VIL 0 0.8 V Load capacitance, CL 5 15 pF THS1401 0.1 1 1 MHz CClloocckk ffrreeqquueennccyy,, ffCCLLKK THS1403 0.1 3 3 MHz THS1408 0.1 8 8 MHz C- and I-suffix 40 50 60 CClloocckk dduuttyy ccyyccllee %% Q- and M-suffix 45 50 55 C-suffix 0 25 70 I-suffix −40 25 85 OOppeerraattiinngg ffrreeee--aaiirr tteemmppeerraattuurree °°CC Q-suffix −40 25 125 M-suffix −55 25 125 4

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply IDDA Analog supply current AVDD = 3.6 V 81 90 mA IDDD Digital supply current DVDD = 3.6 V 5 10 mA Power AVDD = DVDD = 3.6 V 270 360 mW Power down current 20 µA DC Characteristics Resolution 14 Bits DNL Differential nonlinearity ±0.6 ±1 LSB THS1401 ±1.5 ±2.5 THS1403C/I ±1.5 ±2.5 IINNLL IInntteeggrraall nnoonnlliinneeaarriittyy THS1403Q BBeesstt ffiitt ±2 ±3 LLSSBB THS1408C/I ±3 ±5 THS1408Q/M ±3.5 ±7.5 Offset error IN+ = IN−, PGA = 0 dB 0.3 %FSR C and I suffix 1 %FSR GGaaiinn eerrrroorr PPGGAA == 00 ddBB Q and M suffix 1.75 %FSR AC Characteristics ENOB Effective number of bits 11.2 11.5 Bits THS1401/3/8 fi = 100 kHz −81 TTHHDD TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn THS1403/8 fi = 1 MHz −78 ddBB THS1408 fi = 4 MHz −77 THS1401/3/8 fi = 100 kHz 72 SSNNRR SSiiggnnaall--ttoo--nnooiissee rraattiioo THS1403/8 fi = 1 MHz 70 72 ddBB THS1408 fi = 4 MHz 71 THS1401/3/8 fi = 100 kHz 70 SSIINNAADD SSiiggnnaall--ttoo--nnooiissee rraattiioo ++ ddiissttoorrttiioonn THS1403/8 fi = 1 MHz 69 70 ddBB THS1408 fi = 4 MHz 70 THS1401/3/8 fi = 100 kHz 80 THS1403C/I, THS1408C/I 73 80 SSFFDDRR SSppuurriioouuss--ffrreeee ddyynnaammiicc rraannggee ffii == 11 MMHHzz ddBB THS1403Q, THS1408Q/M 71 80 THS1408 fi = 4 MHz 80 Analog input bandwidth 140 MHz 5

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (Cont.) Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Voltage Bandgap voltage, internal mode 1.425 1.5 1.575 V Input impedance 40 kΩ Positive reference voltage, REF+ 2.5 V Negative reference voltage, REF− 0.5 V Reference difference, ∆REF, REF+ − REF− 2 V Accuracy, internal reference 5% Temperature coefficient 40 ppm/°C Voltage coefficient 200 ppm/V Analog Inputs Positive analog input, IN+ 0 AVDD V Negative analog input, IN− 0 AVDD V Analog input voltage difference ∆AIN = IN+ − IN−, VREF = REF+ − REF− −VREF VREF V Input impedance 25 kΩ PGA range 0 7 dB PGA step size 1 dB PGA gain error ±0.25 dB Digital Inputs VIH High-level digital input 2 V VIL Low-level digital input 0.8 V Input capacitance 5 pF Input current ±1 µA Digital Outputs VOH High-level digital output IOH = 50 µA 2.6 V VOL Low-level digital output IOL = 50 µA 0.4 V IOZ Output current, high impedance ±10 µA Clock Timing (CS low) THS1401 0.1† 1 1 MHz ffCCLLKK CClloocckk ffrreeqquueennccyy THS1403 0.1† 3 3 MHz THS1408 0.1† 8 8 MHz td Output delay time 25 ns Latency 9.5 Cycles †This parameter is not production tested for Q- and M-suffix devices. 6

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION sample timing The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results appear on the digital output 9.5 clock cycles after the input signal was sampled. S11 S12 S9 Analog S10 Input tw(CLK) tw(CLK) CLK td Data C1 C2 C3 Out Figure 1. Sample Timing The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available at address 0. The timing of the control signals is described in the following sections. 7

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION read timing (15-pF load) PARAMETER MIN TYP MAX UNIT tsu(OE−ACS) Address and chip select setup time 4 ns ten Output enable 15 ns tdis Output disable 10 ns th(A) Address hold time 1 ns th(CS) Chip select hold time 0 ns NOTE: All timing parameters refer to a 50% level. CS th(CS) OE tsu(OE−ACS) ten tdis D[13:0] DATA O V th(A) A[1:0] X ADDRESS X Figure 2. Read Timing 8

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION write timing (15-pF load) PARAMETER MIN TYP MAX UNIT tsu(WE−CS) Chip select setup time 4 ns tsu(DA) Data and address setup time 29 ns th(DA) Data and address hold time 0 ns th(CS) Chip select hold time 0 ns twH(WE) Write pulse duration high 15 ns NOTE: All timing parameters refer to a 50% level. CS th(CS) WE tsu(WE−CS) tsu(DA) D[13:0] X DATA X th(DA) A X ADDRESS X Figure 3. Write Timing 9

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS POWER SUPPLY CURRENT vs vs FREQUENCY TIME 284 90 282 80 70 280 A m − 60 W 278 nt m re 50 − ur Power 227746 upply C 40 − S 30 C 272 C 20 I 270 10 268 0 0.1 1 10 0 50 100 150 200 250 300 f − Frequency − MHz t − Time − ns Figure 4 Figure 5 FAST FOURIER TRANSFORM 0 fs = 1 MSPS, −20 fI = 100 kHz, −1 dB −40 B d − −60 ut p −80 ut O −100 −120 −140 0 100 200 300 400 500 f − Frequency − kHz Figure 6 10

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 0 −20 fs = 3 MSPS, fI = 1 MHz, −40 −1 dB B d − −60 ut p −80 ut O −100 −120 −140 0.1 0.4 0.7 1 1.3 f − Frequency − MHz Figure 7 FAST FOURIER TRANSFORM 0 fs = 8 MSPS, −20 fI = 1 MHz, −1 dB −40 B d − −60 ut p −80 ut O −100 −120 −140 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 f − Frequency − MHz Figure 8 INTEGRAL NONLINEARITY 2 SB fs = 1 MSPS L 1.5 − rity 1 a e 0.5 n nli 0 o N al −0.5 r g e −1 nt − I −1.5 L N −2 I 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 9 11

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY 2 B S L 1.5 fs = 3 MSPS − rity 1 a e 0.5 n onli 0 N al −0.5 r g e −1 nt − I −1.5 L N −2 I 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 10 INTEGRAL NONLINEARITY 4 B S L 3 fs = 8 MSPS − rity 2 a e 1 n onli 0 N al −1 r g e −2 nt − I −3 L N −4 I 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 11 DIFFERENTIAL NONLINEARITY B S 1 L − 0.8 fs = 1 MSPS y rit 0.6 a e 0.4 n nli 0.2 o N 0 ntial −0.2 e −0.4 r e Diff −0.6 − −0.8 L −1 N D 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 12 12

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY B S 1 L − 0.8 fs = 3 MSPS y rit 0.6 a e 0.4 n nli 0.2 o N 0 ntial −0.2 e −0.4 r e Diff −0.6 − −0.8 NL −1 D 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 13 DIFFERENTIAL NONLINEARITY B S 1 L − 0.8 fs = 8 MSPS y rit 0.6 a e 0.4 n nli 0.2 o N 0 ntial −0.2 e −0.4 r e Diff −0.6 − −0.8 L −1 N D 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 14 13

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION vs vs FREQUENCY FREQUENCY −70 −70 fs = 3 MSPS, fs = 8 MSPS, −72 fI at −1 dB −72 fI at −1 dB B B d d − −74 − −74 n n o o rti −76 rti −76 o o st st Di −78 Di −78 c c ni −80 ni −80 o o m m r r a −82 a −82 H H al al ot −84 ot −84 T T − − D −86 D −86 H H T T −88 −88 −90 −90 10 100 1000 1500 10 100 1000 4000 f − Frequency − Hz f − Frequency − Hz Figure 15 Figure 16 SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE RATIO vs vs FREQUENCY FREQUENCY 80 80 fs = 3 MSPS, fs = 8 MSPS, 78 fI at −1 dB 78 fI at −1 dB B 76 B 76 d d − − atio 74 atio 74 R R e 72 e 72 s s oi oi N 70 N 70 o- o- al-t 68 al-t 68 n n g g − Si 66 − Si 66 R R N 64 N 64 S S 62 62 60 60 10 100 1000 1500 10 100 1000 4000 f − Frequency − Hz f − Frequency − Hz Figure 17 Figure 18 14

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION registers The device contains several registers. The A register is selected by the values of bits A1 and A0: A1 A0 Register 0 0 Conversion result 0 1 PGA 1 0 Offset 1 1 Control Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default values (were applicable) show the state after a power-on reset. Table 1. Conversion Result Register, Address 0, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function MSB ... … … … … … … … … … … … LSB The output can be configured for 2s complement or straight binary format (see D11/control register). The output code is given by: 2s complement: Straight binary: −8192 at ∆IN = −∆REF 0 at ∆IN = −∆REF 0 at ∆IN = 0 8192 at ∆IN = 0 8191 ∆IN = +∆REF − 1 LSB 16383 at ∆IN = + ∆REF − 1 LSB 1LSB(cid:1)2(cid:1)REF 16384 Table 2. PGA Gain Register, Address 1, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X X X X X G2 G1 G0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The PGA gain is determined by writing to G2−0. Gain (dB) = 1dB × G2−0. max = 7dB. The range of G2−0 is 0 to 7. Table 3. Offset Register, Address 2, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X MSB … … … … … … LSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC. 15

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION Table 4. Control Register, Address 3, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES Table 5. Control Register, Address 3, Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWD: Power down 0 = normal operation 1 = power down REF: Reference select 0 = internal reference 1 = external reference FOR: Output format 0 = straight binary 1 = 2s complement TM2−0: Test mode 000 = normal operation 001 = both inputs = REF− 010 = IN+ at VCM (Voltage at CML pin), IN− at REF− 011 = IN+ at REF+, IN− at REF− 100 = normal operation 101 = both inputs = REF+ 110 = IN+ at REF−, IN− at VCM (Voltage at CML pin) 111 = IN+ at REF−, IN− at REF+ OF: Offset correction 0 = enable 1 = disable RES Reserved Must be set to 0. APPLICATION INFORMATION driving the analog input The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR, SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended input. There are three basic input configurations: (cid:1) Fully differential (cid:1) Transformer coupled single-ended to differential (cid:1) Single-ended fully differential configuration In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN−. 22 Ω IN+ 100 pF THS1401/3/8 22 Ω IN− 100 pF Figure 19. Differential Input 16

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass filters to attenuate out of band noise. The input range on both inputs is 0 V to AV . The full-scale value is determined by the voltage reference. The DD positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals −∆REF. ∆IN [V] OUTPUT −∆REF − full scale 0 0 ∆REF + full scale APPLICATION INFORMATION transformer coupled single-ended to differential configuration If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled. The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus increasing the ADC ac performance. 22 Ω IN+ 100 pF R THS1401/3/8 22 Ω IN− CML 100 pF + 1 µF 0.1 µF Figure 20. Transformer Coupled The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: IN [VPEAK] OUTPUT [PEAK] −∆REF − full scale† 0 0 ∆REF + full scale† †n = 1 (winding ratio) The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R = n2 Rs, where Rs is the source impedance and n is the transformer winding ratio. APPLICATION INFORMATION single-ended configuration In this configuration, the input signal is level shifted by ∆REF/2. 17

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 10 kΩ + 10 kΩ REF+ 10 kΩ 10 kΩ 100 pF IN+ THS1401/3/8 − 22 Ω IN− REF− + 100 pF 10 kΩ 10 kΩ Figure 21. Single-Ended With Level Shift The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: ∆IN+ [V] OUTPUT −∆REF − full scale 0 0 ∆REF + full scale Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be trimmed by varying the values of the resistors. Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve (best linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative is described in the following section. APPLICATION INFORMATION AC-coupled single-ended configuration If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 21 is not necessary. 10 kΩ 10 kΩ REF+ 10 kΩ 10 kΩ 100 pF IN+ THS1401/3/8 10 nF − IN− REF− + 22 Ω 100 pF 10 kΩ 10 kΩ Figure 22. Single-Ended With Level Shift Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within the linear region of the op-amp transfer function, thus increasing the overall ac performance. IN [VPEAK] OUTPUT [PEAK] −∆REF − full scale 0 0 ∆REF + full scale Compared to the transformer-coupled configuration, the swing on IN− is twice as big, which can decrease the ac performance (SNR, SFD, and THD). 18

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register), the internal/external reference operation value in the offset register (address 2) is automatically added to the output of the ADC. The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an In order to set the correct value of the offset external precision reference in case very high dc compensation register, the ADC result when the accuracy is needed. input signal is 0 must be read by the host processor and written to the offset register The REF+ and REF+ outputs are given by: (address 2). (cid:3) (cid:4) REF(cid:2)(cid:1) VBG 1(cid:2)2 andREF– test modes 3 The ADC core operation can be tested by If the built-in reference is used, VBG equals 1.5 V selecting one of the available test modes (see which results in REF+ = 2.5 V, REF− = 0.5 V and ∆REF = 2V. control register description). The test modes apply various voltages to the differential input The internal reference can be disabled by writing depending on the setting in the control register. 1 to D12 (REF) in the control register (address 3). The band gap reference is then disconnected and digital I/O can be substituted by a voltage on the VBG pin. The digital inputs and outputs of the THS1401/3/8 programmable gain amplifier ADC are 3-V CMOS compatible. In order to avoid current feed back errors, the capacitive load on The on-chip programmable gain amplifier (PGA) the digital outputs should be as low as possible (50 has eight gain settings. The gain can be changed pF max). Series resistors (100 Ω) on the digital by writing to the PGA gain register (address 1). outputs can improve the performance by limiting The range is 0 to 7dB in steps of one dB. the current during output transitions. The parallel interface of the THS1401/3/8 ADC out of range indication features 3-state buffers, making it possible to The OV output of the ADC indicates an out of directly connect it to a data bus. The output buffers range condition. Every time the difference on the are enabled by driving the OE input low. analog inputs exceeds the differential reference, Refer to the read and write timing diagrams in the this signal is asserted. This signal is updated the parameter measurement information section for same way as the digital data outputs and therefore information on read and write access. subject to the same pipeline delay. offset compensation With the offset register it is possible to automatically compensate system offset errors, including errors caused by additional signal 19

(cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:1) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:9) (cid:18)(cid:27)(cid:12)(cid:1)(cid:2)(cid:29)(cid:10) www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 Revision History DATE REV PAGE SECTION DESCRIPTION 1 — Updated page 1 format and layout. 1 — Moved funtional block diagram from page 2. 2 — Moved Terminal Function table from page 3. 2 — Moved Absolute Maximum table from page 4. 3 — Moved package pinout from page 1. 99//0055 DD 3 — Moved Ordering Options table from page 2. Table 1. In section 2s complement: 8191 (cid:1)IN = − (cid:1)REF − 1 LSB changed to 15 Principles of Operation 8191 (cid:1)IN = +(cid:1)REF − 1 LSB. In section Straight Binary: 16383 at (cid:1)IN = − (cid:1)REF − 1 LSB should be changed to 16383 (cid:1)IN = +(cid:1)REF − 1 LSB Table 5. In section TM2−0: Test Mode: 010 = IN+ at VREF/2, IN− at REF−, 16 Principles of Operation changed to, 010 = IN+ at VCM (Voltage at CML pin), IN− at REF−. Same section: 110 = IN+ at REF−, IN− at VREF/2, changed to, 110 = IN+ at REF−, IN− at VCM (Voltage at CML pin) NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 20

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-0051101NXD ACTIVE HTQFP PHP 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -55 to 125 0051101 & no Sb/Br) NXD THS1401IPFB ACTIVE TQFP PFB 48 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TJ1401 & no Sb/Br) THS1403IPFB ACTIVE TQFP PFB 48 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TJ1403 & no Sb/Br) THS1408IPFB ACTIVE TQFP PFB 48 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TJ1408 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS1408, THS1408M : •Catalog: THS1408 •Enhanced Product: THS1408-EP, THS1408-EP •Military: THS1408M NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 2

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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 36 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ Gage Plane 6,80 9,20 SQ 8,80 0,25 0,05 MIN 0°–7° 1,05 0,95 0,75 Seating Plane 0,45 0,08 1,20 MAX 4073176/B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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