THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 features DA PACKAGE (cid:0) (TOP VIEW) Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal D0 1 32 OV_FL (cid:0) Integrated 16 Word FIFO D1 2 31 RESET (cid:0) Signal-to-Noise and Distortion Ratio: 66 dB D2 3 30 AINP at fI = 2 MHz D3 4 29 AINM (cid:0) Differential Nonlinearity Error: ±1 LSB D4 5 28 REFIN (cid:0) Integral Nonlinearity Error: ±1.5 LSB D5 6 27 REFOUT (cid:0) BVDD 7 26 REFP Auto-Scan Mode for 2 Inputs BGND 8 25 REFM (cid:0) 3-V or 5-V Digital Interface Compatible D6 9 24 AGND (cid:0) Low Power: 216 mW Max D7 10 23 AVDD (cid:0) 5-V Analog Single Supply Operation D8 11 22 CS0 (cid:0) Internal Voltage References...50 PPM/°C D9 12 21 CS1 and ±5% Accuracy RA0/D10 13 20 WR (R/W) (cid:0) RA1/D11 14 19 RD Parallel µC/DSP Interface CONV_CLK (CONVST) 15 18 DVDD applications DATA_AV 16 17 DGND (cid:0) Radar Applications (cid:0) Communications (cid:0) Control Applications (cid:0) High-Speed DSP Front-End (cid:0) Automotive Applications description The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In the single conversion mode, a single and simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal clock oscillator is switched off in the continuous conversion mode. The THS12082C is characterized for operation from 0°C to 70°C, and the THS12082I is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 AVAILABLE OPTIONS PACKAGED DEVICE TA TSSOP (DA) 0°C to 70°C THS12082CDA –40°C to 85°C THS12082IDA functional block diagram AVDD DVDD 3.5 V 2.5 V REFP 1.225 V 1.5 V REF REFOUT REFM DATA_AV REFP REFM OV_FL REFIN BVDD Singalned-E/onrded + 12-Bit 12 FIFO 12 – Pipeline D0 AINP S/H Differential ADC 16 × 12 D1 MUX D2 D3 AINM S/H D4 D5 Buffers D6 D7 D8 D9 CONV_CLK (CONVST) D10/RA0 D11/RA1 CS0 Logic CS1 Control BGND and Register RD Control WR (R/W) RESET AGND DGND 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. AINP 30 I Analog input, single-ended or positive input of differential channel A AINM 29 I Analog input, single-ended or negative input of differential channel A AVDD 23 I Analog supply voltage AGND 24 I Analog ground BVDD 7 I Digital supply voltage for buffer BGND 8 I Digital ground for buffer CONV_CLK 15 I Digital input. This input is used to apply an external conversion clock in the continuous conversion mode. (CONVST) In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14. DGND 17 I Digital ground. Ground reference for digital circuitry. DVDD 18 I Digital supply voltage D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB RA0/D10 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. RA1/D11 14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. OV_FL 32 O Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO. REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. RESET 31 I Hardware reset of the THS12082. Sets the control register to default values. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires a capacitor of 10 µF to AGND for filtering and stability. RD† 19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. WR (R/W)† 20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input (WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section. †The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range: DGND to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V DD BGND to BV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V DD AGND to AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V DD Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AV + 1.5 V DD Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 + AGND to AV + 0.3 V DD Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to BV /DV + 0.3 V DD DD Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C Operating free-air temperature range: THS12082C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C THS12082I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions power supply MIN NOM MAX UNIT AVDD 4.75 5 5.25 Supply voltage DVDD 3 3.3 5.25 V BVDD 3 3.3 5.25 analog and reference inputs MIN NOM MAX UNIT Analog input voltage in single-ended configuration VREFM VREFP V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,VREFP (optional) 3.5 AVDD–1.2 V External reference voltage, VREFM (optional) 1.4 1.5 V Input voltage difference, REFP – REFM 2 V digital inputs MIN NOM MAX UNIT BVDD = 3 V 2 V HHiigghh-lleevveell iinnppuutt vvoollttaaggee, VVIIHH BVDD = 5.25 V 2.6 V BVDD = 3 V 0.6 V LLooww-lleevveell iinnppuutt vvoollttaaggee, VVIILL BVDD = 5.25 V 0.6 V Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 8 MHz CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 3 V to 5.25 V 62 83 5000 ns CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 3 V to 5.25 V 62 83 5000 ns THS12082CDA 0 70 OOppeerraattiinngg ffrreeee-aaiirr tteemmppeerraattuurree, TTAA °°CC THS12082IDA –40 85 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 electrical characteristics over recommended operating conditions, V = 3.5 V, V = 1.5 V REFP REFM (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital inputs IIH High-level input current DVDD = digital inputs –50 50 µA IIL Low-level input current Digital input = 0 V –50 50 µA Ci Input capacitance 5 pF Digital outputs VOH High-level output voltage IOH = –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V VOL Low-level output voltage IOL = 50 µA, BVDD = 3.3 V, 5 V 0.4 V IOZ High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA CO Output capacitance 5 pF CL Load capacitance at databus D0–D11 30 pF electrical characteristics over recommended operating conditions, AV = 5 V, DD DV = BV = 3.3-V, f = 8 MSPS, V = internal (unless otherwise noted) DD DD s REF dc specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bits Accuracy Integral nonlinearity, INL ±1.5 LSB Differential nonlinearity, DNL ±1 LSB After calibration in single-ended mode 20 LSB OOffffsseett eerrrroorr After calibration in differential mode –20 20 LSB Gain error –20 20 LSB Analog input Input capacitance 15 pF Input leakage current VAIN = VREFM to VREFP ±10 µA Internal voltage reference Accuracy, VREFP 3.3 3.5 3.7 V Accuracy, VREFM 1.4 1.5 1.6 V Temperature coefficient 50 PPM/°C Reference noise 100 µV Accuracy, REFOUT 2.475 2.5 2.525 V Power supply IDDA Analog supply current AVDD =5 V, BVDD = DVDD = 3.3 V 36 40 mA IDDD Digital supply current AVDD = 5 V BVDD = DVDD = 3.3 V 0.5 1 mA IDDB Buffer supply current AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA IDD_AP Analog supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 8 mA Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 electrical characteristics over recommended operating conditions, V = internal, f = 8 MSPS, REF s f = 2 MHz at –1dBFS (unless otherwise noted) I ac specifications, AV = 5 V, BV = DV = 3.3 V, C < 30 pF DD DD DD L PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential mode 63 65 dB SSIINNAADD SSiiggnnaall-ttoo-nnooiissee rraattiioo ++ ddiissttoorrttiioonn Single-ended mode (see Note 1) 64 dB Differential mode 64 69 dB SSNNRR SSiiggnnaall-ttoo-nnooiissee rraattiioo Single-ended mode (see Note 1) 68 dB Differential mode –70 –67 dB TTHHDD TToottaall hhaarrmmoonniicc ddiissttoorrttiioonn Single-ended mode –68 dB ENOB Differential mode 10.17 10.5 Bits EEffffeeccttiivvee nnuummbbeerr ooff bbiittss (SNR) Single-ended mode (see Note 1) 10.34 Bits Differential mode 67 71 dB SSFFDDRR SSppuurriioouuss ffrreeee ddyynnaammiicc rraannggee Single-ended mode 69 dB Analog Input Full-power bandwidth with a source impedance of 150 Ω Full scale sinewave, –3 dB 96 MHz in differential configuration. Full-power bandwidth with a source impedance of 150 Ω Full scale sinewave, –3 dB 54 MHz in single-ended configuration. Small-signal bandwidth with a source impedance of 100 mVpp sinewave, –3 dB 96 MHz 150 Ω in differential configuration. Small-signal bandwidth with a source impedance of 100 mVpp sinewave, –3 dB 54 MHz 150 Ω in single-ended configuration. NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing specifications (AV = BV = DV = 5 V, V = 3.5 V, V = 1.5 V, C < 30 pF )† DD DD DD REFP REFM L PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA_AV) Delay time 5 ns td(o) Delay time 5 ns CONV td(pipe) Latency 5 CLK †Refer to Figure 2 timing specification of the single conversion mode‡ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tc Clock cycle of the internal clock oscillator 117 125 133 ns 1 analog input 1.5×tc tt11 PPuullssee dduurraattiioonn, CCOONNVVSSTT nnss 2 analog inputs 2.5×tc tdA Aperture time 1 ns Time between consecutive start of singgle 1 analog input 2×tc tt22 nnss conversion 2 analog inputs 3×tc 1 analog input, TL = 1 6.5×tc+15 nnss 2 analog inputs, TL = 2 7.5×tc+15 1 analog input, TL = 4 3×t2 +6.5×tc+15 nnss Delayy time,, DATA__AV becomes active for the 2 analog inputs, TL = 4 t2 +7.5×tc+15 ttdd((DDAATTAA_AAVV)) trigger level condition: TRIG0 = 1, TRIG1 = 1 1 analog input, TL = 8 7×t2 +6.5×tc+15 nnss 2 analog inputs, TL = 8 3×t2 +7.5×tc+15 1 analog input, TL = 14 13×t2 +6.5×tc+15 nnss 2 analog inputs, TL = 12 5×t2 +7.5×tc+15 ‡Refer to Figure 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 detailed description reference voltage The THS12082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. analog inputs The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed. analog-to-digital converter The THS12082 uses a 12-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit stages, which achieves a high sample rate with low power consumption. The THS12082 distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. data_av In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of CONV_CLK after a FIFO reset command. This is due to the latency of the pipeline architecture of the THS12082. conversion modes The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations. Table 1. Maximum Conversion Rate MAXIMUM CONVERSION CHANNEL CONFIGURATION NUMBER OF CHANNELS RATE PER CHANNEL 1 single-ended channel 1 8 MSPS 2 single-ended channels 2 4 MSPS 1 differential channel 1 8 MSPS The maximum conversion rate in the continuous conversion mode per channel, fc, is given by: (cid:0) 8 MSPS fc # channels Table 2 shows the maximum conversion rate in the single conversion mode. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 sampling rate (continued) Table 2. Maximum Conversion Rate in Single Conversion Mode† NUMBER OF MAXIMUM CONVERSION CHANNEL CONFIGURATION CHANNELS RATE PER CHANNEL 1 single-ended channel 1 4 MSPS 2 single-ended channels 2 2.67 MSPS 1 differential channel 1 4 MSPS †Maximum conversion rate with respect to the typical internal oscillator speed [i.e., 8 MHz × (tc/t2)]. In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1. A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13. Figure 1 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be selected to be sampled simultaneously (see Table 2). t2 CONVST t1 t1 td(A) AIN Sample N tDATA_AV DATA_AV, Trigger Level = 1 Figure 1. Timing of Single Conversion Mode The time (t ) between consecutive starts of single conversions is dependent on the number of selected analog 2 input channels. The time t , until DATA_AV becomes active is given by: t = t + n ×t . This DATA_AV DATA_AV pipe c equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer to the timing specifications of single conversion mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 continuous conversion mode The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO. Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 8 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set to 1 or 4. Sample N Sample N+1 Sample N+2 Sample N+3 Sample N+4 Sample N+5 Sample N+6 Sample N+7 Sample N+8 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) 50% 50% CONV_CLK tc td(O) Data Into Data N–5 Data N–4 Data N–3 Data N–2 Data N–1 Data N Data N+1 Data N+2 Data N+3 FIFO Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 td(DATA_AV) DATA_AV, Trigger Level = 1 td(DATA_AV) DATA_AV, Trigger Level = 4 Figure 2. Timing of Continuous Conversion Mode (1-channel operation) Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4. Sample N Sample N+1 Sample N+2 Sample N+3 Sample N+4 Channel 1,2 Channel 1,2 Channel 1,2 Channel 1,2 Channel 1,2 AIN td(A) td(Pipe) tw(CONV_CLKH) tw(CONV_CLKL) 50% 50% CONV_CLK tc td(O) Data Into Data N–3 Data N–2 Data N–2 Data N–1 Data N–1 Data N Data N Data N+1 Data N+1 FIFO Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 td(DATA_AV) DATA_AV, Trigger Level = 2 td(DATA_AV) DATA_AV, Trigger Level = 4 Figure 3. Timing of Continuous Conversion Mode (2-channel operation) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 digital output data format The digital output data format of the THS12082 can be in either binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 3. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP FFFh AIN = (VREFP + VREFM)/2 800h AIN = VREFM 000h Table 4. Twos Complement Output Format for Single-Ended Configuration SINGLE-ENDED, TWOS COMPLEMENT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP 7FFh AIN = (VREFP + VREFM)/2 000h AIN = VREFM 800h Table 5. Binary Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP – AINM VREF = VREFP – VREFM Vin = VREF FFFh Vin = 0 800h Vin = –VREF 000h Table 6. Twos Complement Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP – AINM VREF = VREFP – VREFM Vin = VREF 7FFh Vin = 0 000h Vin = –VREF 800h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 FIFO description In order to facilitate an efficient connection to today’s processors, the THS12082 is supplied with a FIFO. This integrated FIFO enables a problem-free processing of data. The FIFO is provided as a flexible circular buffer. The circular buffer integrated in the THS12082 can store up to 16 conversion values. Therefore, the number of interrupts to be served by a processor can be reduced significantly. 16 1 15 2 14 Read Pointer 3 13 4 12 5 Trigger Pointer 11 6 Data in FIFO 10 7 9 8 Free Write Pointer Figure 4. Circular Buffer The converted data of the THS12082 is automatically written into the FIFO. To control the writing and reading process, a write pointer, a read pointer, and a trigger pointer are used. The read pointer always shows the location which will be read next. The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is continually maintained. The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger level from Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values as selected for the trigger level where written into the FIFO. The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel according to the autoscan mode, which is shown in Table 10. The channel information is therefore always maintained. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 reading data from the FIFO The THS12082 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion values is ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle of reading the data. In Figure 5, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 5. Trigger Level 1 Selected In Figure 6, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 6. Trigger Level 4 Selected In Figure 7, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 7. Trigger Level 8 Selected In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse. CONV_CLK DATA_AV READ Figure 8. Trigger Level 14 Selected READ is always the logical combination of CS0, CS1 and RD. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 ADC control register The THS12082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7. Table 7. Bit Definitions of Control Register CR0 and CR1 REG BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF CR1 RBACK OFFSET BIN/2’s R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET writing to control register 0 and control register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control register. Table 8. Control Register Addressing D0 – D9 D10/RA0 D11/RA1 Addressed Control Register Desired register value 0 0 Control register 0 Desired register value 1 0 Control register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 initialization of the THS12082 The initialization of the THS12082 should be done according to the configuration flow shown in Figure 9. Start No Use Default Values? Yes Write 0x401 to Write 0x401 to THS12082 THS12082 (Set Reset Bit in (Set Reset Bit in CR1) CR1) Clear RESET By Clear RESET By Writing 0x400 to Writing 0x400 to CR1 CR1 Write the User Configuration to CR0 Write the User Configuration to CR1 (Can Include FIFO Reset, Must Exclude RESET) Continue Figure 9. THS12082 Configuration Flow POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 ADC control registers control register 0 (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF Table 9. Control Register 0 Bit Functions RESET BITS NAME FUNCTION VALUE 0 0 VREF Vref select: Bit 0 = 0 → The internal reference is selected. Bit 0 = 1 → The external reference voltage is selected. 1 0 MODE Continuous conversion mode/single conversion mode Bit 1 = 0 → Continuous conversion mode is selected. An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 → Single conversion mode is selected. In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the THS12082 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is satisfied. 2 0 PD Power down. Bit 2 = 0 → The ADC is active. Bit 2 = 1 → Power down The reading and writing to and from the digital outputs is possible during power down. It is also possible to read out the FIFO. 3, 4 0,0 CHSEL0, Channel select CHSEL1 Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10. 5,6 1,0 DIFF0, DIFF1 Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10. 7 0 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10. 8,9 0,0 TEST0, Test input enable TEST1 Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation. Refer to Table 11 for selection of the three different test voltages. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 analog input channel selection The analog input channels of the THS12082 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections. Table 10. Analog Input Channel Configurations BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 DESCRIPTION OF THE SELECTED INPUTS AS DF1 DF0 CHS1 CHS0 0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Reserved 0 0 0 1 1 Reserved 0 0 1 0 0 Differential channel (AINP–AINM) 0 0 1 0 1 Reserved 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, … 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 1 0 0 1 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11. Table 11. Test Mode BIT 9 BIT 8 OUTPUT RESULT TEST1 TEST0 0 0 Normal mode 0 1 VREFP 1 0 ((VREFM)+(VREFP))/2 1 1 VREFM Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 analog input channel selection (continued) control register 1 (see Table 8) BIT11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 RBACK OFFSET BIN/2s R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET Table 12. Control Register 1 Bit Functions RESET BITS NAME FUNCTION VALUE 0 0 RESET Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first value is converted and written into the FIFO. 1 0 OVFL Overflow flag (read only) (read only) Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 → no overflow occurred. Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor. FRST FRST: FIFO reset (write only) (write only) By writing a 1 into this bit, the FIFO is reset. 2, 3 0,0 TRIG0, FIFO trigger level TRIG1 Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This indicates to the processor that the ADC values can be read. Refer to Table 13. 4 1 DATA_T DATA_AV type Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a pulse. Refer to Table 14. 5 1 DATA_P DATA_AV polarity Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0, DATA_AV is active low. Refer to Table 14. 6 0 R/W R/W, RD/WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. 7 0 BIN/2s Complement select If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6. 8 0 OFFSET Offset cancellation mode Bit 8 = 0 → normal conversion mode Bit 8 = 1 → offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a con- version. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error. 9 0 RBACK Debug mode Bit 9 = 0 → normal conversion mode Bit 9 = 1 → enable debug mode When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 FIFO trigger level Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read. Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be selected, is dependent on the number of input channels. Either a differential or a single-ended input is considered as one channel. The processor, therefore, always reads the data from the FIFO in the same order and is able to distinguish between the channels. Table 13. FIFO Trigger Level TRIGGER LEVEL TRIGGER LEVEL BIT 3 BIT 2 FOR 1 CHANNEL FOR 2 CHANNELS TRIG1 TRIG0 (ADC values) (ADC values) 0 0 01 02 0 1 04 04 1 0 08 8 1 1 14 12 timing and signal description of the THS12082 The reading from the THS12082 and writing to the THS12082 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS12082 takes place by an internal RD signal, which is generated from the logical int combination of the external signals CS0, CS1 and RD (see Figure 10). This signal is then used to strobe the words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RD active while the write input (WR) is inactive. The first of those external signals going int to its inactive state will then deactivate RD again. int Writing to the THS12082 takes place by an internal WR signal, which is generated from the logical combination int of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WR active while int the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate WR again. int CS0 Read Enable CS1 RD Write Enable WR Control/Data Registers Data Bits Figure 10. Logical Combination of CS0, CS1, RD, and WR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 DATA_AV type Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in Table 14. Table 14. DATA_AV Type BIT 5 BIT 4 DATA_AV TYPE DATA_P DATA_T 0 0 Active low level 0 1 Active low pulse 1 0 Active high level 1 1 Active high pulse The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of the DATA_T selection (pulse or level). If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of READ). The trigger condition is checked again after TL reads. For single conversion mode, DATA_AV type should be programmed to active level mode (set bit 4 of CR1 to zero). If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous conversion mode. When the TL values previously written into the FIFO were read out by the processor, the next DATA_AV pulse (when the trigger condition is satisfied) is sent out first. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing and signal description of the THS12082 read timing (using R/W, CS0-controlled) Figure 11 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid. tw(CS) 90% CS0 10% 10% CS1 ÎÎÎ tsu(R/W) th(R/W) ÏÏÏ ÎÎÎ90% 90Ï% ÏÏ R/W ÎÎÎ ÏÏÏ RD ta th 90% 90% D(0–11) td(CSDAV) 90% DATA_AV Figure 11. Read Timing Diagram Using R/W (CS0-controlled) read timing parameter (CS0-controlled)† PARAMETER MIN TYP MAX UNIT tsu(R/W) Setup time, R/W high to last CS valid 0 ns ta Access time, last CS valid to data valid 0 10 ns td(CSDAV) Delay time, last CS valid to DATA_AV inactive 12 ns th Hold time, first CS invalid to data invalid 0 5 ns th(R/W) Hold time, first external CS invalid to R/W change 5 ns tw(CS) Pulse duration, CS active 10 ns †CS = CSO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing and signal description of the THS12082 (continued) write timing (using R/W, CS0-controlled) Figure 12 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid. tw(CS) 90% CS0 10% 10% CS1 tsu(R/W) th(R/W) ÎÎÎ ÎÎÎ WR ÎÎÎ ÎÎÎ RD tsu th 90% 90% D(0–11) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ DATA_AV ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Figure 12. Write Timing Diagram Using R/W (CS0-controlled) write timing parameter (CSO-controlled)† PARAMETER MIN TYP MAX UNIT tsu(R/W) Setup time, R/W stable to last CS valid 0 ns tsu Setup time, data valid to first CS invalid 5 ns th Hold time, first CS invalid to data invalid 2 ns th(R/W) Hold time, first CS invalid to R/W change 5 ns tw(CS) Pulse duration, CS active 10 ns †CS = CSO 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing and signal description of the THS12082 (continued) interfacing the THS12082 to the TMS320C30/31/33 DSP The following application circuit shows an interface of the THS12082 to the TMS320C30/31/33 DSPs. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. THS12082 TMS320C30/31/33 DVDD CS0 STRB CS1 A23 RD R/W R/W DATA_AV INTX CONV_CLK TOUT DATA DATA interfacing the THS12082 to the TMS320C54x using I/O strobe The following application circuit shows an interface of the THS12082 to the TMS320C54x. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface. THS12082 TMS320C54x DVDD CS0 I/O STRB CS1 A15 RD R/W R/W DATA_AV INTX CONV_CLK BCLK DATA DATA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing and signal description of the THS12082 (continued) read timing (using RD, RD-controlled) Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD that becomes valid. CS0 CS1 tsu(CS) th(CS) ÎÎÎÎÎ ÏÏÏÏ WRÎÎÎÎÎ ÏÏÏÏ tw(RD) RD 10% 10% ta th 90% 90% D(0–11) td(CSDAV) 90% DATA_AV Figure 13. Read Timing Diagram Using RD (RD-controlled) read timing parameter (RD-controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) Setup time, RD low to last CS valid 0 ns ta Access time, last CS valid to data valid 0 10 ns td(CSDAV) Delay time, last CS valid to DATA_AV inactive 12 ns th Hold time, first CS invalid to data invalid 0 5 ns th(CS) Hold time, RD change to first CS invalid 5 ns tw(RD) Pulse duration, RD active 10 ns 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 timing and signal description of the THS12082 (continued) write timing (using WR, WR-controlled) Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR that becomes valid. CS0 CS1 tsu(CS) th(CS) tw(WR) WR 10% 10% ÎÎÎÎ ÏÏÏÏ RD ÎÎÎÎ ÏÏÏÏ tsu th 90% 90% D(0–11) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ DATA_AV ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Figure 14. Write Timing Diagram Using WR (WR-controlled) write timing parameter using WR (WR-controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) Setup time, CS stable to last WR valid 0 ns tsu Setup time, data valid to first WR invalid 5 ns th Hold time, WR invalid to data invalid 2 ns th(CS) Hold time, WR invalid to CS change 5 ns tw(WR) Pulse duration, WR active 10 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 interfacing the THS12082 to the TMS320C6201 DSP The following application circuit shows an interface of the THS12082 to the TMS320C6201. The read (using RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface. THS12082–1 TMS320C6201 CS0 CE1 CS1 EA20 RD ARE WR AWE DATA_AV EXT_INT6 DATA DATA CONV_CLK TOUT1 TOUT2 EA21 THS12082–2 EXT_INT7 CS0 CS1 RD WR DATA_AV DATA CONV_CLK analog input configuration and reference voltage The THS12082 features two analog input channels. These can be configured for either single-ended or differential operation. Best performance is achieved in differential mode. Figure 15 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are V and V (either internal or external reference voltage). The analog input voltage range goes from REFP REFM V to V . This means that V defines the minimum voltage, which can be applied to the ADC. V REFM REFP REFM REFP defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage V of 1.5 V and the voltage V of 3.5 V. The resulting analog input voltage swing of 2 V can be REFM REFP expressed by: V (cid:0)AINP(cid:0)V REFM REFP (1) VREFP 12-Bit AINP ADC VREFM Figure 15. Single-Ended Input Stage 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 analog input configuration and reference voltage (continued) A differential operation is desired for many applications. Figure 16 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which are discussed in the following paragraphs. VREFP AINP + Σ VADC 12-Bit ADC – AINM VREFM Figure 16. Differential Input Stage In comparison to the single-ended configuration it can be seen that the voltage, V , which is applied at the ADC input of the ADC, is the difference between the input AINP and AINM. This means that V defines the REFM minimum voltage (V ), which can be applied to the ADC. V defines the maximum voltage (VADC), which ADC REFP can be applied to the ADC. The voltage V can be calculated as follows: ADC (cid:0) V ABS(AINP–AINM) ADC (2) An advantage to single-ended operation is that the common-mode voltage (cid:0)AINM(cid:0)AINP V CM 2 (3) can be rejected in the differential configuration, if the following condition for the analog input voltages is true: AGND(cid:2)AINM, AINP(cid:2)AV DD (4) 1 V(cid:2)V (cid:2)4 V CM (5) In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection, which is common to both analog inputs. See also Figure 18. single-ended mode of operation The THS12082 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the THS12082 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS12082 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc- and ac-coupling. An application example is shown for dc-coupled level shifting in the following section, dc-coupling. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 dc coupling An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS12082. The analog input voltage range of the THS12082 goes from 1.5 V to 3.5 V. An operational amplifier specified for 5-V single supply can be used as shown in Figure 17. Figure 17 shows an application example where the analog input signal in the range from –1 V up to 1 V is shifted by an operational amplifier to the analog input range of the THS12082 (1.5 V to 3.5 V). The operational amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS12082 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors. R 3.5 V 2.5 V 5 V 1.5 V 1 V R 0 V _ RS THS12082 AINP –1 V 1.25 V + REFIN REFOUT R R Figure 17. Level-Shift for DC-Coupled Input differential mode of operation For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode. Mini Circuits T4–1 49.9 Ω R THS12082 AINP C 200 Ω R AINM C REFOUT Figure 18. Transformer Coupled Input 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs SAMPLING FREQUENCY (SINGLE-ENDED) SAMPLING FREQUENCY (SINGLE-ENDED) 80 70 B d 75 – B n 65 d o n – 70 orti Distortio 65 and Dist 60 onic 60 oise 55 m N al Har 55 nal-to- 50 Tot 50 Sig HD – 45 AVDD = 5 V, DVDD = BVDD = 3 V, AD – 45 AVfDIND = = 5 50 0V ,k DHVzD, ADI N= =B V–D1 Dd B=F 3S V, T fIN = 500 kHz, AIN = –1 dBFS N SI 40 40 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz fs – Sampling Frequency – MHz Figure 19 Figure 20 SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE vs vs SAMPLING FREQUENCY (SINGLE-ENDED) SAMPLING FREQUENCY (SINGLE-ENDED) 90 70 B – d 85 e 65 g n 80 a B R d c 75 – mi e 60 s na 70 oi y N ree D 65 al-to- 55 F n us 60 Sig urio 55 R – 50 p N S S R – 50 45 AVDD = 5 V, DVDD = BVDD = 3 V, D fIN = 500 kHz, AIN = –1 dBFS SF 45 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –1 dBFS 40 40 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz fs – Sampling Frequency – MHz Figure 21 Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs SAMPLING FREQUENCY (DIFFERENTIAL) SAMPLING FREQUENCY (DIFFERENTIAL) 85 80 B 80 d – 75 B n n – d 75 ortio 70 ortio 70 Dist Dist 65 and 65 c e moni 60 Nois 60 al Har 55 nal-to- 55 Tot 50 Sig 50 – – D D TH 45 AVfDIND = = 5 50 0V ,k DHVzD, ADI N= =B V–D1 Dd B=F 3S V, SINA 45 AVfDIND = = 5 50 0V ,k DHVzD, ADI N= =B V–D1 Dd B=F 3S V, 40 40 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz fs – Sampling Frequency – MHz Figure 23 Figure 24 SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE vs vs SAMPLING FREQUENCY (DIFFERENTIAL) SAMPLING FREQUENCY (DIFFERENTIAL) 100 80 B d 95 – 75 ge 90 n Ra 85 dB 70 c – mi 80 e na ois 65 y 75 N ree D 70 al-to- 60 F n us 65 Sig 55 urio 60 R – Sp 55 SN 50 – R 50 AVDD = 5 V, DVDD = BVDD = 3 V, AVDD = 5 V, DVDD = BVDD = 3 V, FD fIN = 500 kHz, AIN = –1 dBFS 45 fIN = 500 kHz, AIN = –1 dBFS S 45 40 40 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz fs – Sampling Frequency – MHz Figure 25 Figure 26 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs INPUT FREQUENCY (SINGLE-ENDED) INPUT FREQUENCY (SINGLE-ENDED) 80 80 B AVDD = 5 V, DVDD = BVDD = 3 V, – d 75 dB 75 fs = 8 MSPS, AIN = –1 dBFS n – o n storti 70 ortio 70 Di st c 65 Di 65 ni d o n rm 60 e a 60 a s al H 55 Noi ot o- 55 – T al-t THD 50 Sign 50 45 AVDD = 5 V, DVDD = BVDD = 3 V, D – 45 fs = 8 MSPS, AIN = –1 dBFS A N 40 SI 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz fi – Input Frequency – MHz Figure 27 Figure 28 SIGNAL-TO-NOISE SPURIOUS FREE DYNAMIC RANGE vs vs INPUT FREQUENCY (SINGLE-ENDED) INPUT FREQUENCY (SINGLE-ENDED) 80 100 – dB 95 AVDfsD = = 8 5 M VS, PDSV,D ADIN = =B –V1D dDB =F S3 V, 75 AVDfsD = = 8 5 M VS, PDSV,D ADIN = =B –V1D dDB =F S3 V, ge 90 Ran 85 dB 70 ynamic 7850 Noise – 65 D o- ee 70 al-t 60 Fr n us 65 Sig 55 urio 60 R – p N 50 S 55 S – R 50 D 45 F S 45 40 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz fi – Input Frequency – MHz Figure 29 Figure 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs INPUT FREQUENCY (DIFFERENTIAL) INPUT FREQUENCY (DIFFERENTIAL) 80.00 80.00 B AVDD = 5 V, DVDD = BVDD = 3 V, dB 75.00 – d 75.00 fs = 8 MSPS, AIN = –1 dBFS – n n o ortio 70.00 storti 70.00 st Di Di 65.00 d 65.00 c n oni e a m 60.00 s 60.00 r oi a N otal H 55.00 al-to- 55.00 T n HD – 50.00 – Sig 50.00 T AVDD = 5 V, DVDD = BVDD = 3 V, D 45.00 fs = 8 MSPS, AIN = –1 dBFS NA 45.00 SI 40.00 40.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz fi – Input Frequency – MHz Figure 31 Figure 32 SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE vs vs INPUT FREQUENCY (DIFFERENTIAL) INPUT FREQUENCY (DIFFERENTIAL) 100.00 80.00 dB 95.00 AVDD = 5 V, DVDD = BVDD = 3 V, AVDD = 5 V, DVDD = BVDD = 3 V, e – 90.00 fs = 8 MSPS, AIN = –1 dBFS 75.00 fs = 8 MSPS, AIN = –1 dBFS g n mic Ra 8805..0000 e – dB 70.00 yna 75.00 Nois 65.00 s Free D 6750..0000 gnal-to- 60.00 ou Si 55.00 uri 60.00 R – – Sp 55.00 SN 50.00 R 50.00 D F 45.00 S 45.00 40.00 40.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz fi – Input Frequency – MHz Figure 33 Figure 34 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs vs SAMPLING FREQUENCY (SINGLE-ENDED) SAMPLING FREQUENCY (DIFFERENTIAL) 12 12 AVDD = 5 V, DVDD = BVDD = 3 V, s fin = 500 kHz, AIN = –1 dBFS s Bit 11 Bit 11 – – s s Bit Bit of 10 of 10 r r e e b b m m u 9 u 9 N N e e v v cti cti e 8 e 8 Eff Eff – – B B O 7 O 7 AVDD = 5 V, DVDD = BVDD = 3 V, N N fin = 500 kHz, AIN = –1 dBFS E E 6 6 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 fs – Sampling Frequency – MHz fs – Sampling Frequency – MHz Figure 35 Figure 36 EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs vs INPUT FREQUENCY (SINGLE-ENDED) INPUT FREQUENCY (DIFFERENTIAL) 12 12 AVDD = 5 V, DVDD = BVDD = 3 V, AVDD = 5 V, DVDD = BVDD = 3 V, s fs = 8 MSPS, AIN = –1 dBFS s fs = 8 MSPS, AIN = –1 dBFS Bit 11 Bit 11 – – s s Bit Bit of 10 of 10 r r e e b b m m u 9 u 9 N N e e v v cti cti e 8 e 8 Eff Eff – – B B O 7 O 7 N N E E 6 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi – Input Frequency – MHz fi – Input Frequency – MHz Figure 37 Figure 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs ADC CODE B S 1.00 – L 0.80 AVDD = 5 V y DVDD = BVDD = 3 V rit 0.60 fs = 8 MSPS a e 0.40 n nli 0.20 o N –0.00 ntial –0.20 e –0.40 r e Diff –0.60 – –0.80 NL –1 D 0 500 1000 1500 2000 2500 3000 3500 4000 ADC Code Figure 39 INTEGRAL NONLINEARITY vs ADC CODE 1.00 B LS 0.80 y – 0.60 rit 0.40 a e n 0.20 nli –0.00 o N al –0.20 gr –0.40 nte –0.60 AVDD = 5 V L – I –0.80 fDsV =D 8D M=S BPVSDD = 3 V N –1 I 0 500 1000 1500 2000 2500 3000 3500 4000 ADC Code Figure 40 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY 0 –20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS B –40 fin = 1.25 MHz d – e –60 d u nit –80 g a M –100 –120 –140 0 1000000 2000000 3000000 4000000 f – Frequency – Hz Figure 41 FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY 0 AVDD = 5 V, DVDD = BVDD = 3 V, –20 fs = 8 MSPS, AIN = –1 dBFS B –40 fin = 1.25 MHz d – e –60 d u nit –80 g a M –100 –120 –140 0 1000000 2000000 3000000 4000000 f – Frequency – Hz Figure 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 definitions of specifications and terminology integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. zero offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. gain error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, (cid:0) (cid:0)(SINAD 1.76) N 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 MECHANICAL DATA DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 38 PINS SHOWN 0,30 0,65 0,13 M 0,19 38 20 6,20 8,40 NOM 7,80 0,15 NOM Gage Plane 1 19 0,25 A 0°–8° 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 28 30 32 38 DIM A MAX 9,80 11,10 11,10 12,60 A MIN 9,60 10,90 10,90 12,40 4040066/D 11/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37

PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 5962-0051901NXD PREVIEW TSSOP DA 32 TBD CallTI CallTI THS12082CDA ACTIVE TSSOP DA 32 46 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082CDAG4 ACTIVE TSSOP DA 32 46 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082CDAR ACTIVE TSSOP DA 32 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082CDARG4 ACTIVE TSSOP DA 32 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082IDA ACTIVE TSSOP DA 32 46 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082IDAG4 ACTIVE TSSOP DA 32 46 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082IDAR ACTIVE TSSOP DA 32 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082IDARG4 ACTIVE TSSOP DA 32 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) THS12082QDA PREVIEW TSSOP DA 32 TBD CallTI CallTI THS12082QDAR PREVIEW TSSOP DA 32 TBD CallTI CallTI (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) THS12082CDAR TSSOP DA 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 THS12082IDAR TSSOP DA 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS12082CDAR TSSOP DA 32 2000 346.0 346.0 41.0 THS12082IDAR TSSOP DA 32 2000 346.0 346.0 41.0 PackMaterials-Page2

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