TCS3471 Color Light-to-Digital Converter General Description The TCS3471 family of devices provides red, green, blue, and clear light sensing (RGBC) that detects light intensity under a variety of lighting conditions and through a variety of attenuation materials. An internal state machine provides the ability to put the device into a low power mode in between RGBC measurements providing very low average power consumption. The TCS3471 is directly useful in lighting conditions containing minimal IR content such as LED RGB backlight control, reflected LED color sampler, or fluorescent light color temperature detector. With the addition of an IR blocking filter, the device is an excellent ambient light sensor, color temperature monitor, and general purpose color sensor. OrderingInformation and ContentGuide appear at end of datasheet. Key Benefits & Features The benefits and features of TCS3471, Color Light-to-Digital Converter are listed below: Figure 1: Added Value Of Using TCS3471 Benefits Features • Enables Accurate Color and Ambient Light • 1M:1 Dynamic Range Sensing Under Varying Lighting Conditions • Minimizes Motion / Transient Errors • Four Independent Analog-to-Digital Converters • Clear-Channel Provides a Reference Allows for • A Reference-Channel for Color Analysis (Clear Channel Isolation of Color Content Photo-diode) • Reduces Micro-Processor Interrupt Overhead • Programmable Interrupt Function • Reduces Board Space Requirements While • Area Efficient 2mm x 2.4mm Dual Flat No-Lead (FN) Simplifying Designs Package • Color Light Sensing • Programmable Analog Gain, Integration Time, and Interrupt Function with Upper and Lower Thresholds • Resolution Up to 16 Bits • Very High Sensitivity - Ideally Suited for Operation Behind Dark Glass • Up to 1,000,000:1 Dynamic Range ams Datasheet Page 1 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − General Description • Low Power Wait State • 65 μA Typical Current • Wait Timer is Programmable from 2.4 ms to > 7seconds • Sleep Mode - 2.5 μA Typical Current • I²C Interface Compatible • Up to 400 kHz (I²C Fast Mode) • Dedicated Interrupt Pin • Pin and Register Set Compatible with the TCS3x7x Family of Devices Applications TCS3471, Color Light-to-Digital Converter is ideal for: • Color Temperature Sensing • RGB LED Backlight Control • Color Display Closed-Loop Feedback Control • Ambient Light Sensing for Display Brightness Control • Industrial Process Control • Medical Diagnostics End Products and Market Segments • HDTVs, Mobile Handsets, Tablets, Laptops, Monitors, PMP (Portable Media Payers) • Medical Instrumentation • Consumer Toys • Industrial/Commercial Lighting Page 2 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − General Description Functional Block Diagram The functional blocks of this device are shown below: Figure 2: TCS3471 Block Diagram Wait Control Interrupt INT VDD Upper Limit RGBC Control SCL e Clear ADC Clear Data ac Clear rf Lower Limit e Red ADC Red Data nt Red C I Green ADC Green Data 2I Green SDA Blue ADC Blue Data Blue GND ams Datasheet Page 3 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Pin Assignments Pin Assignments Figure 3: Package FN Dual Flat No-Lead (Top View) Pin Diagram: Package Drawing Not to Scale V 1 6 SDA DD SCL 2 5 INT GND 3 4 NC Figure 4: Terminal Functions Terminal Type Description Name No. V 1 Supply voltage. DD SCL 2 I I²C Serial clock input terminal - clock signal for I²C serial data. GND 3 Power supply ground. All voltages are referenced to GND. NC 4 Do not connect INT 5 O Interrupt - open drain. SDA 6 I/O I²C Serial data I/O terminal - serial data I/O for I²C. Page 4 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Detailed Description Detailed Description The TCS3471 light-to-digital device contains a 4 × 4 photodiode array, integrating amplifiers, ADCs, accumulators, clocks, buffers, comparators, a state machine, and an I²C interface. The 4 × 4 photodiode array is composed of red-filtered, green-filtered, blue-filtered, and clear photodiodes — four of each type. Four integrating ADCs simultaneously convert the amplified photodiode currents to a digital value providing up to 16 bits of resolution. Upon completion of the conversion cycle, the conversion result is transferred to the data registers. The transfers are double-buffered to ensure that the integrity of the data is maintained. Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I²C serial bus for easy connection to a microcontroller or embedded controller. The TCS3471 provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. An interrupt is generated when the value of an RGBC conversion exceeds either an upper or lower threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. ams Datasheet Page 5 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted) Symbol Parameter Min Max Units V (1) Supply voltage 3.8 V DD V Digital output voltage range -0.5 3.8 V O I Digital output current -1 20 mA O T Storage temperature range -40 85 ºC STRG ESD ESD tolerance, human body model ±2000 V HBM Note(s): 1. All voltages are with respect to GND. Figure 6: Recommended Operating Conditions Symbol Parameter Min Nom Max Unit V Supply voltage 2.7 3 3.3 V DD T Operating free-air temperature -30 70 ºC A Page 6 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Absolute Maximum Ratings Figure 7: Operating Characteristics; V = 3 V, T = 25ºC (unless otherwise noted) DD A Symbol Parameter Test Conditions Min Typ Max Unit Active 235 330 I Supply current Wait mode 65 μA DD Sleep mode - no I²C activity 2.5 10 3 mA sink current 0 0.4 INT, SDA output low V V OL voltage 6 mA sink current 0 0.6 Leakage current, SDA, I −5 5 μA LEAK SCL, INT pins Leakage current, LDR I -1 +10 μA LEAK pin TCS34711 & TCS34715 0.7 V SCL, SDA input high DD V V IH voltage TCS34713 & TCS34717 1.25 TCS34711 & TCS34715 0.3 V SCL, SDA input low DD V V IL voltage TCS34713 & TCS34717 0.54 Figure 8: Optical Characteristics; V = 3 V, T = 25ºC, GAIN = 16, ATIME = 0xF6 (unless otherwise noted) DD A Red Green Blue Clear Channel Test Channel Channel Channel Parameter Unit Conditions Min Max Min Max Min Max Min Typ Max λ = 465 nm(2) 0% 15% 10% 42% 65% 88% 19.2 24 28.8 D R e counts/ Irradiance λ = 525 nm(3) 8% 25% 60% 85% 9% 35% 22.4 28 33.6 D (μW/cm2) responsivtiy λ = 625 nm(4) 85% 110% 0% 15% 5% 25% 27.2 34 40.8 D Note(s): 1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel value. 2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ = 465 nm, spectral halfwidth Δλ½ = 22 nm, and luminous efficacy = 75 lm/W. D 3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ = 525 nm, spectral halfwidth Δλ½ = 35 nm, and luminous efficacy = 520 lm/W. D 4. The 625 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics: dominant wavelength λ = 625 nm, spectral halfwidth Δλ½ = 9 nm, and luminous efficacy = 155 lm/W. D ams Datasheet Page 7 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Absolute Maximum Ratings Figure 9: RGBC Characteristics; V = 3 V, T = 25ºC, AGAIN = 16, AEN = 1 (unless otherwise noted) DD A Parameter Test Conditions Min Typ Max Unit Ee = 0, AGAIN = 60×, ATIME= 0xD6 Dark ADC count value 0 1 5 counts (100 ms) ADC integration time step ATIME = 0xFF 2.27 2.4 2.56 ms size ADC number of integration 1 256 steps steps ADC counts per step 0 1024 counts ADC count value ATIME = 0xC0 (153.6 ms) 0 65535 counts 4× 3.8 4 4.2 Gain scaling, relative to 1× 16× 15 16 16.8 % gain setting 60× 58 60 63 Figure 10: Wait Characteristics; V = 3 V, T = 25ºC, Gain = 16, WEN = 1 (unless otherwise noted) DD A Test Parameter Channel Min Typ Max Unit Conditions Wait step size WTIME = 0xFF 2.27 2.4 2.56 ms Wait number steps 1 256 steps Page 8 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Absolute Maximum Ratings Figure 11: AC Electrical Characteristics; V = 3 V, T = 25ºC, (unless otherwise noted) DD A Test Symbol Parameter(1) Min Typ Max Unit Conditions f Clock frequency (I²C) 0 400 kHz (SCL) Bus free time between start and stop t 1.3 μs (BUF) condition Hold time after (repeated) start t condition. After this period, the first 0.6 μs (HDSTA) clock is generated. t Repeated start condition setup time 0.6 μs (SUSTA) t Stop condition setup time 0.6 μs (SUSTO) t Data hold time 0 μs (HDDAT) t Data setup time 100 ns (SUDAT) t SCL clock low period 1.3 μs (LOW) t SCL clock high period 0.6 μs (HIGH) t Clock/data fall time 300 ns F t Clock/data rise time 300 ns R C Input pin capacitance 10 pF i Note(s): 1. Specified by design and characterization; not production tested. ams Datasheet Page 9 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Absolute Maximum Ratings Parameter Measurement Information Figure 12: Timing Diagrams t(LOW) t(R) t(F) SCL VIH VIL t(HDSTA) t(HIGH) t(SUSTA) t(BUF) t(HDDAT) t(SUDAT) t(SUSTO) SDA VIH VIL P S S P Stop Start Start Stop Condition Condition t(LOWSEXT) SCLACK SCLACK t(LOWMEXT) t(LOWMEXT) t(LOWMEXT) SCL SDA Page 10 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Typical Operating Characteristics Typical Operating Characteristics Figure 13: Photodiode Spectral Responsivity 1 Normalized to 0.9 Clear @ 755 nm 0.8 Clear TA = 25°C y 0.7 vit Red si 0.6 n o p s 0.5 e R ve 0.4 ati el 0.3 R Blue 0.2 Green 0.1 0 300 500 700 900 1100 λ − Wavelength − nm Figure 14: Normalized I vs.V and Temperature DD DD V and TEMPERATURE DD 110% 108% 75(cid:2)C 106% 104% 50(cid:2)C 25(cid:2)C 102% 100% 0(cid:2)C 98% 96% 94% 92% 2.7 2.8 2.9 3 3.1 3.2 3.3 VDD — V ams Datasheet Page 11 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Typical Operating Characteristics Figure 15: Normalized Responsivity vs. Angular Displacement 1.0 0.8 y vit s si xi pon 0.6 al A s c Re pti d O e z 0.4 ali m r o N 0.2 (cid:3)(cid:2) (cid:4)(cid:2) 0 −90 −60 −30 0 30 60 90 (cid:2) − Angular Displacement − ° Figure 16: Responsivity Temperature Coefficient 10,000 C (cid:2) m/ p p — nt e ci effi 1000 o C e r u at r e p m e T 100 400 500 600 700 800 900 1000 λ − Wavelength − nm Page 12 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Principles Of Operation Principles Of Operation System State Machine The TCS3471 provides control of RGBC and power management functionality through an internal state machine (Figure17). After a power-on-reset, the device is in the sleep mode. As soon as the PON bit is set, the device will move to the start state. It will then continue through the Wait and RGBC states. If these states are enabled, the device will execute each function. If the PON bit is set to 0, the state machine will continue until all conversions are completed and then go into a low power sleep mode. Figure 17: Simplified State Diagram Sleep PON = 1 (r0:b0) PON = 0 (r0:b0) Start Wait RGBC Note(s): In this document, the nomenclature uses the bit field name in italics followed by the register number and bit number to allow the user to easily identify the register and bit that controls the function. For example, the power on (PON) is in register 0, bit 0. This is represented as PON (r0:b0). ams Datasheet Page 13 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Principles Of Operation RGBC Operation The RGBC engine contains RGBC gain control (AGAIN) and four integrating analog-to-digital converters (ADC) for the RGBC photodiodes. The RGBC integration time (ATIME) impacts both the resolution and the sensitivity of the RGBC reading. Integration of all four channels occurs simultaneously and upon completion of the conversion cycle, the results are transferred to the color data registers. This data is also referred to as channel count. The transfers are double-buffered to ensure that invalid data is not read during the transfer. After the transfer, the device automatically moves to the next state in accordance with the configured state machine. Figure 18: RGBC Operation ATIME(r1) AGAIN(r0x0F, b1:0) 2.4 ms to 700 ms 1(cid:3), 4(cid:3), 16(cid:3), 60(cid:3) Gain RGBC Control Clear ADC Clear Data CDATAH(r0x15), CDATA(r0x14) Clear Red ADC Red Data RDATAH(r0x17), RDATA(r0x16) Red Green ADC Green Data GDATAH(r0x19), GDATA(r0x18) Green Blue ADC Blue Data BDATAH(r0x1B), BDATA(r0x1A) Blue The registers for programming the integration and wait times are a 2’s compliment values. The actual time can be calculated as follows: (EQ1) ATIME = 256 - Integration Time / 2.4 ms Inversely, the time can be calculated from the register value as follows: (EQ2) Integration Time = 2.4 ms × (256 - ATIME) For example, if a 100ms integration time is needed, the device needs to be programmed to: 256 - (100 / 2.4) = 256 - 42 = 214 = 0xD6 Conversely, the programmed value of 0xC0 would correspond to: (256 - 0xC0) × 2.4 = 64 × 2.4 = 154 ms. Page 14 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Principles Of Operation Interrupts The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC interrupt enable (AIEN) field in the enable register (0x00). Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range. An interrupt can be generated when the RGBC Clear data (CDATA) falls outside of the desired light level range, as determined by the values in the RGBC interrupt low threshold registers (AILTx) and RGBC interrupt high threshold registers (AIHTx). It is important to note that the low threshold value must be less than the high threshold value for proper operation. To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows the user to specify the number of consecutive out-of-range RGBC occurrences before an interrupt is generated. The persistence register (0x0C) allows the user to set the persistence (APERS) value. See the Persistence Register (0x0C) for details on the persistence filter values. Once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see Command Register). Figure 19: Programmable Interrupt AIHTH(r07), AIHTL(r06) PPERS(r0x0C, b3:0) Upper Limit RGBC Persistence Clear Clear ADC Data Lower Limit Clear AILTH(r05), AILTL(r04) ams Datasheet Page 15 [v1-01] 2018-Mar-27 DocumentFeedback

State Diagram Figure20 shows a more detailed flow for the state machine. The device starts in the sleep mode. The PON bit is written to enable the device. A 2.4ms delay will occur before entering the start state. If the WEN bit is set, the state machine will cycle through the wait state. If the WLONG bit is set, the wait cycles are extended by 12× over normal operation. When the wait counter terminates, the state machine will step to the RGBC state. The AEN should always be set. In this case, a minimum of 1 integration time step should be programmed. The RGBC state machine will continue until it reaches the terminal count, at which point the data will be latched in the RGBC register and the interrupt set, if enabled. Figure 20: Expanded State Diagram 1 to 256steps Sleep Step: 2.4 ms Time: 2.4 ms − 614 ms PON = 1 PON = 0 WLONG = 0 1 to 256 steps Step: 2.4 ms Start Time: 2.4 ms − 614 ms ALS Minimum − 2.4 ms Wait ALS Check Check WLONG = 1 ALS 1 to 256 steps WEN = 1 AEN = 1 Delay Step: 29 ms Time: 29 ms − 7.4 s Wait Time: 2.4 ms Minimum − 29 ms Page 16 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Principles Of Operation I²C Protocols Interface and control are accomplished through an I²C serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. The devices support the 7-bit I²C addressing protocol. The I²C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure21). During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the register address from the previous command will be used for data access. Likewise, if the MSB of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. The command byte contains either control information or a 5-bit register address. The control commands can also be used to clear interrupts. The I²C bus protocol was developed by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at http://www.i2c-bus.org/references/. Figure 21: I²C Protocols 1 7 1 1 8 1 8 1 1 ... S Slave Address W A Command Code A Data Byte A P I2C Write Protocol 1 7 1 1 8 1 8 1 1 ... S Slave Address R A Data A Data A P I2C Read Protocol 1 7 1 1 8 1 1 7 1 1 S Slave Address W A Command Code A Sr Slave Address R A 8 1 8 1 1 ... Data A Data A P I2C Read Protocol — Combined Format A Acknowledge (0) N Not Acknowledged (1) P Stop Condition R Read (1) S Start Condition Sr Repeated Start Condition W Write (0) ... Continuation of protocol Master-to-Slave Slave-to-Master ams Datasheet Page 17 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Register Description Register Description The TCS3471 is controlled and monitored by data registers and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Figure22. Figure 22: Register Set Address Register Name R/W Register Function Reset Value −− COMMAND W Specifies register address 0x00 0x00 ENABLE R/W Enables states and interrupts 0x00 0x01 ATIME R/W RGBC ADC time 0xFF 0x03 WTIME R/W Wait time 0xFF 0x04 AILTL R/W RGBC interrupt low threshold low byte 0x00 0x05 AILTH R/W RGBC interrupt low threshold high byte 0x00 0x06 AIHTL R/W RGBC interrupt high threshold low byte 0x00 0x07 AIHTH R/W RGBC interrupt high threshold high byte 0x00 0x0C PERS R/W Interrupt persistence filters 0x00 0x0D CONFIG R/W Configuration 0x00 0x0F CONTROL R/W Gain control register 0x00 0x12 ID R Device ID ID 0x13 STATUS R Device status 0x00 0x14 CDATA R Clear ADC low data register 0x00 0x15 CDATAH R Clear ADC high data register 0x00 0x16 RDATA R Red ADC low data register 0x00 0x17 RDATAH R Red ADC high data register 0x00 0x18 GDATA R Green ADC low data register 0x00 0x19 GDATAH R Green ADC high data register 0x00 0x1A BDATA R Blue ADC low data register 0x00 0x1B BDATAH R Blue ADC high data register 0x00 The mechanics of accessing a specific register depends on the specific protocol used. See the section on I²C protocols on the previous pages. In general, the COMMAND register is written first to specify the specific control/status register for the following read/write operations. Page 18 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Register Description Command Register The command registers specifies the address of the target register for future write and read operations. Figure 23: Command Register 7 6 5 4 3 2 1 0 COMMAND TYPE ADD Field Bits Description COMMAND 7 Select Command Register. Must write as 1 when addressing COMMAND register. TYPE 6:5 Selects type of transaction to follow in subsequent data transfers: FIELD VALUE INTEGRATION TIME 00 Repeated byte protocol transaction 01 Auto-increment protocol transaction 10 Reserved — Do not use 11 Special function — See description below Byte protocol will repeatedly read the same register with each data access. Block protocol will provide auto-increment function to read successive bytes. ADD 4:0 Address field/special function field. Depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. The field values listed below apply only to special function commands: FIELD VALUE READ VALUE 00000 Normal — no action 00110 RGBC interrupt clear other Reserved — Do not write RGBC Interrupt Clear. Clears any pending RGBC interrupt. This special function is self clearing. ams Datasheet Page 19 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Register Description Enable Register (0x00) The Enable register is used primarily to power the TCS3471 device on and off, and enable functions and interrupts as shown in Figure24. Figure 24: Enable Register 7 6 5 4 3 2 1 0 Reserved AIEN WEN Reserved AEN PON Field Bits Description Reserved 7:5 Reserved. Write as 0. RGBC interrupt enable. When asserted, permits RGBC interrupts to be AIEN 4 generated. Wait enable. This bit activates the wait feature. Writing a 1 activates the WEN 3 wait timer. Writing a 0 disables the wait timer. Reserved 2 Reserved. Write as 0. RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates AEN 1 the RGBC. Writing a 0 disables the RGBC. Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 PON(1) 0 disables the oscillator. During reads and writes over the I²C interface, this bit is temporarily overridden and the oscillator is enabled, independent of the state of PON. Note(s): 1. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated. Page 20 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Register Description RGBC Timing Register (0x01) The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in 2.4 ms increments. Max RGBC Count = (256 - ATIME) × 1024 up to a maximum of 65535. Figure 25: RGBC Timing Register Field Bits Description VALUE INTEG_CYCLES TIME MAX COUNT 0xFF 1 2.4 ms 1024 0xF6 10 24 ms 10240 ATIME 7:0 0xD5 42 101 ms 43008 0xC0 64 154 ms 65535 0x00 256 700 ms 65535 Wait Time Register (0x03) Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12x longer. WTIME is programmed as a 2’s complement number. Figure 26: Wait Time Register Field Bits Description REGISTER WAIT TIME TIME (WLONG = 0) TIME (WLONG = 1) VALUE 0xFF 1 2.4 ms 0.029 s WTIME 7:0 0xAB 85 204 ms 2.45 s 0x00 256 614 ms 7.4 s ams Datasheet Page 21 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Register Description RGBC Interrupt Threshold Registers (0x04 - 0x07) The RGBC interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation. If the value generated by the clear channel crosses below the lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. Figure 27: RGBC Interrupt Threshold Register Register Address Bits Description AILTL 0x04 7:0 RGBC clear channel low threshold lower byte AILTH 0x05 7:0 RGBC clear channel low threshold upper byte AIHTL 0x06 7:0 RGBC clear channel high threshold lower byte AIHTH 0x07 7:0 RGBC clear channel high threshold upper byte Page 22 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Register Description Persistence Register (0x0C) The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result that is outside of the values specified by the threshold register for some specified amount of time. Figure 28: Persistence Register 7 6 5 4 3 2 1 0 Reserved APERS Field Bits Description Reserved 7:4 Reserved. Interrupt persistence. Controls rate of interrupt to the host processor. FIELD VALUE MEANING INTERRUPT PERSISTENCE FUNCTION 0000 Every Every RGBC cycle generates an interrupt 0001 1 1 clear channel value outside of threshold range 0010 2 2 clear channel consecutive values out of range 0011 3 3 clear channel consecutive values out of range 0100 5 5 clear channel consecutive values out of range 0101 10 10 clear channel consecutive values out of range 0110 15 15 clear channel consecutive values out of range APERS 3:0 0111 20 20 clear channel consecutive values out of range 1000 25 25 clear channel consecutive values out of range 1001 30 30 clear channel consecutive values out of range 1010 35 35 clear channel consecutive values out of range 1011 40 40 clear channel consecutive values out of range 1100 45 45 clear channel consecutive values out of range 1101 50 50 clear channel consecutive values out of range 1110 55 55 clear channel consecutive values out of range 1111 60 60 clear channel consecutive values out of range ams Datasheet Page 23 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Register Description Configuration Register (0x0D) The configuration register sets the wait long time. Figure 29: Configuration Register 7 6 5 4 3 2 1 0 Reserved WLONG Reserved Field Bits Description Reserved 7:2 Reserved. Write as 0. Wait Long. When asserted, the wait cycles are increased by a factor 12x from that WLONG 1 programmed in the WTIME register. Reserved 0 Reserved. Write as 0. Control Register (0x0F) The Control register provides eight bits of miscellaneous control to the analog block. These bits typically control functions such as gain settings and/or diode selection. Figure 30: Control Register 7 6 5 4 3 2 1 0 Reserved AGAIN Field Bits Description Reserved 7:2 Reserved. Write bits as 0 RGBC Gain Control. FIELD VALUE RGBC GAIN VALUE 00 1x gain AGAIN 1:0 01 4x gain 10 16x gain 11 60x gain Page 24 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Register Description ID Register (0x12) The ID Register provides the value for the part number. The ID register is a read-only register. Figure 31: ID Register 7 6 5 4 3 2 1 0 ID Field Bit Description 0x14 = TCS34711 & TCS34715 ID 7:0 Part number identification 0x1D = TCS34713 & TCS34717 Status Register (0x13) The Status Register provides the internal status of the device. This register is read only. Figure 32: Status Register 7 6 5 4 3 2 1 0 Reserved AINT Reserved AVALID Field Bit Description Reserved 7:5 Reserved. AINT 4 RGBC clear channel Interrupt. Reserved 3:1 Reserved. RGBC Valid. Indicates that the RGBC channels have AVALID 0 completed an integration cycle. ams Datasheet Page 25 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Register Description RGBC Channel Data Registers (0x14 - 0x1B) Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read I²C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Figure 33: ADC Channel Data Registers Register Address Bits Description CDATA 0x14 7:0 Clear data low byte CDATAH 0x15 7:0 Clear data high byte RDATA 0x16 7:0 Red data low byte RDATAH 0x17 7:0 Red data high byte GDATA 0x18 7:0 Green data low byte GDATAH 0x19 7:0 Green data high byte BDATA 0x1A 7:0 Blue data low byte BDATAH 0x1B 7:0 Blue data high byte Page 26 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Application Information: Hardware Application Information: Hardware Typical Hardware Application A typical hardware application circuit is shown in Figure34. A 1-μF low-ESR decoupling capacitor should be placed as close as possible to the V pin. DD Figure 34: Typical Application Hardware Circuit VDD VBUS VDD RP RP RPI 1 (cid:5)F TCS3471 INT SCL GND SDA V in Figure34 refers to the I²C bus voltage, which is either BUS V or 1.8 V. Be sure to apply the specified I²C bus voltage shown DD in the Available Options table for the specific device being used. The I²C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R ) value is a P function of the I²C bus speed, the I²C bus voltage, and the capacitive load. The ams EVM running at 400 kbps, uses 1.5-kΩ resistors. A 10-kΩ pull-up resistor (R ) can be used for the PI interrupt line. ams Datasheet Page 27 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Application Information: Hardware PCB Pad Layouts Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in Figure35. Note(s): Pads can be extended further if hand soldering is needed. Figure 35: Suggested FN Package PCB Layout 2500 1000 1000 400 650 1700 650 400 Note(s): 1. All linear dimensions are in micrometers. 2. This drawing is subject to change without notice. Page 28 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Mechanical Data Mechanical Data Figure 36: Package FN — Dual Flat No-Lead Packaging Configuration PACKAGE FN Dual Flat No-Lead TOP VIEW 496 (cid:4) 10 PIN OUT TOP VIEW PIN 1 VDD 1 6 SDA 406 (cid:4) 10 2400 (cid:4) 75 SCL 2 5 INT GND 3 4 NC 2000 Photodiode Active Area (cid:4) 75 END VIEW SIDE VIEW 295 Nominal 650 (cid:4) 50 203 (cid:4) 8 650 BOTTOM VIEW BSC 300 (cid:4) 50 CLof Solder Contacts and Photodiode Array Area (Note 2B) 125 Nominal RoHS CLof Solder Contacts CL of Photodiode Array Area (Note 2B) Green PIN 1 Pb 750 (cid:4) 100 Lead Free Note(s): 1. All linear dimensions are in micrometers. 2. The die is centered within the package within a tolerance of ± 75 μm. 3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55. 4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish. 5. This package contains no lead (Pb). 6. This drawing is subject to change without notice. ams Datasheet Page 29 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Mechanical Data Figure 37: Package FN Carrier Tape TOP VIEW 2.00 (cid:4) 0.05 1.75 4.00 4.00 (cid:5) 1.50 B + 0.30 8.00 − 0.10 3.50 (cid:4) 0.05 (cid:5) 0.50 (cid:4) 0.05 A A B DETAIL A DETAIL B 5(cid:2) Max 5(cid:2) Max 0.254 2.21 (cid:4) 0.05 (cid:4) 0.02 0.83 (cid:4) 0.05 2.61 (cid:4) 0.05 Ao Ko Bo Green RoHS Note(s): 1. All linear dimensions are in millimeters. Dimension tolerance is ±0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481-B 2001. o o o 4. Each reel is 178 millimeters in diameter and contains 3500 parts. 5. ams packaging tape and reel conform to the requirements of EIA Standard 481-B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Page 30 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Manufacturing Information Manufacturing Information The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 38: Solder Reflow Profile Parameter Reference Device Average temperature gradient in preheating 2.5°C/s Soak time t 2 to 3 minutes soak Time above 217°C (T ) t Max 60 s 1 1 Time above 230°C (T ) t Max 50 s 2 2 Time above T −10°C (T ) t Max 10 s peak 3 3 Peak temperature in reflow T 260°C peak Temperature gradient in cooling Max −5°C/s Figure 39: Solder Reflow Profile Graph Not to scale — for reference o T peak T 3 T 2 T 1 C) (cid:2) e ( r u at r e p m e T Time (s) t 3 t 2 tsoak t1 Note(s): 1. Not to scale — for reference only ams Datasheet Page 31 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Manufacturing Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under the following conditions: • Temperature Range: 5ºC to 50ºC • Relative Humidity: 60% maximum • Total Time: 12 months from the date code on the aluminized envelope — if unopened • Opened Time: 168 hours or fewer Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. If rebaking is required, it should be done at 50ºC for 12 hours. Page 32 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Ordering & Contact Information Ordering & Contact Information Figure 40: Ordering Information Ordering Code Description Device Address Package - Leads TCS34711FN I²C Vbus = V Interface TCS34711 0x39 FN−6 DD TCS34713FN I²C Vbus = 1.8 V Interface TCS34713 0x39 FN−6 TCS34715FN I²C Vbus = V Interface TCS34715 0x29 FN−6 DD TCS34717FN I²C Vbus = 1.8 V Interface TCS34717 0x29 FN−6 Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30 8141 Premstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com ams Datasheet Page 33 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − RoHS Compliant & ams Green Statement RoHS Compliant & ams Green RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor Statement products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Page 34 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. ams Datasheet Page 35 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Document Status Document Status Document Status Product Status Definition Information in this datasheet is based on product ideas in the planning phase of development. All specifications are Product Preview Pre-Development design goals without any warranty and are subject to change without notice Information in this datasheet is based on products in the design, validation or qualification phase of development. Preliminary Datasheet Pre-Production The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Information in this datasheet is based on products in ramp-up to full production or full production which Datasheet Production conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Information in this datasheet is based on products which conform to specifications in accordance with the terms of Datasheet (discontinued) Discontinued ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Page 36 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

TCS3471 − Revision Information Revision Information Changes from 1-00 (2016-May-23) to current revision 1-01 (2018-Mar-27) Page Updated Figure 40 33 Note(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision 2. Correction of typographical errors is not explicitly mentioned. ams Datasheet Page 37 [v1-01] 2018-Mar-27 DocumentFeedback

TCS3471 − Content Guide Content Guide 1 General Description 1 Key Benefits & Features 2 Applications 2 End Products and Market Segments 3 Functional Block Diagram 4 Pin Assignments 5 Detailed Description 6 Absolute Maximum Ratings 10 Parameter Measurement Information 11 Typical Operating Characteristics 13 Principles Of Operation 13 System State Machine 14 RGBC Operation 15 Interrupts 16 State Diagram 17 I²C Protocols 18 Register Description 19 Command Register 20 Enable Register (0x00) 21 RGBC Timing Register (0x01) 21 Wait Time Register (0x03) 22 RGBC Interrupt Threshold Registers (0x04 - 0x07) 23 Persistence Register (0x0C) 24 Configuration Register (0x0D) 24 Control Register (0x0F) 25 ID Register (0x12) 25 Status Register (0x13) 26 RGBC Channel Data Registers (0x14 - 0x1B) 27 Application Information: Hardware 27 Typical Hardware Application 28 PCB Pad Layouts 29 Mechanical Data 31 Manufacturing Information 32 Moisture Sensitivity 33 Ordering & Contact Information 34 RoHS Compliant & ams Green Statement 35 Copyrights & Disclaimer 36 Document Status 37 Revision Information Page 38 ams Datasheet DocumentFeedback [v1-01] 2018-Mar-27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: a ms: TCS34717FN TCS34715FN TCS3471EVM TCS3471-DB TCS34711FN