TCN75 2-Wire Serial Temperature Sensor and Thermal Monitor Features: Package Type • Solid-State Temperature Sensing: SOIC 0.5°C Accuracy (Typ.) • Operates from -55°C to +125°C SDA 1 8 VDD • Operating Supply Range: 2.7V to 5.5V SCL 2 7 A0 • Programmable Trip Point and Hysteresis with TCN75MOA Power-up Defaults INT/CMPTR 3 6 A1 • Standard 2-Wire Serial Interface GND 4 5 A2 • Thermal Event Alarm Output Functions as Interrupt or Comparator/Thermostat Output MSOP • Up to 8 TCN75s may Share the Same Bus • Shutdown Mode for Low Standby Power SDA 1 8 VDD Consumption SCL 2 7 A0 • 5V Tolerant I/O at V = 3V TCN75MUA DD • Low Power: INT/CMPTR 3 6 A1 - 250 A (Typ.) Operating GND 4 5 A2 - 1 A (Typ.) Shutdown Mode • 8-Pin SOIC and MSOP Packaging General Description: Applications: The TCN75 is a serially programmable temperature • Thermal Protection for High-Performance CPUs sensor that notifies the host controller when ambient temperature exceeds a user programmed set point. • Solid-State Thermometer Hysteresis is also programmable. The INT/CMPTR • Fire/Heat Alarms output is programmable as either a simple comparator • Thermal Management in Electronic Systems: for thermostat operation or as a temperature event - Computers interrupt. Communication with the TCN75 is - Telecom Racks accomplished via a two-wire bus that is compatible with industry standard protocols. This permits reading the - Power Supplies/UPS/Amplifiers current temperature, programming the set point and • Copiers/Office Electronics hysteresis, and configuring the device. • Consumer Electronics The TCN75 powers up in Comparator mode with a • Process Control default set point of 80°C with 5°C hysteresis. Defaults allow independent operation as a stand-alone thermostat. A shutdown command may be sent via the 2-wire bus to activate the low-power Standby mode. Address selection inputs allow up to eight TCN75s to share the same 2-wire bus for multizone monitoring. All registers can be read by the host and the INT/ CMPTR output’s polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease-of-use make the TCN75 an ideal choice for implementing sophisticated system management schemes.  2001-2012 Microchip Technology Inc. DS21490D-page 1

TCN75 Device Selection Table Part Number Supply Voltage Package Junction Temperature Range TCN75-3.3MOA 3.3 8-Pin SOIC -55°C to +125°C TCN75-5.0MOA 5.0 8-Pin SOIC -55°C to +125°C TCN75-3.3MUA 3.3 8-Pin MSOP -55°C to +125°C TCN75-5.0MUA 5.0 8-PIn MSOP -55°C to +125°C Functional Block Diagram TCN75 INT/CMPTR 9-Bit DS Control A/D Logic Converter Temp Sensor VDD Register Set Configuration TSET Temperature THYST SDA SCL Two Wire Serial Port A0 Interface A1 A2 DS21490D-page 2  2001-2012 Microchip Technology Inc.

TCN75 1.0 ELECTRICAL *Stresses above those listed under “Absolute CHARACTERISTICS Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions Absolute Maximum Ratings* above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Supply Voltage (V )............................................6.0V DD Maximum Rating conditions for extended periods may ESD Susceptibility (Note 3)...............................1000V affect device reliability. Voltage on Pins: A0, A1, A2..........(GND – 0.3V) to (V + 0.3V) DD Voltage on Pins: SDA, SCL, INT/CMPTR..(GND – 0.3V) to 5.5V Thermal Resistance (Junction to Ambient) 8-Pin SOIC..........................................170°C/W 8-Pin MSOP.......................................250°C//W Operating Temperature Range (T ): -55°C to +125°C J Storage Temperature Range (T ): -65°C to +150°C STG TCN75 ELECTRICAL SPECIFICATIONS Electrical Characteristics: V = 2.7V – 5.5V, -55°C  (T = T )  125°C, unless otherwise noted. DD A J Symbol Parameter Min Typ Max Units Test Conditions Power Supply V Power Supply Voltage 2.7 — 5.5 — DD I Operating Current — 0.250 — mA Serial Port Inactive (T = T = 25°C) DD A J — — 1.0 Serial Port Active I Standby Supply Current — 1 — A Shutdown Mode, Serial Port DD1 Inactive (T = T = 25°C) A J INT/CMPTR Output I Sink Current: INT/CMPTR, — 1 4 mA Note 1 OL SDA Outputs t INT/CMPTR Response Time 1 — 6 t User Programmable TRIP CONV V Output Low Voltage — — 0.8 V I = 4.0 mA OL OL Temp-to-Bits Converter T Temperature Accuracy (Note 2) — ±3 — C -55°C  T  +125°C A V = 3.3V: TCN75-3.3 MOA, DD TCN75-3.3 MUA V = 5.0V: TCN75-5.0 MOA, DD TCN75-5.0 MUA — ±0.5 ±3 C 25°C  T  100°C A t Conversion Time — 55 — msec CONV T TEMP Default Value — 80 — C Power-up SET(PU) T T Default Value — 75 — C Power-up HYST(PU) HYST 2-Wire Serial Bus Interface V Logic Input High V x 0.7 — — V IH DD V Logic Input Low — — V x 0.3 V IL DD V Logic Output Low — — 0.4 V I = 3 mA OL OL C Input Capacitance SDA, SCL — 15 — pF IN I I/O Leakage — ±100 — pA (T = T = 25°C) LEAK A J I SDA Output Low Current — — 6 mA OL(SDA)  2001-2012 Microchip Technology Inc. DS21490D-page 3

TCN75 TCN75 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: 2.7V  V  5.5V; -55°C  (T = T )  125°C, C = 80 pF, unless otherwise noted. DD A J L Symbol Parameter Min Typ Max Unit Test Conditions Serial Port Timing f Serial Port Frequency 0 100 400 kHz SC t Low Clock Period 1250 — — nsec LOW t High Clock Period 1250 — — nsec HIGH t SCL and SDA Rise Time — — 250 nsec R t SCL and SDA Fall Time — — 250 nsec F t Start Condition Setup Time (for 1250 — — nsec SU(START) repeated Start Condition) t SCL Clock Period 2.5 — — sec SC t Start Condition Hold Time 100 — — nsec H(START) t Data in Setup Time to SCL High 100 — — nsec DSU t Data in Hold Time after SCL Low 0 — — nsec DH t Stop Condition Setup Time 100 — — nsec SU(STOP) t Bus Free Time Prior to New Transition 1250 — — nsec IDLE Note 1: Output current should be minimized for best temperature accuracy. Power dissipation within the TCN75 will cause self-heating and temperature drift. At maximum rated output current and saturation voltage, 4 mA and 0.8V, respectively, the error amounts to 0.544°C for the SOIC. 2: All part types of the TCN75 will operate properly over the wider power supply range of 2.7V to 5.5V. Each part type is tested and specified for rated accuracy at its nominal supply voltage. As VDD varies from the nominal value, accuracy will degrade 1°C/V of VDD change. 3: Human body model, 100 pF discharged through a 1.5k resistor. TIMING DIAGRAM tSC SCL tH (Start) tSU (Stop) SDA Data In tDSU SDA Data Out tDH DS21490D-page 4  2001-2012 Microchip Technology Inc.

TCN75 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number (8-Pin SOIC) Symbol Description 8-Pin MSOP) 1 SDA Bidirectional Serial Data. 2 SCL Serial Data Clock Input. 3 INT/CMPTR Interrupt or Comparator Output. 4 GND System Ground. 5 A Address Select Pin (MSB). 2 6 A Address Select Pin. 1 7 A Address Select Pin (LSB). 0 8 V Power Supply Input. DD  2001-2012 Microchip Technology Inc. DS21490D-page 5

TCN75 3.0 DETAILED DESCRIPTION A typical TCN75 hardware connection is shown in Figure3-1. +VDD (3V to 5.5V) CBypass 0.1 µF Recommended Unless Device is Mounted Close to CPU 8 Address A0 7 (Set as Desired) A1 6 A2 5 3 To Controller TCN75 INT/CMPTR I2C™ InterfaceSDA 1 SCL 2 4 FIGURE 3-1: Typical Application 3.1 Serial Data (SDA) 3.4 Address (A2, A1, A0) Bidirectional. Serial data is transferred in both Inputs. Sets the three Least Significant bits of the directions using this pin. TCN75 8-bit address. A match between the TCN75’s address and the address specified in the serial bit 3.2 Serial Clock (SCL) stream must be made to initiate communication with the TCN75. Many protocol-compatible devices with Input. Clocks data into and out of the TCN75. other addresses may share the same 2-wire bus. 3.3 INT/CMPTR 3.5 Slave Address Open Collector, Programmable Polarity. In Comparator The four Most Significant bits of the Address Byte (A6, mode, unconditionally driven active any time A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 temperature exceeds the value programmed into the and A0 in the serial bit stream must match the states of TSET register. INT/CMPTR will become inactive when the A2, A1 and A0 address inputs for the TCN75 to temperature subsequently falls below the THYST set- respond with an Acknowledge (indicating the TCN75 is ting. (See Section5.0 “Register Set and Program- on the bus and ready to accept data). The Slave mer’s ModeL”, Register Set and Programmer’s Address is represented in Table3-1. Model). In Interrupt mode, INT/CMPTR is also made active by TEMP exceeding T ; it is unconditionally SET TABLE 3-1: TCN75 SLAVE ADDRESS reset to its inactive state by reading any register via the 2-wire bus. If and when temperature falls below THYST, 1 0 0 1 A2 A1 A0 INT/CMPTR is again driven active. Reading any regis- MSB LSBS ter will clear the T interrupt. In Interrupt mode, the HYST INT/CMPTR output is unconditionally reset upon enter- ing Shutdown mode. If programmed as an active-low output, it can be wire-ORed with any number of other open collector devices. Most systems will require a pull-up resistor for this configuration. Note that current sourced from the pull-up resistor causes power dissipation and may cause internal heat- ing of the TCN75. To avoid affecting the accuracy of ambient temperature readings, the pull-up resistor should be made as large as possible. INT/CMPTR’s output polarity may be programmed by writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low. DS21490D-page 6  2001-2012 Microchip Technology Inc.

TCN75 3.6 Comparator/Interrupt Modes INT/CMPTR behaves differently depending on whether the TCN75 is in Comparator mode or Interrupt mode. Comparator mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds T . When in Comparator mode, INT/ SET CMPTR will remain active until TEMP falls below T , whereupon it will reset to its inactive state. The HYST state of INT/CMPTR is maintained in Shutdown mode when the TCN75 is in Comparator mode. In Interrupt mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below T , until any register is read via HYST the 2-wire bus. Interrupt mode is better suited to inter- rupt driven microprocessor-based systems. The INT/ CMPTR output may be wire-OR’ed with other interrupt sources in such systems. Note that a pull-up resistor is necessary on this pin since it is an open-drain output. Entering Shutdown mode will unconditionally reset INT/ CMPTR when in Interrupt mode.  2001-2012 Microchip Technology Inc. DS21490D-page 7

TCN75 4.0 SHUTDOWN MODE TABLE 4-1: SERIAL BUS CONVENTIONS When the appropriate bit is set in the configuration reg- Term Explanation ister (CONFIG) the TCN75 enters its low-power Shut- Transmitter The device sending data to the bus. down mode (I = 1 A, typical) and the temperature- DD Receiver The device receiving data from the bus. to-digital conversion process is halted. The TCN75’s Master The device which controls the bus: initiating bus interface remains active and TEMP, T , and SET transfers (Start), generating the clock, and T may be read from and written to. Transitions on HYST terminating transfers (Stop). SDA or SCL due to external bus activity may increase Slave The device addressed by the master. the standby power consumption. If the TCN75 is in Start A unique condition signaling the beginning of Interrupt mode, the state of INT/CMPTR will be reset a transfer indicated by SDA falling (High – upon entering Shutdown mode. Low) while SCL is high. Stop A unique condition signaling the end of a 4.1 Fault Queue transfer indicated by SDA rising (Low – High) while SCL is high. To lessen the probability of spurious activation of INT/ CMPTR the TCN75 may be programmed to filter out ACK A Receiver acknowledges the receipt of each transient events. This is done by programming the byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK desired value into the Fault Queue. Logic inside the clock-pulse. The Master provides the clock TCN75 will prevent the device from triggering INT/ pulse for the ACK cycle. CMPTR unless the programmed number of sequential NOT Busy When the bus is idle, both SDA & SCL will temperature-to-digital conversions yield the same remain high. qualitative result. In other words, the value reported in TEMP must remain above T or below T for the Data Valid The state of SDA must remain stable during SET HYST the High period of SCL in order for a data bit consecutive number of cycles programmed in the Fault to be considered valid. SDA only changes Queue. Up to a six-cycle “filter” may be selected. See state while SCL is low during normal data Section5.0 “Register Set and Programmer’s transfers. (See Start and Stop conditions). ModeL”, Register Set and Programmer’s Model. All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which 4.2 Serial Port Operation provides the clock signal for all transfers. The TCN75 The Serial Clock input (SCL) and bidirectional data port always operates as a Slave. This serial protocol is (SDA) form a 2-wire bidirectional serial port for pro- illustrated in Figure5-1. All data transfers have two gramming and interrogating the TCN75. The following phases; and all bytes are transferred MSB first. table indicates TCN75 conventions that are used in this Accesses are initiated by a Start condition, followed by bus scheme. a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop condi- tion. A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for Start and Stop condi- tions). 4.3 Start Condition (Start) The TCN75 continuously monitors the SDA and SCL lines for a Start condition (a HIGH-to-LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. DS21490D-page 8  2001-2012 Microchip Technology Inc.

TCN75 4.3.1 ADDRESS BYTE 4.3.4 STOP CONDITION (STOP) Immediately following the Start condition, the host must Communications must be terminated by a Stop next transmit the address byte to the TCN75. The four condition (a LOW-to-HIGH transition of SDA while SCL Most Significant bits of the Address Byte (A6, A5, A4, is HIGH). The Stop condition must be communicated A3) are fixed to 1001(B). The states of A2, A1 and A0 by the transmitter to the TCN75. in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the TCN75 to respond 4.3.5 POWER SUPPLY with an Acknowledge (indicating the TCN75 is on the To minimize temperature measurement error, the bus and ready to accept data). The eighth bit in the TCN75-3.3 MOA and TCN75-3.3 MUA are factory cal- Address Byte is a Read/Write Bit. This bit is a ‘1’ for a ibrated at a supply voltage of 3.3V ±5% and the read operation or ‘0’ for a write operation. TCN75-5.0 MOA and TCN75-5.0 MUA are factory cal- ibrated at a supply voltage of 5V ±5%. Either device is 4.3.2 ACKNOWLEDGE (ACK) fully operational over the power supply voltage range of Acknowledge (ACK) provides a positive handshake 2.7V to 5.5V, but with a lower measurement accuracy. between the host and the TCN75. The host releases The typical value of this power supply-related error is SDA after transmitting eight bits then generates a ninth ±2°C. clock cycle to allow the TCN75 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address. 4.3.3 DATA BYTE After a successful ACK of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TCN75.  2001-2012 Microchip Technology Inc. DS21490D-page 9

TCN75 5.0 REGISTER SET AND D3 – D4: Fault Queue: Number of sequential PROGRAMMER’S MODEL temperature-to-digital conversions with the same result before the INT/CMPTR output is updated: TABLE 5-1: REGISTER (POINT), 8 BITS, WRITE ONLY D4 D3 Number of Conversions D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 0 1 (Power-up default) Must Be Set To Zero Pointer 0 1 2 1 0 4 1 1 6 Register Selection Via the Pointer Register D1 D0 Register Selection 0 0 TEMP 0 1 CONFIG 1 0 THYST 1 1 TSET TABLE 5-2: CONFIGURATION REGISTER (CONFIG), 8 BITS, READ/ WRITE D D D D D D D D [7] [6] [5] [4] [3] [2] [1] [0] Must Be Set Fault INT/ COM Shut- To Zero Queue CMPTR, P/INT down Polarity D0: Shutdown: 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High DS21490D-page 10  2001-2012 Microchip Technology Inc.

TCN75 TABLE 5-3: TEMPERATURE (TEMP) REGISTER, 16 BITS, READ ONLY The binary value in this register represents ambient temperature following a conversion cycle. D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X TABLE 5-4: TEMPERATURE SET POINT (T ) REGISTER, 16 BITS, READ/WRITE SET D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X TABLE 5-5: HYSTERESIS (T ) REGISTER, 16 BITS, READ/WRITE HYST D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X In the TEMP, T , and T registers, each unit SET HYST value represents one-half degree (Celsius). The value is in 2’s – complement binary format such that a read- ing of 000000000b corresponds to 0°C. Examples of this temperature to binary value relationship are shown in Table5-6. TABLE 5-6: TEMPERATURE TO DIGITAL VALUE CONVERSION Temperature Binary Value HEX Value +125°C 0 11111010 0FA +25°C 0 00110010 032 +0.5°C 0 00000001 001 0°C 0 00000000 00 0.5°C 1 11111111 1FF -25°C 1 11001110 1CE -40°C 1 10110000 1B0 -55°C 1 10010010 192 TABLE 5-7: TCN75’S REGISTER SET SUMMARY Name Description Width Read Write Notes TEMP Ambient Temperature 16 X 2’s Complement Format TSET Temperature Setpoint 16 X X 2’s Complement Format THYST Temperature Hysteresis 16 X X 2’s Complement Format POINT Register Pointer 8 X X CONFIG Configuration Register 8 X X  2001-2012 Microchip Technology Inc. DS21490D-page 11

TCN75 1 9 1 9 1 9 1 0 0 1 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4D3 D2 D1 D0 Stop Start Ack Ack No Ack Cond by Address Byte by Most Significant Data Byte by Least Significant Data Byte by by Master TCN75 Master Master Master (a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, THYST 1 9 1 9 . . . . . 1 0 0 1 A2 A1 A0R/W 0 0 0 0 0 0 D1 D0 . . . . . Start Ack Ack by Address Byte by Pointer Byte by Master TCN75 TCN75 1 9 1 9 1 9 1 0 0 1 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4D3 D2 D1 D0 Stop Repeat Ack Ack No Ack Cond Start Address Byte by Most Significant Data Byte by Least Significant Data Byte by by by TCN75 Master Master Master Master (b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, TOS, THYST 1 9 1 9 1 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Stop Start Ack No Ack Cond by Address Byte by Data Byte by by Master TCN75T Master Master (c) Typical 1-Byte Read From Configuration Register with Preset Pointer FIGURE 5-1: Timing Diagrams DS21490D-page 12  2001-2012 Microchip Technology Inc.

TCN75 Timing Diagrams (Continued) pd re StoConbyMast pd er ck er StoConbyMast 9 No AbyMast 75 D0 9 AckbyCN T D1 D0 e D2 D1 Byt e 2 a D3 Byt D Dat D4 ata D3 ant D5 D D4 nific 91 D7D6 AckbyCN75 StopCondbyMaster75 1 D7D6D5 Least Sig75 R/W T 9 AckbyCN 9 AckbyCN 0 0 T 0 T A D D e A1 e D1 D1 Byt 01A2 Address Byt D4D2D3 guration Byte D4D2D3 nificant Data 0 0 onfi D5 Sig 19 1D0 RepeatAckStartbybyTCN75Masteron Register 19 00D0 AckCbyTCN75 19 D0D6D7 AckMost byTCN75 0 rati D1 D1 u g 0 e nfi 0 e 0 e 0 Byt Co 0 Byt 0 Byt 0 nter rom 0 nter 0 nter 0 Poi d f 0 Poi 0 Poi a e R 0 e 0 0 19 0 AckbyCN75 mmediat 19 0 AckbyCN75T 19 0 AckbyCN75 R/W T by I R/W T R/W T A0 wed A0 rite A0 1 o 1 W 1 A2A s Byte et Foll A2A s Byte gister A2A s Byte Write 100 Addres al Pointer S 100 Addres guration Re 100 Addres nd T HYST 1 1 pic 1 1 nfi 1 1 aS StartbyMaster (d) Ty StartbyMaster (e) Co StartbyMaster (f) TO  2001-2012 Microchip Technology Inc. DS21490D-page 13

TCN75 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Package marking data not available at this time. 6.2 Taping Form Component Taping Orientation for 8-Pin MSOP Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 8-Pin MSOP 12 mm 8 mm 2500 13 in Component Taping Orientation for 8-Pin SOIC (Narrow) Devices User Direction of Feed Pin1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 8-Pin SOIC (N) 12 mm 8 mm 2500 13 in DS21490D-page 14  2001-2012 Microchip Technology Inc.

TCN75 6.3 Package Dimensions Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 8-Pin MSOP Pin 1 .122 (3.10) .197 (5.00) .114 (2.90) .189 (4.80) .026 (0.65) Typ. .122 (3.10) .114 (2.90) .043 (1.10) Max. 6° Max. .008 (0.20) .005 (0.13) .016 (0. 40) .006 (0.15) .028 (0.70) .010 (0.25) .002 (0.05) .016 (0.40) Dimensions: inches (mm) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 8-Pin SOIC Pin 1 .157 (3.99) .244 (6.20) .150 (3.81) .228 (5.79) .050 (1.27) Typ. .197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) 8° Max. .010 (0.25) .007 (0.18) .020 (0.51) .010 (0.25) .013 (0.33) .004 (0.10) .050 (1.27) .016 (0.40) Dimensions: inches (mm)  2001-2012 Microchip Technology Inc. DS21490D-page 15

TCN75 7.0 REVISION HISTORY Revision D (December 2012) Added a note to each package outline drawing. DS21490D-page 16  2001-2012 Microchip Technology Inc.

TCN75 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2001-2012 Microchip Technology Inc. DS21490D-page 17

TCN75 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: TCN75 Literature Number: DS21490D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21490D-page 18  2001-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620768815 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2001-2012 Microchip Technology Inc. DS21490D-page 19

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