Product Order Technical Tools & Support & Folder Now Documents Software Community TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 2 TCA6416A Low-Voltage 16-Bit I C and SMBus I/O Expander With Voltage Translation, Interrupt Output, Reset Input, and Configuration Registers 1 Features 2 Applications • I2CtoParallelPortExpander • Servers 1 • OperatingPower-SupplyVoltageRangeof1.65V • Routers(TelecomSwitchingEquipment) to5.5V • PersonalComputers • AllowsBidirectionalVoltage-LevelTranslationand • PersonalElectronics(ForExample,Gaming GPIOExpansionBetween1.8-V,2.5-V,3.3-V, Consoles) and5-VI2CBusandP-Ports • IndustrialAutomation • LowStandbyCurrentConsumptionof3μA • ProductsWithGPIO-LimitedProcessors • 5-VTolerantI/OPorts • 400-kHzFastI2CBus 3 Description • HardwareAddressPinAllowsTwoTCA6416A The TCA6416A is a 24-pin device that provides 16- DevicesontheSameI2C/SMBusBus bits of general purpose parallel input/output (I/O) expansion for the two-line bidirectional I2C bus (or • Active-LowResetInput(RESET) SMBus) protocol. The device can operate with a • Open-DrainActive-LowInterruptOutput(INT) power supply voltage ranging from 1.65 V to 5.5 V on • Input/OutputConfigurationRegister the I2C bus side (VCCI) and a power supply voltage ranging from 1.65 V to 5.5 V on the P-port side • PolarityInversionRegister (VCCP). • InternalPower-OnReset The device supports both 100-kHz (Standard-mode) • Power-UpWithAllChannelsConfiguredasInputs and 400-kHz (Fast-mode) clock frequencies. I/O • NoGlitchOnPowerUp expanders such as the TCA6416A provide a simple • NoiseFilteronSCL/SDAInputs solution when additional I/Os are needed for • LatchedOutputsWithHigh-CurrentDrive switches,sensors,push-buttons,LEDs,fans,etc. MaximumCapabilityforDirectlyDrivingLEDs DeviceInformation(1) • Latch-UpPerformanceExceeds100mAPer PARTNUMBER PACKAGE BODYSIZE(NOM) JESD78,ClassII TSSOP(24) 7.80mm×4.40mm • ESDProtectionExceedsJESD22 WQFN(24) 4.00mm×4.00mm – 2000-VHuman-BodyModel(A114-A) TCA6416A BGAMicrostar 3.00mm×3.00mm – 200-VMachineModel(A115-A) Junior(24) – 1000-VCharged-DeviceModel(C101) (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic VCCI VCCP P00 Peripheral SSDCAL PPP000123 Devices I2CorSMBus INT P04 B RESET, Master RESET PP0056 ENABLE, (processor) P07 orcontrol TCA6416A inputs P10 B INTor P11 status P12 outputs P13 B LEDs P14 B Keypad ADDR P15 P16 GND P17 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagrams.....................................17 2 Applications........................................................... 1 8.3 FeatureDescription.................................................18 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................19 8.5 Programming..........................................................19 4 RevisionHistory..................................................... 2 8.6 RegisterMaps.........................................................20 5 PinConfigurationandFunctions......................... 3 9 ApplicationandImplementation........................ 25 6 Specifications......................................................... 5 9.1 ApplicationInformation............................................25 6.1 AbsoluteMaximumRatings .....................................5 9.2 TypicalApplication .................................................26 6.2 ESDRatings..............................................................5 10 PowerSupplyRecommendations..................... 29 6.3 RecommendedOperatingConditions.......................5 10.1 Power-OnResetRequirements ...........................29 6.4 ThermalInformation..................................................6 11 Layout................................................................... 31 6.5 ElectricalCharacteristics...........................................7 6.6 I2CInterfaceTimingRequirements...........................8 11.1 LayoutGuidelines.................................................31 6.7 ResetTimingRequirements.....................................8 11.2 LayoutExample....................................................32 6.8 SwitchingCharacteristics..........................................8 12 DeviceandDocumentationSupport................. 33 6.9 TypicalCharacteristics..............................................9 12.1 Trademarks...........................................................33 7 ParameterMeasurementInformation................12 12.2 ElectrostaticDischargeCaution............................33 12.3 Glossary................................................................33 8 DetailedDescription............................................ 16 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................16 Information........................................................... 33 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(September2015)toRevisionD Page • Changedthet MAXvalueFrom:1µsTo:0.9µsintheI2CInterfaceTimingRequirementstable............................... 8 vd(data) • Changedthet MAXvalueFrom:1µsTo:0.9µsintheI2CInterfaceTimingRequirementstable................................ 8 vd(ack) ChangesfromRevisionB(January2015)toRevisionC Page • Changedunitsfort andt parametersfromnstoµs.......................................................................................................... 8 IV IR ChangesfromRevisionA(November2009)toRevisionB Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 5 Pin Configuration and Functions PW Package RTW Package 24-Pin TSSOP 24-Pin WQFN Top View Top View T ZQS Package E P VCINCTI 12 2234 VSCDCAP RESVCCI NTVCC SDA SCL 24-Pin BGTAoMp iVcireowstar Junior I RESET 3 22 SCL 24 23 22 21 20 19 P00 4 21 ADDR E P00 1 18 ADDR P01 5 20 P17 P01 2 17 P17 D P02 6 19 P16 Exposed P02 3 16 P16 C P03 7 18 P15 Center P03 4 Pad 15 P15 B P04 8 17 P14 P04 5 14 P14 A P05 9 16 P13 P05 6 13 P13 P06 10 15 P12 7 8 9 10 11 12 5 4 3 2 1 P07 11 14 P11 6 7 D 0 1 2 GND 12 13 P10 P0 P0 N P1 P1 P1 G The exposed center pad, if used, must be connected only as a secondary GND or must be left electrically open. Table1.ZQSPackagePinAssignments E P13 P11 P10 GND P06 D P15 P14 P12 P07 P05 C P16 P17 P01 P04 P03 B ADDR VCCP VCCI NB(1) P02 A SCL SDA INT RESET P00 5 4 3 2 1 (1) NB—Noballatthisposition Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com PinFunctions PIN TSSOP QFN BGA DESCRIPTION NAME (PW) (RTW) (ZQS) INT 1 22 A3 Interruptoutput.ConnecttoV orV throughapull-upresistor. CCI CCP VCCI 2 23 B3 SupplyvoltageofI2Cbus.ConnectdirectlytothesupplyvoltageoftheexternalI2Cmaster. Active-lowresetinput.ConnecttoV orV throughapull-upresistor,ifnoactiveconnection RESET 3 24 A2 CCI CCP isused. P00 4 1 A1 P-portinput/output(push-pulldesignstructure).Atpoweron,P00isconfiguredasaninput. P01 5 2 C3 P-portinput/output(push-pulldesignstructure).Atpoweron,P01isconfiguredasaninput. P02 6 3 B1 P-portinput/output(push-pulldesignstructure).Atpoweron,P02isconfiguredasaninput. P03 7 4 C1 P-portinput/output(push-pulldesignstructure).Atpoweron,P03isconfiguredasaninput. P04 8 5 C2 P-portinput/output(push-pulldesignstructure).Atpoweron,P04isconfiguredasaninput. P05 9 6 D1 P-portinput/output(push-pulldesignstructure).Atpoweron,P05isconfiguredasaninput. P06 10 7 E1 P-portinput/output(push-pulldesignstructure).Atpoweron,P06isconfiguredasaninput. P07 11 8 D2 P-portinput/output(push-pulldesignstructure).Atpoweron,P07isconfiguredasaninput. GND 12 9 E2 Ground P10 13 10 E3 P-portinput/output(push-pulldesignstructure).Atpoweron,P10isconfiguredasaninput. P11 14 11 E4 P-portinput/output(push-pulldesignstructure).Atpoweron,P11isconfiguredasaninput. P12 15 12 D3 P-portinput/output(push-pulldesignstructure).Atpoweron,P12isconfiguredasaninput. P13 16 13 E5 P-portinput/output(push-pulldesignstructure).Atpoweron,P13isconfiguredasaninput. P14 17 14 D4 P-portinput/output(push-pulldesignstructure).Atpoweron,P14isconfiguredasaninput. P15 18 15 D5 P-portinput/output(push-pulldesignstructure).Atpoweron,P15isconfiguredasaninput. P16 19 16 C5 P-portinput/output(push-pulldesignstructure).Atpoweron,P16isconfiguredasaninput. P17 20 17 C4 P-portinput/output(push-pulldesignstructure).Atpoweron,P17isconfiguredasaninput. ADDR 21 18 B5 Addressinput.ConnectdirectlytoV orground. CCP SCL 22 19 A5 Serialclockbus.ConnecttoV throughapull-upresistor. CCI SDA 23 20 A4 Serialdatabus.ConnecttoV throughapull-upresistor. CCI VCCP 24 21 B4 SupplyvoltageofTCA6416AforP-ports 4 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CCI V Supplyvoltage –0.5 6.5 V CCP V Inputvoltage (2) –0.5 6.5 V I V Outputvoltage (2) –0.5 6.5 V O I Inputclampcurrent ADDR,RESET,SCL V <0 ±20 mA IK I I Outputclampcurrent INT V <0 ±20 mA OK O Pport V <0orV >V ±20 O O CCP I Input/outputclampcurrent mA IOK SDA V <0orV >V ±20 O O CCI Pport V =0toV 50 O CCP I Continuousoutputlowcurrent mA OL SDA,INT V =0toV 25 O CCI I Continuousoutputhighcurrent Pport V =0toV 50 mA OH O CCP ContinuouscurrentthroughGND 200 I ContinuouscurrentthroughV 160 mA CC CCP ContinuouscurrentthroughV 10 CCI T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±1000 V C101(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions MIN MAX UNIT V Supplyvoltage 1.65 5.5 CCI V V Supplyvoltage 1.65 5.5 CCP SCL,SDA 0.7×V V (1) CCI CCI V High-levelinputvoltage RESET 0.7×V 5.5 V IH CCI ADDR,P17–P00 0.7×V 5.5 CCP SCL,SDA,RESET –0.5 0.3×V CCI V Low-levelinputvoltage V IL ADDR,P17–P00 –0.5 0.3×V CCP I High-leveloutputcurrent P17–P00 10 mA OH I Low-leveloutputcurrent P17–P00 25 mA OL T Operatingfree-airtemperature –40 85 °C A (1) TheSCLandSDApinsshallnotbeatahigherpotentialthanthesupplyvoltageV intheapplication,oranincreaseincurrent CCI consumptionwillresult. Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 6.4 Thermal Information TCA6416A THERMALMETRIC(1) PW(TSSOP) RTW(WQFN) ZQS UNIT (BGAMICROSTARJUNIOR) 24PINS 24PINS 24PINS R Junction-to-ambientthermalresistance 108.8 43.6 159.2 °C/W θJA R Junction-to-case(top)thermalresistance 54.0 46.2 138.2 °C/W θJC(top) R Junction-to-boardthermalresistance 62.8 22.1 93.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 11.1 1.5 10.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 62.3 22.2 95.7 °C/W JB R Junction-to-case(bottom)thermalresistance N/A 10.7 N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange,V =1.65Vto5.5V(unlessotherwisenoted) CCI PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CCP Inputdiodeclamp V I =–18mA 1.65Vto5.5V –1.2 V IK voltage I Power-onreset V V =V orGND,I =0 1.65Vto5.5V 1 1.4 V POR voltage I CCP O 1.65V 1.2 2.3V 1.8 I =–8mA OH 3V 2.6 P-porthigh-level 4.5V 4.1 V V OH outputvoltage 1.65V 1.1 2.3V 1.7 I =–10mA OH 3V 2.5 4.5V 4.0 1.65V 0.45 2.3V 0.25 I =8mA OL 3V 0.25 P-portlow-level 4.5V 0.2 V V OL outputvoltage 1.65V 0.6 2.3V 0.3 I =10mA OL 3V 0.25 4.5V 0.2 SDA V =0.4V 1.65Vto5.5V 3 OL I mA OL INT V =0.4V 1.65Vto5.5V 3 15 OL SCL,SDA, V =V orGND ±0.1 I RESET I CCI 1.65Vto5.5V μA I ADDR V =V orGND ±0.1 I CCP I Pport V =V 1 μA IH I CCP 1.65Vto5.5V I Pport V =GND 1 μA IL I 3.6Vto5.5V 10 20 V onSDAandRESET=V orGND, SDA,Pport, I CCI V onPportandADDR=V , 2.3Vto3.6V 6.5 15 ADDR,RESET I CCP I =0,I/O=inputs,f =400kHz I O SCL 1.65Vto2.3V 4 9 CC μA (ICCI+ICCP) 3.6Vto5.5V 1.5 7 V onSCL,SDAandRESET=V orGND, SCL,SDA,Pport, I CCI V onPportandADDR=V , 2.3Vto3.6V 1 3.2 ADDR,RESET I CCP I =0,I/O=inputs,f =0 O SCL 1.65Vto2.3V 0.5 1.7 SCL,SDA, OneinputatV –0.6V, CCI 25 ΔICCI RESET OtherinputsatVCCIorGND 1.65Vto5.5V μA ΔICCP Pport,ADDR OneinputatVCCP–0.6V, 80 OtherinputsatV orGND CCP C SCL V =V orGND 1.65Vto5.5V 6 7 pF i I CCI SDA V =V orGND 7 8 IO CCI C 1.65Vto5.5V pF io Pport V =V orGND 7.5 8.5 IO CCP (1) ExceptforI ,alltypicalvaluesareatnominalsupplyvoltage(1.8-V,2.5-V,3.3-V,or5-VV )andT =25°C.ForI ,thetypical CC CC A CC valuesareatV =V =3.3VandT =25°C. CCP CCI A Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 6.6 I2C Interface Timing Requirements overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure18) STANDARDMODE FASTMODE I2CBUS I2CBUS UNIT MIN MAX MIN MAX f I2Cclockfrequency 0 100 0 400 kHz scl t I2Cclockhightime 4 0.6 μs sch t I2Cclocklowtime 4.7 1.3 μs scl t I2Cspiketime 0 50 0 50 ns sp t I2Cserialdatasetuptime 250 100 ns sds t I2Cserialdataholdtime 0 0 ns sdh t I2Cinputrisetime 1000 20+0.1C (1) 300 ns icr b t I2Cinputfalltime 300 20+0.1C (1) 300 ns icf b t I2Coutputfalltime;10pFto400pFbus 300 20+0.1C (1) 300 μs ocf b t I2CbusfreetimebetweenStopandStart 4.7 1.3 μs buf t I2CStartorrepeaterStartconditionsetuptime 4.7 0.6 μs sts t I2CStartorrepeaterStartconditionholdtime 4 0.6 μs sth t I2CStopconditionsetuptime 4 0.6 μs sps t Validdatatime;SCLlowtoSDAoutputvalid 1 0.9 μs vd(data) ValiddatatimeofACKcondition;ACKsignalfromSCLlowtoSDA t 1 0.9 μs vd(ack) (out)low (1) C =totalcapacitanceofonebuslineinpF b 6.7 Reset Timing Requirements overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure21) STANDARDMODE FASTMODE I2CBUS I2CBUS UNIT MIN MAX MIN MAX t Resetpulseduration 4 4 ns W t Resetrecoverytime 0 0 ns REC t Timetoreset(1) 600 600 ns RESET (1) MinimumtimeforSDAtobecomehighorminimumtimetowaitbeforedoingaSTART 6.8 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C ≤100pF(unlessotherwisenoted)(seeFigure18) L STANDARD FASTMODE MODE I2CBUS PARAMETER FROM TO I2CBUS UNIT MIN MAX MIN MAX t Interruptvalidtime Pport INT 4 4 µs IV t Interruptresetdelaytime SCL INT 4 4 µs IR t Outputdatavalid SCL P7–P0 400 400 ns PV t Inputdatasetuptime Pport SCL 0 0 ns PS t Inputdataholdtime Pport SCL 300 300 ns PH 8 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 6.9 Typical Characteristics T =25°C(unlessotherwisenoted) A 22 2000 20 VCC= 5.5V 1800 VCC= 5.5V µA)(C 1186 VCC= 5V A)(nCC11460000 VCC= 5V C 14 I ent,I 12 rent, 11020000 VCC= 3.3V ply Curr 1806 VVCCCC== 3 2.3.5VV pply Cur 680000 VVCCCC= =2 .15.8VV Sup 4 VCC= 1.8V Su 400 VCC= 1.65V 2 V = 1.65V 200 CC 0 0 -40 -15 10 35 60 85 –40 –15 10 35 60 85 Temperature,T (°C) Temperature,T (°C) A A Figure1.SupplyCurrentvsTemperature Figure2.StandbySupplyCurrentvsTemperature 22 30 20 VCC= 1.65V (µA) 1186 (mA) 25 TA =–40°C upply Current,ICC 11148062 k Current,ISINK121005 TA= 25°C TA= 85°C S 4 Sin 5 2 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SupplyVoltage,V (V) Output LowVoltage,V (V) CC OL Figure3.SupplyCurrentvsSupplyVoltage Figure4.I/OSinkCurrentvsOutputLowVoltage 35 50 VCC= 1.8V VCC= 2.5V A) 30 TA =–40°C A) 40 TA =–40°C m m ( 25 ( NK NK TA= 25°C SI 20 TA= 25°C SI 30 I I nt, nt, re 15 re 20 r r u u C 10 C nk TA= 85°C nk 10 TA= 85°C Si 5 Si 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Output LowVoltage,V (V) Output LowVoltage,V (V) OL OL Figure5.I/OSinkCurrentvsOutputLowVoltage Figure6.I/OSinkCurrentvsOutputLowVoltage Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com Typical Characteristics (continued) T =25°C(unlessotherwisenoted) A 60 70 VCC= 3.3V VCC= 5.0V A) 50 TA =–40°C A) 60 TA =–40°C m m ( ( 50 K 40 K N N SI TA= 25°C SI 40 nt,I 30 nt,I TA= 25°C e e 30 r r r r u 20 u C C 20 nk TA= 85°C nk TA= 85°C Si 10 Si 10 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Output LowVoltage,V (V) Output LowVoltage,V (V) OL OL Figure7.I/OSinkCurrentvsOutputLowVoltage Figure8.I/OSinkCurrentvsOutputLowVoltage 70 250 A) 60 VCC= 5.5V TA =–40°C mV)( 200 VCC= 1.8 V, ISINK= 10 mA m L ( 50 O K V rent,ISIN 3400 TA= 25°C Voltage, 110500 VCC= 5 V, ISINK= 10 mA ur w nk C 20 TA= 85°C ut Lo 50 VCC= 1.8 V, ISINK= 1 mA Si 10 p VCC= 5 V, ISINK= 1 mA ut O 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -15 10 35 60 85 Output LowVoltage,V (V) Temperature,T (°C) OL A Figure9.I/OSinkCurrentvsOutputLowVoltage Figure10.I/OLowVoltagevsTemperature 20 25 A) VCC= 1.65V TA=–40°C A) VCC= 1.8V TA=–40°C m m ( ( 20 E15 E C C R R U U SO TA= 25°C SO15 TA= 25°C nt,I 10 nt,I e e 10 r r e Cur 5 TA= 85°C e Cur 5 TA= 85°C c c r r u u o o S S 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V –V (V) V –V (V) CCP OH CCP OH Figure11.I/OSourceCurrentvsOutputHighVoltage Figure12.I/OSourceCurrentvsOutputHighVoltage 10 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 Typical Characteristics (continued) T =25°C(unlessotherwisenoted) A 35 50 mA) 30 VCC= 2.5V TA=–40°C mA) VCC= 3.3V TA=–40°C ( ( 40 E E C 25 C R R U U nt,ISO2105 TA= 25°C nt,ISO 30 TA= 25°C e e 20 urce Curr 105 TA= 85°C urce Curr 10 TA= 85°C o o S S 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 VCCP–VOH(V) VCCP–VOH(V) Figure13.I/OSourceCurrentvsOutputHighVoltage Figure14.I/OSourceCurrentvsOutputHighVoltage 60 70 A) VCC= 5.0V TA=–40°C A) VCC= 5.5V m 50 m 60 TA=–40°C ( ( E E C C 50 R 40 R U U SO TA= 25°C SO 40 nt,I 30 nt,I 30 TA= 25°C e e r r e Cur 20 TA= 85°C e Cur 20 TA= 85°C rc 10 rc 10 u u o o S S 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V –V (V) V –V (V) CCP OH CCP OH Figure15.I/OSourceCurrentvsOutputHighVoltage Figure16.I/OSourceCurrentvsOutputHighVoltage 350 ISOURCE=–10 mA 300 V) m 250 ( VCC= 1.8 V OH200 V –C150 VCC= 5 V C V 100 50 0 -40 -15 10 35 60 85 Temperature,T (°C) A Figure17.I/OHighVoltagevsTemperature Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 7 Parameter Measurement Information V CCI R = 1 kW L SDA DUT C = 50 pF L (see NoteA) SDALOAD CONFIGURATION Two Bytes for READ Input Port Register (see Figure 9) Stop Start Address R/W Data Data Stop Address ACK Condition Condition Bit 7 Bit 0 Bit 7 Bit 0 Condition Bit 1 (A) (P) (S) (MSB) (LSB) (MSB) (LSB) (P) tscl tsch 0.7´V CCI SCL 0.3´V CCI tbuf ticr ticf tsp tvtdvd tsts tocf tsps 0.7´V CCI SDA 0.3´V CCI ticf ticr tsds tsdh tvd(ack) t sth Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2 Input register port data A. C includesprobeandjigcapacitance.tocfismeasuredwithC of10pFor400pF. L L B. Allinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,Z =50Ω,t/t ≤30ns. O r f C. Allparametersandwaveformsarenotapplicabletoalldevices. Figure18. I2CInterfaceLoadCircuitAndVoltageWaveforms 12 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 Parameter Measurement Information (continued) V CCI R = 4.7 kW L INT DUT C = 100 pF L (see NoteA) INTERRUPT LOAD CONFIGURATION ACK From Slave Start ACK Condition 8 Bits From Slave R/W (One Data Byte) SlaveAddress From Port Data From Port S 0 1 0 0 0 0 AD 1 A Data 1 A Data 2 1 P DR 1 2 3 4 5 6 7 8 A A tir B t ir B INT A t iv t sps A Data Into Address Data 1 Data 2 Port 0.7´V INT 0.5´VCCI SCL R/W A 0.3´VCCI CCI t iv t ir Pn 0.5´V INT 0.5´VCCI CCP ViewA−A View B−B A. C includesprobeandjigcapacitance. L B. Allinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,Z =50Ω,t/t ≤30ns. O r f C. Allparametersandwaveformsarenotapplicabletoalldevices. Figure19. InterruptLoadCircuitandVoltageWaveforms Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com Parameter Measurement Information (continued) Pn 500W DUT 2´V CCP C = 50 pF L 500W (see NoteA) P-PORT LOAD CONFIGURATION 0.7´V SCL CCP P0 A P3 0.3´V CCI Slave ACK SDA t pv (see Note B) Pn Last Stable Bit Unstable Data WRITE MODE (R/W= 0) 0.7´V SCL CCI P0 A P3 0.3´V CCI t ph t ps Pn 0.5´V CCP READ MODE (R/W= 1) A. C includesprobeandjigcapacitance. L B. t ismeasuredfrom0.7×V onSCLto50%I/O(Pn)output. pv CC C. Allinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,Z =50Ω,t/t ≤30ns. O r f D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure20. P-PortLoadCircuitandTimingWaveforms 14 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 Parameter Measurement Information (continued) V CCI R = 1 kW L Pn 500W SDA DUT 2´V DUT CCP CL= 50 pF CL= 50 pF 500W (see NoteA) (see NoteA) SDALOAD CONFIGURATION P-PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3´V CCI t RESET RESET VCCP/2 t t REC REC t W Pn VCCP/2 t RESET A. C includesprobeandjigcapacitance. L B. Allinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,Z =50Ω,t/t ≤30ns. O r f C. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement. D. I/Osareconfiguredasinputs. E. Allparametersandwaveformsarenotapplicabletoalldevices. Figure21. ResetLoadCircuitsandVoltageWaveforms Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 8 Detailed Description 8.1 Overview The TCA6416A is a 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V operation. It provides general-purpose remote I/O expansion and bidirectional voltage translation for processors throughI2Ccommunication,aninterfaceconsistingofserialclock(SCL),andserialdata(SDA)signals. The major benefit of the TCA6416A is its voltage translation capability over a of a wide supply voltage range. This allows the TCA6416A to interface with modern processors on the I2C side, where supply levels are lower to conserve power. In contrast to the dropping power supplies of processors, some PCB components such as LEDs,stillrequirea5-Vpowersupply. TheVCCIpinisthepowersupplyfortheI2Cbus,andthereforethepull-upresistorsconnectedtotheSCL,SDA, INT, and RESET pins should be terminated at V on the opposite side. level of the I2C bus to the TCA6416A. CCI The VCCP pin is the power supply for the P-ports and if pull-up resistors are used on any P-port or LEDs are driven by any P-port, then the resistor(s) or LED(s) connected to P00-P07 and P10-P17 should be terminated at V on the opposite side. The device P-ports configured as outputs have the ability to sink up to 25 mA for CCP directlydrivingLEDs,butthecurrentmustbelimitedexternallywithanadditionalresistance. The features of the device include an interrupt that is generated on the INT pin whenever an input port changes state. The devices can also be reset to its default state by applying a low logic level to the RESET pin or by cycling power to the device and causing a power-on reset. The ADDR hardware selectable address pin allows twoTCA6416AdevicestobeconnectedtothesameI2Cbus. The TCA6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The INT pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the TCA6416A can inform the processor if there is incoming data on the remote I/O ports without having to communicateviatheI2Cbus.Thus,theTCA6416Acanremainasimpleslavedevice. The system master can reset the TCA6416A in the event of a timeout or other improper operation by asserting a low on the RESET input pin or by cycling the power to the VCCP pin and causing a power-on reset (POR). A reset puts the registers in their default state and initializes the I2C /SMBus state machine. The RESET feature and a POR cause the same reset/initialization to occur, but the RESET feature does so without powering down thepart. One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow two devices to sharethesameI2CbusorSMBus. The TCA6416A's digital core consists of eight 8-bit data registers: two Configuration registers (input or output selection),twoInputPortregisters,twoOutputPortregisters,andtwoPolarityInversionregisters.Atpoweronor after a reset, the I/Os are configured as inputs. However, the system master can configure the I/Os as either inputs or outputs by writing to the Configuration registers. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the PolarityInversionregister.Allregisterscanbereadbythesystemmaster. 16 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 8.2 Functional Block Diagrams INT 1 LPFilter InLteorgriucpt 21 4-11 ADDR P00–P07 22 SCL Input I2C Bus Shift SDA 23 Filter Control Register 16 Bits I/O Port 13-20 P10–P17 VCCI 2 Write Pulse 24 Read Pulse VCCP Power-On RESET 3 Reset 12 GND A. AllI/Osaresettoinputsatreset. B. PinnumbersshownareforthePWpackage. Figure22. LogicDiagram(PositiveLogic) Data From Shift Register Output Port Configuration Register Data Data From Register VCCP Shift Register D Q Q1 FF Write Configuration Pulse CK Q D Q FF P00 to P17 Write Pulse CK Q Output Q2 ESD Protection Diode Port Input Register Port GND Register D Q Input Port FF Register Data Read Pulse CK Q ToINT ShiDft aRtae gFirsotemr D Q PRoelgairsitteyr Data FF Write Polarity Pulse CK Q Polarity Inversion Register A. Onpoweruporreset,allregistersreturntodefaultvalues. Figure23. SimplifiedSchematicofP0toP17 Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 8.3 Feature Description 8.3.1 VoltageTranslation Table 2 lists all of the optional voltage supply level combinations for the I2C bus (V ) and the P-ports (V ) CCI CCP supportedbytheTCA6416A. Table2.VoltageTranslation V (SDAANDSCLOFI2CMASTER) V (P-PORTS) CCI CCP (V) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 5 2.5 1.8 2.5 2.5 2.5 3.3 2.5 5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 5 5 1.8 5 2.5 5 3.3 5 5 8.3.2 I/OPort When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The inputvoltagemayberaisedaboveV toamaximumof5.5V. CC If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either V or GND. The external voltage CC appliedtothisI/Opinshouldnotexceedtherecommendedlevelsforproperoperation. 8.3.3 InterruptOutput(INT) Aninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputsintheinputmode.Aftertimet ,thesignal iv INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.EachchangeoftheI/Osafterresettingisdetectedandistransmittedas INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the stateofthepindoesnotmatchthecontentsoftheInputPortregister. The INT output has an open-drain structure and requires pull-up resistor to V or V depending on the CCP CCI application.INT shouldbeconnectedtothevoltagesourceofthedevicethatrequirestheinterruptinformation. 8.3.4 ResetInput(RESET) The RESET input can be asserted to initialize the system while keeping the V at its operating level. A reset CCP can be accomplished by holding the RESET pin low for a minimum of t . The TCA6416A registers and W I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), theI/OlevelsatthePportcanbechangedexternallyorthroughthemaster.Thisinputrequiresapull-upresistor toV ,ifnoactiveconnectionisused. CCI 18 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 8.4 Device Functional Modes 8.4.1 Power-OnReset When power (from 0 V) is applied to V , an internal power-on reset holds the TCA6416A in a reset condition CCP until V has reached V . At that time, the reset condition is released, and the TCA6416A registers and CCP POR I2C/SMBus state machine initializes to their default states. After that, V must be lowered to below V and CCP PORF backuptotheoperatingvoltageforapower-resetcycle. 8.5 Programming 8.5.1 I2CInterface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfermaybeinitiatedonlywhenthebusisnotbusy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 24). After the Start condition, the device address byteissent,mostsignificantbit(MSB)first,includingthedatadirectionbit(R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must notbechangedbetweentheStartandtheStopconditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands(StartorStop)(seeFigure25). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master(seeFigure24). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 26). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold timesmustbemettoensureproperoperation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after thelastbytehasbeenclockedoutoftheslave.ThisisdonebythemasterreceiverbyholdingtheSDAlinehigh. Inthisevent,thetransmittermustreleasethedatalinetoenablethemastertogenerateaStopcondition. SDA SCL S P Start Condition Stop Condition Figure24. DefinitionofStartandStopConditions SDA SCL Data Line Change Figure25. BitTransfer Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com Programming (continued) Data Output by Transmitter NACK Data Output by Receiver ACK SCLFrom Master 1 2 8 9 S Start Clock Pulse for Condition Acknowledgment Figure26. AcknowledgmentontheI2CBus Table3.InterfaceDefinition BIT BYTE 7(MSB) 6 5 4 3 2 1 0(LSB) I2Cslaveaddress L H L L L L ADDR R/W P07 P06 P05 P04 P03 P02 P01 P00 I/Odatabus P17 P16 P15 P14 P13 P12 P11 P10 8.6 Register Maps 8.6.1 DeviceAddress TheaddressoftheTCA6416AisshowninFigure27. Slave Address AD 0 1 0 0 0 0 DR R/W Fixed Programmable Figure27. TCA6416AAddress Table4.AddressReference ADDR I2CBUSSLAVEADDRESS L 32(decimal),20(hexadecimal) H 33(decimal),21(hexadecimal) 20 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation,whilealow(0)selectsawriteoperation. 8.6.2 ControlRegisterandCommandByte Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA6416A. Three bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be writtenorreadthroughtheI2Cbus.Thecommandbyteissentonlyduringawritetransmission. Once a new command has been sent, the register that was addressed continues to be accessed by reads until a newcommandbytehasbeensent. B7 B6 B5 B4 B3 B2 B1 B0 Figure28. ControlRegisterBits Table5.CommandByte CONTROLREGISTERBITS COMMANDBYTE POWER-UP REGISTER PROTOCOL B7 B6 B5 B4 B3 B2 B1 B0 (HEX) DEFAULT 0 0 0 0 0 0 0 0 00 InputPort0 Readbyte xxxxxxxx(1) 0 0 0 0 0 0 0 1 01 InputPort1 Readbyte xxxxxxxx(1) 0 0 0 0 0 0 1 0 02 OutputPort0 Read/writebyte 11111111 0 0 0 0 0 0 1 1 03 OutputPort1 Read/writebyte 11111111 0 0 0 0 0 1 0 0 04 PolarityInversion 0 Read/writebyte 00000000 0 0 0 0 0 1 0 1 05 PolarityInversion1 Read/writebyte 00000000 0 0 0 0 0 1 1 0 06 Configuration0 Read/writebyte 11111111 0 0 0 0 0 1 1 1 07 Configuration1 Read/writebyte 11111111 (1) Undefined 8.6.3 RegisterDescriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Portregisterwillbeaccessednext. Table6.Registers0and1(InputPortRegisters) BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00 DEFAULT X X X X X X X X BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 I-10 DEFAULT X X X X X X X X The Output Port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table7.Registers2and3(OutputPortRegisters) BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00 DEFAULT 1 1 1 1 1 1 1 1 BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10 DEFAULT 1 1 1 1 1 1 1 1 Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com The Polarity Inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is retained. Table8.Registers4and5(PolarityInversionRegisters) BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 P-00 DEFAULT 0 0 0 0 0 0 0 0 BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10 DEFAULT 0 0 0 0 0 0 0 0 The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registersisclearedto0,thecorrespondingportpinisenabledasanoutput. Table9.Registers6and7(ConfigurationRegisters) BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 C-00 DEFAULT 1 1 1 1 1 1 1 1 BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 C-10 DEFAULT 1 1 1 1 1 1 1 1 8.6.4 BusTransactions DataisexchangedbetweenthemasterandTCA6416Athroughwriteandreadcommands. 8.6.4.1 Writes Data is transmitted to the TCA6416A by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 27 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent inonewritetransmission. The eight registers within the TCA6416A are configured to operate as four register pairs. The four pairs are input ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 29 and Figure 30). For example, if the first byte is sendtoOutputPort1(register3),thenextbyteisstoredinOutputPort0(register2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register maybeupdatedindependentlyoftheotherregisters. SCL 1 2 3 4 5 6 7 8 9 Slave Address Command Byte Data to Port 0 Data to Port 1 SDA S 0 1 0 0 0 0 AD 0 A 0 0 0 0 0 0 1 0 A 0.7 Data 0 0.0 A 1.7 Data 1 1.0 A P DR Start Condition R/WAcknowledge Acknowledge Acknowledge From Slave From Slave From Slave Write to Port Data Out from Port 0 t pv Data Out from Port 1 DataValid t pv Figure29. WritetoOutputPortRegister <br/> 22 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SlaveAddress Command Byte Data toRegister Data toRegister AD SDA S 0 1 0 0 0 0 DR 0 A 0 0 0 0 0 1 1/0 0/1 A MSB Data 0 LSB A MSB Data1 LSB A P Start Condition R/W Acknowledge Acknowledge Acknowledge From Slave From Slave From Slave Figure30. WritetoConfigurationorPolarityInversionRegisters 8.6.4.2 Reads The bus master first must send the TCA6416A address with the LSB set to a logic 0 (see Figure 27 for device address).Thecommandbyteissentaftertheaddressanddetermineswhichregisterisaccessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register definedbythecommandbytethenissentbytheTCA6416A(seeFigure31andFigure32). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurswhenInputPort0isbeingread,thestoredcommandbytechangestoreferenceInputPort0.Theoriginal command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next bytereadisInputPort0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledgethedata. Data From Lower Acknowledge Acknowledge Acknowledge or Upper Byte Acknowledge Slave Address From Slave From Slave Slave Address From Slave of Register From Master S 0 1 0 0 0 0 ADDR 0 A Command Byte A S 0 1 0 0 0 0 ADDR 1 A MSB Data LSB A First Byte R/W R/W At this moment,master transmitter becomes master receiver,and slave receiver becomesslave transmitter. Data From Upper or Lower Byte No Acknowledge of Register From Master MSB Data LSB NA P Last Byte Figure31. ReadFromRegister <br/> Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com SCL 1 2 3 4 5 6 7 R 9 SlaveAddress Data From Port Data From Port AD SDA S 0 1 0 0 0 0 1 A Data 1 A Data 4 NA P DR Start R/W ACK From ACK From NACK From Stop Condition Slave Master Master Condition Read From Port Data Into Data 2 Data 3 Data 4 Data 5 Port t t ph ps INTis cleared by Read from Port INT Stop not needed to clearINT t t iv ir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledgephaseisvalid(outputmode).Itisassumedthatthecommandbytepreviouslyhasbeensetto00(read InputPortregister). B. Thisfigureeliminatesthecommandbytetransfer,arestart,andslaveaddresscallbetweentheinitialslaveaddress callandactualdatatransferfromPport(seeFigure31). Figure32. ReadInputPortRegister 24 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information Applications of the TCA6416A will have this device connected as a slave to an I2C master (processor), and the I2C bus may contain any number of other slave devices. The TCA6416A will be in a remote location from the master,placedclosetotheGPIOstowhichthemasterneedstomonitororcontrol. A typical application of the TCA6416A will operate with a lower voltage on the master side (VCCI), and a higher voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices such as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as inputstoreceivedatafrominterrupts,alarms,statusoutputs,orpushbuttons. Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 9.2 Typical Application Figure33showsanapplicationinwhichtheTCA6416Acanbeused. VCCI VCCP V 10 kW(´7) CCI ALARM (1.8 V) (see Note E) 2 24 V 10 kW 10 kW 10 kW 10 kW Subsystem 1 CC VCCI VCCP (e.g.,Alarm) SCL 22 SCL P00 4 Master A 23 Controller SDA SDA INT 1 INT P01 5 3 ENABLE GND RESET RESET B 6 P02 7 P03 8 P04 9 TCA6416A P05 10 P06 11 P07 13 P10 P11 14 Keypad 15 P12 16 21 P13 ADDR 17 P14 18 P15 19 P16 20 P17 GND 12 A. Deviceaddressconfiguredas0100000forthisexample. B. P00andP02–P10areconfiguredasinputs. C. P01andP11–P17areconfiguredasoutputs. D. PinnumbersshownareforthePWpackage. E. Resistorsarerequiredforinputs(onPport)thatmayfloat.Ifadrivertoaninputwillneverlettheinputfloat,aresistor isnotneeded.Outputs(inthePport)donotneedpullupresistors. Figure33. TypicalApplicationSchematic 9.2.1 DesignRequirements Table10.DesignParameters DESIGNPARAMETER EXAMPLEVALUE I2Cinputvoltage(V ) 1.8V CCI P-portinput/outputvoltage(V ) 5V CCP Outputcurrentrating,P-portsinking(I ) 25mA OL Outputcurrentrating,P-portsourcing(I ) 10mA OH I2Cbusclock(SCL)speed 400kHz 26 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 9.2.2 DetailedDesignProcedure The pull-up resistors, R , for the SCL and SDA lines need to be selected appropriately and take into P consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of V ,V ,andI : CC OL,(max) OL - V V = CC OL(max) R p(min) I OL (1) Themaximumpull-upresistanceisafunctionofthemaximumrisetime,t (300nsforfast-modeoperation,f = r SCL 400kHz)andbuscapacitance,C : b t = r R p(max) ´ 0.8473 C b (2) The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9538, C for SCL or i C forSDA,thecapacitanceofwires/connections/traces,andthecapacitanceofadditionalslavesonthebus. io 9.2.2.1 MinimizingI WhenI/OsControlLEDs CC When the I/Os are used to control LEDs, normally they are connected to V through a resistor as shown in CC Figure 34. For a P-port configured as an input, I increases as V becomes lower than V . The LED is a diode, CC I CC with threshold voltage V , and when a P-port is configured as an input the LED will be off but V is a V drop T I T belowV . CC For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or equal to V when the P-ports are configured as input to minimize current consumption. Figure 34 shows a high- CC value resistor in parallel with the LED. Figure 35 shows V less than the LED supply voltage by at least V . CC T Both of these methods maintain the I/O V at or above V and prevents additional supply current consumption I CC whentheP-portisconfiguredasaninputandtheLEDisoff. V CC LED 100 k V CC LEDx Figure34. High-ValueResistorinParallelWithLED 3.3 V 5 V V LED CC LEDx Figure35. DeviceSuppliedbyaLowerVoltage Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 9.2.3 ApplicationCurves 25 1.8 Standard-mode Fast-mode 1.6 20 1.4 m) m) 1.2 Oh 15 Oh 1 R (kp(max) 10 R (kp(min) 00..68 5 0.4 0.2 VCC > 2V VCC <= 2 0 0 0 50 100 150 200 250 300 350 400 450 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Cb (pF) D008 VCC (V) D009 Standard-mode:f =100kHz,t =1µs V =0.2×V ,I =2mAwhenV ≤2V SCL r OL CC OL CC Fast-mode:f =400kHz,t=300ns V =0.4V,I =3mAwhenV >2V SCL r OL OL CC Figure36.MaximumPullupResistance(R )vsBus Figure37.MinimumPullupResistance(R )vsPullup p(max) p(min) Capacitance(C ) ReferenceVoltage(V ) b CC 28 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 10 Power Supply Recommendations 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, TCA6416A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This resetalsohappenswhenthedeviceispoweredonforthefirsttimeinanapplication. Thetwotypesofpower-onresetareshowninFigure38andFigure39. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time Time to Re-Ramp VCC_RT VCC_FT VCC_RT Figure38. V isLoweredBelow0.2Vor0VandThenRampeduptoV CC CC V CC Ramp-Down Ramp-Up V CC_TRR_VPOR50 V drops below POR levels IN Time Time to Re-Ramp V V CC_FT CC_RT Figure39. V isLoweredBelowthePORThreshold,ThenRampedBackuptoV CC CC Table11specifiestheperformanceofthepower-onresetfeatureforTCA6416Aforbothtypesofpower-onreset. Table11.RecommendedSupplySequencingandRampRates(1) (2) PARAMETER MIN TYP MAX UNIT t Fallrate SeeFigure38 0.1 2000 ms FT t Riserate SeeFigure38 0.1 2000 ms RT t Timetore-ramp(whenV dropstoGND) SeeFigure38 1 μs TRR_GND CC t Timetore-ramp(whenV dropstoV –50mV) SeeFigure39 1 μs TRR_POR50 CC POR_MIN LevelthatV canglitchdownto,butnotcauseafunctional V CCP SeeFigure40 1.2 V CC_GH disruptionwhenV =1μs CCX_GW Glitchwidththatwillnotcauseafunctionaldisruptionwhen t SeeFigure40 10 μs GW V =0.5×V CCX_GH CCx V VoltagetrippointofPORonfallingV 0.7 V PORF CC V VoltagetrippointofPORonfisingV 1.4 V PORR CC (1) T =25°C(unlessotherwisenoted). A (2) Nottested.Specifiedbydesign. Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V ) and height (V ) are dependent on each other. The bypass capacitance, source impedance, and CC_GW CC_GH device impedance are factors that affect power-on reset performance. Figure 40 and Table 11 provide more informationonhowtomeasurethesespecifications. V CC V CC_GH Time V CC_GW Figure40. GlitchWidthandGlitchHeight V is critical to the power-on reset. V is the voltage level at which the reset condition is released and all the POR POR registers and the I2C/SMBus state machine are initialized to their default states. The value of V differs based POR ontheV beingloweredtoorfrom0.Figure41andTable11providemoredetailsonthisspecification. CC V CC V POR V PORF Time POR Time Figure41. V POR 30 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 11 Layout 11.1 Layout Guidelines For printed circuit board (PCB) layout of the TCA6416A, common PCB layout practices should be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairsarenotaconcernforI2Csignalspeeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCCP pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high- frequency ripple. These capacitors should be placed as close to the TCA6416A as possible. These best practicesareshowninFigure42. For the layout example provided in Figure 42, it would be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (V and V ) and CCI CCP ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to V , V , or GND and the via is connected electrically to the internal layer or the other side of the CCI CCP board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this techniqueisnotdemonstratedinFigure42. Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TCA6416A

TCA6416A SCPS194D–MAY2009–REVISEDAUGUST2017 www.ti.com 11.2 Layout Example LEGEND Partial view of plane (inner layer) Via to power plane Via to GND plane V Bypass/decoupling C capacitors V sor CI C s e C c pro P o T 1 INT PW package VCCP 16 2 VCCI SDA 15 3 RESET SCL 14 4 P00 ADDR 13 A 5 P01 P17 16 6 1 6 P02 P16 15 4 6 7 P03 A P15 14 C Os 8 P04 T P14 13 To I/ 9 P05 P13 16 To 10 P06 P12 15 I/O s 11 P07 P11 14 12 GND P10 13 G N D Figure42. TCA6416ALayout 32 SubmitDocumentationFeedback Copyright©2009–2017,TexasInstrumentsIncorporated ProductFolderLinks:TCA6416A

TCA6416A www.ti.com SCPS194D–MAY2009–REVISEDAUGUST2017 12 Device and Documentation Support 12.1 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2009–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TCA6416A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TCA6416APWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 PH416A & no Sb/Br) TCA6416ARTWR ACTIVE WQFN RTW 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PH416A & no Sb/Br) TCA6416AZQSR LIFEBUY BGA ZQS 24 2500 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 PH416A MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TCA6416APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TCA6416ARTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TCA6416AZQSR BGAMI ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TCA6416APWR TSSOP PW 24 2000 367.0 367.0 38.0 TCA6416ARTWR WQFN RTW 24 3000 367.0 367.0 35.0 TCA6416AZQSR BGAMICROSTAR ZQS 24 2500 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE RTW0024B WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK-NO LEAD B 4.1 A 3.9 4.1 3.9 PIN 1 INDEX AREA C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 (0.2) TYP EXPOSED 7 12 THERMAL PAD 20X 0.5 6 13 2X SYMM 25 2.45±0.1 2.5 1 18 0.34 24X 0.24 24 19 PIN 1 ID 0.1 C A B (OPTIONAL) SYMM 0.05 C 0.5 24X 0.3 4219135/A 11/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT RTW0024B WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK-NO LEAD ( 2.45) SYMM 24 19 24X (0.6) 1 18 24X (0.24) (0.97) SYMM 25 (3.8) 20X (0.5) (R0.05) 6 13 TYP (Ø0.2) TYP VIA 7 12 (0.97) (3.8) LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN SOLDER MASK METAL ALL AROUND OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS 4219135/A 11/2016 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN RTW0024B WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK-NO LEAD 4X( 1.08) (0.64) TYP (R0.05) TYP 24 19 24X (0.6) 25 1 18 (0.64) 24X (0.24) TYP SYMM 20X (0.5) (3.8) 6 13 7 12 METAL SYMM TYP (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED COVERAGE BY AREA UNDER PACKAGE SCALE: 20X 4219135/A 11/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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