TC7106/A/TC7107/A 3-1/2 Digit Analog-to-Digital Converters Features: General Description: • Internal Reference with Low Temperature Drift: The TC7106A and TC7107A 3-1/2 digit direct display - TC7106/TC7107: 80ppm/°C (Typical) drive Analog-to-Digital Converters allow existing TC7106/TC7107 based systems to be upgraded. Each - TC7106A/TC7107A: 20ppm/°C (Typical) device has a precision reference with a 20ppm/°C • Drives LCD (TC7106) or LED (TC7107) maximum temperature coefficient. This represents a 4 Display Directly to 7 times improvement over similar 3-1/2 digit • Zero Reading with Zero Input converters. Existing TC7106 and TC7107 based • Low Noise for Stable Display systems may be upgraded without changing external • Auto-Zero Cycle Eliminates Need for Zero passive component values. The TC7107A drives Adjustment common anode light emitting diode (LED) displays directly with 8mA per segment. A low cost, high • True Polarity Indication for Precision Null resolution indicating meter requires only a display, four Applications resistors, and four capacitors. The TC7106A low-power • Convenient 9V Battery Operation (TC7106A) drain and 9V battery operation make it suitable for por- • High-Impedance CMOS Differential Inputs: 1012Ω table applications. • Differential Reference Inputs Simplify Ratiometric The TC7106A/TC7107A reduces linearity error to less Measurements than 1 count. Rollover error – the difference in readings • Low-Power Operation: 10mW for equal magnitude, but opposite polarity input signals, is below ±1 count. High-impedance differential inputs Applications: offer 1pA leakage current and a 1012Ω input impedance. The differential reference input allows • Thermometry ratiometric measurements for ohms or bridge • Bridge Readouts: Strain Gauges, Load Cells, Null transducer measurements. The 15µV noise P–P Detectors performance ensures a “rock solid” reading. The auto- • Digital Meters: Voltage/Current/Ohms/Power, pH zero cycle ensures a zero display reading with a zero • Digital Scales, Process Monitors volts input. • Portable Instrumentation © 2008 Microchip Technology Inc. DS21455D-page 1

TC7106/A/TC7107/A Package Type 40-Pin PDIP 44-Pin PLCC C1 C2 C3 ST FHI V+ 1 Normal Pin 40 OSC1 A1 B1 C1 D1 V+ NC OS OS OS TE RE D1 2 Configuration 39 OSC2 6 5 4 3 2 1 44 43 42 41 40 C1 3 38 OSC3 B1 4 37 TEST 1s' A1 5 36 VREF+ F1 7 39 REF LO F1 6 35 VREF- G1 8 38 CREF G1 7 34 CREF- E1 9 37 CREF E1 8 TC7106ACPL 33 CREF- D2 10 36 COMMON DC22 190 TC7107AIPL 3321 ACVNOINAM+LMOOGN C2 11 TC7106ACLW 35 IN HI 10s' B2 11 30 VIN- 12 TC7107ACLW 34 NC A2 12 29 CAZ B2 13 33 IN LO F2 13 28 VBUFF A2 14 32 A/Z E2 14 27 VINT F2 15 31 BUFF 100s' DBF333 111567 222654 VGC-32 100s' DE22 1167 3209 IVN-T E3 18 23 A3 1000s' AB4 19 22 G3 18 19 20 21 22 23 24 25 26 27 28 (MinusP SOiLgn2)0 21 (B7P1/0G6NAD/7107A) B3 F3 E3 AB4 POL NC GND G3 A3 C3 G2 P/ B 44-Pin MQFP REF HI REF LO CREF CREF COM IN HI IN LO A/Z BUFF INT V- 44 43 42 41 40 39 38 37 36 35 34 NC 1 33 NC NC 2 32 G2 TEST 3 31 C3 OSC3 4 30 A3 NC 5 29 G3 TC7106ACKW OSC2 6 28BP/GND TC7107ACKW OSC1 7 27 POL V+ 8 26 AB4 D1 9 25 E3 C1 10 24 F3 B1 11 23 B3 12 13 14 15 16 17 18 19 20 21 22 A1 F1 G1 E1 D1 C1 B2 A2 F2 E2 D3 DS21455D-page 2 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A Typical Application 0.1µF LCD Display (TC7106/A) or 34 33 Common Node with LED Display (TC7107/A) 1MΩ CREF+ CREF- + 31 VIN+ 222 -- 2159 SDerigvement Analog Input 0.01µF 20 – 30 VIN- POL Minus Sign Backplane ANALOG BP 21 Drive 32 COMMON 1 V+ TC7106/A TC7107/A 24kΩ 28 VBUFF + 9V 47kΩ 0.47µF VREF+ 36 VREF 1kΩ 0.22µF 29 CAZ VREF- 35 100mV 27 VINT V- 26 OSC2 OSC3 OSC1 To Analog 39 38 C 40 Common (Pin 32) OSC R 100pF 3 Conversions/Sec OSC 200mV Full Scale 100kΩ © 2008 Microchip Technology Inc. DS21455D-page 3

TC7106/A/TC7107/A 1.0 ELECTRICAL TC7107A CHARACTERISTICS Supply Voltage (V+)..........................................................+6V Supply Voltage (V-)............................................................-9V Absolute Maximum Ratings† Analog Input Voltage (either Input) (Note 1)..............V+ to V- Reference Input Voltage (either Input).......................V+ to V- TC7106A Clock Input.............................................................GND to V+ Package Power Dissipation (T ≤ 70°C) (Note 2): Supply Voltage (V+ to V-)..................................................15V A Analog Input Voltage (either Input) (Note 1)..............V+ to V- 40-Pin PDIP......................................................1.23W 44-Pin PLCC....................................................1.23W Reference Input Voltage (either Input).......................V+ to V- 44-Pin MQFP....................................................1.00W Clock Input..............................................................Test to V+ Package Power Dissipation (T ≤ 70°C) (Note 2): Operating Temperature Range: A C (Commercial) Devices.......................0°C to +70°C 40-Pin PDIP......................................................1.23W I (Industrial) Devices..........................-25°C to +85°C 44-Pin PLCC.....................................................1.23W 44-Pin MQFP....................................................1.00W Storage Temperature Range.........................-65°C to +150°C Operating Temperature Range: † Notice: Stresses above those listed under “Absolute Maximum C (Commercial) Devices........................0°C to +70°C Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or I (Industrial) Devices..........................-25°C to +85°C any other conditions above those indicated in the operation sections of Storage Temperature Range.........................-65°C to +150°C the specifications is not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect device reliability. TC7106/A AND TC7107/A ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, specifications apply to both the TC7106/TC7106A and TC7107/TC7107A at T = +25°C, f = 48kHz. Parts are tested in the circuit of the Typical Operating Circuit. A CLOCK Parameter Symbol Min Typ Max Unit Test Conditions Zero Input Reading Z -000.0 ±000.0 +000.0 Digital V = 0.0V IR IN Reading Full Scale = 200.0mV Ratiometric Reading 999 999/1000 1000 Digital V = V IN REF Reading V = 100mV REF Rollover Error (Difference in Reading for R/O -1 ±0.2 +1 Counts V - = + V + ≅ 200mV IN IN Equal Positive and Negative Reading Near Full Scale) Linearity (Maximum Deviation from Best -1 ±0.2 +1 Counts Full Scale = 200mV or Straight Line Fit) Full Scale = 2.000V Common Mode Rejection Ratio (Note 3) CMRR — 50 — µV/V V = ±1V, V = 0V, CM IN Full Scale = 200.0mV Noise (Peak to Peak Value not e — 15 — µV V = 0V N IN Exceeded 95% of Time) Full Scale - 200.0mV Leakage Current at Input I — 1 10 pA V = 0V L IN Zero Reading Drift — 0.2 1 µV/°C V = 0V IN “C” Device = 0°C to +70°C — 1.0 2 µV/°C V = 0V IN “I” Device = -25°C to +85°C Scale Factor Temperature Coefficient TC — 1 5 ppm/°C V = 199.0mV, SF IN “C” Device = 0°C to +70°C (Ext. Ref = 0ppm°C) — — 20 ppm/°C V = 199.0mV IN “I” Device = -25°C to +85°C Supply Current (Does not include LED I — 0.8 1.8 mA V = 0.8 DD IN Current For TC7107/A) Analog Common Voltage (with Respect V 2.7 3.05 3.35 V 25kΩ Between Common and C to Positive Supply) Positive Supply Note 1: Input voltages may exceed the supply voltages, provided the input current is limited to ±100µA. 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3: Refer to “Differential Input” discussion. 4: Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times the conversion rate. Average DC component is less than 50mV. DS21455D-page 4 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A TC7106/A AND TC7107/A ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, specifications apply to both the TC7106/TC7106A and TC7107/TC7107A at T = +25°C, f = 48kHz. Parts are tested in the circuit of the Typical Operating Circuit. A CLOCK Parameter Symbol Min Typ Max Unit Test Conditions Temperature Coefficient of Analog V — — — — 25kΩ Between Common and CTC Common (with Respect to Positive Positive Supply Supply) 7106/7/A 20 50 ppm/°C 0°C ≤ T ≤ +70°C A 7106/7 80 — ppm/°C (“C” Commercial Temperature Range Devices) Temperature Coefficient of Analog V — — 75 ppm/°C 0°C ≤ T ≤ +70°C CTC A Common (with Respect to Positive (“I” Industrial Temperature Supply) Range Devices) TC7106A ONLY Peak to Peak V 4 5 6 V V+ to V- = 9V SD Segment Drive Voltage (Note 4) TC7106A ONLY Peak to Peak V 4 5 6 V V+ to V- = 9V BD Backplane Drive Voltage (Note 4) TC7107A ONLY Segment Sinking 5 8.0 — mA V+ = 5.0V Current (Except Pin 19) Segment Voltage = 3V TC7107A ONLY Segment Sinking 10 16 — mA V+ = 5.0V Current (Pin 19) Segment Voltage = 3V Note 1: Input voltages may exceed the supply voltages, provided the input current is limited to ±100µA. 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3: Refer to “Differential Input” discussion. 4: Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times the conversion rate. Average DC component is less than 50mV. © 2008 Microchip Technology Inc. DS21455D-page 5

TC7106/A/TC7107/A 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin No. (40-Pin PDIP) (40-Pin PDIP) Symbol Description Normal (Reversed 1 (40) V+ Positive supply voltage. 2 (39) D Activates the D section of the units display. 1 3 (38) C Activates the C section of the units display. 1 4 (37) B Activates the B section of the units display. 1 5 (36) A Activates the A section of the units display. 1 6 (35) F Activates the F section of the units display. 1 7 (34) G Activates the G section of the units display. 1 8 (33) E Activates the E section of the units display. 1 9 (32) D Activates the D section of the tens display. 2 10 (31) C Activates the C section of the tens display. 2 11 (30) B Activates the B section of the tens display. 2 12 (29) A Activates the A section of the tens display. 2 13 (28) F Activates the F section of the tens display. 2 14 (27) E Activates the E section of the tens display. 2 15 (26) D Activates the D section of the hundreds display. 3 16 (25) B Activates the B section of the hundreds display. 3 17 (24) F Activates the F section of the hundreds display. 3 18 (23) E Activates the E section of the hundreds display. 3 19 (22) AB Activates both halves of the 1 in the thousands display. 4 20 (21) POL Activates the negative polarity display. 21 (20) BP/GND LCD Backplane drive output (TC7106A). Digital Ground (TC7107A). 22 (19) G Activates the G section of the hundreds display. 3 23 (18) A Activates the A section of the hundreds display. 3 24 (17) C Activates the C section of the hundreds display. 3 25 (16) G Activates the G section of the tens display. 2 26 (15) V- Negative power supply voltage. 27 (14) V Integrator output. Connection point for integration capacitor. See INTEGRATING INT CAPACITOR section for more details. 28 (13) V Integration resistor connection. Use a 47kΩ resistor for a 200mV full scale range BUFF and a 47kΩ resistor for 2V full scale range. 29 (12) C The size of the auto-zero capacitor influences system noise. Use a 0.47µF capacitor AZ for 200mV full scale, and a 0.047µF capacitor for 2V full scale. See Section7.1 “Auto-Zero Capacitor (CAZ)” on Auto-Zero Capacitor for more details. 30 (11) V - The analog LOW input is connected to this pin. IN 31 (10) V + The analog HIGH input signal is connected to this pin. IN 32 (9) ANALOG This pin is primarily used to set the Analog Common mode voltage for battery COMMON operation or in systems where the input signal is referenced to the power supply. It also acts as a reference voltage source. See Section8.3 “Analog Common (Pin 32)” on ANALOG COMMON for more details. 33 (8) C - See Pin 34. REF 34 (7) C + A 0.1µF capacitor is used in most applications. If a large Common mode voltage REF exists (for example, the V - pin is not at analog common), and a 200mV scale is IN used, a 1µF capacitor is recommended and will hold the rollover error to 0.5 count. 35 (6) V - See Pin 36. REF DS21455D-page 6 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin No. (40-Pin PDIP) (40-Pin PDIP) Symbol Description Normal (Reversed 36 (5) V + The analog input required to generate a full scale output (1999 counts). Place REF 100mV between Pins 35 and 36 for 199.9mV full scale. Place 1V between Pins 35 and 36 for 2V full scale. See paragraph on Reference Voltage. 37 (4) TEST Lamp test. When pulled HIGH (to V+) all segments will be turned on and the display should read -1888. It may also be used as a negative supply for externally generated decimal points. See paragraph under TEST for additional information. 38 (3) OSC3 See Pin 40. 39 (2) OSC2 See Pin 40. 40 (1) OSC1 Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock (3 readings per section), connect Pin 40 to the junction of a 100kΩ resistor and a 100pF capacitor. The 100kΩ resistor is tied to Pin 39 and the 100pF capacitor is tied to Pin 38. © 2008 Microchip Technology Inc. DS21455D-page 7

TC7106/A/TC7107/A 3.0 DETAILED DESCRIPTION For a constant V : IN (All Pin designations refer to 40-Pin PDIP.) EQUATION 3-2: 3.1 Dual Slope Conversion Principles V = V TRI IN R T SI The TC7106A and TC7107A are dual slope, integrating Analog-to-Digital Converters. An understanding of the The dual slope converter accuracy is unrelated to the dual slope conversion technique will aid in following the integrating resistor and capacitor values as long as detailed operation theory. they are stable during a measurement cycle. An The conventional dual slope converter measurement inherent benefit is noise immunity. Noise spikes are cycle has two distinct phases: integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large • Input Signal Integration conversion errors that plague successive • Reference Voltage Integration (De-integration) approximation converters in high noise environments. The input signal being converted is integrated for a Interfering signals with frequency components at fixed time period (TSI). Time is measured by counting multiples of the averaging period will be attenuated. clock pulses. An opposite polarity constant reference Integrating ADCs commonly operate with the signal voltage is then integrated until the integrator output integration period set to a multiple of the 50/60Hz voltage returns to zero. The reference integration time power line period (see Figure3-2). is directly proportional to the input signal (T ). See RI Figure3-1. 30 C Analog B) SInigpnuat l Int–egrator Comparator on (d20 – cti + + eje R e +/– d Switch o Driver M10 VoRlEtaFge Polarity ControPClhoanstreol CLoongtircol Normal T = Measured Period 0 Counter 0.1/T 1/T 10/T DISPLAY ntegratorOutput VVIINN µµ 1V/2R EVFREF FIGURE 3-2: NInpourtm Fraelq uMenocdye Rejection of I Dual Slope Converter. Fixed Variable Signal Reference Integrate Integrate Time Time (4000)⎛------1-------⎞⎛--V----F---S--⎞ ⎝F ⎠⎝R ⎠ FIGURE 3-1: Basic Dual Slope Converter. C = ------------------------O----S---C-------------I--N---T----- INT V INT In a simple dual slope converter, a complete Where: conversion requires the integrator output to “ramp-up” F = Clock Frequency at Pin 38 and “ramp-down.” A simple mathematical equation OSC relates the input signal, reference voltage and VFS = Full Scale Input Voltage integration time. R = Integrating Resistor INT V = Desired Full Scale Integrator Output INT EQUATION 3-1: Swing ---1-----∫TSIV (t)dt = V----R----T---R----I RC IN RC 0 Where: V = Reference voltage R T = Signal integration time (fixed) SI T = Reference voltage integration time RI (variable). DS21455D-page 8 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A 4.0 ANALOG SECTION 4.3 Reference Integrate Phase In addition to the basic signal integrate and de- The third phase is reference integrate or de-integrate. integrate cycles discussed, the circuit incorporates an VIN- is internally connected to analog common and auto-zero cycle. This cycle removes buffer amplifier, VIN+ is connected across the previously charged integrator, and comparator offset voltage error terms reference capacitor. Circuitry within the chip ensures from the conversion. A true digital zero reading results that the capacitor will be connected with the correct without adjusting external potentiometers. A complete polarity to cause the integrator output to return to zero. conversion consists of three cycles: an auto-zero, The time required for the output to return to zero is signal integrate, and reference integrate cycle. proportional to the input signal and is between 0 and 2000 counts. 4.1 Auto-Zero Cycle The digital reading displayed is: During the auto-zero cycle, the differential input signal is disconnected from the circuit by opening internal EQUATION 4-2: analog gates. The internal nodes are shorted to analog V common (ground) to establish a zero input condition. 1000 = ------I--N----- V Additional analog gates close a feedback loop around REF the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on C compensates for AZ device offset voltages. The offset error referred to the input is less than 10µV. The auto-zero cycle length is 1000 to 3000 counts. 4.2 Signal Integrate Cycle The auto-zero loop is entered and the internal differential inputs connect to V + and V -. The IN IN differential input signal is integrated for a fixed time period. The TC7106/TC7106A signal integration period is 1000 clock periods or counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is: EQUATION 4-1: 4 T = -------------×1000 SI F OSC Where: F = Externally set clock frequency OSC The differential input voltage must be within the device Common mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, V -should be tied to analog common. IN Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. © 2008 Microchip Technology Inc. DS21455D-page 9

TC7106/A/TC7107/A 5.0 DIGITAL SECTION (TC7106A) The TC7106A (Figure5-2) contains all the segment drivers necessary to directly drive a 3-1/2 digit liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversionsper second, the backplane frequency is 60Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal, the segment is “OFF.” An out of phase segment drive signal causes the segment to be “ON” or visible. This AC drive configuration results in negligible DC voltage across each LCD segment. This insures long LCD display life. The polarity segment driver is “ON” for negative analog inputs. If V + and V -are reversed, IN IN this indicator will reverse. When the TEST pin on the TC7106A is pulled to V+, all segments are turned “ON.” The display reads -1888. During this mode, the LCD segments have a constant DC voltage impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE FOR MORE THAN SEVERAL MINUTES! LCD displays may be destroyed if operated with DC levels for extended periods. The display font and the segment drive assignment are shown in Figure5-1. Display Font 1000s' 100s' 10s' 1s' FIGURE 5-1: Display Font and Segment Assignment In the TC7106A, an internal digital ground is generated from a 6-volt zener diode and a large P channel source follower. This supply is designed to absorb the large capacitive currents when the backplane voltage is switched. DS21455D-page 10 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A T S E T ne V+ V- a ckpl 1 37 26 a Ω B 21 µ 200 6.2V 500 egmentecode Units SD 7 s LCD Display LCD Segment Driver 7 Segment7 SegmentDecodeDecode Data Latch TensHundreds Control Logic Digital GroundV= 1V TH 4µ nal er Segment OutputV+ 0.5mA SegmentOutput 2mA nal Digital Ground CINT VINT 27 ToDigital Section+ – paratorThousands To Switch DriversFrom Comparator Output ClockFOSC Int 3938OSC2OSC3 ROSCCOSC Typical Inter CAZ 29Integrator – + A/Z Com 40OSC1 1 o RINT V+ 28 LowTempcVREF A FF 06 VBU – + 0V TC71 C-REF 33 – + V+ – 3. 6 2 - 5 A/Z V- EFVREF 3 DE(+) DE (–) & DE (±) CR+EF 36 A/Z DE(–) DE (+) AZ R VC+REF 34 10mA 31 INT A/Z 32 30 NT I + GN - VIN LOMO VIN AM ANO C FIGURE 5-2: TC7106A Block Diagram. © 2008 Microchip Technology Inc. DS21455D-page 11

TC7106/A/TC7107/A 6.0 DIGITAL SECTION (TC7107A) 6.2 Clock Circuit Figure6-2 shows a TC7106A block diagram. It is Three clocking methods may be used (see Figure6-1): designed to drive common anode LEDs. It is identical 1. An external oscillator connected to Pin 40. to the TC7106A, except that the regulated supply and 2. A crystal between Pins 39 and 40. backplane drive have been eliminated and the segment 3. An RC oscillator using all three pins. drive is typically 8mA. The 1000’s output (Pin 19) sinks current from two LED segments, and has a 16mA drive capability. TC7106A In both devices, the polarity indication is “ON” for TC7107A negative analog inputs. If V - and V + are reversed, IN IN µ4 To this indication can be reversed also, if desired. Counter The display font is the same as the TC7106A. 40 39 38 6.1 System Timing Crystal EXT The oscillator frequency is divided by 4 prior to clocking OSC RC Network the internal decade counters. The four-phase measurement cycle takes a total of 4000 counts, or To TEST Pin on TSC7106A To GND Pin on TSC7107A 16,000 clock pulses. The 4000-count cycle is indepen- dent of input signal magnitude. FIGURE 6-1: Clock Circuits. Each phase of the measurement cycle has the following length: 1. Auto-zero phase: 1000 to 3000 counts (4000 to 12000 clock pulses). For signals less than full scale, the auto-zero phase is assigned the unused reference integrate time period: 2. Signal integrate: 1000 counts (4000 clock pulses). This time period is fixed. The integration period is: EQUATION 6-1: 4 T = -------------×1000 SI F OSC Where: F = Externally set clock frequency OSC 3. Reference Integrate: 0 to 2000 counts (0 to 8000 clock pulses). The TC7106A/TC7107A are drop-in replacements for the TC7106/TC7107 parts. External component value changes are not required to benefit from the low drift internal reference. DS21455D-page 12 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A d V+ DigitalGroun 1 1 2 7 T 3 S E T nt ee SegmDecod Units 500Ω 7 s er ol ed Display Segment Driv 7 SegmentDecode Data Latch Tens Logic Contr L LCD 7 SegmentDecode Hundreds Digital Ground 4 µ utV+ egmentOutput d ToDigital Section Thousands To Switch DriversComparator Output FOSC 38OSC3 COSC Typical Segment Outp 0.5mA S 8mA Internal Digital Groun CCAZINT VINT2927Integrator –++–A/Z Comparator from Clock 3940OSC2OSC1 ROSC 1 o RINT V+ 28 LowTempcVREF A FF TC7107 CV-REFBU 33 – + – + V+ – 3.0V 6 2 V- - 5 EFVREF 3 DE(+) DE (–) & DE (±) CR+EF 36 A/Z DE(–) DE (+) AZ R V 4 3 +F 10mA INT A/Z NT RE I C 31 32 30 V+IN LOGMON V-IN AM ANCO FIGURE 6-2: TC7107A Block Diagram. © 2008 Microchip Technology Inc. DS21455D-page 13

TC7106/A/TC7107/A 7.0 COMPONENT VALUE 7.4 Integrating Resistor (R ) INT SELECTION The input buffer amplifier and integrator are designed with class A output stages. The output stage idling 7.1 Auto-Zero Capacitor (C ) current is 100µA. The integrator and buffer can supply AZ 20µA drive currents with negligible linearity errors. The C capacitor size has some influence on system AZ R is chosen to remain in the output stage linear drive INT noise. A 0.47µF capacitor is recommended for 200mV region, but not so large that printed circuit board full scale applications where 1LSB is 100µV. A leakage currents induce errors. For a 200mV full scale, 0.047µF capacitor is adequate for 2.0V full scale R is 47kΩ. 2.0V full scale requires 470kΩ. INT applications. A mylar type dielectric capacitor is adequate. TABLE 7-1: COMPONENT VALUES AND NOMINAL FULL SCALE 7.2 Reference Voltage Capacitor VOLTAGE (C ) REF Nominal Full Scale Voltage Component The reference voltage used to ramp the integrator out- Value put voltage back to zero during the reference integrate 200.0mV 2.000V cycle is stored on CREF. A 0.1µF capacitor is CAZ 0.47µF 0.047µF acceptable when V - is tied to analog common. If a IN R 47kΩ 470kΩ large Common mode voltage exists (V - – analog INT REF common) and the application requires 200mV full CINT 0.22µF 0.22µF scale, increase CREF to 1.0µF. Rollover error will be Note: FOSC = 48kHz (3 readings per sec). held to less than 1/2 count. A mylar dielectric capacitor is adequate. 7.5 Oscillator Components 7.3 Integrating Capacitor (CINT) ROSC (Pin 40 to Pin 39) should be 100kΩ. COSC is selected using the equation: C should be selected to maximize the integrator INT output voltage swing without causing output saturation. EQUATION 7-2: Due to the TC7106A/TC7107A superior temperature 0.45 coefficient specification, analog common will normally F = ---------- OSC RC supply the differential voltage reference. For this case, Where: a ±2V full scale integrator output swing is satisfactory. For 3 readings/second (FOSC = 48kHz), a 0.22µF FOSC = 48kHz value is suggested. If a different oscillator frequency is C = 100pF OSC used, C must be changed in inverse proportion to INT maintain the nominal ±2V integrator swing. Note that F is divided by four to generate the OSC An exact expression for C is: TC7106A internal control clock. The backplane drive INT signal is derived by dividing F by 800. OSC EQUATION 7-1: To achieve maximum rejection of 60Hz noise pickup, (4000)⎝⎛F------1-------⎠⎞⎝⎛R--V----F---S--⎠⎞ t6h0e Hszi.g nOasl ciinlltaetgorra tfere qpueerinocdi essh oouf ld2 4b0ek Ha z,m u1l2ti0plkeH oz,f C = ------------------------O----S---C-------------I--N---T----- 80kHz, 60kHz, 48kHz, 40kHz, etc. should be INT V INT selected. For 50Hz rejection, oscillator frequencies of Where: 200kHz, 100kHz, 66-2/3kHz, 50kHz, 40kHz, etc. F = Clock Frequency at Pin 38 would be suitable. Note that 40kHz (2.5 readings/ OSC V = Full Scale Input Voltage second) will reject both 50Hz and 60Hz. FS R = Integrating Resistor INT 7.6 Reference Voltage Selection V = Desired Full Scale Integrator Output INT Swing A full scale reading (2000 counts) requires the input signal be twice the reference voltage. C must have low dielectric absorption to minimize INT Required Full Scale Voltage* V rollover error. A polypropylene capacitor is REF recommended. 200.0mV 100.0mV 2.000V 1.000V * V = 2V FS REF DS21455D-page 14 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a V+ V+ pressure transducer output is 400mV for 2000lb/in2. V+ Rreafethreenr cteh avno ldtaivgied insgh othueld inbpeu t sevot lttaog e2 0b0y mtwV.o , Tthhies VREF+ 6Z.e8nVer V+ 6.8kΩ permits the transducer input to be used directly. VREF- TC7106A 20kΩ TC7107A TC7106A The differential reference can also be used when a I TC7107A Z digital zero reading is required when VIN is not equal to VREF+ zero. This is common in temperature measuring V - 1.2V instrumentation. A compensating offset voltage can be REF Ref Common applied between analog common and V -. The IN transducer output is connected between V + and (a) (b) IN analog common. FIGURE 7-1: External Reference. The internal voltage reference potential available at analog common will normally be used to supply the converter’s reference. This potential is stable whenever the supply potential is greater than approximately 7V. In applications where an externally generated reference voltage is desired, refer to Figure7-1. © 2008 Microchip Technology Inc. DS21455D-page 15

TC7106/A/TC7107/A 8.0 DEVICE PIN FUNCTIONAL 8.2 Differential Reference DESCRIPTION V + (Pin 36), V - (Pin 35) REF REF The reference voltage can be generated anywhere 8.1 Differential Signal Inputs within the V+ to V- power supply range. V + (Pin 31), V - (Pin 30) IN IN To prevent rollover type errors being induced by large The TC7106A/TC7107A is designed with true Common mode voltages, CREF should be large differential inputs and accepts input signals within the compared to stray node capacitance. input stage common mode voltage range (VCM). The The TC7106A/TC7107A circuits have a significantly typical range is V+ – 1.0 to V+ + 1V. Common mode lower analog common temperature coefficient. This voltages are removed from the system when the gives a very stable voltage suitable for use as a TC7106A/TC7107A operates from a battery or floating reference. The temperature coefficient of analog power source (isolated from measured system) and common is 20ppm/°C typically. V - is connected to analog common (V ) (see IN COM Figure8-2). 8.3 Analog Common (Pin 32) In systems where Common mode voltages exist, the The analog common pin is set at a voltage potential 86dB Common mode rejection ratio minimizes error. approximately 3.0V below V+. The potential is between Common mode voltages do, however, affect the 2.7V and 3.35V below V+. Analog common is tied integrator output level. Integrator output saturation internally to the N channel FET capable of sinking must be prevented. A worst-case condition exists if a 20mA. This FET will hold the common line at 3.0V large positive V exists in conjunction with a full scale CM should an external load attempt to pull the common line negative differential signal. The negative signal drives toward V+. Analog common source current is limited to the integrator output positive along with V (see CM 10µA. Analog common is, therefore, easily pulled to a Figure8-1). For such applications the integrator output more negative voltage (i.e., below V+ – 3.0V). swing can be reduced below the recommended 2.0V full scale swing. The integrator output will swing within The TC7106A connects the internal VIN+ and VIN- 0.3V of V+ or V- without increasing linearity errors. inputs to analog common during the auto-zero cycle. During the reference integrate phase, V - is IN connected to analog common. If V - is not externally CI connected to analog common, aIN Common mode Input Buffer + + RI voltage exists. This is rejected by the converter’s 86dB – Common mode rejection ratio. In battery operation, VIN – + VI analog common and VIN- are usually connected, Integrator removing Common mode voltage concerns. In systems – where V- is connected to the power supply ground, or VCM Where: VI = RIT ICI [ VCM – VIN [ tcoo nnae cgteivde tno VvIoNl-t.age, analog common should be 4000 TI = Integration Time = FOSC CI = Integration Capacitor RI = Integration Resistor FIGURE 8-1: Common Mode Voltage Reduces Available Integrator Swing (V ≠ V ). COM IN DS21455D-page 16 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A Segment Drive LCD Display Measured V C V POL BP BUF AZ INT System OSC1 VIN+ TC7106A V+ OSC3 VIN- V- GND Analog OSC2 Common VREF- VREF+ V+ V- V+ V- GND Power + Source 9V FIGURE 8-2: Common Mode Voltage Removed in Battery Operation with V - = Analog Common. IN The analog common pin serves to set the analog section external voltage references. External R and C values reference or common point. The TC7106A is specifically do not need to be changed. Figure8-4 shows analog designed to operate from a battery, or in any common supplying the necessary voltage reference for measurement system where input signals are not the TC7106A/TC7107A. referenced (float), with respect to the TC7106A power source. The analog common potential of V+ – 3.0V gives 200 a 6V end of battery life voltage. The common potential has a 0.001% voltage coefficient and a 15Ω output 180 No Maximum Specified No impedance. °C)m/ 160 MSapxeicmifuiemd With sufficiently high total supply voltage (V+ – V- > pp 140 Typical 7e.x0cVe)ll,e annt atleomg pceormatmuroen sista ab ilviteyr,y tsytpaibcalell yp o2te0nptipaml w/°iCth. cient ( 120 No This potential can be used to generate the reference effi 100 Maximum vuonlntaegcee.s saArny ine mxtoesrnt acla sevso lbtaegcea usree foefr ethnec e5 0wppillm /b°Ce ure Co 80 MaLxiimmiutm STpyepcicifaield maximum temperature coefficient. See Section8.5 erat 60 Typical “Internal Voltage Reference”. mp 40 e T 20 TC 8.4 TEST (Pin 37) 7106A ICL7106 ICL7136 0 The TEST pin potential is 5V less than V+. TEST may FIGURE 8-3: Analog Common be used as the negative power supply connection for Temperature Coefficient. external CMOS logic. The TEST pin is tied to the internally generated negative logic supply (Internal Logic Ground) through a 500Ω resistor in the TC7106A. The TEST pin load should be no more than 1mA. 1 If TEST is pulled to V+ all segments plus the minus sign V- V+ 24kΩ TC7106A will be activated. Do not operate in this mode for more TC7107A than several minutes with the TC7106A. With TEST=V+, the LCD segments are impressed with a 36 DC voltage which will destroy the LCD. VREF+ 1kΩ V REF The TEST pin will sink about 10mA when pulled to V+. 35 V - REF Analog 32 8.5 Internal Voltage Reference Common The analog common voltage temperature stability has Set V = 1/2 V REF FULL SCALE been significantly improved (Figure8-3). The “A” version of the industry standard circuits allow users to FIGURE 8-4: Internal Voltage Reference upgrade old systems and design new systems without Connection. © 2008 Microchip Technology Inc. DS21455D-page 17

TC7106/A/TC7107/A 9.0 POWER SUPPLIES 9.1 TC7107 Power Dissipation Reduction The TC7107A is designed to work from ±5V supplies. However, if a negative supply is not available, it can be The TC7107A sinks the LED display current and this generated from the clock output with two diodes, two causes heat to build up in the IC package. If the internal capacitors, and an inexpensive IC (Figure9-1). voltage reference is used, the changing chip temperature can cause the display to change reading. By reducing the LED common anode voltage, the V+ TC7107A package power dissipation is reduced. CD4009 Figure9-3 is a curve tracer display showing the V+ relationship between output current and output voltage OSC1 for a typical TC7107CPL. Since a typical LED has 1.8 OSC2 0.047 1N914 volts across it at 7mA, and its common anode is µF OSC3 10 + connected to +5V, the TC7107A output is at 3.2V (point TC7107A µF – A on Figure9-3). Maximum power dissipation is 1N914 8.1mA x 3.2V x 24 segments = 622mW. GND V- 10.000 V- = -3.3V FIGURE 9-1: Generating Negative Supply mA) 9.000 From +5V. nt ( A In selected applications a negative supply is not Curre 8.000 C B required. The conditions to use a single +5V supply put 7.000 are: ut O • The input signal can be referenced to the center 6.000 of the Common mode range of the converter. 2.00 2.50 3.00 3.50 4.00 • The signal is less than ±1.5V. Output Voltage (V) • An external reference is used. FIGURE 9-3: TC7107 Output Current vs. The TSC7660 DC-to-DC converter may be used to Output Voltage. generate -5V from +5V (Figure9-2). Notice, however, that once the TC7107A output voltage is above two volts, the LED current is essentially +5V constant as output voltage increases. Reducing the output voltage by 0.7V (point B in Figure9-3) results in 7.7mA of LED current, only a 5 percent reduction. Maximum power dissipation is only 7.7mA x 2.5V x 24 = 462mW, a reduction of 26%. An output voltage 1 reduction of 1 volt (point C) reduces LED current by V+VREF+ 36 10% (7.3mA) but power dissipation by 38% (7.3mA x 2.2V x 24 = 385mW). 35 LED VREF- Reduced power dissipation is very easy to obtain. DRIVE 32 COM Figure9-4 shows two ways: either a 5.1Ω, 1/4W TC7107A resistor, or a 1A diode placed in series with the display 31 VIN+ (but not in series with the TC7107A). The resistor will VIN reduce the TC7107A output voltage, when all 24 V - 30 segments are “ON,” to point “C” of Figure9-4. When IN 21 segments turn off, the output voltage will increase. The V- GND 8 26 diode, on the other hand, will result in a relatively 2 steady output voltage, around point “B”. + 5 (-5V) 10µF 4 TC7660 3 + 10µF FIGURE 9-2: Negative Power Supply Generation with TC7660. DS21455D-page 18 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A In addition to limiting maximum power dissipation, the resistor reduces the change in power dissipation as the display changes. This effect is caused by the fact that, as fewer segments are “ON,” each “ON” output drops more voltage and current. For the best case of six segments (a “111” display) to worst-case (a “1888” display), the resistor will change about 230mW, while a circuit without the resistor will change about 470mW. Therefore, the resistor will reduce the effect of display dissipation on reference voltage drift by about 50%. The change in LED brightness caused by the resistor is almost unnoticeable as more segments turn off. If display brightness remaining steady is very important to the designer, a diode may be used instead of the resistor. +5V IN -5V + – 1MΩ 24kΩ 150Ω TP3 1kΩ 0.47 100pF 0µ.0F1 µF 0.µ2F2 TP5 TP2 0.1 Display 100 µF 47 kΩ TP1 kΩ 40 30 TP 21 4 TC7107A 1 10 20 5.1Ω 1/4W Display 1N4001 FIGURE 9-4: Diode or Resistor Limits Package Power Dissipation. © 2008 Microchip Technology Inc. DS21455D-page 19

TC7106/A/TC7107/A 10.0 TYPICAL APPLICATIONS input and the voltage across the known resistor is applied to the reference input. If the unknown equals the standard, the display will read 1000. 10.1 Decimal Point and Annunciator Drive The displayed reading can be determined from the following expression: The TEST pin is connected to the internally generated digital logic supply ground through a 500Ω resistor. The EQUATION 10-1: TEST pin may be used as the negative supply for R external CMOS gate segment drivers. LCD display Displayed (Reading) = -----U---N----K---N----O----W----N--×1000 R annunciators for decimal points, low battery indication, STANDARD or function indication may be added without adding an additional supply. No more than 1mA should be The display will over range for: supplied by the TEST pin; its potential is approximately R ≥ 2 x R UNKNOWN STANDARD 5V below V+ (see Figure10-1). V + V+ REF R V - V+ STANDARD REF V+ LCD Display V + IN TC7106A 4049 R TC7106A UNKNOWN 21 To LCD BP Decimal V - Point IN Analog TEST37 GND Common To LCD Backplane FIGURE 10-2: Low Parts Count Ratiometric Resistance Measurement. V+ V+ BP + 9V 160kΩ 300kΩ 300kΩ TC7106A Decimal To LCD V+ V- SPeolienctt DPoeicnitmal VIN- 1SNen4s1o4r8 50Rk1Ω VIN+TC7106A TEST 403G0ND 50RkΩ2 VREF+VFS = 2V V - REF Common FIGURE 10-1: Decimal Point Drive Using Test as Logic Ground. FIGURE 10-3: Temperature Sensor. 10.2 Ratiometric Resistance Measurements The true differential input and differential reference make ratiometric reading possible. Typically in a ratiometric operation, an unknown resistance is measured, with respect to a known standard resistance. No accurately defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage developed across the unknown is applied to the DS21455D-page 20 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A + 9V To Pin 1 Set V = 100mV 40 REF 5.6kΩ 160kΩ 39 100kΩ V+ V- 38 37 100pF 1N914 R1 VIN- 36 20kΩ 35 +5V VINT+C7106A 3334 0.1µF 1kΩ 212MkΩΩ + 0.7%PT/×CC R3 20Rk2Ω VREF+ TC7107A 3312 0.01µF IN 30 0.47µF – 29 VREF- 28 47kΩ 27 0.22µF Common 26 -5V 25 24 To Display 23 FIGURE 10-4: Positive Temperature 22 21 Coefficient Resistor Temperature Sensor. FIGURE 10-6: TC7107 Internal Reference: 200mV Full Scale, 3RPS, V - Tied to GND for To Pin 1 IN Single Ended Inputs. Set V = 100mV 40 REF 100kΩ 39 38 37 100pF V+ 36 1 40 35 34 1kΩ 22kΩ 0.1µF 33 1MΩ + To Logic TC7106A 32 VCC 31 0.01µF IN To Logic 30 TC7106A V 0.47µF + – CC 29 47kΩ 28 9V 27 – 0.22µF 26 25 24 To Display O/R V- 23 22 21 To Backplane U/R 20 21 CD4023 FIGURE 10-5: TC7106A, Using the Internal OR 74C10 CD4077 O/R = Over Range U/R = Under Range Reference: 200mV Full Scale, 3 Readings-Per- Second (RPS). FIGURE 10-7: Circuit for Developing Under Range and Over Range Signals from TC7106A Outputs. © 2008 Microchip Technology Inc. DS21455D-page 21

TC7106/A/TC7107/A To Pin 1 To PIn 1 Set V = 1V 40 REF 100kΩ 40 39 100kΩ 38 3389 Set VREF = 100mV 37 100pF 37 100pF 36 24kΩ 36 10kΩ 10kΩ 35 V+ 35 V+ 34 0.1µF 25kΩ 34 1kΩ TC7106A 33 1MΩ + 33 0.1µF 1.2V + TC7107A 3312 0.01µF IN TC7107A 3312 0.01µF 1MΩ IN 2390 0.047µF – 2390 0.47µF – 470kΩ 47kΩ 28 28 27 0.22µF 27 0.22µF 26 V- 26 25 25 2234 To Display 2234 To Display 22 22 21 21 FIGURE 10-8: TC7106/TC7107: FIGURE 10-9: TC7107 Operated from Recommended Component Values for 2.00V Full Single +5V Supply. Scale. + 9V + 200mINV4148 1mF – 26 VIN 10kΩ 1 14 1 V+ V- 27 9MΩ 2V 0m.0F2 1MΩ 2 13 24kΩ TC7106A 29 3 12 900kΩ 20V 1MΩ 4 AD636 11 1kΩ 36 VREF+ 90kΩ 471kWΩ 6.8µF – 5 10 35 VREF- 28 200V 10% + 6 9 32 Analog Common 10kΩ 7 8 1MΩ 10% 31 VIN+ 40 20kΩ 2.2µF 0.01 COM 10% µF 30 VIN- 38 C1 = 3 - 10pF Variable 26 39 C2 = 132pF Variable V- SEG BP DRIVE LCD Display FIGURE 10-10: 3-1/2 Digit True RMS AC DMM. DS21455D-page 22 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A 9V 2 1 Constant 5V V+ V+ VREF+ TC7106A REF02 6 51kΩ 5.1kΩ TC911 50kΩ VOUT R R R2 VREF- 4 5 ADJ 5 NC 2 – 8 VFS= 2.00V 1 3 3 + VIN- TEMP 4 VOUT= 1.86V @ VIN+ Temperature 25×C 50kΩ Dependent 1.3k R1 Common Output GND V- 4 26 FIGURE 10-11: Integrated Circuit Temperature Sensor. © 2008 Microchip Technology Inc. DS21455D-page 23

TC7106/A/TC7107/A 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 40-Pin PDIP Example: XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX TC7106CPL^e^3 XXXXXXXXXXXXXXXXXX 0743256 YYWWNNN *h *h 44-Pin MQFP Example: M M XXXXXXXXXX XXXXXXXXXX TC106CKW XXXXXXXXXX ^e^30743256 YYWWNNN 44-Pin PLCC Example: 1 M M XXXXXXXXXXX TC7106CLW XXXXXXXXXXX ^e3^0743256 XXXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21455D-page 24 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:3)(cid:3)(cid:9)(cid:24)(cid:14)(cid:11)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)(cid:10)(cid:16)(cid:18)(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 1(cid:6)(cid:5)(cid:17)(cid:9) 23(cid:31)4"(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 ’% (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:3)(cid:2)%%(cid:7)+(cid:29)(cid:31) -(cid:23)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ( 8 8 (cid:3)(cid:27)*% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:3)(cid:2)(cid:27)* 8 (cid:3)(cid:2)9* +(cid:11)(cid:9)(cid:14)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ((cid:2) (cid:3)%(cid:2)* 8 8 (cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) " (cid:3)*9% 8 (cid:3);(cid:27)* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3)’<* 8 (cid:3)*<% 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:2)(cid:3)9<% 8 (cid:27)(cid:3)%9* -(cid:5)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) 5 (cid:3)(cid:2)(cid:2)* 8 (cid:3)(cid:27)%% 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) (cid:3)%%< 8 (cid:3)%(cid:2)* 1##(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) (cid:22)(cid:2) (cid:3)% % 8 (cid:3)%=% 5(cid:23)(cid:25)(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) (cid:3)%(cid:2)’ 8 (cid:3)%(cid:27) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)>(cid:23)(cid:25)(cid:7)(cid:29)#(cid:11)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)(cid:7)(cid:28) (cid:14)+ 8 8 (cid:3)=%% (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)(cid:3)%(cid:2)%&(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%(cid:2);+ © 2008 Microchip Technology Inc. DS21455D-page 25

TC7106/A/TC7107/A (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9) (cid:6)(cid:13)!(cid:14)(cid:15)(cid:9)"(cid:17)(cid:7)(cid:8)(cid:9)#(cid:11)(cid:7)(cid:13)$(cid:7)(cid:15)%(cid:9)(cid:20)&’(cid:21)(cid:9)(cid:22)(cid:9)((cid:3))((cid:3))*(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)+(cid:9),-*(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:28) "#(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D D1 E e E1 N b NOTE1 1 23 NOTE2 α c φ A1 A β L L1 A2 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:9) 3 ’’ 5(cid:14)(cid:11)(cid:13)(cid:7)(cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) %(cid:3)<%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( 8 8 (cid:27)(cid:3)’* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:2)(cid:3)<% (cid:27)(cid:3)%% (cid:27)(cid:3)(cid:27)% (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7)(cid:7)(cid:28) ((cid:2) %(cid:3)%% 8 %(cid:3)(cid:27)* .(cid:23)(cid:23)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3)= %(cid:3)<< (cid:2)(cid:3)% .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17) 5(cid:2) (cid:2)(cid:3);%(cid:7)>". .(cid:23)(cid:23)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14) (cid:2) %B 8 =B 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) " (cid:2) (cid:3)(cid:27)%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:2) (cid:3)(cid:27)%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:2)%(cid:3)%%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) !(cid:2) (cid:2)%(cid:3)%%(cid:7)+(cid:29)(cid:31) 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) %(cid:3)(cid:2)(cid:2) 8 %(cid:3)(cid:27) 5(cid:14)(cid:11)(cid:13)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3)(cid:27)9 8 %(cid:3)’* $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)-(cid:23)# (cid:3) *B 8 (cid:2);B $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)+(cid:23)(cid:17)(cid:17)(cid:23)(cid:19) (cid:4) *B 8 (cid:2);B (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18)(cid:9)(cid:7)(cid:11)(cid:17)(cid:7)(cid:24)(cid:23)(cid:18)(cid:6)(cid:14)(cid:18)(cid:9)(cid:7)(cid:11)(cid:18)(cid:14)(cid:7)(cid:23)#(cid:17)(cid:5)(cid:23)(cid:6)(cid:11)(cid:12)@(cid:7)(cid:9)(cid:5)A(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:2)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)%(cid:3)(cid:27)*(cid:7)(cid:19)(cid:19)(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) *(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%=(cid:2)+ DS21455D-page 26 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:6)(cid:8)(cid:9)./(cid:14)$(cid:9).(cid:7)!!(cid:14)(cid:6)!(cid:9)(cid:20)(cid:5)’(cid:21)(cid:9)(cid:22)(cid:9)01(cid:17)(cid:7)!(cid:6)(cid:9)(cid:28)(cid:10)(cid:5)..(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D D1 CH2x45° E E1 N123 NOTE1 CH1x45° CH3x45° c A A2 A1 e b1 A3 b D2 E2 1(cid:6)(cid:5)(cid:17)(cid:9) 23(cid:31)4"(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 ’’ (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:3)%*% 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( (cid:3)(cid:2);* (cid:3)(cid:2)=(cid:27) (cid:3)(cid:2)<% (cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ((cid:2) (cid:3)%9% (cid:3)(cid:2)%* (cid:3)(cid:2)(cid:27)% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:17)(cid:23)(cid:7)(cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17) ((cid:27) (cid:3)%;(cid:27) 8 (cid:3)%< (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7)(cid:7)(cid:28) ( (cid:3)%(cid:27)% 8 8 (cid:31)(cid:23)(cid:18)(cid:6)(cid:14)(cid:18)(cid:7)(cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18) (cid:31)4(cid:2) (cid:3)%’(cid:27) 8 (cid:3)%’< (cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18)(cid:9) (cid:31)4(cid:27) 8 8 (cid:3)%(cid:27)% (cid:29)(cid:5)(cid:13)(cid:14)(cid:7)(cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18) (cid:31)4 (cid:3)%’(cid:27) 8 (cid:3)%*; 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) " (cid:3);<* (cid:3);9% (cid:3);9* 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:3);<* (cid:3);9% (cid:3);9* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3);*% (cid:3);* (cid:3);*; $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) !(cid:2) (cid:3);*% (cid:3);* (cid:3);*; .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) "(cid:27) (cid:3)*<(cid:27) (cid:3);(cid:2)% (cid:3); < .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) !(cid:27) (cid:3)*<(cid:27) (cid:3);(cid:2)% (cid:3); < 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) (cid:3)%%=* 8 (cid:3)%(cid:2)(cid:27)* 1##(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) (cid:22)(cid:2) (cid:3)%(cid:27); 8 (cid:3)% (cid:27) 5(cid:23)(cid:25)(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7):(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) (cid:3)%(cid:2) 8 (cid:3)%(cid:27)(cid:2) (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:2)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)(cid:3)%(cid:2)%&(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%’<+ © 2008 Microchip Technology Inc. DS21455D-page 27

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TC7106/A/TC7107/A APPENDIX A: REVISION HISTORY Revision D (February 2008) The following is the list of modifications. 1. Updated Section11.0 “Packaging Informa- tion”. 2. 3. Added Appendix A. 4. Updated the Product Identification System page. Revision C (April 2006) The following is the list of modifications: • Undocumented Changes. Revision B (May 2002) The following is the list of modifications: • Undocumented Changes. Revision A (April 2002) • Original Release of this Document. © 2008 Microchip Technology Inc. DS21455D-page 29

TC7106/A/TC7107/A NOTES: DS21455D-page 30 © 2008 Microchip Technology Inc.

TC7106/A/TC7107/A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X XX XXX Examples: a) TC7106CLW: 3-3/4 A/D Converter, Device Temperature Package Tape & 44LD PLCC package. Range Reel b) TC7106CPL: 3-3/4 A/D Converter, 40LD PDIP package. c) TC7106CKW713: 3-3/4 A/D Converter, Device: TC7106: 3-3/4 Digit A/D, with Frequency Counter and Probe 44LD MQFP package, TC7106A: 3-3/4 Digit A/D, with Frequency Counter and Probe Tape and Reel. TC7106: 3-3/4 Digit A/D, with Frequency Counter and Probe TC7107A: 3-3/4 Digit A/D, with Frequency Counter and Probe a) TC7106ACLW: 3-3/4 A/D Converter, 44LD PLCC package. b) TC7106ACPL: 3-3/4 A/D Converter, Temperature Range: C = 0°C to +70°C 40LD PDIP package. I = -25°C to +85°C c) TC7106ACKW713: 3-3/4 A/D Converter, 44LD MQFP package, Tape and Reel Package: LW = Plastic Leaded Chip Carrier (PLCC), 44-lead PL = Plastic DIP, (600 mil Body), 40-lead a) TC7107CLW: 3-3/4 A/D Converter, KW = Plastic Metric Quad Flatpack, (MQFP), 44-lead 44LD PLCC package. b) TC7107CLP: 3-3/4 A/D Converter, 40LD PDIP package. Tape & Reel: 713 = Tape and Reel c) TC7107CKW713: 3-3/4 A/D Converter, 44LD MQFP package Tape and Reel. a) TC7107ACLW: 3-3/4 A/D Converter, 44LD PLCC package. b) TC7107ACLP: 3-3/4 A/D Converter, 40LD PDIP package. c) TC7107ACKW: 3-3/4 A/D Converter, 44LD MQFP package. © 2008 Microchip Technology Inc. DS21455D-page 31

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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PROMATE, rfPIC and SmartShunt are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. DS21455D-page 33

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