TC654/TC655 Dual SMBus™ PWM Fan Speed Controllers With Fan Fault Detection Features: Description: • Temperature Proportional Fan Speed for Reduced The TC654 and TC655 are PWM mode fan speed con- Acoustic Noise and Longer Fan Life trollers with FanSense technology for use with brush- • FanSense™ Protects against Fan Failure and less DC fans. These devices implement temperature Eliminates the Need for 3-wire Fans proportional fan speed control which lowers acoustic fan noise and increases fan life. The voltage at V • Overtemperature Detection (TC655) IN (Pin1) represents temperature and is typically pro- • Efficient PWM Fan Drive vided by an external thermistor or voltage output tem- • Provides RPM Data perature sensor. The PWM output (V ) is adjusted OUT • 2-Wire SMBus™-Compatible Interface between 30% and 100%, based on the voltage at V . IN • Supports Any Fan Voltage The PWM duty cycle can also be programmed via • Software Controlled Shutdown Mode for "Green" SMBus to allow fan speed control without the need for Systems an external thermistor. If VIN is not connected, the TC654/TC655 will start driving the fan at a default duty • Supports Low-Cost NTC/PTC Thermistors cycle of 39.33%. See Section4.3 “Fan Start-up” for • Space Saving 10-Pin MSOP Package more details. • Temperature Range: -40°C to +85ºC In normal fan operation, pulse trains are present at Applications: SENSE1 (Pin 8) and SENSE2 (Pin 7). The TC654/ TC655 use these pulses to calculate the fan revolu- • Personal Computers and Servers tions per minute (RPM). The fan RPM data is used to • LCD Projectors detect a worn out, stalled, open or unconnected fan. An RPM level below the user-programmable threshold • Datacom and Telecom Equipment causes the TC654/TC655 to assert a logic low alert • Fan Trays signal (FAULT). The default threshold value is • File Servers 500RPM. Also, if this condition occurs, F1F (bit 0<0>) • Workstations or F2F (bit 1<0>) in the Status Register will also be set • General Purpose Fan Speed Control to a ‘1’. An over-temperature condition is indicated when the Package Type voltage at V exceeds 2.6V (typical). The TC654/ IN TC655 devices indicate this by setting OTF(bit 5<X>) in 10-Pin MSOP the Status Register to a '1'. The TC655 device also pulls the FAULT line low during an over-temperature condition. VIN 1 10 VDD The TC654/TC655 devices are available in a 10-Pin CF 2 9 VOUT MSOP package and consume 150µA during opera- TC654 tion. The devices can also enter a low-power Shutdown SCLK 3 TC655 8 SENSE1 mode (5µA, typ.) by setting the appropriate bit in the SDA 4 7 SENSE2 Configuration Register. The operating temperature range for these devices is -40°C to +85ºC. GND 5 6 FAULT  2002-2014 Microchip Technology Inc. DS20001734C-page 1

TC654/TC655 Functional Block Diagram TC654/TC655 – Note V VIN – OTF + VDD OTF + Control + V Logic OUT – Start-up FAULT Timer C F Missing V Pulse MIN Clock Detect Generator 50k  SENSE1 SCLK – Serial Port Interface 100mV (typ.) SDA 50k  SENSE2 – GND 100mV (typ.) Note: OTF condition applies for the TC655 device only. DS20001734C-page 2  2002-2014 Microchip Technology Inc.

TC654/TC655 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Absolute Maximum Ratings * V Analog Input IN VDD...................................................................................6.5V CF Analog Output Input Voltages ......................................-0.3V to (V + 0.3V) SCLK Serial Clock Input DD Output Voltages ....................................-0.3V to (V + 0.3V) SDA Serial Data In/Out (Open Drain) DD Storage temperature.....................................-65°C to +150°C GND Ground Ambient temp. with power applied................-40°C to +125°C FAULT Digital (Open Drain) Output Maximum Junction Temperature, TJ.............................150°C SENSE2 Analog Input ESD protection on all pins4kV SENSE1 Analog Input *Notice: Stresses above those listed under “Maximum rat- V Digital Output ings” may cause permanent damage to the device. This is a OUT stress rating only and functional operation of the device at VDD Power Supply Input those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all limits are specified for V = 3.0V to 5.5V, DD -40°C <T < +85°C. A Parameters Sym. Min. Typ. Max. Units Conditions Supply Voltage V 3.0 — 5.5 V DD Operating Supply Current I — 150 300 µA Pins 7, 8, 9 Open DD Shutdown Mode Supply Current I — 5 10 µA Pins 7, 8, 9 Open DDSHDN V PWM Output OUT V Rise Time t — — 50 µsec I = 5mA, Note1 OUT R OH V Fall Time t — — 50 µsec I = 1mA, Note1 OUT F OL Sink Current at V Output I 1.0 — — mA V = 10% of V OUT OL OL DD Source Current at V Output I 5.0 — — mA V = 80% of V OUT OH OH DD PWM Frequency F 26 30 34 Hz C = 1µF F V Input IN V Input Voltage for 100% PWM V 2.45 2.6 2.75 V IN C(MAX) duty-cycle V - V V 1.25 1.4 1.55 V C(MAX) C(MIN) CRANGE V Input Resistance — 10M —  V = 5.0V IN DD V Input Leakage Current I -1.0 — +1.0 µA IN IN SENSE Input SENSE Input Threshold Voltage with V 80 100 120 mV THSENSE Respect to GND FAULT Output FAULT Output LOW Voltage V — — 0.3 V I = 2.5mA OL OL FAULT Output Response Time t — 2.4 — sec FAULT Fan RPM-to-Digital Output Fan RPM ERROR -15 — +15 % RPM > 1600 Note 1: Not production tested, ensured by design, tested during characterization. 2: For 5.0V > V  5.5V, the limit for V = 2.2V. DD IH  2002-2014 Microchip Technology Inc. DS20001734C-page 3

TC654/TC655 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all limits are specified for V = 3.0V to 5.5V, DD -40°C <T < +85°C. A Parameters Sym. Min. Typ. Max. Units Conditions 2-Wire Serial Bus Interface Logic Input High V 2.1 — — V Note2 IH Logic Input Low V — — 0.8 V IL Logic Output Low V — — 0.4 V I = 3mA OL OL Input Capacitance SDA, SCLK C — 10 15 pF Note1 IN I/O Leakage Current I -1.0 — +1.0 µA LEAK SDA Output Low Current I 6 — — mA V = 0.6V OLSDA OL Note 1: Not production tested, ensured by design, tested during characterization. 2: For 5.0V > V  5.5V, the limit for V = 2.2V. DD IH TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 3.0V to 5.5V DD Parameters Symbol Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 10 Pin MSOP  — 113 — °C/W JA TIMING SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all limits are specified for V = 3.0V to 5.5V, DD -40°C <T < +85°C A Parameters Sym Min Typ Max Units Conditions SMBus Interface (See Figure1-1) Serial Port Frequency f 0 — 100 kHz Note1 SC Low Clock Period t 4.7 — — µsec Note1 LOW High Clock Period t 4.7 — — µsec Note1 HIGH SCLK and SDA Rise Time t — — 1000 nsec Note1 R SCLK and SDA Fall Time t — — 300 nsec Note1 F Start Condition Setup Time t 4.7 — — µsec Note1 SU(START) SCLK Clock Period Time t 10 — — µsec Note1 SC Start Condition Hold Time t 4.0 — — µsec Note1 H(START) Data in SetupTime to SCLK t 250 — — nsec Note1 SU-DATA High Data in Hold Time after SCLK t 300 — — nsec Note1 H-DATA Low Stop Condition Setup Time t 4.0 — — µsec Note1 SU(STOP) Bus Free Time Prior to New t 4.7 — µsec Note1 and Note2 IDLE Transition Note 1: Not production tested, ensured by design, tested during characterization. 2: Time the bus must be free before a new transmission can start. DS20001734C-page 4  2002-2014 Microchip Technology Inc.

TC654/TC655 SMBus Write Timing Diagram A B C D EE F G H I J K L M tLOW tHIGH SCLK SDA tSU(START) tH(START) tSU-DATA tH-DATA tSU(STOP)tIDLE A = Start Condition F = Acknowledge Bit Clocked into Master J = Acknowledge Clocked into Master B = MSB of Address Clocked into Slave G = MSB of Data Clocked into Slave K = Acknowledge Clock Pulse C = LSB of Address Clocked into Slave H = LSB of Data Clocked into Slave L = Stop Condition, Data Executed by Slave D = R/W Bit Clocked into Slave I = Slave Pulls SDA Line Low M = New Start Condition E = Slave Pulls SDA Line Low SMBus Read Timing Diagram A B C D E F G H I J K tLOW tHIGH SCLK SDA tSU(START)tH(START) tSU-DATA tSU(STOP) tIDLE A = Start Condition E = Slave Pulls SDA Line Low I = Acknowledge Clock Pulse B = MSB of Address Clocked into Slave F = Acknowledge Bit Clocked into Master J = Stop Condition C = LSB of Address Clocked into Slave G = MSB of Data Clocked into Master K = New Start Condition D = R/W Bit Clocked into Slave H = LSB of Data Clocked into Master FIGURE 1-1: Bus Timing Data.  2002-2014 Microchip Technology Inc. DS20001734C-page 5

TC654/TC655 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 180 14 175 Pins 7,8, and 9 Open VDD = 5.5 V VOL = 0.1 VDD 12 170 A) I (µA)DD 111114556650505 VDD = 3.0 V nk Current (m1068 VVDDDD == 55..05 VV 140 Si VDD = 4.0 V 4 135 VDD = 3.0 V 130 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) FIGURE 2-1: I vs. Temperature. FIGURE 2-4: PWM, Sink Current vs. DD Temperature. 9.000 50 IOL = 2.5 mA 8.000 45 A)7.000 VDD = 3.0 V wn I (µDD56..000000 VDD = 5.5 V V (mV)OL 3450 Shutdo34..000000 VDD = 3.0 V Fault 2350 VDD = 4.0 V VDVDD =D =5 .55. 0V V 2.000 20 1.000 15 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (ºC) Temperature (ºC) FIGURE 2-2: I Shutdown vs. FIGURE 2-5: Fault V vs. Temperature. DD OL Temperature. 32 CF = 1.0 µF mA) 3305 VOH = 0.8VDD ncy (Hz)3301 VDD = 5.5 V nt ( 25 VDD = 5.5 V que urce Curre 1250 VDD = 5.0 V VDD = 4.0 V PWM Fre2289 VDD = 3.0 V So 10 VDD = 3.0 V 27 5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (ºC) Temperature (°C) FIGURE 2-6: PWM Frequency vs. FIGURE 2-3: PWM, Source Current vs. Temperature. Temperature. DS20001734C-page 6  2002-2014 Microchip Technology Inc.

TC654/TC655 50 10 VOL = 0.4 V 9 CF = 1.0 µF 45 8 A I (mA)OL3450 VDD = 5.5 V VDD = 5.0 V M Error (%) 4567 VDD = 3.0 V SD30 RP 3 25 VDD = 4.0 V 2 VDD = 5.0 V VDD = 3.0 V 1 VDD = 5.5 V 20 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (ºC) Temperature (ºC) FIGURE 2-7: SDA I vs. Temperature. FIGURE 2-10: RPM %error vs. OL Temperature. 2.620 45 2.615 VDD = 5.5 V V) 2.610 s (m 40 V (V)CMax222...566900505 VDD = 5.0 V Hysteresi 3305 VDD = 3.0V 2.590 VDD = 4.0 V NSE 2.585 HSE 25 VDD = 5.5V 2.580 VDD = 3.0 V VT 2.575 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (ºC) Temperature (ºC) FIGURE 2-8: V vs. Temperature. FIGURE 2-11: Sense Threshold CMAX (V ) Hysteresis vs. Temperature. THSENSE 1.205 V)150 m 1.200 VDD = 3.0 V s (140 (V)N1.195 VDD = 5.5 V VDD = 5.0 V ysteresi112300 VDD = 3.0 V MI H VC1.190 K 110 VDD = 5.0 V L C S100 1.185 VDD = 4.0 V & A 90 D 1.180 S 80 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (ºC) Temperature (ºC) FIGURE 2-9: VCMIN vs. Temperature. FIGURE 2-12: SDA, SCLK Hysteresis vs. Temperature.  2002-2014 Microchip Technology Inc. DS20001734C-page 7

TC654/TC655 3.0 PIN FUNCTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE Name Function V Analog Input IN C Analog Output F SCLK Serial Clock Input SDA Serial Data In/Out (Open Drain) GND Ground FAULT Digital (Open Drain) Output SENSE2 Analog Input SENSE1 Analog Input V Digital Output OUT V Power Supply Input DD 3.1 Analog Input (V ) 3.6 Analog Input (SENSE2) IN A voltage range of 1.62V to 2.6V (typical) on this pin Fan current pulses are detected at this pin. These drives an active duty-cycle of 30% to 100% on the pulses are counted and used in the calculation of the V pin. Fan 2 RPM. OUT 3.2 Analog Output (C ) 3.7 Analog Input (SENSE1) F Positive terminal for the PWM ramp generator timing Fan current pulses are detected at this pin. These capacitor. The recommended C is 1µF for 30Hz pulses are counted and used in the calculation of the F PWM operation. Fan 1 RPM. 3.3 SMBus Serial Clock Input (SCLK) 3.8 Digital Output (V ) OUT Clocks data into and out of the TC654/TC655. See This active high complimentary output drives the base Section5.0 “Serial Communication” for more infor- of an external transistor or the gate of a MOSFET. mation on the serial interface. 3.9 Power Supply Input (V ) DD 3.4 Serial Data (Bi-directional) (SDA) The V pin with respect to GND provides power to the DD Serial data is transferred on the SMBus in both direc- device. This bias supply voltage may be independent of tions using this pin. See Section5.0 “Serial Commu- the fan power supply. nication” for more information on the serial interface. 3.5 Digital (Open Drain) Output (FAULT) When the fan’s RPM falls below the user-set RPM threshold (or OTF occurs with TC655), a logic low sig- nal is asserted. DS20001734C-page 8  2002-2014 Microchip Technology Inc.

TC654/TC655 4.0 DEVICE OPERATION can be set to provide a predictive fan failure feature. This feature can be used to give a system warning and, The TC654 and TC655 devices allow you to control, in many cases, help to avoid a system thermal shut- monitor and communicate (via SMBus) fan speed for 2- down condition. The fan RPM data and threshold reg- wire and 3-wire DC brushless fans. By pulse-width isters are available over the SMBus interface which modulating (PWM) the voltage across the fan, the allows for complete system control. TC654/TC655 controls fan speed according to the sys- The TC654/TC655 devices are identical in every tem temperature.The goal of temperature proportional aspect except for how they indicate an over-tempera- fan speed control is to reduce fan power consumption, ture condition. When V voltage exceeds 2.6V (typi- increase fan life and reduce system acoustic noise. IN cal), both devices will set OTF (bit 5<X>) in the Status With the TC654 and TC655 devices, fan speed can be Register to a '1'. The TC655 will additionally pull the controlled by the analog input V or the SMBus inter- IN FAULT output low during an over-temperature condi- face, allowing for high system flexibility. tion. The TC654 and TC655 also measure and monitor fan revolutions per minute (RPM). A fan’s speed (RPM) is a measure of its health. As a fan’s bearings wear out, the fan slows down and eventually stops (locked rotor). By monitoring the fan’s RPM level, the TC654/TC655 devices can detect open, shorted, unconnected and locked rotor fan conditions. The fan speed threshold +12V +5V +5V FAN FAN 1 2 C2 RISO1 1µF R1 NTC Thermistor 34.8k 100k @ 25°C 715 10 R ISO2 1 9 C VIN VDD VOUT 1 715 R2 0.01µF C 14.7k 8 SENSE1 SENSE1 2 CF 0.1µF R CF 1.0µF SENSE1 TC654/TC655 C SENSE2 7 R SENSE2 SCLK +5V 20k 3 0.1µF SCLK R SENSE2 +5V PIC® +5V RFAULT Microcontroller 4 SDA FAULT 6 20k GND 5 R SDA 20k Note: Refer to Table7-1 for R and R values. SENSE1 SENSE2 FIGURE 4-1: Typical Application Circuit.  2002-2014 Microchip Technology Inc. DS20001734C-page 9

TC654/TC655 4.1 Fan Speed Control Methods The speed of a DC brushless fan is proportional to the T voltage across it. For example, if a fan’s rating is 5000RPM at 12V, it’s speed would be 2500RPM at 6V. This, of course, will not be exact, but should be close. There are two main methods for fan speed control. The first is pulse width modulation (PWM) and the second Ton Toff is linear. Using either method the total system power requirement to run the fan is equal. The difference between the two methods is where the power is D = Duty Cycle T = Period consumed. D = Ton / T T = 1/F F = Frequency The following example compares the two methods for a 12V, 120mA fan running at 50% speed. With 6V FIGURE 4-2: Duty Cycle Of A PWM applied across the fan, the fan draws an average cur- Waveform. rent of 68mA. Using a linear control method, there are The TC654 and TC655 generate a pulse train with a 6V across the fan and 6V across the drive element. typical frequency of 30Hz (C = 1µF). The duty cycle With 6V and 68mA, the drive element is dissipating F can be varied from 30% to 100%. The pulse train gen- 410mW of power. Using the PWM approach, the fan is erated by the TC654/TC655 devices drives the gate of modulated at a 50% duty cycle, with most of the 12V an external N-channel MOSFET or the base of an NPN being dropped across the fan. With 50% duty cycle, the transistor (Figure4-3). See Section7.5 “Output Drive fan draws an RMS current of 110mA and an average Device Selection” for more information on output current of 72mA. Using a MOSFET with a 1 RDS (on) drive device selection. (a fairly typical value for this low current) the power dis- sipation in the drive element would be: 12mW (Irms2 * RDS ). Using a standard 2N2222A NPN transistor 12V (on) (assuming a Vce-sat of 0.8V), the power dissipation would be 58mW (Iavg* Vce-sat). The PWM approach to fan speed control causes much FAN V DD less power dissipation in the drive element. This allows smaller devices to be used and will not require any spe- cial heatsinking to get rid of the power being dissipated D in the package. TC654/ VOUT G Qdrive The other advantage to the PWM approach is that the TC655 S voltage being applied to the fan is always near 12V. GND This eliminates any concern about not supplying a high enough voltage to run the internal fan components, which is very relevant in linear fan speed control. FIGURE 4-3: PWM Fan Drive. 4.2 PWM Fan Speed Control By modulating the voltage applied to the gate of the MOSFET Qdrive, the voltage applied to the fan is also The TC654 and TC655 devices implement PWM fan modulated. When the V pulse is high, the gate of OUT speed control by varying the duty cycle of a fixed fre- the MOSFET is turned on, pulling the voltage at the quency pulse train. The duty cycle of a waveform is the drain of Qdrive to 0V. This places the full 12V across on time divided by the total period of the pulse. For the fan for the Ton period of the pulse. When the duty example, given a 100Hz waveform (10msec.) with an cycle of the drive pulse is 100% (full on, Ton = T), the on time of 5.0msec, the duty cycle of this waveform is fan will run at full speed. As the duty cycle is decreased 50% (5.0msec/10.0msec). An example of this is (pulse on time “Ton” is lowered), the fan will slow down illustrated in Figure4-2. proportionally. With the TC654 and TC655 devices, the duty cycle can be controlled through the analog input pin (V ) or through the SMBus interface by using the IN Duty-Cycle Register. See Section4.5 “Duty Cycle Control (V and Duty-Cycle Register)” for more IN details on duty cycle control. DS20001734C-page 10  2002-2014 Microchip Technology Inc.

TC654/TC655 4.3 Fan Start-up quency is linear. If a frequency of 15Hz is desired, a capacitor value of 2.0µF should be used. The fre- Often overlooked in fan speed control is the actual quency should be kept in the range of 15Hz to 35Hz. start-up control period. When starting a fan from a non- See Section7.2 “Setting the PWM Frequency” for operating condition (fan speed is zero RPM), the more details. desired PWM duty cycle or average fan voltage can not be applied immediately. Since the fan is at a rest posi- 4.5 Duty Cycle Control (V and Duty- IN tion, the fan’s inertia must be overcome to get it started. Cycle Register) The best way to accomplish this is to apply the full rated voltage to the fan for one second. This will ensure that The duty cycle of the V PWM drive signal can be OUT in all operating environments, the fan will start and controlled by either the V analog input pin or by the IN operate properly. Duty-Cycle Register, which is accessible via the SMBus interface. The control method is selectable via The TC654 and TC655 devices implement this fan con- DUTYC (bit 5<0>) of the Configuration Register. The trol feature without any user programming. During a default state is for V control. If V control is selected power-up or release from shutdown condition, the IN IN and the V pin is open, the PWM duty cycle will default TC654 and TC655 devices force the V output to a IN OUT to 39.33%. The duty cycle control method can be 100% duty cycle, turning the fan full on for one second changed at any time via the SMBus interface. (C = 1µF). Once the one second period is over, the F TC654/TC655 devices will look to see if SMBus or V V is an analog input pin. A voltage in the range of IN IN control has been selected in the Configuration Register 1.62V to 2.6V (typical) at this pin commands a 30% to (DUTYC bit 5<0>). Based on this register, the device 100% duty cycle on the V output, respectively. If the OUT will choose which input will control the V duty cycle. voltage at V falls below the 1.62V level, the duty cycle OUT IN Duty cycle control based on V is the default state. If will not go below 30%. The relationship between the IN V control is selected and the V pin is open (nothing voltage at V and the PWM duty cycle is shown in IN IN IN is connected to the V pin), then the TC654/TC655 will Figure4-5. IN default to a duty cycle of 39.33%. This sequence is shown in Figure4-4. This integrated one second start- 100 up feature will ensure the fan starts-up every time. 90 80 %) 70 Powferro-mUp S oHrD RNelease cle ( 60 y 50 C y 40 One Second Pulse Dut 30 20 10 0 YES Select SMBus 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 Input Voltage (V ) IN NO Default PWM: 39.33% SMBus PWM Duty FIGURE 4-5: PWM Duty Cycle vs. V Cycle Control IN Voltage (Typical). YES VIN Open? For the TC655 device, if the voltage at V exceeds the IN NO 2.6V (typical) level, an over-temperature fault indica- tion will be given by asserting a low at the FAULT output VIN PWM Duty and setting OTF (bit 5<X>) in the Status Register to a Cycle Control ‘1’. A thermistor network or any other voltage output ther- FIGURE 4-4: Power-Up Flow Chart. mal sensor can be used to provide the voltage to the V input. The voltage supplied to the V pin can actu- 4.4 PWM Drive Frequency (C ) IN IN F ally be thought of as a temperature. For example, the As previously discussed, the TC654 and TC655 circuit shown in Figure4-6 represents a typical solution devices operate with a fixed PWM frequency. The fre- for a thermistor based temperature sensing network. quency of the PWM drive output (V ) is set by a See Section7.3 “Temperature Sensor Design” for OUT capacitor at the C pin. With a 1µF capacitor at the C more details. F F pin, the typical drive frequency is 30Hz. This frequency can be raised, by decreasing the capacitor value, or lowered, by increasing the capacitor value. The rela- tionship between the capacitor value and the PWM fre-  2002-2014 Microchip Technology Inc. DS20001734C-page 11

TC654/TC655 This method of control allows for more sophisticated algorithms to be implemented by utilizing microcontrol- +5V lers or microprocessors in the system. In this way, mul- tiple system temperatures can be taken into account for determining the necessary fan speed. As shown in Table4-1, the duty cycle has more of a R NTC Thermistor 1 step function look than did the V control approach. 34.8k 100k @ 25°C IN Because the step changes in duty cycle are small, they are rarely audibly noticeable, especially when the fans V IN are integrated into the system. C 1 TC654/ R2 0.01µF TC655 4.6 PWM Output (VOUT) 14.7k GND The V pin is designed to drive two low-cost NPN OUT transistors or N-channel MOSFETs as the low side power switching elements in the system as is shown in Figure4-7. These switching elements are used to turn FIGURE 4-6: NTC Thermistor Sensor the fans on and off at the PWM duty cycle commanded Network. by the V output. OUT The second method for controlling the duty cycle of the This output has complementary drive (pull up and pull PWM output (VOUT) is via the SMBus interface. In order down) and is optimized for driving NPN transistors or to control the PWM duty cycle via the SMBus, DUTYC N-channel MOSFETs (see Section2.0 “Typical Per- (bit 5<0>) of the Configuration Register (Register6.3) formance CURVES” for sink and source current capa- must be set to a ‘1’. This tells the TC654/TC655 device bility of the V drive stage). OUT that the duty cycle should be controlled by the Duty The external device needs to be chosen to fit the volt- Cycle Register. Next, the Duty Cycle Register must be age and current rating of the fan in a particular applica- programmed to the desired value. The Duty Cycle Reg- tion (Refer to Section7.5 “Output Drive Device ister is a 4 Bit read/write register that allows duty cycles Selection” Output Drive Device Selection). NPN tran- from 30% to 100% to be programmed. Table4-1 shows sistors are often a good choice for low-current fans. If a the binary codes for each possible duty cycle. NPN transistor is chosen, a base current-limiting resis- tor should be used. When using a MOSFET as the TABLE 4-1: DUTY-CYCLE REGISTER switching element, it is sometimes a good idea to have (DUTY-CYCLE) 4-BITS, a gate resistor to help slow down the turn on and turn READ/WRITE off of the MOSFET. As with any switching waveform, Duty-Cycle Register (Duty Cycle) fast rising and falling edges can sometimes lead to noise problems. D(3) D(2) D(1) D(0) Duty-Cycle As previously stated, the V output will go to 100% OUT 0 0 0 0 30% duty cycle during power-up and release from shutdown 0 0 0 1 34.67% conditions. The V output only shuts down when OUT 0 0 1 0 39.33% (default for V commanded to do so via the Configuration Register IN open and when SMBus (SDM (bit 0<0>)). Even when a locked rotor condition is not selected) is detected, the V output will continue to pulse at OUT 0 0 1 1 44% the programmed duty cycle. 0 1 0 0 48.67% 4.7 Sensing Fan Operation (SENSE1 & 0 1 0 1 53.33% SENSE2) 0 1 1 0 58% The TC654 and TC655 also feature Microchip's propri- 0 1 1 1 62.67% etary FanSense technology. During normal fan opera- 1 0 0 0 67.33% tion, commutation occurs as each pole of the fan is 1 0 0 1 72% energized. The fan current pulses created by the fan 1 0 1 0 76.67% commutation are sensed using low value current sense 1 0 1 1 81.33% resistors in the ground return leg of the fan circuit. The voltage pulses across the sense resistor are then AC 1 1 0 0 86% coupled through capacitors to the SENSE pins of the 1 1 0 1 90.67% TC654/TC655 device. These pulses are utilized for cal- 1 1 1 0 95.33% culating the RPM of the individual fans. The threshold 1 1 1 1 100% voltage for the SENSE pins is 100mV (typical). The DS20001734C-page 12  2002-2014 Microchip Technology Inc.

TC654/TC655 peak of the voltage pulse at the SENSE pins must 4.8 Fan Fault Threshold and exceed the 100mV (typical) threshold in order for the Indication (FAULT) pulse to be counted in the fan RPM measurement. For the TC654 and TC655 devices, a fault condition See Section7.4 “FanSense Network (R & SENSE exists whenever a fan’s sensed RPM level falls below C )” for more details on selecting the appropriate SENSE the user programmable threshold. The RPM threshold current sense resistor and coupling capacitor values. values for fan fault detection are set in the FAN_- FAULT1 and FAN_FAULT2 Registers (8-bit, read/ write). The RPM threshold represents the fan speed at which the TC654/TC655 devices will indicate a fan fault. This FAN FAN 1 2 threshold can be set at lower levels to indicate fan locked rotor conditions or set to higher levels to give indications for predictive fan failure. It is recommended R ISO1 that the RPM threshold be at least 10% lower than the minimum fan speed which occurs at the lowest duty cycle set point. The default value for the fan RPM VOUT RISO2 thresholds is 500RPM. If the fan's sensed RPM is less than the fan fault threshold for 2.4 seconds (typical), a fan fault condition is indicated. SENSE1 When a fault condition due to low fan RPM occurs, a TC654/ C logic low is asserted at the FAULT output. F1F (bit TC655 SENSE1 R SENSE1 0<0>) and F2F (bit 1<0>) in the Status Register are set to ‘1’ for respective low RPM levels on the SENSE1 and SENSE2 inputs. The FAULT output and the fault SENSE2 bits in the Status Register can be reset by setting CSENSE2 FFCLR (bit 7<0>) in the Configuration Register to a ‘1’. R GND SENSE2 For the TC655 device, a fault condition is also indicated when an Over-Temperature Fault condition occurs. This condition occurs when the V duty cycle OUT exceeds the 100% value indicating that no additional FIGURE 4-7: Fan Current Sensing. cooling capability is available. For this condition, a logic By selecting F1PPR (bits 2-1<01>) and F2PPR (bits 4- low is asserted at the FAULT output and OTF (bit 5<X>) 3<01>) in the Configuration Register, the TC654 and of the Status Register, the over-temperature fault indi- TC655 can be programmed to calculate RPM data for cator, is set to a ‘1’ (The TC654 also indicates an over- fans with 1, 2, 4 or 8 current pulses per rotation. The temperature condition via the OTF bit in the status reg- default state assumes a fan with 2 pulses per rotation. ister). If the duty cycle then decreases below 100%, the FAULT output will be released and OTF (bit 5<X>) of The measured RPM data is then stored in the RPM- the Status Register will be reset to ‘0’. OUTPUT1 (RPM1, for SENSE1 input) and RPM-OUT- PUT2 (RPM2, for SENSE2 input) Registers. These 4.9 Low-Power Shutdown Mode registers are 9-Bit Read-Only registers which store RPM data with 25RPM resolution. By setting RES (bit Some applications may have operating conditions 6<0>) of the Configuration Register to a ‘1’, the RPM where fan cooling is not required as a result of low data can be read with 25RPM resolution. If this Bit is ambient temperature or light system load. During these left in the default state of '0', the RPM data will only be times it may be desirable to shut the fans down to save readable with resolution of 50RPMs, which represents power and reduce system noise. 8-Bit data. The TC654/TC655 devices can be put into a low-power The maximum fan RPM reading is 12775RPM. If this Shutdown mode by setting SDM (bit 0<0>) in the Con- value is exceeded, counter overflow bits in the Status figuration register to a ‘1’ (this bit is the shutdown bit). Register are set. R1CO (bit 3<0>) and R2CO (bit 4<0>) When the TC654/TC655 devices are in Shutdown in the Status Register represent the RPM1 and RPM2 mode, all functions except for the SMBus interface are counter overflow bits for the RPM1 and RPM2 regis- suspended. During this mode of operation, the TC654 ters, respectively. These bits will automatically be reset and TC655 devices will draw a typical supply current of to zero if the fan RPM reading has been below the max- only 5µA. Normal operation will resume as soon as Bit imum value of 12775RPM for 2.4 seconds. 0 in the Configuration Register is reset to ‘0’. See Table6-1 for RPM1, RPM2 and Status Register command byte assignments.  2002-2014 Microchip Technology Inc. DS20001734C-page 13

TC654/TC655 When the TC654/TC655 devices are brought out of a Shutdown mode by resetting SDM (bit 0<0>) in the Configuration Register, all of the registers (except for the Configuration and FAN_FAULT1 and 2 registers) assume their default power-up states. The Configura- tion Register and the FAN_FAULT1 and 2 Registers maintain the states they were in prior to the device being put into the Shutdown mode. Since these are the registers which control the parts operation, the part does not have to be reprogrammed for operation when it comes out of Shutdown mode. 4.10 SMBus Interface (SCLK & SDA) The TC654/TC655 feature an industry-standard, 2-wire serial interface with factory-set addresses. By commu- nicating with the TC654/TC655 device registers, func- tions like PWM duty cycle, low-power Shutdown mode and fan RPM threshold can be controlled. Critical infor- mation, such as fan fault, over-temperature and fan RPM, can also be obtained via the device data regis- ters. The available data and control registers make the TC654/TC655 devices very flexible and easy to use. All of the available registers are detailed in Section6.0 “Register Set”. 4.11 SMBus Slave Address The slave address of the TC654/TC655 is 0011 011 and is fixed. This address is different from industry- standard digital temperature sensors (like TCN75) and, therefore, allows the TC654/TC655 to be utilized in systems in conjunction with these components. Please contact Microchip Technology Inc. if alternate addresses are required. DS20001734C-page 14  2002-2014 Microchip Technology Inc.

TC654/TC655 5.0 SERIAL COMMUNICATION are initiated by a Start condition (Start), followed by a device address byte and one or more data bytes. The 5.1 SMBus 2-Wire Interface device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop Condi- The Serial Clock Input (SCLK) and the bi-directional tion (Stop). A convention call Acknowledge (ACK) con- data port (SDA) form a 2-wire bi-directional serial port firms the receipt of each byte. Note that SDA can only for communicating with the TC654/TC655. The follow- change during periods when SCLK is low (SDA ing bus protocols have been defined: changes while SCLK is high are reserved for Start and • Data transfer may be initiated only when the bus Stop conditions). All bytes are transferred MSB (most is not busy. significant bit) first. • During data transfer, the data line must remain 5.1.2 MASTER/SLAVE stable whenever the clock line is high. Changes in the data line while the clock line is high will be The device that sends data onto the bus is the transmit- interpreted as a Start or Stop condition. ter and the device receiving data is the receiver. The bus is controlled by a master device which generates Accordingly, the following Serial Bus conventions have the serial clock (SCLK), controls the bus access and been defined. generates the Start and Stop conditions. The TC654/ TC655 always work as a slave device. Both master and TABLE 5-1: TC654/TC655 SERIAL BUS slave devices can operate as either transmitter or CONVENTIONS receiver, but the master device determines which mode Term Description is activated. Transmitter The device sending data to the bus. 5.1.3 START CONDITION (START) Receiver The device receiving data from the bus. A high-to-low transition of the SDA line while the clock (SCLK) is high determines a Start condition. All com- Master The device which controls the bus: ini- mands must be preceded by a Start condition. tiating transfers (Start), generating the clock and terminating transfers (Stop). 5.1.4 ADDRESS BYTE Slave The device addressed by the master. Immediately following the Start Condition, the host Start A unique condition signaling the must transmit the address byte to the TC654/TC655. beginning of a transfer indicated by The 7-bit SMBus address for the TC654/TC655 is SDA falling (High to Low) while SCLK 0011 011. The 7-bit address transmitted in the serial is high. bit stream must match for the TC654/TC655 to respond Stop A unique condition signaling the end with an Acknowledge (indicating the TC654/TC655 is of a transfer indicated by SDA rising on the bus and ready to accept data). The eighth bit in (Low to High) while SCLK is high. the Address Byte is a Read-Write Bit. This bit is a ‘1’ for ACK A Receiver acknowledges the receipt a read operation or ‘0’ for a write operation. During the of each byte with this unique condi- first phase of any transfer, this bit will be set = 0 to indi- tion. The Receiver pulls SDA low cate that the command byte is being written. during SCLK high of the ACK clock- 5.1.5 STOP CONDITION (STOP) pulse. The Master provides the clock pulse for the ACK cycle. A low-to-high transition of the SDA line while the clock Busy Communication is not possible (SCLK) is high determines a Stop condition. All opera- because the bus is in use. tions must be ended with a Stop condition. NOT Busy When the bus is idle, both SDA and 5.1.6 DATA VALID SCLK will remain high. Data Valid The state of SDA must remain stable The state of the data line represents valid data when, during the high period of SCLK in after a Start condition, the data line is stable for the order for a data bit to be considered duration of the high period of the clock signal. valid. SDA only changes state while The data on the line must be changed during the low SCLK is low during normal data trans- period of the clock signal. There is one clock pulse per fers. (See Start and Stop conditions) bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The 5.1.1 DATA TRANSFER number of the data bytes transferred between the Start The TC654/TC655 support a bi-directional 2-Wire bus and Stop conditions is determined by the master device and data transmission protocol. The serial protocol and is unlimited. sequencing is illustrated in Figure1-1. Data transfers  2002-2014 Microchip Technology Inc. DS20001734C-page 15

TC654/TC655 5.1.7 ACKNOWLEDGE (ACK) last byte that has been clocked out of the slave. In this case, the slave (TC654/TC655) will leave the data line Each receiving device, when addressed, is obliged to high to enable the master device to generate the Stop generate an acknowledge bit after the reception of condition. each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge 5.2 SMBus Protocols bit. The TC654/TC655 devices communicate with three The device that acknowledges has to pull down the standard SMBus protocols. These are the write byte, SDA line during the acknowledge clock pulse in such a read byte and receive byte. The receive byte is a short- way that the SDA line is stable low during the high ened method for reading from, or writing to, a register period of the acknowledge related clock pulse. Setup which had been selected by the previous read or write and hold times must be taken into account. During command. These transmission protocols are shown in reads, a master device must signal an end of data to Figures 5-1, 5-2 and 5-3. the slave by not generating an acknowledge bit on the S ADDRESS WR ACK COMMAND ACK DATA ACK P 7 Bits 8 Bits 8 Bits Slave Address Command Byte: selects Data Byte: data goes which register you are into the register set writing to. by the command byte. FIGURE 5-1: SMBus Protocol: Write Byte Format. S ADDRESS WR ACK COMMAND ACK 7 Bits 8 Bits Slave Address Command Byte: selects which register you are writing to. S ADDRESS RD ACK DATA NACK P 7 Bits 8 Bits Slave Address: Data Byte: reads from repeated due to change the register set by the in data flow direction. command byte. FIGURE 5-2: SMBus Protocol: Read Byte Format. S ADDRESS RD ACK DATA NACK P 7 Bits 8 Bits Slave Address Data Byte: reads data from the register commanded by the last Read Byte or Write Byte transmission FIGURE 5-3: SMBus Protocol: Receive Byte Format. S = Start Condition ACK = Acknowledge = 0 P = Stop Condition NACK = Not Acknowledged = 1 Shaded = Slave Transmission WR = Write = 0 RD = Read = 1 DS20001734C-page 16  2002-2014 Microchip Technology Inc.

TC654/TC655 6.0 REGISTER SET The TC654/TC655 devices contain 9 registers that pro- vide a variety of data and functionality control to the outside system. These registers are listed below in Table6-1. Of key importance is the command byte information, which is needed in the read and write pro- tocols in order to select the individual registers. TABLE 6-1: COMMAND BYTE ASSIGNMENTS Register Command Read Write POR Default State Function RPM1 0000 0000 X — 0 0000 0000 RPM Output 1 RPM2 0000 0001 X — 0 0000 0000 RPM Output 2 FAN_FAULT1 0000 0010 X X 0000 1010 Fan Fault 1 Threshold FAN_FAULT2 0000 0011 X X 0000 1010 Fan Fault 2 Threshold CONFIG 0000 0100 X X 0000 1010 Configuration STATUS 0000 0101 X — 00X0 0X00 Status. See Section6.4 “Status Register (Status)”, Status Register explanation of X DUTY_CYCLE 0000 0110 X X 0000 0010 Fan Speed Duty Cycle MFR_ID 0000 0111 X — 0101 0100 Manufacturer Identification VER_ID 0000 1000 X — 0000 000X Version Identification: (X = ‘0’ TC654, X = ‘1’ TC655) 6.1 RPM-OUTPUT1 & RPM-OUTPUT2 the RPM information in 50RPM (8-bit) or 25RPM (9- Registers (RPM1 & RPM2) bit) increments. This is selected via RES (bit 6<0>) in the Configuration Register, with ‘0’ = 50RPM and As discussed in Section4.7 “Sensing Fan Operation ‘1’=25RPM. The default state is zero (50RPM). The (SENSE1 & SENSE2)”, fan current pulses are detected maximum fan RPM value that can be read is at the SENSE1 and SENSE2 inputs of the TC654/ 12775RPM. If this value is exceeded, R2CO (bit 4<0>) TC655 device. The current pulse information is used to and R1CO (bit 3<0>) in the Status Register will be set to calculate the fan RPM. The fan RPM data for fans 1 and a '1' to indicate that a counter overflow of the respective 2 is then written to registers RPM1 and RPM2, respec- RPM register has occurred. Register6-1 shows the tively. RPM1 and RPM2 are 9-bit registers that provide RPM output register 9-bit format. REGISTER 6-1: RPM OUTPUT REGISTERS (RPM1 & RPM2) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) RPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 1 0 12750 1 1 1 1 1 1 1 1 1 12775  2002-2014 Microchip Technology Inc. DS20001734C-page 17

TC654/TC655 6.2 FAN_FAULT1 & FAN_FAULT2 in RPM1 and RPM2 Registers) drops below the value Threshold Registers that is set in the Fan Fault Registers for more than 2.4sec, a fan fault indication will be given. F1F (bit (FAN_FAULT1 & FAN_ FAULT2) 0<0>) and F2F (bit 1<0>) in the Status Register indi- The Fan Fault Threshold Registers (FAN_FAULT1 and cate fan fault conditions for fan 1 and fan 2, respec- FAN_ FAULT2) are used to set the fan fault threshold tively. The FAULT output will also be pulled low in a fan levels for fan 1 and fan 2, respectively. The Fan Fault fault condition. Changing FFCLR (bit 7<0>) in the Con- Registers are 8-bit, read/writable registers that allow figuration Register will reset the fan fault bits in the Sta- the fan fault RPM threshold to be set in 50RPM incre- tus Register as well as the FAULT output. See ments. The default setting for both Fan Fault registers Register6-2 for the Fan Fault Threshold Register 8-bit is 500RPM (0000 1010). The maximum set point format. value is 12750 RPM. If the measured fan RPM (stored REGISTER 6-2: FAN FAULT THRESHOLD REGISTERS (FAN_FAULT1 & FAN_FAULT2) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) RPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 1 0 100 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 0 12700 1 1 1 1 1 1 1 1 12750 DS20001734C-page 18  2002-2014 Microchip Technology Inc.

TC654/TC655 6.3 CONFIGURATION REGISTER V duty cycle (fan speed) control method, select the OUT (CONFIG) fan current pulses per rotation for fans 1 and 2 (for fan RPM calculation) and put the TC654/TC655 device into The Configuration Register is an 8-bit read/writable a Shutdown mode to save power consumption. See multi-function control register. This register allows the Register6-3 below for the Configuration Register bit user to clear fan faults, select RPM resolution, select descriptions. REGISTER 6-3: CONFIGURATION REGISTER (CONFIG) R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 FFCLR RES DUTYC F2PPR F2PPR F1PPR F1PPR SDM bit 7 bit 0 bit 7 FFCLR: Fan Fault Clear 1 = Clear Fan Fault. This will reset the Fan Fault bits in the Status Register and the FAULT output. 0 = Normal Operation (default) bit 6 RES: Resolution Selection for RPM Output Registers 1 = RPM Output Registers (RPM1 and RPM2) will be set for 25RPM (9-bit) resolution. 0 = RPM Output Registers (RPM1 and RPM2) will be set for 50RPM (8-bit) resolution. (default) bit 5 DUTYC: Duty Cycle Control Method 1 = The VOUT duty cycle will be controlled via the SMBus interface. The value for the VOUT duty cycle will be taken from the duty cycle register (DUTY_CYCLE). 0 = The VOUT duty cycle will be controlled via the VIN analog input pin. The VOUT duty cycle value will be between 30% and 100% for V values between 1.62V and 2.6V typical. If the V pin is open IN IN when this mode is selected, the V duty cycle will default to 39.33%. (default) OUT bit 4-3 F2PPR: Fan 2 Pulses Per Rotation The TC654/TC655 device uses this setting to understand how many current pulses per revolution Fan 2 should have. It then uses this as part of the calculation for the fan 2RPM value in the RPM2 Register. See Section7.7 “Determining Current Pulses Per Revolution of Fans” for application information on determining your fan’s number of current pulses per revolution. 00 = 1 01 = 2 (default) 10 = 4 11 = 8 bit 2-1 F1PPR: Fan 1 Pulses Per Rotation The TC654/TC655 device uses this setting to understand how many current pulses per revolution Fan 1 should have. It then uses this as part of the calculation for the fan 1RPM value for the RPM1 Register. See Section7.7 “Determining Current Pulses Per Revolution of Fans” for application information on determining your fan’s number of current pulses per revolution. 00 = 1 01 = 2 (default) 10 = 4 11 = 8 bit 0 SDM: Shutdown Mode 1 = Shutdown mode. See Section4.9 “Low-Power Shutdown Mode” for more information on low- power Shutdown mode. 0 = Normal operation. (default) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2002-2014 Microchip Technology Inc. DS20001734C-page 19

TC654/TC655 6.4 STATUS REGISTER (STATUS) and over-temperature indication are all available in the Status register. The Status register is an 8-bit Read- The Status register provides all the information about Only register with bits 6 and 7 unused. See Register6- what is going on within the TC654/TC655 devices. Fan 4 below for the bit descriptions. fault information, V status, RPM counter overflow, IN REGISTER 6-4: STATUS REGISTER (STATUS) U-0 U-0 R-X R-0 R-0 R-X R-0 R-0 — — OTF R2CO R1CO VSTAT F2F F1F bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OTF: Over-Temperature Fault Condition For the TC654/TC655 device, this bit is set to the proper state immediately at start-up and is therefore treated as an unknown (X). If V is greater than the threshold required for 100% duty cycle on V IN OUT (2.6V typical), then the bit will be set to a ‘1’. If it is less than the threshold, the bit will be set to ‘0’. This is determined at power-up. 1 = Over-Temperature condition has occurred. 0 = Normal operation. VIN is less than 2.6V. bit 4 R2CO: RPM2 Counter Overflow 1 = Fault condition. The maximum RPM reading of 12775RPM in register RPM2 has been exceeded. This bit will automatically reset to zero when the RPM reading comes back into range. 0 = Normal operation. RPM reading is within limits (default). bit 3 R1CO: RPM1 Counter Overflow 1 = Fault condition. The maximum RPM reading of 12775RPM in register RPM1 has been exceeded. This bit will automatically reset to zero when the RPM reading comes back into range. 0 = Normal operation. RPM reading is within limits (default). bit 2 VSTAT: V Input Status IN For the TC654/TC655 devices, the V pin status is checked immediately at power-up. If no external IN thermistor or voltage output network is connected (V is open), this bit is set to a ‘1’. If an external net- IN work is detected, this bit is set to ‘0’. If the V pin is open and SMBus operation has not been selected IN in the Configuration Register, the V duty cycle will default to 39.33%. OUT 1 = VIN is open. 0 = Normal operation. voltage present at VIN. bit 1 F2F: Fan 2 Fault 1 = Fault Condition. The value for fan RPM in the RPM2 Register has fallen below the value set in the FAN_FAULT2 Threshold Register. The speed of Fan 2 is too low and a fault condition is being indi- cated. The FAULT output will be pulled low at the same time. This fault bit can be cleared using the Fan Fault Clear bit (FFCLR (bit 7<0>)) in the Configuration Register. 0 = Normal Operation (default). bit 0 F1F: Fan 1 Fault 1 = Fault Condition. The value for fan RPM in the RPM1 Register has fallen below the value set in the FAN_FAULT1 Threshold Register. The speed of Fan 1 is too low and a fault condition is being indi- cated. The FAULT output will be pulled low at the same time. This fault bit can be cleared using the Fan Fault Clear bit (FFCLR (bit 7<0>)) in the Configuration Register. 0 = Normal Operation (default). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS20001734C-page 20  2002-2014 Microchip Technology Inc.

TC654/TC655 6.5 DUTY-CYCLE Register 6.6 Manufacturer’s Identification (DUTY_CYCLE) Register (MFR_ID) The DUTY_CYCLE register is a 4-bit read/writable reg- This register allows the user to identify the manufac- ister used to control the duty cycle of the V output. turer of the part. The MFR_ID register is an 8-bit Read- OUT The controllable duty cycle range via this register is Only register. See Register6-6 for the Microchip man- 30% to 100%, with programming steps of 4.67%.This ufacturer ID. method of duty cycle control is mainly used with the SMBus interface. However, if the VIN method of duty REGISTER 6-6: MANUFACTURER’S cycle control has been selected (or defaulted to), and IDENTIFICATION the VIN pin is open, the duty cycle will go to the default REGISTER (MFR_ID) setting of this register, which is 0010 (39.33%). The duty cycle settings are shown in Register6-5. D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 1 0 1 0 1 0 0 REGISTER 6-5: DUTY-CYCLE REGISTER (DUTY_CYCLE) 6.7 Version ID Register (VER_ID) D(3) D(2) D(1) D(0) Duty-Cycle This register is used to indicate which version of the 0 0 0 0 30% device is being used, either the TC654 or the TC655. 0 0 0 1 34.67% This register is a simple 2-bit Read-Only register. 0 0 1 0 39.33% (default for V IN open and when SMBus REGISTER 6-7: VERSION ID REGISTER is not selected) (VER_ID) 0 0 1 1 44% D[1] D[0] Version 0 1 0 0 48.67% 0 0 TC654 0 1 0 1 53.33% 0 1 TC655 0 1 1 0 58% 0 1 1 1 62.67% 1 0 0 0 67.33% 1 0 0 1 72% 1 0 1 0 76.67% 1 0 1 1 81.33% 1 1 0 0 86% 1 1 0 1 90.67% 1 1 1 0 95.33% 1 1 1 1 100%  2002-2014 Microchip Technology Inc. DS20001734C-page 21

TC654/TC655 7.0 APPLICATIONS INFORMATION SDA SCLK 7.1 Connecting to the SMBus PIC16F876 The SMBus is an open-collector bus, requiring pull-up Microcontroller resistors connected to the SDA and SCLK lines. This configuration is shown in Figure7-1. 24LC01 EEPROM V TC654/TC655 DD Fan Speed Controller TCN75 oller R R TC654/TC655 TemSepnersaotrure ®Contr SDA PIc SCLK o FIGURE 7-2: Multiple Devices on SMBus. r c Mi 7.2 Setting the PWM Frequency Range for R: 13.2kto 46k for V = 5.0V DD The PWM frequency of the V output is set by the OUT FIGURE 7-1: Pull-up Resistors On capacitor value attached to the C pin. The PWM fre- F SMBus. quency will be 30Hz (typical) for a 1µF capacitor. The relationship between frequency and capacitor value is The number of devices connected to the bus is limited linear, making alternate frequency selections easy. only by the maximum rise and fall times of the SDA and SCLK lines. Unlike I2C specifications, SMBus As stated in previous sections, the PWM frequency should be kept in the range of 15Hz to 35Hz. This will does not specify a maximum bus capacitance value. eliminate the possibility of having audible frequencies Rather, the SMBus specification calls out that the max- when varying the duty cycle of the fan drive. imum current through the pull-up resistor be 350µA (minimum, 100µA, is also specified). Therefore, the A very important factor to consider when selecting the value of the pull-up resistors will vary depending on the PWM frequency for the TC654/TC655 devices is the system’s bias voltage, V . Minimizing bus capaci- RPM rating of the selected fan and the minimum duty DD tance is still very important as it directly affects the rise cycle for operation. For fans that have a full-speed rat- and fall times of the SDA and SCLK lines. The range ing of 3000RPM or less, it is desirable to use a lower for pull-up resistor values for a 5V system are shown PWM frequency. A lower PWM frequency allows for a in Figure7-1. longer time period to monitor the fan current pulses. The goal is to be able to monitor at least two fan current Although SMBus specifications only require the SDA pulses during the on time of the V output. and SCLK lines to pull down 350µA, with a maximum OUT voltage drop of 0.4V, the TC654/TC655 has been Example: Your system design requirement is to oper- designed to meet a maximum voltage drop of 0.4V, with ate the fan at 50% duty cycle when ambient tempera- 3mA of current. This allows lower values of pull-up tures are below 20°C. The fan full-speed RPM rating is resistors to be used, which will allow higher bus capac- 3000RPM and has four current pulses per rotation. At itance. If this is to be done, though, all devices on the 50% duty cycle, the fan will be operating at approxi- bus must be able to meet the same pull-down current mately 1500RPM. requirements as well. A possible configuration using multiple devices on the EQUATION SMBus is shown in Figure7-2. 601000 Time for one revolution (msec.) = ------------------------ = 40 1500 If one fan revolution occurs in 40msec, then each fan pulse occurs 10msec apart. In order to detect two fan current pulses, the on time of the V pulse must be OUT at least 20msec. With the duty cycle at 50%, the total period of one cycle must be at least 40msec, which makes the PWM frequency 25Hz. For this example, a PWM frequency of 20Hz is recommended. This would define a C capacitor value of 1.5µF. F DS20001734C-page 22  2002-2014 Microchip Technology Inc.

TC654/TC655 7.3 Temperature Sensor Design EQUATION As discussed in previous sections, the V analog input V R IN Vt1 = -------------D---D--------------2---------- has a range of 1.62V to 2.6V (typical), which represents R t1+R TEMP 2 a duty cycle range on the V output of 30% to 100%, OUT respectively. The VIN voltages can be thought of as rep- VDDR2 resenting temperatures. The 1.62V level is the low tem- Vt2 = ---------------------------------------- R t2+R TEMP 2 perature at which the system only requires 30% fan speed for proper cooling. The 2.6V level is the high temperature, for which the system needs maximum In order to solve for the values of R1 and R2, the values cooling capability. Therefore, the fan needs to be at for VIN and the temperatures at which they are to occur 100% speed. need to be selected. The variables, t1 and t2, represent the selected temperatures. The value of the thermistor One of the simplest ways of sensing temperature over at these two temperatures can be found in the thermis- a given range is to use a thermistor. By using an NTC tor data sheet. With the values for the thermistor and thermistor as shown in Figure7-3, a temperature vari- the values for V , you now have two equations from ant voltage can be created. IN which the values for R and R can be found. 1 2 Example: The following design goals are desired: VDD • Duty Cycle = 50% (V = 1.9V) with Temperature IN (t1) = 30°C IDIV • Duty Cycle = 100% (V = 2.6V) with Temperature IN (t2) = 60°C Using a 100k thermistor (25°C value), we look up the Rt R1 thermistor values at the desired temperatures: • R = 79428 @ 30°C VIN t • R = 22593 @ 60°C t Substituting these numbers into the given equations, R2 we come up with the following numbers for R and R . 1 2 • R = 34.8k 1 FIGURE 7-3: Temperature Sensing • R2 = 14.7k Circuit. Figure7-3 represents a temperature dependent volt- 140000 4.000 aRaRglT1lee Eal M dnrPidev si(RdRise2Tt roaE crrM eirPc cs ou=tmai tRn.b Rd1ina t* ari sdRti oart/en cRs oit1shn t+avoet r Rsnw.tt )iRi.ol ln1A baasel n tN hdrTe eR Cftete frtmohrerepmdrem rataoi spt utaoarrers-, esistance () 11028000000000000 VIN Voltage 2233....050500000000 (V)N iRnTcEreMaPs wesil,l dtheec rveaalusee wofi thR ti td. eAccrceoarsdeinsg alyn, dth teh ev ovlatalugee oatf ork R 4600000000 NTC Thermistor 1.500 VI V increases as temperature increases, giving the w 100K @ 25ºC 1.000 deINsired relationship for the VIN input. The purpose of Net 20000 RTEMP 0.500 R is to help linearize the response of the sensing net- 0 0.000 1 work. Figure7-4 shows an example of this. 20 30 40 50 60 70 80 90 100 There are many values that can be chosen for the NTC Temperature (ºC) thermistor. There are also thermistors which have a lin- FIGURE 7-4: How Thermistor Resistance, ear resistance instead of logarithmic, which can help to V , And R Vary With Temperature. eliminate R1. If less current draw from VDD is desired, IN TEMP then a larger value thermistor should be chosen. The Figure7-4 graphs three parameters versus tempera- voltage at the VIN pin can also be generated by a volt- ture. They are Rt, R1 in parallel with Rt, and VIN. As age output temperature sensor device. The key is to described earlier, you can see that the thermistor has a get the desired VIN voltage to system (or component) logarithmic resistance variation. When put in parallel temperature relationship. with R , though, the combined resistance becomes 1 The following equations apply to the circuit in more linear, which is the desired effect. This gives us Figure7-3. the linear looking curve for VIN.  2002-2014 Microchip Technology Inc. DS20001734C-page 23

TC654/TC655 7.4 FanSense Network (R & TABLE 7-1: R VS. FAN CURRENT SENSE SENSE C ) SENSE Nominal Fan Current R (ohm) (mA) SENSE The network comprised of R and C allows SENSE SENSE the TC654/TC655 devices to detect commutation of the 50 9.1 fan motor. RSENSE converts the fan current into a volt- 100 4.7 age. C AC couples this voltage signal to the SENSE 150 3.0 SENSE pins (SENSE1 and SENSE2). The goal of the SENSE network is to provide a voltage pulse to the 200 2.4 SENSE pin that has a minimum amplitude of 120mV. 250 2.0 This will ensure that the current pulse caused by the 300 1.8 fan commutation is recognized by the TC654/TC655 350 1.5 device. 400 1.3 A 0.1µF ceramic capacitor is recommended for C . Smaller values will require larger sense resis- 450 1.2 SENSE tors be used. Using a 0.1µF capacitor results in rea- 500 1.0 sonable values for R . Figure7-5 illustrates a SENSE Figure7-6 shows some typical waveforms for the fan typical SENSE network. current and the voltage at the Sense pins. FAN FAN 1 2 R ISO1 715 RR IISSOO22 V OUT 715 SENSE1 C SENSE1 R SENSE1 (0.1µF typical) SENSE2 C SENSE2 R (0.1µF typical) SENSE2 FIGURE 7-6: Typical Fan Current and Note: See Table7-1 for RSENSE1 and RSENSE2 values. Sense Pin Waveforms. FIGURE 7-5: Typical Sense Network. 7.5 Output Drive Device Selection The value of R will change with the current rating SENSE of the fan. A key point is that the current rating of the The TC654/TC655 is designed to drive two external fan specified by the manufacturer may be a worst case NPN transistors or two external N-channel MOSFETs rating. The actual current drawn by the fan may be as the fan speed modulating elements. These two lower than this rating. For the purposes of setting the arrangements are shown in Figure7-7. For lower cur- value for RSENSE, the operating fan current should be rent fans, NPN transistors are a very economical measured. choice for the fan drive device. It is recommended that, for higher-current fans (500mA and above), MOSFETs Table7-1 shows values of R according to the SENSE be used as the fan drive device. Table7-2 provides nominal operating current of the fan. The fan currents some possible part numbers for use as the fan drive are average values. If the fan current falls between two element. of the values listed, use the higher resistor value. When using an NPN transistor as the fan drive ele- ment, a base current limiting resistor must be used. This is shown in Figure7-7. When using MOSFETs as the fan drive element, it is very easy to turn the MOSFETs on and off at very high rates. Because the gate capacitances of these small DS20001734C-page 24  2002-2014 Microchip Technology Inc.

TC654/TC655 MOSFETs are very low, the TC654/TC655 can charge • Ask how the fan is designed. If the fan has clamp and discharge them very quickly, leading to very fast diodes internally, you will not experience this edges. Of key concern is the turn-off edge of the MOS- problem. If the fan does not have internal clamp FET. Since the fan motor winding is essentially an diodes, it is a good idea to put one externally inductor, once the MOSFET is turned off, the current (Figure7-8). You can also put a resistor between that was flowing through the motor wants to continue to V and the gate of the MOSFET, which will help OUT flow. If the fan does not have internal clamp diodes slow down the turn-off and limit this condition. around the windings of the motor, there is no path for this current to flow through, and the voltage at the drain of the MOSFET may rise until the drain to source rating of the MOSFET is exceeded. This will most likely cause the MOSFET to go into Avalanche mode. Since there is very little energy in this occurrence, it will probably not fail the device, but it would be a long term reliability issue. The following is recommended: VDD VDD FAN FAN RBASE VOUT Q1 VOUT Q1 RSENSE RSENSE GND GND a) Single Bipolar Transistor b) N-Channel MOSFET FIGURE 7-7: Output Drive Device Configurations. TABLE 7-2: FAN DRIVE DEVICE SELECTION TABLE (Note2) Max Vbe sat / Fan Current Suggested Device Package Min hfe Vce/V Vgs(V) DS (mA) Rbase (ohms) MMBT2222A SOT-23 1.2 50 40 150 800 MPS2222A TO-92 1.2 50 40 150 800 MPS6602 TO-92 1.2 50 40 500 301 SI2302 SOT-23 2.5 NA 20 500 Note1 MGSF1N02E SOT-23 2.5 NA 20 500 Note1 SI4410 SO-8 4.5 NA 30 1000 Note1 SI2308 SOT-23 4.5 NA 60 500 Note1 Note 1: A series gate resistor may be used in order to control the MOSFET turn-on and turn-off times. 2: These drive devices are suggestions only. Fan currents listed are for individual fans.  2002-2014 Microchip Technology Inc. DS20001734C-page 25

TC654/TC655 The first piece of information required is the fan's full- speed RPM rating. The fan RPM rating can then be converted to give the time for one revolution using the following equation: FAN EQUATION 601000 Time for one revolution (msec.) = ------------------------ Fan RPM The fan current can now be monitored over this time VOUT Q1 period. The number of pulses occurring in this time period is the fan's "Current Pulses per Rotation" rating which is needed in order to accurately read fan RPM. RSENSE Example: The full-speed fan RPM rating is 8200RPM. From this, the time for one fan revolution is calculated to be 7.3msec, using the previously discussed equa- tion. Using a current probe, the fan current can be mon- itored as the fan is operating at full speed. Figure7-9 GND shows the fan current pulses for this example. The Q1- N-Channel MOSFET 7.44msec window, marked by the cursors, is very near the 7.3msec calculated above, and is within the toler- FIGURE 7-8: Clamp Diode For Fan Turn- ance of the fan ratings. Four current pulses occur within Off. this 7.44msec time frame. Given this information, F2PPR (bits 4-3<01>) and F1PPR (bits 2-1<01>) in the 7.6 Bias Supply Bypassing and Noise Configuration Register, should be set to '10' to indicate Filtering 4 current pulses per revolution. The bias supply (V ) for the TC654/TC655 devices DD should be bypassed with a 1µF ceramic capacitor. This capacitor will help supply the peak currents that are required to drive the base/gate of the external fan drive devices. As the V pin controls the duty cycle in a linear fashion, IN any noise on this pin can cause duty cycle jittering. For this reason, the V pin should be bypassed with a IN 0.01µF capacitor. In order to keep fan noise off of the TC654/TC655 device ground, individual ground returns for the TC654/ TC655 and the low side of the fan current sense resis- tor should be used. 7.7 Determining Current Pulses Per Revolution of Fans There are many different fan designs available in the FIGURE 7-9: Four Current Pulses Per marketplace today. The motor designs can vary and, Revolution Fan. along with it, the number of current pulses in one fan revolution. In order to correctly measure and communi- 7.8 How to Eliminate False Current cate the fan speed, the TC654/TC655 must be pro- Pulse Sensing grammed for the proper number of fan current pulses per revolution. This is done by setting the F2PPR and During the PWM mode of operation, some fans will F1PPR bits in the Configuration Register to the proper generate an extra current pulse. This pulse occurs values (see Section6.3 “Configuration Register when the external drive device is turned on and is, in (Config)” for settings). A fan's current pulses per revo- most cases, caused by the fan's electronics that control lution can be determined in the following manner. the fan motor. This pulse does not represent true fan current and needs to be blanked out. This is particularly important for detecting a fan in a locked rotor condition. Figure7-10 shows the voltage pulse at the Sense pin, DS20001734C-page 26  2002-2014 Microchip Technology Inc.

TC654/TC655 which is caused by the fan's "extra" current pulse during PWM output turn-on. FAN FAN 1 2 RISO1 CSLOW1 (0.1uF typical) Sense Pin Voltage V RISO2 "Extra Pulse" OUT CSLOW2 SENSE1 CSENSE (0.1 µF typical) TC654/ (0.1 µF typical) RSENSE1 TC655 VOUT PWM SENSE2 GND (C0.1S µEFN tySpEica2l) RSENSE2 FIGURE 7-11: Transistor Drive with C FIGURE 7-10: Extra Pulse at Sense Pin. SLOW Capacitor. This problem occurs mainly with fans that have a cur- rent waveshape like the one shown in Figure7-9. For configurations where an NPN transistor is being used as the external drive device, the typical R and SENSE FAN FAN C scheme can continue to be used to sense the 1 2 SENSE fan current pulses. In order to eliminate the extra cur- rent pulse, a slow-down capacitor can be placed from the base of the transistor to ground. A 0.1µF capacitor is appropriate in most cases. This arrangement is V shown in Figure7-11. This capacitor will help to slow OUT down the turn-on edge of the transistor and reduce the RSLOW1 amplitude of the extra current pulse. (1k typical) SENSE1 For configurations using an N-channel MOSFET as the CSLOW1 dcorinved itdioenvsic ea,n dth eth sel ocwu-rdreonwtn s ceanpsaincgit osrc dhoeemse nmotu fsixt baell TTCC665545/ (1000pF typical) RSENSE1 changed. Since the current for this type of fan always (1RkSL tOyWpi2cal) returns to zero, the coupling capacitor (C ) is not SENSE2 SENSE needed. Instead, it will be replaced by an R-C configu- GND CSLOW2 RSENSE2 ration to eliminate the voltage pulse generated by the (1000pF typical) extra current pulse. This new sensing configuration is shown in Figure7-12. The values of the resistor/capac- FIGURE 7-12: FET Drive with R / SLOW itor combination should be adjusted so that the voltage C Sense Scheme. SLOW pulse generated by the extra current pulse is smoothed and is not registered by the TC654/TC655 as a true fan current pulse. Typical values for R and C are SLOW SLOW 1K and 1000pF, respectively.  2002-2014 Microchip Technology Inc. DS20001734C-page 27

TC654/TC655 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 10-Lead MSOP (3x3 mm) Example TC654E 135256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001734C-page 28  2002-2014 Microchip Technology Inc.

TC654/TC655 UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2014 Microchip Technology Inc. DS20001734C-page 29

TC654/TC655 UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001734C-page 30  2002-2014 Microchip Technology Inc.

TC654/TC655 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2014 Microchip Technology Inc. DS20001734C-page 31

TC654/TC655 NOTES: DS20001734C-page 32  2002-2014 Microchip Technology Inc.

TC654/TC655 APPENDIX A: REVISION HISTORY Revision C (July 2014) The following is the list of modifications. 1. Updated the package marking drawing. 2. Added Appendix A. Revision B (January 2013) The following is the list of modifications. 1. Added a note to the package outline drawing. Revision A (2002) • Original Release of this Document.  2002-2014 Microchip Technology Inc. DS20001734C-page 33

TC654/TC655 NOTES: DS20001734C-page 34  2002-2014 Microchip Technology Inc.

TC654/TC655 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) TC654EUN: PWM Fan Speed Controller w/ Range Fault Detection b) TC654EUNT: PWM Fan Speed Controller w/Fault Detection (Tape and Reel) Device: TC654: PWM Fan Speed Controller w/Fault Detection c) TC655EUN: PWM Fan Speed Controller w/ TC654T: PWM Fan Speed Controller w/Fault Detection Fault Detection (Tape and Reel) TC655: PWM Fan Speed Controller w/Fault Detection d) TC655EUNT: PWM Fan Speed Controller TC655T: PWM Fan Speed Controller w/Fault Detection w/Fault Detection (Tape and Reel) (Tape and Reel) Temperature Range: E = -40C to +85C Package: UN = Plastic Micro Small Outline (MSOP), 10-lead  2002-2014 Microchip Technology Inc. DS20001734C-page35

TC654/TC655 NOTES: DS20001734C-page 36  2002-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2002-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-362-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2002-2014 Microchip Technology Inc. DS20001734C-page 37

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