TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 QUAD DIFFERENTIAL PECL DRIVERS FEATURES The TB5D1M device is a pin and functional 1 • FunctionalReplacementsfortheAgere replacement for the Agere systems BDG1A and BPNGA quad differential drivers. The TB5D1M has a BDG1A,BPNGAandBDGLA built-in lightning protection circuit to absorb large • Pin-EquivalenttotheGeneral-Trade26LS31 transitions on the transmission lines without Device destroying the device. When the circuit is powered • 2.0nsMaximumPropagationDelays down it loads the transmission line, because of the protectioncircuit. • 0.15nsOutputSkewTypicalBetweenPairs • CapableofDriving50-ΩLoads The TB5D2H device is a pin and functional replacement for the Agere systems BDG1A and • 5.0-Vor3.3-VSupplyOperation BDGLA quad differential drivers. Upon power down • TB5D1MIncludesSurgeProtectionon the TB5D2H output circuit appears as an open circuit DifferentialOutputs anddoesnotloadthetransmissionline. • TB5D2HNoLineLoadingWhenVCC=0 Both drivers feature a 3-state output with a third-state • ThirdStateOutputCapability leveloflessthan0.1V. • -40Cto85COperatingTempRange The packaging options available for these quad • ESDProtectionHBM>3kVandCDM>2kV differential line drivers include a 16-pin SOIC • AvailableinGull-WingSOIC(JEDECMS-013, gull-wing(DW)anda16-pinSOIC(D)package. DW)andSOIC(D)Packages Both drivers are characterized for operation from -40Cto85C APPLICATIONS The logic inputs of this device include internal pull-up • DigitalDataorClockTransmissionOver resistors of approximately 40 kΩ that are connected BalancedTransmissionLines to V to ensure a logical high level input if the inputs CC areopencircuited. DESCRIPTION These quad differential drivers are TTL input to pseudo-ECL differential output used for digital data transmissionoverbalancedtransmissionlines. DW AND D PACKAGE FUNCTIONAL DIAGRAM (TOP VIEW) AO AI AI 1 16 VCC AO AO 2 15 DI BO AO 3 14 DO BI E1 4 13 DO BO ENABLE TRUTH TABLE BO 5 12 E2 CO E1 E2 Condition BO 6 11 CO CI 0 0 Active CO BI 7 10 CO 1 0 Active GND 8 9 CI DO DI 0 1 Disabled DO 1 1 Active E1 E2 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION PARTNUMBER PARTMARKING PACKAGE LEADFINISH STATUS TB5D1MDW TB5D1M Gull-wingSOIC NiPdAu Production TB5D1MD TB5D1M SOIC NiPdAu Production TB5D2HDW TB5D2H Gull-wingSOIC NiPdAu Production TB5D2HD TB5D2H SOIC NiPdAu Production PACKAGE DISSIPATION RATINGS CIRCUIT T ≤25°C THERMALRESISTANCE, DERATINGFACTOR(1) T =85CPOWER A A PACKAGE BOARD POWER JUNCTION-TO-AMBIENT ABOVET =25C RATING A MODEL RATING WITHNOAIRFLOW Low-K(2) 754mW 132.6C/W 7.54mW/C 301mW D High-K(3) 1166mW 85.8C/W 11.7mW/C 466mW Low-K(2) 816mW 122.5C/W 8.17mW/C 326mW DW High-K(3) 1206mW 82.9C/W 12.1mW/C 482mW (1) Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedwithnoairflow. (2) Inaccordancewiththelow-KthermalmetricdefinitionsofEIA/JESD51-3. (3) Inaccordancewiththehigh-KthermalmetricdefinitionsofEIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER PACKAGE VALUE UNITS D 51.4 C/W q Junction-to-boardthermalresistance JB DW 56.6 C/W D 45.7 C/W q Junction-to-casethermalresistance JC DW 49.2 C/W ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) TB5D1M,TB5D2H Supplyvoltage,V 0Vto6V CC Inputvoltage -0.3Vto(V +0.3V) CC HumanBodyModel(2) AllPins 3kV ESD Charged-DeviceModel(3) AllPins 2kV Continuouspowerdissipation SeeDissipationRatingTable Storagetemperature,T -65Cto130C stg Junctiontemperature,T 130C J DPackage -80Vto100V Lightningsurge,TB5D1Monly,seeFigure6 DWPackage -100Vto100V (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) TestedinaccordancewithJEDECStandard22,TestMethodA114-A. (3) TestedinaccordancewithJEDECStandard22,TestMethodC101. 2 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 RECOMMENDED OPERATING CONDITIONS(1) MIN NOM MAX UNIT Supplyvoltage,V 5.0-Vnominalsupply 4.5 5 5.5 V CC 3.3-Vnominalsupply 3.0 3.3 3.6 V Operatingfree-airtemperature,T -40 85 C A (1) Thealgebraicconvention,inwhichtheleastpositive(mostnegative)limitisdesignatedasminimumisusedinthisdatasheet,unless otherwisestated. ELECTRICAL CHARACTERISTICS overrecommendedoperatingconditionsunlessotherwisenoted parameter testconditions min typ(1) max unit V =4.5Vto5.5V, CC 40 noloads I Supplycurrent mA CC V =3.0Vto3.6V, CC 40 noloads V =4.5Vto5.5V, CC 290 360 Figure3loadsalloutputs P Powerdissipation mW D V =3.0Vto3.6V, CC 280 360 Figure4loadsalloutputs V Outputhighvoltage V -1.8 V -1.3 V -0.8 V OH CC CC CC V =4.5Vto5.5V, V Outputlowvoltage CC V -1.4 V -1.2 V -0.7 V OL Figure3 OH OH OH V Differentialoutputvoltage|V -V | 0.7 1.2 1.4 V OD OH OL V Outputhighvoltage V -1.8 V -1.3 V -0.8 V OH CC CC CC V =3.0Vto3.6V, V Outputlowvoltage CC V -1.4 V -1.1 V -0.5 V OL Figure4 OH OH OH V Differentialoutputvoltage|V -V | 0.5 1.1 1.4 V OD OH OL Peak-to-peakcommon-modeoutput V C =5pF,Figure5 230 600 mV OC(PP) voltage L V Third-stateoutputvoltage Figure3orFigure4load 0.1 V OZ V Lowlevelinputvoltage(2) 0.8 V IL V Highlevelinputvoltage 2 V IH V Enableinputclampvoltage V =4.5V,I =-5mA -1(3) V IK CC I V =5.5V,V =0V -250(3) I Outputshort-circuitcurrent(4) CC O mA OS V =5.5V,V =0V 10(3) CC OD I Inputlowcurrent,enableordata V =5.5V,V =0.4V -400(3) A IL CC I Inputhighcurrent,enableordata V =5.5V,V =2.7V 20 A CC I I IH Inputreversecurrent,enableordata V =5.5V,V =5.5V 100 A CC I C Inputcapacitance 5 pF IN (1) Alltypicalvaluesareat25Candwitha3.3-Vor5-Vsupply. (2) Theinputlevelprovidesnonoiseimmunityandshouldbetestedonlyinastatic,noise-freeenvironment. (3) Thisparameterislistedusingamagnitudeandpolarity/directionconvention,ratherthananalgebraicconvention,tomatchtheoriginal Ageredatasheet. (4) Testmustbeperformedoneoutputatatimetopreventdamagetothedevice.Notestcircuitattached. Copyright©2003–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 THIRD STATE—A TB5D1M (or TB5D2H) driver produces pseudo-ECL levels, and has a third-state mode, which is different than a conventional TTL device. When a TB5D1M (or TB5D2H) driver is placed in the third state, the base of the output transistors is pulled low, bringing the outputs below the active-low level of standard PECL devices. [For example: The TB5D1M low output level is typically 2.7 V, while the third state output level is less than 0.1 V.] In a bidirectional, multipoint, bus application, the driver of one device, which is in its third state, may be back driven by another driver on the bus whose voltage in the low state is lower than the third-stated device. This could come about due to differences in the driver's independent power supplies. In this case, the device in the third state controls the line, thus clamping the line and reducing the signal swing. If the difference voltage between the independent driver power supplies is small, this consideration can be ignored. Again using the TB5D1M driver as an example, a typical supply voltage difference between separate drivers of > 2 V can exist withoutsignificantlyaffectingtheamplitudeofthesignal. SWITCHING CHARACTERISTICS, 5-V NOMINAL SUPPLY overrecommendedoperatingconditionsunlessotherwisenoted parameter testconditions min typ(1) max unit tP1 Propagationdelaytime,inputhightooutput(2) CL=5pF,SeeFigure1and 1.2 2 ns t Propagationdelaytime,inputlowtooutput(2) Figure3 1.2 2 P2 Δt Capacitivedelay 0.01 0.03 ns/pF P Propagationdelaytime, t 7 12 PHZ high-level-to-high-impedanceoutput Propagationdelaytime, t 7 12 PLZ low-level-to-high-impedanceoutput C =5pF,SeeFigure2and L ns Propagationdelaytime, Figure3 t 5 12 PZH high-impedance-to-high-leveloutput Propagationdelaytime, t 4 12 PZL high-impedance-to-low-leveloutput t Outputskew,|t -t | 0.15 0.3 skew1 P1 P2 tshew2 Outputskew,|tPHH-tPHL|,|tPLH-tPLL| CL=5pF,SeeFigure1and 0.15 1.1 ns t Part-to-partskew(3) Figure3 0.1 1 skew(pp) Δt Outputskew,differencebetweendrivers(4) 0.3 skew tTLH Risetime(20%-80%) CL=5pF,SeeFigure1and 0.7 2 ns t Falltime(80%-20%) Figure3 0.7 2 THL (1) Alltypicalvaluesareat25Candwitha5-Vsupply. (2) Parameterst andt aremeasuredfromthe1.5Vpointoftheinputtothecrossoverpointoftheoutputs(seeFigure1). P1 P2 (3) t isthemagnitudeofthedifferenceindifferentialpropagationdelaytimes,t ort ,betweenanyspecifiedoutputsoftwodevices skew(pp) P1 P2 whenbothdevicesoperatewiththesamesupplyvoltage,atthesametemperature,andhaveidenticalpackagesandtestcircuits. (4) Δt isthemagnitudeofthedifferenceindifferentialskewt betweenanyspecifiedoutputsofasingledevice. skew skew1 4 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 SWITCHING CHARACTERISTICS, 3.3-V NOMINAL SUPPLY overrecommendedoperatingconditionsunlessotherwisenoted typ(1 parameter testconditions min ) max unit tP1 Propagationdelaytime,inputhightooutput(2) CL=5pF,SeeFigure1and 1.2 3.5 ns t Propagationdelaytime,inputlowtooutput(2) Figure4 1.2 3.5 P2 Δt Capacitivedelay 0.01 0.03 ns/pF P t Propagationdelaytime,high-level-to-high-impedanceoutput 8 12 PHZ tPLZ Propagationdelaytime,low-level-to-high-impedanceoutput CL=5pF,SeeFigure2and 5 12 ns t Propagationdelaytime,high-impedance-to-high-leveloutput Figure4 5 12 PZH t Propagationdelaytime,high-impedance-to-low-leveloutput 8 12 PZL t Outputskew,|t -t | 0.15 0.3 skew1 P1 P2 tshew2 Outputskew,|tPHH-tPHL|,|tPLH-tPLL| CL=5pF,SeeFigure1and 0.15 1.2 ns t Part-to-partskew(3) Figure4 0.1 1 skew(pp) Δt Outputskew,differencebetweendrivers(4) 0.3 skew tTLH Risetime(20%-80%) CL=5pF,SeeFigure1and 0.7 2 ns t Falltime(80%-20%) Figure4 0.7 2 THL (1) Alltypicalvaluesareat25Candwitha3.3-Vsupply. (2) Parameterst andt aremeasuredfromthe1.5Vpointoftheinputtothecrossoverpointoftheoutputs(seeFigure1). P1 P2 (3) t isthemagnitudeofthedifferenceindifferentialpropagationdelaytimes,t ort ,betweenanyspecifiedoutputsoftwodevices skew(pp) P1 P2 whenbothdevicesoperatewiththesamesupplyvoltage,atthesametemperature,andhaveidenticalpackagesandtestcircuits. (4) Δt isthemagnitudeofthedifferenceindifferentialskewt betweenanyspecifiedoutputsofasingledevice. skew skew1 Copyright©2003–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 2.4 V INPUT 1.5 V 0.4 V tP1 tP2 VOH OUTPUTS VOL tPHH tPLL VOH OUTPUT (VOH + VOL)/2 VOL tPHL tPLH VOH OUTPUT (VOH + VOL)/2 VOL 80% 80% VOH OUTPUT 20% 20% VOL ttLH ttHL Figure1.PropagationDelayTimeWaveforms 2.4 V E1(1) 1.5 V 0.4 V 2.4 V E2(2) 1.5 V 0.4 V tPHZ tPZH VOH VOL + 0.2 V OUTPUT VOL VOL − 0.1 V tPLZ tPZL VOL OUTPUT VOL − 0.1 V (1) E2 = 1 while E1 changes state (2) E1 = 0 while E2 changes state NOTE: In the third state, both outputs (OUTPUT and OUTPUT) are 0.1 V (max). Figure2.EnableandDisableDelayTimeWaveforms 6 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 TEST CONDITIONS Parametric values specified under the Electrical Characteristics and Switching Characteristics sections are measuredwiththefollowingoutputloadcircuit. OUTPUT 100 W OUTPUT 200 W 200 W CL CL Figure3.DriverTestCircuits,5-VNominalSupplies OUTPUT 100 W OUTPUT 75 W 75 W CL CL Figure4.DriverTestCircuits,3.3-VNominalSupplies VOC VOC OUTPUT 50 W 50 W OUTPUT OUTPUT 50 W 50 W OUTPUT 200 W 200 W 75 W 75 W CL CP = 2 pF CL CL CP = 2 pF CL Note: VOC(PP) load circuit for 5-V nominal supplies. Note: VOC(PP) load circuit for 3.3-V nominal supplies. VOH OUTPUT VOL VOC VOC(PP) Note: All input pulses are supplied by a generator having the following characteristics: tr or tf = 1 ns, pulse repetition rate (PRR) = 0.25 Mbps, pulse width = 500 ± 10 ns. CP includes the instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure5.TestCircuitsandDefinitionsfortheDriverCommon-ModeOutputVoltage Copyright©2003–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 VCC 110 W DUT 110 W + _ Lightning Surge Test Generators + _ Note: Surges may be applied simultaneously, but never in opposite polarities. Surge test pulses have tr = tf = 2 m s, pulse width = 7 m s (50% points), and period = 250 ms. Figure6.Lightning-SurgeTestingConfigurationforTB5D1M TYPICAL CHARACTERISTICS OUTPUTVOLTAGERELATIVETOV OUTPUTVOLTAGERELATIVETOV CC CC vs vs OUTPUTCURRENT FREE-AIRTEMPERATURE 0 0 TA = 25(cid:1)C VCC = 4.5 V to 5.5 V, Figure 3 Load V V - -0.5 - -0.5 C C C C V -1 VOH V o o -1 VOH Max T T e e v v ati -1.5 ati VOH Min el el -1.5 R R e -2 e g g a a olt olt -2 put V -2.5 VOL put V VOL Max Out Out -2.5 VOL Min - -3 - O O V V -3.5 -3 -50 -40 -30 -20 -10 0 -50 0 50 100 150 IO - Output Current - mA TA - Free-Air Temperature - °C Figure7. Figure8. 8 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 TYPICAL CHARACTERISTICS (continued) OUTPUTVOLTAGERELATIVETOV DIFFERENTIALOUTPUTVOLTAGE CC vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 0 1.6 VCC = 3 V to 3.6 V, VCC = 4.5 V to 5.5 V, Figure 4 Load Figure 3 Load - VC -0.5 e - V VOD Max C g 1.4 oV -1 VOH Max Volta e T put VOD Nom Relativ -1.5 VOH Min al Out 1.2 e nti g e a r ut Volt -2 VOL Max - Diffe 1 VOD Min p D Out -2.5 VOL Min VO - O V -3 0.8 -50 0 50 100 150 -50 0 50 100 150 TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C Figure9. Figure10. DIFFERENTIALOUTPUTVOLTAGE PROPAGATIONDELAYTIMEt ort P1 P2 vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE 1.4 1.6 VCC = 4.5 V to 5.5 V, VOD Max Figure 3 Load V e - ns 1.4 g 1.2 − olta VOD Nom me ut V y Ti 1.2 p a Out Del Max Delay al 1 on enti gati 1 Differ VOD Min Propa Min Delay - OD 0.8 − P 0.8 V VCC = 3 V to 3.6 V, t Figure 4 Load 0.6 0 -50 0 50 100 150 −50 0 50 100 150 TA - Free-Air Temperature - °C TA - Free-Air Temperature - (cid:1)C Figure11. Figure12. Copyright©2003–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 TYPICAL CHARACTERISTICS (continued) PROPAGATIONDELAYTIMEt ort P1 P2 vs FREE-AIRTEMPERATURE 3.5 VCC = 3 V to 3.6 V, Figure 4 Load 3 s n − e 2.5 m Ti Max Delay y a el 2 D n o ati 1.5 g a p o Min Delay Pr 1 − P t 0.5 0 −50 0 50 100 150 TA - Free-Air Temperature - (cid:1)C Figure13. 10 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 APPLICATION INFORMATION the device and PCB. JEDEC/EIA has defined Power Dissipation standardized test conditions for measuring q . Two JA commonly used conditions are the low-K and the The power dissipation rating, often listed as the high-K boards, covered by EIA/JESD51-3 and package dissipation rating, is a function of the EIA/JESD51-7 respectively. Figure 14 shows the ambient temperature, TA, and the airflow around the low-K and high-K values of q versus air flow for this device. This rating correlates with the device's JA deviceanditspackageoptions. maximum junction temperature, sometimes listed in the absolute maximum ratings tables. The maximum The standardized q values may not accurately JA junction temperature accounts for the processes and represent the conditions under which the device is materials used to fabricate and package the device, used. This can be due to adjacent devices acting as inadditiontothedesiredlifeexpectancy. heat sources or heat sinks, to nonuniform airflow, or to the system PCB having significantly different There are two common approaches to estimating the thermal characteristics than the standardized test internal die junction temperature, T . In both of these J PCBs. The second method of system thermal methods, the device’s internal power dissipation, P , D analysis is more accurate. This calculation uses the needs to be calculated. This is done by totaling the power dissipation and ambient temperature, along supply power(s) to arrive at the system power withtwodeviceandtwosystem-levelparameters: dissipation: • q , the junction-to-case thermal resistance, in (cid:1)(V (cid:1)I ) JC Sn Sn (1) degreesCelsiusperwatt • q , the junction-to-board thermal resistance, in and then subtracting the total power dissipation of the JB degreesCelsiusperwatt externalload(s): (cid:1)(V (cid:1)I ) • q CA, the case-to-ambient thermal resistance, in Ln Ln (2) degreesCelsiusperwatt The first TJ calculation uses the power dissipation • q BA, the board-to-ambient thermal resistance, in and ambient temperature, along with one parameter: degreesCelsiusperwatt. q , the junction-to-ambient thermal resistance, in JA In this analysis, there are two parallel paths, one degreesCelsiusperwatt. through the case (package) to the ambient, and The product of P and q is the junction temperature another through the device to the PCB to the D JA riseabovetheambienttemperature.Therefore: ambient. The system-level junction-to-ambient T (cid:3) T (cid:2)(P (cid:1)(cid:1) ) thermal impedance,q JA(S), is the equivalent parallel J A D JA (3) impedanceofthetwoparallelpaths: T (cid:3) T (cid:2)(P (cid:1)(cid:1) ) 140 J A D JA(S) (4) where D, Low−K ((cid:1) (cid:2)(cid:1) )(cid:1)((cid:1) (cid:2)(cid:1) ) 120 (cid:1) (cid:3) JC CA JB BA C/W DW, Low−K JA(S) ((cid:1)JC (cid:2) (cid:1)CA(cid:2) (cid:1)JB(cid:2) (cid:1)BA) − e The device parameters q and q account for the c 100 JC JB an internal structure of the device. The system-level ed parameters q and q take into account details of p CA BA m the PCB construction, adjacent electrical and al I 80 mechanical components, and the environmental m er DW, High−K conditions including airflow. Finite element (FE), finite Th difference (FD), or computational fluid dynamics D, High−K (CFD) programs can determine q and q . Details 60 CA BA on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. 40 0 100 200 300 400 500 Air Flow − LFM Figure14.ThermalImpedancevsAirFlow Note that q is highly dependent on the PCB on JA which the device is mounted, and on the airflow over Copyright©2003–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TB5D1M TB5D2H

TB5D1M, TB5D2H www.ti.com SLLS579C–SEPTEMBER2003–REVISEDJANUARY2008 Load Circuits Transmission Line The test load circuits shown in Figure 3 and Figure 4 are based on a recommended pi type of load circuit INPUT OUTPUT shown in Figure 15. The 100-Ω differential load Recommended Resistor Values: RT/2 RT/2 rfoersitshtoerinRtTeractonthneecretincegivtrearnpsrmovisidsieonprloinpee,ratessrmuminiantgionit FFoorr 35. 3V VN oNmom S uSpupplpielise,s R, TR =T =20 100 W0 ,W R, SR =S =9 03 0W W RS has a 100-Ω characteristic impedance. The two resistors RS to ground at the driver end of the Figure16.ARecommendedYLoadCircuit transmission line link provide dc current paths for the emitter follower output transistors. The two resistors An additional load circuit, similar to one commonly to ground normally should not be placed at the usedwithECLandPECL,isshowninFigure17. receiver end, as they shunt the termination resistor, potentially creating an impedance mismatch with Transmission Line undesirablereflections. INPUT OUTPUT Transmission Line Recommended Resistor Values: RT/2 RT/2 For 5 V and 3.3 V Nom Supplies, RT = 100 W , INPUT RT = 100 (cid:1) OUTPUT VT = VCC - 2.55 V _+ VT RS RS Recommended Resistor Values: For 5-V Nominal Supplies, RS = 200 (cid:1) Figure17.ARecommendedPECL-StyleLoad For 3.3-V Nominal Supplies, RS = 75 (cid:1) Circuit Figure15.ARecommendedpiLoadCircuit An important feature of all of these recommended load circuits is that they ensure that both of the Another common load circuit, a Y load, is shown in emitter follower output transistors remain active Figure 16. The receiver-end line termination of RT is (conducting current) at all times. When deviating from provided by the series combination of the two RT/2 these recommended values, it is important to make resistors, while the dc current path to ground is sure that the low-side output transistor does not turn provided by the single resistor RS. Recommended off. Failure to do so increases the tskew2 and VOC(PP) values, as a function of the nominal supply voltage values, increasing the potential for electromagnetic range,areindicatedinthefigure. radiation. 12 SubmitDocumentationFeedback Copyright©2003–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TB5D1M TB5D2H

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TB5D1MD ACTIVE SOIC D 16 40 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D1M (RoHS) Level-1-220C-UNLIM TB5D1MDE4 ACTIVE SOIC D 16 40 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D1M (RoHS) Level-1-220C-UNLIM TB5D1MDW ACTIVE SOIC DW 16 40 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D1M (RoHS) Level-1-220C-UNLIM TB5D1MDWR ACTIVE SOIC DW 16 2000 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D1M (RoHS) Level-1-220C-UNLIM TB5D2HD ACTIVE SOIC D 16 40 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D2H (RoHS) Level-1-220C-UNLIM TB5D2HDR ACTIVE SOIC D 16 2500 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D2H (RoHS) Level-1-220C-UNLIM TB5D2HDW ACTIVE SOIC DW 16 40 Pb-Free NIPDAU Level-2-250C-1YEAR/ -40 to 85 TB5D2H (RoHS) Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TB5D2HDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TB5D2HDR SOIC D 16 2500 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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