TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 125W STEREO/250W MONO PurePath™ HD ANALOG-INPUT POWER STAGE CheckforSamples:TAS5611A FEATURES APPLICATIONS 1 • PurePath™HDEnabledIntegratedFeedback • HomeTheaterSystems 23 Provides: • AVReceivers – SignalBandwidthupto80kHzforHigh • DVD/Blu-rayReceivers FrequencyContentFromHDSources • MiniComboSystem – Ultralow0.03%THDat1Winto4Ω • ActiveSpeakersandSubwoofers – FlatTHDatallFrequenciesforNatural Sound DESCRIPTION – 80dBPSRR(BTL,NoInputSignal) The TAS5611A is a high performance analog input – >100dB(Aweighted)SNR Class D amplifier with integrated closed loop – ClickandPopFreeStartup feedback technology (known as PurePath™ HD) with • PincompatiblewithTAS5630,TAS5615and the ability to drive up to 125W (1) Stereo into 4 to 8 Ω TAS5613 Speakersfromasingle32.5Vsupply. • MultipleConfigurationsPossibleontheSame PurePath™ HD technology enables traditional PCBWithStuffingOptions: AB-Amplifier performance (<0.03% THD) levels while – MonoParallelBridgeTiedLoad(PBTL) providing the power efficiency of traditional class D amplifiers. – StereoBridgeTiedLoad(BTL) – 2.1SingleEndedStereoPairandBridge Unlike traditional Class D amplifiers, the distortion TiedLoadSubwoofer curve only increases once the output levels move into • TotalOutputPowerat10%THD+N clipping.PurePath™HDPowerPAD™ – 250WinMonoPBTLConfigurationinto2Ω PurePath™ HD technology enables lower idle losses – 125WperChannelinStereoBTL makingthedeviceevenmoreefficient. Configurationinto4Ω TTOOTTAALLHHAARRMMOONNIICCDDIISSTTOORRTTIIOONN++NNOOIISSEE • TotalOutputPowerinBTLconfigurationat VVSS OOUUTTPPUUTTPPOOWWEERR 1%THD+N 1100 44OOhhmm((66kkHHzz)) – 130WStereointo3Ω 44OOhhmm ((11kkHHzz)) %% • –––>90175%0055WWEWfSSfiSctteeiteerreenreootoPiinnointtwootoe68r4ΩΩSΩtageWith60-mΩ monicDistortion-monicDistortion- 00,,1111 OutputMOSFETs HarHar • Self-ProtectionDesign(Including talTotal N- 0,01 Undervoltage,Overtemperature,Clipping,and + D H Short-CircuitProtection)WithErrorReporting T TC=75C CONFIG=BTL • EMICompliantWhenUsedWith 0,001 RecommendedSystemDesign 0,01 1 100 • ThermallyEnhancedPackageOptions: PO-OutputPower-W – PHD(64-PinQFP) (1) Achievableoutputpowerlevelsaredependentonthethermal configurationofthetargetapplication.Ahighperformance thermalinterfacematerialbetweenthepackageexposed heatslugandtheheatsinkshouldbeusedtoachievehigh outputpowerlevels. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PurePath,PowerPADaretrademarksofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 UNLESS OTHERWISE NOTED this document contains Copyright©2010–2011,TexasInstrumentsIncorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. DEVICE INFORMATION Pin Assignment TheTAS5611Aisavailableinathermallyenhancedpackages: • 64-PinQFP(PHD)PowerPackage The package types contain heat slugs that are located on the top side of the device for convenient thermal couplingtotheheatsink. PHD PACKAGE (TOPVIEW) VDDPSU_REFNCNCNCNCGNDGNDGVDD_BGVDD_ABST_AOUT_AOUT_APVDD_APVDD_AGND_A PIN ONE LOCATION PHD PACKAGE 4321098765432109 Electrical Pin 1 OC_ADJ 1666665555555555448 GND_A RESET 2 47 GND_B C_STARTUP 3 46 GND_B INPUT_A 4 45 OUT_B INPUT_B 5 44 OUT_B VI_CM 6 43 PVDD_B Pin 1 Marker GND 7 42 PVDD_B White Dot AGND 8 41 BST_B VREG 9 40 BST_C INPUT_C 10 39 PVDD_C INPUT_D 11 38 PVDD_C FREQ_ADJ 12 37 OUT_C OSC_IO+ 13 36 OUT_C OSC_IO- 14 35 GND_C SD 15 64-pins QFPpackage 34 GND_C OTW1 16 33 GND_D 17181920212223242526272829303132 OTW2CLIPREADYM1M2M3GNDGNDVDD_CVDD_DBST_DOUT_DOUT_DVDD_DVDD_DGND_D GG PP MODE SELECTION PINS MODEPINS OUTPUT ANALOGINPUT DESCRIPTION M3 M2 M1 CONFIGURATION 0 0 0 Differential 2×BTL ADmode 0 0 1 — — Reserved 0 1 0 Differential 2×BTL BDmode DifferentialSingle 0 1 1 1×BTL+2×SE BDmode,BTLDifferential Ended 1 0 0 SingleEnded 4×SE ADmode INPUT_C (1) INPUT_D (1) 1 0 1 Differential 1×PBTL 0 0 ADmode 1 0 BDmode 1 1 0 Reserved 1 1 1 (1) INPUT_CandDareusedtoselectbetweenasubsetofADandBDmodeoperationsinPBTLmode(1=VREGand0=GND). 2 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 PACKAGE HEAT DISSIPATION RATINGS(1) PARAMETER TAS5611APHD R (°C/W)–2BTLor4SEchannels 3.2 θJC R (°C/W)–1BTLor2SEchannel(s) 5.4 θJC R (°C/W)–1SEchannel 7.9 θJC PadArea (2) 64mm2 (1) J isjunction-to-case,CHiscase-to-heatsink C (2) R isanimportantconsideration.Assumea2-milthicknessofthermalgreasewithathermalconductivityof2.5W/mKbetweenthe θCH padareaandtheheatsinkandbothchannelsactive.TheR withthisconditionis1.1°C/WforthePHDpackageand0.44°C/Wfor θCH theDKDpackage. Table1. ORDERINGINFORMATION(1) T PACKAGE DESCRIPTION A 0°C–70°C TAS5611APHD 64pinHTQFP (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted (1) VALUE UNIT VDDtoGND –0.3to13.2 V GVDDtoGND –0.3to13.2 V PVDD_XtoGND_X(2) –0.3to53 V OUT_XtoGND_X(2) –0.3to53 V BST_XtoGND_X(2) –0.3to66.2 V BST_XtoGVDD_X(2) –0.3to53 V VREGtoGND –0.3to4.2 V GND_XtoGND –0.3to0.3 V GNDtoAGND –0.3to0.3 V OC_ADJ,M1,M2,M3,OSC_IO+,OSC_IO-,FREQ_ADJ,VI_CM,C_STARTUP,PSU_REF –0.3to4.2 V toGND INPUT_X –0.3to7 V RESET,SD,OTW1,OTW2,CLIP,READYtoGND –0.3to7 V Continuoussinkcurrent(SD,OTW1,OTW2,CLIP,READY) 9 mA Operatingjunctiontemperaturerange,T 0to150 °C J Storagetemperature,T –40to150 °C stg Humanbodymodel(3)(allpins) ±2 kV Electrostaticdischarge Chargeddevicemodel(3)(allpins) ±500 V (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) ThesevoltagesrepresentstheDCvoltage+peakACwaveformmeasuredattheterminalofthedeviceinallconditions. (3) Failuretofollowgoodanti-staticESDhandlingduringmanufactureandreworkwillcontributetodevicemalfunction.Pleaseensure operatorshandlingthedeviceareadequatelygroundedthroughtheuseofgroundstrapsoralternativeESDprotection. Copyright©2010–2011,TexasInstrumentsIncorporated 3

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT PVDD_x Half-bridgesupply DCsupplyvoltage 16 32.5 34.1 V GVDD_x Supplyforlogicregulatorsandgate-drivecircuitry DCsupplyvoltage 10.8 12 13.2 V VDD Digitalregulatorsupplyvoltage DCsupplyvoltage 10.8 12 13.2 V RL(BTL) 3.5 4 Outputfilteraccordingtoschematicsinthe RL(SE) Loadimpedance applicationinformationsection 1.8 2 Ω RL(PBTL) 1.6 2 Outputfilteraccordingtoschematicsinthe applicationinformationsectionandadd RL(BTL) Loadimpedance SchottkydiodesonalloutputnodestoGND_X, 2.8 3 Ω ROC=22kΩ LOUTPUT(BTL) 7 10 LOUTPUT(SE) Outputfilterinductance MinimumoutputinductanceatIOC 7 15 μH LOUTPUT(PBTL) 7 10 Nominal 385 400 415 PWMframerateselectableforAMinterference FPWM avoidance;1%Resistortolerance. AM1 315 333 350 kHz AM2 260 300 335 Nominal;Mastermode 9.9 10 10.1 RFREQ_ADJ PWMframerateprogrammingresistor AM1;Mastermode 19.8 20 20.2 kΩ AM2;Mastermode 29.7 30 30.3 CPVDD PVDDclosedecouplingcapacitors 2.0 μF ROC Over-currentprogrammingresistor Resistortolerance=5% 22 30 kΩ ROC_LATCHED Over-currentprogrammingresistor Resistortolerance=5% 47 64 kΩ VoltageonFREQ_ADJpinforslavemode VFREQ_ADJ operation Slavemode 3.3 V TJ Junctiontemperature 0 125 °C PINFUNCTIONS PIN FUNCTION(1) DESCRIPTION NAME PHDNO. AGND 8 P Analogground BST_A 54 P HSbootstrapsupply(BST),external0.033μFcapacitortoOUT_Arequired. BST_B 41 P HSbootstrapsupply(BST),external0.033μFcapacitortoOUT_Brequired. BST_C 40 P HSbootstrapsupply(BST),external0.033μFcapacitortoOUT_Crequired. BST_D 27 P HSbootstrapsupply(BST),external0.033μFcapacitortoOUT_Drequired. CLIP 18 O Clippingwarning;opendrain;activelow C_STARTUP 3 O Startupramprequiresachargingcapacitorof4.7nFtoGNDinBTLmode FREQ_ADJ 12 I PWMframerateprogrammingpinrequiresresistortoGND GND 7,23,24,57,58 P Ground GND_A 48,49 P Powergroundforhalf-bridgeA GND_B 46,47 P Powergroundforhalf-bridgeB GND_C 34,35 P Powergroundforhalf-bridgeC GND_D 32,33 P Powergroundforhalf-bridgeD GVDD_A 55 P Gatedrivevoltagesupplyrequires0.1μFcapacitortoGND_A GVDD_B 56 P Gatedrivevoltagesupplyrequires0.1μFcapacitortoGND_B GVDD_C 25 P Gatedrivevoltagesupplyrequires0.1μFcapacitortoGND_C GVDD_D 26 P Gatedrivevoltagesupplyrequires0.1μFcapacitortoGND_D GVDD_AB — P Gatedrivevoltagesupplyrequires0.22μFcapacitortoGND_A/GND_B GVDD_CD — P Gatedrivevoltagesupplyrequires0.22μFcapacitortoGND_C/GND_D (1) I=Input,O=Output,P=Power 4 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 PINFUNCTIONS(continued) PIN FUNCTION(1) DESCRIPTION NAME PHDNO. INPUT_A 4 I InputsignalforhalfbridgeA INPUT_B 5 I InputsignalforhalfbridgeB INPUT_C 10 I InputsignalforhalfbridgeC INPUT_D 11 I InputsignalforhalfbridgeD M1 20 I Modeselection M2 21 I Modeselection M3 22 I Modeselection NC 59–62 — Noconnect,pinsmaybegrounded. OC_ADJ 1 O Analogovercurrentprogrammingpinrequires30kΩresistortoGND. OSC_IO+ 13 I/O Oscillatormaster/slaveoutput/input. OSC_IO– 14 I/O Oscillatormaster/slaveoutput/input. OTW — O Overtemperaturewarningsignal,opendrain,activelow. OTW1 16 O Overtemperaturewarningsignal,opendrain,activelow. OTW2 17 O Overtemperaturewarningsignal,opendrain,activelow. OUT_A 52,53 O Output,halfbridgeA OUT_B 44,45 O Output,halfbridgeB OUT_C 36,37 O Output,halfbridgeC OUT_D 28,29 O Output,halfbridgeD PSU_REF 63 P PSUReferencerequiresclosedecouplingof330pFtoGND PowersupplyinputforhalfbridgeArequiresclosedecouplingof2uFcapacitor PVDD_A 50,51 P GND_A PowersupplyinputforhalfbridgeBrequiresclosedecouplingof2uFcapacitor PVDD_B 42,43 P GND_B PowersupplyinputforhalfbridgeCrequiresclosedecouplingof2uFcapacitor PVDD_C 38,39 P GND_C PowersupplyinputforhalfbridgeDrequiresclosedecouplingof2uFcapacitor PVDD_D 30,31 P GND_D READY 19 O Normaloperation;opendrain;activehigh RESET 2 I DeviceresetInput;activelow SD 15 O Shutdownsignal,opendrain,activelow Powersupplyfordigitalvoltageregulatorrequiresa10-μFcapacitorinparallelwitha VDD 64 P 0.1-μFcapacitortoGNDfordecoupling. VI_CM 6 O Analogcomparatorreferencenoderequiresclosedecouplingof1nFtoGND VREG 9 P Digitalregulatorsupplyfilterpinrequires0.1-μFcapacitortoGND Copyright©2010–2011,TexasInstrumentsIncorporated 5

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com TYPICAL SYSTEM BLOCK DIAGRAM Capsfor External System microcontroller Filtering or & Analog circuitry Startup/Stop (2) Oscillator OSC_I/SDO+/RESET OTW2,/OTW /CLIP READY VI_CM PSU_REF C_STARTUP BST_A Synchronization OSC_IO- TW1,/ BST_B BoCoatsptsrap O / INPUT_A OUT_A 2ndOrder ANALOG_IN_A Input DC Input Output L-C Output Blocking INPUT_B H-Bridge1 H-Bridge1 OUT2_B Filter for ANALOG_IN_B Caps each 2 H-Bridge Hardwire 2-CHANNEL PWM Frame RateAdjust H-BRIDGE FREQ_ADJ & BTL MODE Master/Slave Mode ANALOG_IN_C Input DC INPUT_C Input Output OUT_C L2-Cnd OOurdtpeurt ANALOG_IN_D BlCocakpisng INPUT_D H-Bridge2 H-Bridge2 OUT2_D Fieltaecr hfor 2 H-Bridge HCaMorodndwtreoirle MMM213 PVDD_A,B,C,D GND_A,B,C,D GVDD_A,B,C,D GND VDD VREG AGND OC_ADJ BBSSTT__CD BoCoatsptsrap 8 8 4 PVDD PVDD GVDD,VDD, Hardwire 32.5V Power Supply &VREG Over- SYSTEM Decoupling Power Supply Current Power Decoupling Limit Supplies GND GND GVDD(12V)/VDD(12V) 12V VAC 6 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 FUNCTIONAL BLOCK DIAGRAM /CLIP READY /OTW1 /OTW2 /SD MM12 LOGIC VDD M3 &I/O CTION PORWEESRE-TUP UVP VREG VREG /RESET PROTE TEMP GVDD_A GVDD_C AGND C_STARTUP CSOTANRTTRUOPL SENSE GVDD_B GVDD_D GND PORVOETRE-CLOTIAODN CB3C CUSERNRSEENT OC_ADJ OSC_SYNC_IO+ OSC_SYNC_IO- OSCILLATOR 4 PVDD_X PPSC 4 OUT_X FREQ_ADJ 4 GND_X GVDD_A PWM ACTIVITY BST_A DETECTOR PSU_REF 4 PVDD_X PVDD_A PSU_FF VI_CM GND REPCWEIMVER CONTROL COTINMTINRGOL GATE-DRIVE OUT_A GND_A GVDD_B - ANALOG + BST_B INPUT_A LOOPFILTER PVDD_B + ANALOG - REPCWEIMVER CONTROL COTINMTINRGOL GATE-DRIVE OUT_B INPUT_B LOOPFILTER MUX GND_B INPUT_C LOAONPAFLIOLTGER ANALOGINPUTMUX +- ANALOGCOMPARATOR REPCWEIMVER CONTROL COTINMTINRGOL GATE-DRIVE GOPBVSVUDTDT_D_DCC__CC + INPUT_D ANALOG - GND_C LOOPFILTER GVDD_D BST_D PVDD_D REPCWEIMVER CONTROL COTINMTINRGOL GATE-DRIVE OUT_D GND_D Copyright©2010–2011,TexasInstrumentsIncorporated 7

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com AUDIO CHARACTERISTICS (BTL) PCBandsystemconfigurationareinaccordancewithrecommendedguidelines.Audiofrequency=1kHz,PVDD_X=32.5V, GVDD_X=12V,R =4Ω,f =400kHz,R =30kΩ,T =75°C,OutputFilter:L =7μH,C =680nF, L S OC C DEM DEM MODE=010,unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT R =3Ω,10%THD+N(addSchottkydiodeson L alloutputnodesOUT_XtoGND_X,ROC= 165 22kΩ) R =4Ω,10%THD+N 125 L P Poweroutputperchannel W O R =3Ω,1%THD+N(addSchottkydiodeson L alloutputnodesOUT_XtoGND_X,ROC= 130 22kΩ) R =4Ω,1%THD+N 105 L THD+N Totalharmonicdistortion+noise 1W 0.03% A-weighted,AES17filter,InputCapacitor V Outputintegratednoise 168 μV n Grounded |V | Outputoffsetvoltage InputsACcoupledtoGND 5 18 mV OS SNR Signal-to-noiseratio(1) A-weighted,AES17filter 100 dB DNR Dynamicrange A-weighted,AES17filter 100 dB P PowerdissipationduetoIdlelosses(I ) P =0,4channelsswitching(2) 1.3 W idle PVDD_X O (1) SNRiscalculatedrelativeto1%THD+Noutputlevel.. (2) Actualsystemidlelossesalsoareaffectedbycorelossesofoutputinductors. AUDIO CHARACTERISTICS (PBTL) PCBandsystemconfigurationareinaccordancewithrecommendedguidelines.Audiofrequency=1kHz,PVDD_X=32.5V, GVDD_X=12V,R =2Ω,f =400kHz,R =30kΩ,T =75°C,OutputFilter:L =7μH,C =1.5μF, L S OC C DEM DEM MODE=101-10,unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT R =2Ω,10%THD+N 250 L R =3Ω,10%THD+N 165 L R =4Ω,10%THD+N 125 L P Poweroutputperchannel W O R =2Ω,1%THD+N 210 L R =3Ω,1%THD+N 135 L R =4Ω,1%THD+N 105 L THD+N Totalharmonicdistortion+noise 1W 0.03% V Outputintegratednoise A-weighted 170 μV n SNR Signaltonoiseratio(1) A-weighted 100 dB DNR Dynamicrange A-weighted 100 dB P Powerdissipationduetoidlelosses(IPVDD_X) P =0,4channelsswitching(2) 1.3 W idle O (1) SNRiscalculatedrelativeto1%THD-Noutputlevel. (2) Actualsystemidlelossesareaffectedbycorelossesofoutputinductors. 8 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 ELECTRICAL CHARACTERISTICS PVDD_X=32.5V,GVDD_X=12V,VDD=12V,T (Casetemperature)=75°C,f =400kHz,unlessotherwisespecified. C S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INTERNALVOLTAGEREGULATORANDCURRENTCONSUMPTION Voltageregulator,onlyusedasreference VREG VDD=12V 3 3.3 3.6 V node,VREG VI_CM Analogcomparatorreferencenode,VI_CM 1.5 1.75 1.9 V Operating,50%dutycycle 20 I VDDsupplycurrent mA VDD Idle,resetmode 20 50%dutycycle 10 I GVDD_xgate-supplycurrentperhalf-bridge mA GVDD_X Resetmode 1.5 50%dutycyclewithrecommendedoutput 10 mA I Half-bridgesupplycurrent filter PVDD_X Resetmode,Noswitching 540 μA ANALOGINPUTS R Inputresistance READY=HIGH 33 kΩ IN V Maximuminputvoltageswing 7 V IN I Maximuminputcurrent 1 mA IN G VoltageGain(V /V ) 20 dB OUT IN OSCILLATOR Nominal,MasterMode 3.85 4 4.15 f AM1,MasterMode F ×10 3.15 3.33 3.5 MHz OSC_IO+ PWM AM2,MasterMode 2.6 3 3.35 V Highlevelinputvoltage 1.86 V IH V Lowlevelinputvoltage 1.45 V IL OUTPUT-STAGEMOSFETs Drain-to-sourceresistance,lowside(LS) T =25°C,excludesmetallization 60 100 mΩ R J DS(on) Drain-to-sourceresistance,highside(HS) resistance,GVDD=12V 60 100 mΩ Copyright©2010–2011,TexasInstrumentsIncorporated 9

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PVDD_X=32.5V,GVDD_X=12V,VDD=12V,T (Casetemperature)=75°C,f =400kHz,unlessotherwisespecified. C S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I/OPROTECTION Undervoltageprotectionlimit,GVDD_xand V 9.5 V uvp,G VDD V (1) 0.6 V uvp,hyst OTW1(1) Overtemperaturewarning1 95 100 105 °C OTW2(1) Overtemperaturewarning2 115 125 135 °C TemperaturedropneededbelowOTW OTW (1) temperatureforOTWtobeinactiveafter 25 °C hyst OTWevent. Overtemperatureerror 145 155 165 °C OTE(1) OTE-OTWdifferential 30 °C OTE (1) AresetneedstooccurforSDtobereleased 25 °C hyst followinganOTEevent OLPC Overloadprotectioncounter f =400kHz 2.6 ms PWM Resistor–programmable,nominalpeak 12.6 A currentin1Ωload,R =30kΩ OCP I Overcurrentlimitprotection Resistor–programmable,nominalpeak OC currentin1Ωload,R =22kΩ(add OCP 16.3 A Schottkydiodesonalloutputnodes OUT_XtoGND_X) Resistor–programmable,nominalpeak 12.6 A currentin1Ωload,R =64kΩ OCP I Overcurrentlimitprotection Resistor–programmable,nominalpeak OC_LATCHED currentin1Ωload,R =47kΩ(add OCP 16.3 A Schottkydiodesonalloutputnodes OUT_XtoGND_X) Timefromswitchingtransitiontoflip-state I Overcurrentresponsetime 150 ns OCT inducedbyovercurrent ConnectedwhenRESETisactiveto Internalpulldownresistoratoutputofeach I providebootstrapcharge.NotusedinSE 3 mA PD halfbridge mode. STATICDIGITALSPECIFICATIONS V Highlevelinputvoltage 1.9 V IH INPUT_X,M1,M2,M3,RESET V Lowlevelinputvoltage 0.8 V IL I Inputleakagecurrent 100 μA lkg OTW/SHUTDOWN(SD) Internalpullupresistance,OTW1toVREG, R 20 26 32 kΩ INT_PU OTW2toVREG,SDtoVREG Internalpullupresistor 3 3.3 3.6 V Highleveloutputvoltage V OH Externalpullupof4.7kΩto5V 4.5 5 V Lowleveloutputvoltage I =4mA 200 500 mV OL O DevicefanoutOTW1,OTW2,SD,CLIP, FANOUT Noexternalpullup 30 devices READY (1) Specifiedbydesign. 10 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTALHARMONIC+NOISE OUTPUTPOWER vs vs OUTPUTPOWER SUPPLYVOLTAGE 10 200 % TC= 75°C 3W TC= 75°C e - THD+N = 10% ois 4W + N 1 6W 150 3W n W nic Distortio 0.1 8W put Power - 100 8W 6W 4W mo ut r O al Ha P- O ot 0.01 50 T N - + D H T 0.001 0 0.01 0.1 1 10 100 1000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PO- Output Power - W PVDD- Supply Voltage - V Figure1. Figure2. UNCLIPPEDOUTPUTPOWER SYSTEMEFFICIENCY vs vs SUPPLYVOLTAGE OUTPUTPOWER 150 100 T = 75°C C 90 3W 4W 80 8W 6W 4W W 100 6W 70 ower - 8W y - % 60 put P cienc 50 Out Effi 40 - 50 O 30 P 20 T = 25°C 10 C THD+N = 10% 0 0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 50 100 150 200 250 300 PVDD- Supply Voltage - V 2 Channel Output Power - W Figure3. Figure4. Copyright©2010–2011,TexasInstrumentsIncorporated 11

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) SYSTEMPOWERLOSS OUTPUTPOWER vs vs OUTPUTPOWER CASETEMPERATURE 40 200 3W T = 25°C C THD+N = 10% 4W 30 150 W W 4W r - ss - 6W Powe 6W r Lo 20 put 100 we 8W ut o O P - O P 8W 10 50 THD+N = 10% 0 0 0 50 100 150 200 250 300 20 30 40 50 60 70 80 90 100 2 Channel Output Power - W T - Case Temperature - °C C Figure5. Figure6. NOISEAMPLITUDE TOTALHARMONICDISTORTION+NOISE vs vs FREQUENCY FREQUENCY 0 10 TC= 75°C, RL= 4W, -20 VREF = 22.98 V, % TC= 75°C, SFFaTm Splieze R =a t1e6 =3 8448 kHz, n - Toroidal Output Inductors o -40 rti 1 dB sto ude - -60 nic Di plit -80 mo 0.1 m ar A H Noise --112000 4W N - Total 0.01 1W + D H -140 T 17.3 W (1/8 Power) -160 0.001 0 5 10 15 20 10 100 1k 10k 100k f - Frequency - kHz f - Frequency - Hz Figure7. Figure8. 12 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTALHARMONICDISTORTION+NOISE OUTPUTPOWER vs vs OUTPUTPOWER SUPPLYVOLTAGE 10 300 % TC= 75°C 2W TC= 75°C oise - 3W 250 THD+N = 10% 2W + N 1 4W 3W Distortion 86WW ower - W 200 6W 4W nic 0.1 ut P 150 8W o p m ut r O Ha - 100 al PO ot 0.01 T N - 50 + D H T 0.001 0 0.01 0.1 1 10 100 1000 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P - Output Power - W PV - Supply Voltage - V O DD Figure9. Figure10. OUTPUTPOWER vs CASETEMPERATURE 300 250 2W 3W W r - 200 we 4W o P ut 150 p 6W ut O - 100 O P 50 8W THD+N = 10% 0 20 30 40 50 60 70 80 90 100 T - Case Temperature - °C C Figure11. Copyright©2010–2011,TexasInstrumentsIncorporated 13

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 Glass Epoxy material with 2 oz. (70μm) is recommended for use with the TAS5611A. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lowerPCBtraceinductance). PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000μF, 50V will support more applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speedswitching. DECOUPLING CAPACITOR RECOMMENDATIONS To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance,aqualitydecouplingcapacitorsshouldbeused.Inpractice,X7Rshouldbeusedinthisapplication. The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 2μF that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 50V is required for use with a 32.5V power supply. SYSTEM DESIGN RECOMMENDATIONS ThefollowingschematicsandPCBlayoutsillustratebestpracticesusedfortheTAS5611A. 14 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 GVDD/VDD (+12V) PVDD OUT_LEFT_M - + OUT_LEFT_P PVDDR74R743.3R3.3R GNDC78C781010nFnF GND GNDOUT_RIGHT_M - + OUT_RIGHT_P PVDD GVDD/VDD (+12V) C64C641001000uF0uF GND C69C692.2uF2.2uF GND GND C67C67101000uF00uF GND R70R703.3R3.3R C74C7410nF10nF C75C7510nF10nF R71R713.3R3.3R C68C6847uF47uF63V63V GND R72R723.3R3.3R C76C7610n10nFF C77C7710nF10nF R73R733.3R3.3R GND C50C50C70C70680nF680nF1nF1nF GND C51C51C71C71680nF680nF1nF1nF 1001000uF0uFC66C66 GNDGND C72C72C52C521nF1nF680nF680nF GND C53C53C73C73680nF680nF1nF1nF 1001000uF0uFC65C65 L10L107u7uHH L11L117uH7uH C41C4133nF33nF C42C423333nFnF 7uH7uHL12L12 L13L137uH7uH GND C61C612uF C62C622uF GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND GND_A GND_B GND_B OUT_B OUT_B PVDD_B PVDD_B BST_B BST_C PVDD_C PVDD_C OUT_C OUT_C GND_C GND_C GND_D C60C602uF 94 A_DNG D_DNG 23 C63C632uF 05 A_DDVP D_DDVP 13 15 A_DDVP D_DDVP 03 25 A_TUO D_TUO 92 R31R31C40C4033nF33nF3.3.3R3R C30C30C31C31100nF100nF100nF100nF GND 24365789015555555666 ABAADDCCCC____NNNNNNTDDTGGUSDDBOVVGG U10TAS5611APHD CDY__DDDDD__DDDDTATNNUVVE123SMMMGGGGORB 90143256871222222222 GND VREG C43C4333nF33nF R32R32GND3.3R3.3RR33R33 3.3R3.3R C33C33C32C32100nF100nF100nF100nF GNDGND R3R300 3.3R3.3R 3466 FDEDRV_USP 2WPITLOC// 7811 C26C26C25C25101010100nF0nFuFuF GNDGND 1OC_ADJ2/RESET3C_STARTUP4INPUT_A5INPUT_B6VI_CM7GND8AGND9VREG10INPUT_C11INPUT_D12FREQ_ADJ13OSC_IO+14OSC_IO-15/SD16/OTW1 GND C23C23 330pF330pF R20R20 30kC20C20 4.7nF4.7nF C21C21 1nF1nF VREG GND GND GND GND C22C22 1100nF00nF R21R21 10k10k GND VREG R19R1947k47k GND GND R18R18 C18C1810100R0R100pF100pF R10R10 C11C11100R100R100pF100pF R11R11 C13C13100R100R100pF100pF R12R12 C15C15100R100R100p100pFF R13R13 C17C171100R00R100pF100pF OSC_IO+ OSC_IO- /SD /OTW1 /OTW2 /CLIP READY C10C10 10uF10uF C12C12 10uF10uF C14C14 110uF0uF C16C16 10uF10uF /RESET IN_LEFT_P IN_LEFT_N IN_RIGHT_P R_RIGHT_N Figure12. TypicalDifferentialInputBTLApplicationWithBDModulationFilters Copyright©2010–2011,TexasInstrumentsIncorporated 15

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com GVDD (+12V) PVDD 3.3R3.3R2.2uF2.2uF100V100V10nF10nF100V100V GNDGND OUT_LEFT_M 3.3R3.3R 10nF10nF100V100V- +GND10nF10nF100V100V 3.3R3.3R OUT_LEFT_P PVDD GVDD (+12V) 47uF47uF1000uF1000uF63V63V63V63V GNDGND 1000uF1000uF63V63V GND 1uF250V250V 1nF1nF100V100V GND1nF1nF100V100V 1uF250V250V 1000u1000uFF63V63V GND 1000u1000uFF63V63V GND 7uH7uH 7uH7uH 7uH7uH 7uH7uH 33nF33nF 33nF33nF GND 2uF 2uF GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2uF GND GND_A GND_B GND_B OUT_B OUT_B PVDD_B PVDD_B BST_B BST_C PVDD_C PVDD_C OUT_C OUT_C GND_C GND_C GND_D 2uF 94 A_DNG D_DNG 23 05 A_DDVP D_DDVP 13 15 A_DDVP D_DDVP 03 3.33.3RR 3.3R3.3R 100nF100nF100nF100nF33nF33nF GNDGND GND 23456789015555555566 ACCCAADDBA_____NNNNNTTTDDGGSUUDDBOOVVGG TAS5611APHD CD__DDDDD___DDDDTTTNNUUVV123SMMMGGGGOOB 01234568972222222222 GNDGND VREG 33nF33nF3.3R3.3R 3.3R3.3R 100nF100nF100nF100nF GNDGND 26 CN YDAER 91 36 FER_USP PILC/ 81 100nF100nF10uF10uF GNDGND 330pF330pF46 DDV 1OC_ADJ2/RESET3C_STARTUP4INPUT_A5INPUT_B6VI_CM7GND8AGND9VREG10INPUT_C11INPUT_D12FREQ_ADJ13OSC_IO+14OSC_IO-15/SD16/OTW1 2WTO/ 71 GND GND VREG 30k 4.7nF4.7nF 1nF1nF 100nF100nF 10k10k GND GND GND GND GND VREG 47k47k VREG GND 100p100pFF 100pF100pF 100pF100pF GND GND GND 10100R0R 100R100R 100R100R 10uF10uF 10uF10uF VDD (+12V) /RESET IN_P IN_N OSC_IO+ OSC_IO- /SD /OTW1 /OTW2 /CLIP READY Figure13. TypicalDifferential(2N)PBTLApplicationWithBDModulationFilters 16 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5611A needs only a 12V supply in addition to the (typical) 32.5V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodatedbybuilt-inbootstrapcircuitryrequiringonlyanexternalcapacitorforeachhalf-bridge. To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors mustbeavoided.(Seereferenceboarddocumentationforadditionalinformation.) Foraproperlyfunctioningbootstrapcircuit,asmallceramiccapacitormustbeconnectedfromeachbootstrappin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the powerstage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors, size0603or0805,forthebootstrapsupply.These33nFcapacitorsensuresufficientenergystorage,evenduring minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining partofthePWMcycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 2μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5611A reference design. For additional information on recommended power supplyandrequiredcomponents,seetheapplicationdiagramsinthisdatasheet. The 12V supply should be from a low-noise, low-output impedance voltage regulator. Likewise, the 32.5V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5611A is fully protected against erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-criticalwithinthespecifiedrange(seetheRecommendedOperatingConditionstableofthisdatasheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE PoweringUp The TAS5611A does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedancestateuntilthegate-drivesupplyvoltage(GVDD_X)andVDDvoltageareabovetheundervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. PoweringDown The TAS5611A does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a goodpracticetoholdRESETlowduringpowerdown,thuspreventingaudibleartifactsincludingpopsorclicks. Copyright©2010–2011,TexasInstrumentsIncorporated 17

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com ERROR REPORTING The SD, OTW, OTW1 and OTW2 pins are active low, open-drain outputs. Their function is for protection-mode signalingtoaPWMcontrollerorothersystem-controldevice. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds100°C(seethefollowingtable). OTW2, SD OTW1 DESCRIPTION OTW 0 0 0 Overtemperature(OTE)oroverload(OLP)orundervoltage(UVP) Overload(OLP)orundervoltage(UVP).Junctiontemperaturehigherthan100°C(overtemperature 0 0 1 warning) 0 1 1 Overload(OLP)orundervoltage(UVP) 1 0 0 Junctiontemperaturehigherthan125°C(overtemperaturewarning) 1 0 1 Junctiontemperaturehigherthan100°C(overtemperaturewarning) 1 1 1 Junctiontemperaturelowerthan100°CandnoOLPorUVPfaults(normaloperation) Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown(OTE). To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see the ElectricalCharacteristicstableofthisdatasheetforfurtherspecifications). DEVICE PROTECTION SYSTEM TheTAS5611Acontainsadvancedprotectioncircuitrycarefullydesignedtofacilitatesystemintegrationandease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5611A responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed,i.e.,thesupplyvoltagehasincreased. Thedevicewillfunctiononerrors,asshowninthefollowingtable. BTLMode PBTLMode SEMode Localerrorin TurnsOfforin Localerrorin TurnsOfforin Localerrorin TurnsOfforin A A A A+B A+B B B B A+B+C+D C C C C+D C+D D D D BootstrapUVPdoesnotshutdownaccordingtothetable,itshutsdowntherespectivehalfbridge. PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC) The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an over current after the demodulationfilterwherePPSCdetectsshortsdirectlyatthepinbeforethefilter.PPSCdetectionisperformedat startupi.e.whenVDDissupplied,consequentlyashorttoeitherGND_XorPVDD_Xaftersystemstartupwillnot activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shortsfromOUT_XtoGND_X,thesecondstepteststhattherearenoshortsfromOUT_XtoPVDD_X.Thetotal duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is 18 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 <15ms/μF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A device resetwillnotstartanewPPSCdetection.PPSCdetectionisenabledinBTLandPBTLoutputconfigurations,the detection is not performed in SE mode. To make sure the PPSC detection system is not tripped, it is recommendednottoinsertresistiveloadtoGND_XorPVDD_X. OVERTEMPERATURE PROTECTION PHDPackage: The TAS5611A PHD package option has a three-level temperature-protection system that asserts an active low warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device junctiontemperatureexceeds125°C(typical)and,ifthedevicejunctiontemperatureexceeds155°C(typical),the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter,thedeviceresumesnormaloperation. UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR) The UVP and POR circuits of the TAS5611A fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increasedabovetheUVPthreshold. DEVICE RESET When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z)state. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the fallingedgeofSD. SYSTEM DESIGN CONSIDERATION Arising-edgetransitiononresetinputallowsthedevicetoexecutethestartupsequenceandstartsswitching. Apply only audio when the state of READY is high that will start and stop the amplifier without having audible artifactsthatisheardintheoutputtransducers.IfanovercurrentprotectioneventisintroducedtheREADYsignal goeslow,hence,filteringisneededifthesignalisintendedforaudiomutinginnonmicrocontrollersystems. The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio volumedecreaseorintelligentpowersupplycontrollingalowandahighrail. Thedeviceisinvertingtheaudiosignalfrominputtooutput. TheVREGpinisnotrecommendedtobeusedasavoltagesourceforexternalcircuitry. OSCILLATOR TheoscillatorfrequencycanbetrimmedbyexternalcontroloftheFREQ_ADJpin. To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower values. These values should be chosen such that the nominal and the lower value switching frequencies together results in the fewest cases of interference throughout the AM band, andcanbeselectedbythevalueoftheFREQ_ADJresistorconnectedtoGNDinmastermode. For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This will configure the OSC_I/Opinsasinputsandneedstobeslavedfromanexternalclock. Copyright©2010–2011,TexasInstrumentsIncorporated 19

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com PRINTED CIRCUIT BOARD RECOMMENDATION Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing the audio input should be kept short and together with the accompanied audio source ground. A local ground areaunderneaththedeviceisimportanttokeepsolidtominimizegroundbounce. NetlistforthisprintedcircuitboardisgeneratedfromtheschematicinFigure12. NoteT1:PVDDdecouplingbulkcapacitorsC60-C64shouldbeascloseaspossibletothePVDDandGND_Xpins, theheatsinksetsthedistance.Widetracesshouldberoutedonthetoplayerwithdirectconnectiontothepinsand withoutgoingthroughvias.Noviasortracesshouldbeblockingthecurrentpath. NoteT2:ClosedecouplingofPVDDwithlowimpedanceX7Rceramiccapacitorsisplacedundertheheatsinkand closetothepins. NoteT3:HeatsinkneedstohaveagoodconnectiontoPCBground. NoteT4:Outputfiltercapacitorsmustbelinearintheappliedvoltagerangepreferablemetalfilmtypes. Figure14. PrintedCircuitBoard-TopLayer 20 Copyright©2010–2011,TexasInstrumentsIncorporated

TAS5611A www.ti.com SLAS709B–JUNE2010–REVISEDJULY2011 NoteB1:Itisimportanttohaveadirectlowimpedancereturnpathforhighcurrentbacktothepowersupply.Keep impedancelowfromtoptobottomsideofPCBthroughalotofgroundvias. NoteB2:BootstraplowimpedanceX7Rceramiccapacitorsplacedonbottomsideprovidingashortlowinductance currentloop. NoteB3:Returncurrentsfrombulkcapacitorsandoutputfiltercapacitors. Figure15. PrintedCircuitBoard–BottomLayer SPACER Copyright©2010–2011,TexasInstrumentsIncorporated 21

TAS5611A SLAS709B–JUNE2010–REVISEDJULY2011 www.ti.com REVISION HISTORY ChangesfromOriginal(June2010)toRevisionA Page • DeletedtheDKD44-PinpackageformtheFeatures ........................................................................................................... 1 • DeletedDKDpackagedrawingfromthePinAssignmentsection........................................................................................ 2 • DeletedtheTAS5611ADKDfromthePACKAGEHEATDISSIPATIONRATINGStable .................................................... 3 • DeletedtheTAS5611ADKDfromtheORDERINGINFORMATIONtable............................................................................ 3 • ChangedtheF andR valuesintheRECOMMENDEDOPERATINGCONDITIONStable.......................... 4 PWMMIN FREQ_ADJ • ChangedtheT MaxvalueFrom:150To:125intheROCtable......................................................................................... 4 J • Changedthe|V |valuesintheAUDIOCHARACTERISTICS(BTL)tableFrom:TYP=20,MAX=40To:TYP=5, OS MAX=18 .............................................................................................................................................................................. 8 • ChangedthevaluesfotheOSCILLATORsectionoftheELECTRICALCHARACTERISTICSTABLE .............................. 9 • DeletedFigure14.TypicalDifferential......DKDPackagedrawing ..................................................................................... 14 • DeletedtheDKDPackagetextfromtheOVERTEMPERATUREPROTECTIONsection ................................................. 19 ChangesfromRevisionA(March2011)toRevisionB Page • ChangedVoltagegain(G)TYPspecfrom"21"to"20"dbdb ............................................................................................. 9 22 Copyright©2010–2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) TAS5611APHD ACTIVE HTQFP PHD 64 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5611A & no Sb/Br) TAS5611APHDR ACTIVE HTQFP PHD 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5611A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TAS5611APHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TAS5611APHDR HTQFP PHD 64 1000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW PHD 64 HTQFP - 1.20 mm max height 14 x 14, 0.8 mm pitch QUAD FLATPACK This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224851/A www.ti.com

PACKAGE OUTLINE PHD0064B HTQFP - 1.2 mm max height PLASTIC QUAD FLATPACK 14.05 13.95 B NOTE 3 PIN 1 ID 8.00 64 6.68 49 48 1 THERMAL PAD 4 14.05 16.15 8.00 13.95 15.85 6.68 NOTE 3 TYP 16 33 17 32 A 60 X 0.8 64 X 00..4300 4 X 12 0.2 C A B SEE DETAIL A C 1.2 MAX SEATING PLANE (0.127) TYP 17 32 16 33 0.25 GAGE PLANE (1) 0°-7° 0.15 0.05 0.75 0.1 C 0.45 DETAIL A TYPICAL 1 48 64 49 4224850/A 05/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. See technical brief. PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004) for information regarding recommended board layout. www.ti.com

EXAMPLE BOARD LAYOUT PHD0064B HTQFP - 1.2 mm max height PLASTIC QUAD FLATPACK SYMM 64 49 64 X (1.5) 1 48 64 X (0.55) 60 X (0.8) SYMM (15.4) 33 (R0.05) TYP 16 17 32 (15.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 6X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND METAL SOLDER MASK OPENING EXPOSED EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4224850/A 05/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN PHD0064B HTQFP - 1.2 mm max height PLASTIC QUAD FLATPACK SYMM 64 49 64 X (1.5) 1 48 64 X (0.55) 60 X (0.8) SYMM (15.4) 33 (R0.05) TYP 16 17 32 (15.4) SOLDER PASTE EXAMPLE SCALE: 6X 4224850/A 05/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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