Si4311 315/433.92 MHZ FSK RECEIVER Features  Single chip receiver with only six  Data rates up to 10kbps external components  Direct battery operation with on-  Selectable 315/433.92MHz carrier chip low drop out (LDO) voltage frequency regulator  Supports FSK modulation  16MHz crystal oscillator support  High sensitivity (–104dBm @ 5kbps)  3x3x0.85mm 20L QFN package  Excellent interference rejection (RoHS compliant)  Selectable IF bandwidths  –40 to +85°C temperature range Ordering Information:  Automatic Frequency Centering (AFC) See page14. Applications  Satellite set-top box receivers  Remote keyless entry Pin Assignments  Remote controls, IR  After market alarms replacement/extension  Telemetry Si4311  Garage and gate door openers  Wireless point of sale (Top View)  Home automation and security  Toys 0 1 Description V V C C C E E N N N D D The Si4311 is a fully-integrated FSK CMOS RF receiver that operates in the VDD 1 20 19 18 17 16 unlicensed 315 and 433.92MHz ultra high frequency (UHF) bands. It is designed RFGND 2 15 BT0 for high-volume, cost-sensitive RF receiver applications, such as set-top box RF receivers, remote controls, garage door openers, home automation, security, RX_IN 3 GND 14 BT1 remote keyless entry systems, wireless POS, and telemetry. The Si4311 offers RST 4 PAD 13 DOUT industry-leading RF performance, high integration, flexibility, low BOM, small board area, and ease of design. No production alignment is necessary as all RF AFC 5 12 GND functions are integrated into the device. 6 7 8 9 10 11 VDD Functional Block Diagram 4 D D 1 2 5/43 GN VD XTL XTL 1 3 Si4311 Antenna Patents pending ADC DOUT RX_IN LNA PGA DSP MCU AFC ADC BASEBAND 315/434 AGC PROCESSOR DEV[1:0] SQUELCH BT[1:0] 2.7 –3.6 V VDD XTAL GND LDO AFC OSC RST 16 MHz Rev. 0.5 3/10 Copyright © 2010 by Silicon Laboratories Si4311 This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si4311 2 Rev. 0.5

Si4311 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. Typical Application Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. Carrier Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. Bit Time BT[1:0] Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5. Frequency Deviation Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6. Automatic Frequency Centering (AFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7. Low Noise Amplifier Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.9. Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4. Pin Descriptions: Si4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.1. Si4311 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 7. Package Outline: Si4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. PCB Land Pattern: Si4311-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Rev. 0.5 3

Si4311 1. Electrical Specifications Table 1. Recommended Operating Conditions* Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage V 2.7 3.3 3.6 V DD Supply Voltage Powerup Rise Time V 10 — — μs DD-RISE Ambient Temperature T –40 25 85 °C A *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at V = 3.3V and 25 C unless otherwise stated. Parameters are tested in production unless DD otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Supply Voltage V –0.5 to 3.9 V DD 3 Input Current I 10 mA IN 3 Input Voltage V –0.3 to (V + 0.3) V IN DD Operating Temperature T –45 to 95 C OP Storage Temperature T –55 to 150 C STG 4 RF Input Level 0.4 V PK Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4311 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For input pins 315/434, AFC, BT[1:0], and DEV[1:0]. 4. At RF input pin RX_IN. 4 Rev. 0.5

Si4311 Table 3. DC Characteristics (T = 25°C, V = 3.3V, R = 50Ω, F = 433.92MHz unless otherwise noted) A DD s RF Parameter Symbol Test Condition Min Typ Max Unit Supply Current I — 20 — mA VDD Reset Supply Current I Reset asserted — 2 TBD µA RST High Level Input Voltage1 V 0.7xV — V +0.3 V IH DD DD Low Level Input Voltage1 V –0.3 — 0.3xV V IL DD High Level Input Current1 I V =V =3.6V –10 — 10 µA IH IN DD Low Level Input Current1 I V =0V, V =3.6V –10 — 10 µA IL IN DD High Level Output Voltage2 V I =500µA 0.8xV — — V OH OUT DD Low Level Output Voltage2 V I =–500µA — — 0.2xV V OL OUT DD Notes: 1. For input pins 315/434, AFC, BT[1:0], and DEV[1:0]. 2. For output pin DOUT. Table 4. Reset Timing Characteristics (V =3.3V, T =25°C) DD A Parameter Symbol Min Typ Max Unit RST Pulse Width t 100 — — µs SRST t SRST 70% RST 30% Figure 1. Reset Timing Rev. 0.5 5

Si4311 Table 5. Si4311 Receiver Characteristics (T =25°C, V =3.3V, R =50Ω, F =433.92MHz unless otherwise noted) A DD s RF Parameter Symbol Test Condition Min Typ Max Unit 1.0kbps, f=50kHz, xtal=±20ppm, — –104 — dBm 315MHz (Note 2) 10kbps, f=50kHz, xtal=±20ppm, — –101 — dBm 315MHz (Note 2) Sensitivity @ BER = 10-3 (Note 1) 1.0kbps, f=50kHz, xtal=±20ppm, — –102 — dBm 433.92MHz (Note 2) 10kbps, f=50kHz, xtal=±20ppm, TBD –100 — dBm 433.92MHz Data Rate3 — — 10 kbps Desired signal is 3dB above sensitivity (BER=10–3), unmodulated interferer Adjacent Channel Rejection is at ±200kHz, rejection measured as TBD 35 — dB ±200kHz1 difference between desired signal and interferer level in dB when BER=10–3 Desired signal is 3 dB above sensitivity (BER = 10–3), unmodulated interferer Alternate Channel Rejection is at ±400kHz, rejection measured as — 55 — dB ±400kHz1,2 difference between desired signal and interferer level in dB when BER=10–3 Image Rejection, IF=128kHz1,2 — 35 — dB ±2MHz, 2.4kbps, desired signal is 3dB above sensitivity, CW interferer — 65 — dB level is increased until BER=10–3 Blocking1,2 ±10MHz, 2.4kbps, desired signal is 3dB above sensitivity, CW interferer — 70 — dB level is increased until BER=10–3 Maximum RF Input Power 1,2 — 8 — dBm | f –f |=5MHz, high gain mode, 2 1 desired signal is 3dB above sensitivity, Input IP33 — –10 — dBm CW interference levels are increased until BER=10–3 FSK Deviation Input Range3 10 — 90 kHz LNA Input Capacitance3 — 7 — pF RX Boot Time3 From reset — 320 — ms Notes: 1. 1.0kbps, f=50kHz, xtal=±20ppm, AFC=0, BT[1:0]=00, DEV[1:0]=01. 2. Guaranteed by characterization. 3. Guaranteed by design. 6 Rev. 0.5

Si4311 Table 6. Crystal Characteristics (V =3.3V, T =25°C) DD A Parameter Symbol Test Condition Min Typ Max Unit Crystal Oscillator Frequency — 16 — MHz Crystal ESR — — 100  XTL1, XTL2 Input Capacitance — 11 — pF Rev. 0.5 7

Si4311 2. Typical Application Schematic DEV0 DEV1 0 9 8 7 6 RX 2 1 1 1 1 BT0 ANTENNA VDD C C C 0 1 BT1 N N N V V E E 1 D D 15 VDD BT0 2 14 L1 RFGND BT1 3 U1 13 RX_IN DOUT DOUT C3 4 Si4311-GM 12 RST GND 5 11 VDD VBATTERY AFC VDD 2.7 to 3.6 V 2R01 k 1C u2F GPANDD 434 GND VDD XTL1 XTL2 22C 1nF 6 7 8 9 0 1 AFC X1 (16 MHz) Figure 2. Si4311 FSK 433.92 MHz Application Schematic 2.1. Typical Application Bill of Materials Table 7. Si4311 Typical Application Bill of Materials Component(s) Value/Description Supplier(s) C1 Supply bypass capacitor, 22nF, 20%, Z5U/X7R Murata C2 Time constant capacitor, 1µF Murata C3 Antenna matching capacitor, 15pF Murata L1 Antenna matching inductor, Murata 33nH for 433.92MHz and 62nH for 315MHz R1 Time constant resistor, 20k Murata X1 16MHz crystal Hosonic U1 Si4311 315/433.92MHz FSK receiver Silicon Laboratories 8 Rev. 0.5

Si4311 3. Functional Description 3.1. Overview Si4311 Antenna ADC DOUT RX_IN LNA PGA DSP MCU AFC ADC BASEBAND 315/434 AGC PROCESSOR DEV[1:0] SQUELCH BT[1:0] 2.7 –3.6 V VDD XTAL GND LDO AFC OSC RST 16 MHz Figure 3. Functional Block Diagram The Si4311 is a fully-integrated FSK CMOS RF receiver 3.2. Receiver Description that operates in the unlicensed 315 and 433.92MHz The RF input signal is amplified by a low-noise amplifier ultra high frequency (UHF) bands. It is designed for (LNA) and down-converts to a low intermediate high-volume, cost-sensitive RF receiver applications. frequency with a quadrature image-reject mixer. The The chip operates at a carrier frequency of 315 or mixer output is amplified by a programmable gain 433.92MHz and supports FSK digital modulation with amplifier (PGA), filtered, and digitized with a high- data rates of up to 10kbps. resolution analog-to-digital converter (ADC). All RF The device leverages Silicon Labs’ patented and proven functions are integrated into the device eliminating any digital low-IF architecture and offers superior sensitivity production alignment issues associated with external and interference rejection. The Si4311 can achieve components, such as SAW and ceramic IF filters. superior sensitivity in the presence of large interference Silicon Labs’ advanced digital low-IF architecture due to its high dynamic range ADCs and digital filters. achieves superior performance by using the DSP to The digital low-IF architecture also enables superior perform channel filtering, demodulation, automatic gain blocking ability and low intermodulation distortion for control (AGC), automatic frequency control (AFC), and robust reception in the presence of wide-band other baseband processing. DSP implementation of the interference. channel filters provides better repeatability and control Digital integration reduces the number of required of the bandwidth and frequency response of the filter external components compared to traditional offerings, compared to analog implementations. No off-chip resulting in a solution that only requires a 16MHz ceramic filters are needed with the Si4311 since all IF crystal and passive components allowing a small and channel filtering is performed in the digital domain. compact printed circuit board (PCB) implementation 3.3. Carrier Frequency Selection area. The high integration of the Si4311 improves the system manufacturing reliability, improves quality, eases The Si4311 can be tuned to either 315 or 433.92MHz design-in, and minimizes costs. by driving Pin 6 (315/434) to VDD or GND. The 315MHz operation is chosen by driving Pin 6 (315/434) to VDD, and 433.92MHz operation is chosen by driving Pin 6 (315/434) to GND. Rev. 0.5 9

Si4311 Table 8. Carrier Frequency Selection Pin 6 (315/434) Frequency [MHz] 0 433.92 1 315 3.4. Bit Time BT[1:0] Selection The Si4311 can operate with data rates of up to 10kbps non-return to zero (NRZ) data or 5kbps Manchester encoded data. However, FSK modulation uses other encoding schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM) in which a bit can be encoded into a pulse with a certain duty cycle or pulse width (see Figure4). Digital Data “1” “0” “1” “1” NRZ Encoding Manchester Encoding PPM 100 us Encoding 1000 us Figure 4. Example Data Waveforms In order to set the data filter bandwidth correctly, the shortest pulse width of the transmitted encoded data should be chosen as the bit time. In the PPM example shown in Figure4, the shortest pulse width is 100µs, so the bit time is chosen as BT=100µs even though the actual data rate is 1kbps (1000µs). After finding BT, Table9 can be used to find the bit settings for pins 14 and 15, BT[1:0]. In this PPM example, BT[1:0] is set as logic BT1=1 and BT0=1 or BT[1:0]=(1,1) since BT=100µs. Table 9. How to Choose BT[1:0] Based on the Bit Time Bit Time [us] BT1 (pin 14) BT0 (pin 15) BT ≥ 1000 0 0 1000< BT ≤ 500 0 1 500 < BT ≤ 200 1 0 200 < BT ≤ 100 1 1 10 Rev. 0.5

Si4311 3.5. Frequency Deviation Selection In order to accommodate wide frequency deviation ranges, the Si4311 FSK receiver uses two input pins, pins 16 and 17, to select a range of frequency deviations as shown in Table10. For example, if the FSK signal has a frequency deviation (F) of 50kHz, then the DEV[1:0]=(0,1) or pin 16=0 and pin 17=1. Table 10. Frequency Deviation Range Settings DEV1 (pin 16) DEV0 (pin 17) Frequency Deviation [kHz] 0 0 1 < ∆F ≤ 30 0 1 ∆ 30 < F ≤ 50 1 0 ∆ 50 < F ≤ 70 1 1 ∆ 70 < F ≤ 90 3.6. Automatic Frequency Centering (AFC) The channel bandwidth directly affects the sensitivity of any wireless receiver. Typical analog FSK receivers use an external ceramic filter with a large bandwidth to accommodate the data rate, frequency deviation, crystal tolerances, and transmit carrier frequency offsets, which leads to unnecessary amounts of noise and lower sensitivity levels. The Si4311 uses a narrow channel bandwidth of 200kHz and automatic frequency centering (AFC) to obtain excellent sensitivity levels (–104dBm at data rate of 5kbps at 315MHz) while still accommodating up to ±200kHz of frequency tracking from its center frequency. IF BW TX OFFSET 100kHz TX OFFSET 100kHz 200kHz (a) (b) (c) Figure 5. (a) Ideal case (b) Scenario with Tx Offset (c) Si4311 AFC Re-Centers IF BW In the ideal case of no transmit carrier frequency errors or receiver frequency errors, both FSK tones for a logic "1" and "0" from the transmitter appear in the receiver IF channel bandwidth as shown in Figure5 (a). However, if the transmitter has a large carrier offset such as shown in Figure5 (b), then only one of the FSK tones falls in the receiver channel bandwidth and thus the receiver produces errors. The standard approach to resolving this problem is to use an IF channel filter that is large enough to accommodate the transmitter frequency error, but this leads to degraded sensitivity. The Si4311 uses AFC to re-center the channel bandwidth about the two FSK tones as shown in Figure5 (c) to maintain excellent sensitivity with a small IF channel filter. The algorithm requires one FSK tone to be in-band and at most three alternating sequences of 0/1 data typically found in a preamble plus 700µs of fixed delay time (approximately 230µs per 0/1 data pair) to re-center the IF bandwidth. Worst case acquisition time is 1.3ms for a data rate of 10kbps. The AFC algorithm includes a 200ms hold time. The device holds the frequency found by the AFC algorithm for a time of 200ms after no RF signal activity before restarting the frequency search. This allows a frequency found in the first packet of transmission to be held for any subsequent retransmissions of packets if the retransmissions occur before 200ms. This hold frequency ensures all bits of the second and subsequent packets are recovered completely. The AFC frequency search resumes after 200ms of no RF signal activity. The AFC algorithm can be disabled by setting the logic level on pin 5 to a logic zero as shown in Table11. Rev. 0.5 11

Si4311 Table 11. AFC Selection Pin 5 Pin 5 AFC 0 Disable 1 Enable 3.7. Low Noise Amplifier Input Circuit Figure2 shows the typical application circuit with 50 matching. Components C3 and L1 are used to transform the input impedance of the LNA. C3 is equal to 15pF and L1 is equal to 33nH at 433.92MHz and 62nH at 315MHz for 50 matching. 3.8. Crystal Oscillator An on-board crystal oscillator is used to generate a 16MHz reference clock for the Si4311. This reference frequency is required for proper operation of the Si4311 and is used for calibration of the on-chip VCO and other timing references. No external load capacitors are required to set the 16MHz reference frequency if the recommended crystal load capacitor is around 14pF, assuming the effective board capacitance between pins XTL1 and XTL2 is 3pF and the chip input capacitance on pins XTL1 or XTL2 is 11pF. Refer to Table6, “Crystal Characteristics,” on page7 for board capacitance and frequency tolerance information. The frequency tolerance of the crystal should be chosen such that the received signal is within the IF bandwidth of the Si4311 receiver. Additionally, the Si4311 can be driven by an external 16MHz reference clock. The clock signal can be applied to either the XTL1 or XTL2 inputs. When the 16MHz reference clock is applied to one of the inputs, the other crystal input pin must be floating. 3.9. Reset Pin Driving the RST pin (pin 4) low will disable the Si4311 and place the device into reset mode. All active blocks in the device are powered off in this mode, bringing the current consumption to <10uA. The Si4311 is enabled by driving the RST pin (pin 4) to VDD. Refer to Table 4 "Reset Timing Characteristics" for the reset timing requirements. The chip requires about 320ms to go from reset to active mode. The Si4311 can output invalid data during the 320ms turn-on time. 12 Rev. 0.5

Si4311 4. Pin Descriptions: Si4311-B10-GM 0 1 V V C C C E E N N N D D VDD 1 20 19 18 17 16 RFGND 2 15 BT0 RX_IN 3 GND 14 BT1 PAD RST 4 13 DOUT AFC 5 12 GND 6 7 8 9 10 11 VDD 4 D D 1 2 3 N D L L 4 T T 5/ G V X X 1 3 Pin Number(s) Name Description 1, 8, 11 VDD Supply voltage, may connect to external battery. 2 RFGND RF ground. Connect to ground plane on PCB. 3 RX_IN RF receiver input. 4 RST Device reset, active low input. 5 AFC AFC selection input pin. 6 315/434 Selectable logic input for 315 or 433.92 MHz operation. 7, 12, GND PAD GND Ground. Connect to ground plane on PCB. 9 XTL1 Crystal input. 10 XTL2 Crystal input. 13 DOUT Data output. 14, 15 BT[1:0] Bit time selection input pins. 16,17 DEV[1:0] Frequency deviation input pins. 18,19,20 NC No connect. Leave floating. Rev. 0.5 13

Si4311 5. Ordering Guide Part Number* Description Package Operating Type Temperature Si4311-B10-GM 315/433.92MHz FSK Receiver QFN –40 to 85°C Pb-free *Note: Add an “(R)” at the end of the device part number to denote tape and reel option. 14 Rev. 0.5

Si4311 6. Package Markings (Top Marks) 6.1. Si4311 Top Mark Figure 6. Si4311 Top Mark Example 6.2. Top Mark Explanation Mark Method: YAG Laser Line 1 Marking: Part Number 11=Si4311 Firmware Revision 10=Firmware Revision 1.0 Line 2 Marking: Die Revision B=Revision B Die TTT = Internal Code Internal tracking code Line 3 Marking: Circle = 0.5mm Diameter Pin 1 Identifier (Bottom-Left Justified) YWW=Date Code Assigned by the Assembly House. Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date. Rev. 0.5 15

Si4311 7. Package Outline: Si4311-B10-GM Figure7 illustrates the package details for the Si4311-B10-GM. Table12 lists the values for the dimensions shown in the illustration. Figure 7. 20-Pin Quad Flat No-Lead (QFN) Table 12. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max Min Nom Max A 0.80 0.85 0.90 f 2.53 BSC A1 0.00 0.02 0.05 L 0.30 0.35 0.40 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 D 3.00 BSC bbb — — 0.05 D2 1.65 1.70 1.75 ccc — — 0.08 e 0.50 BSC ddd — — 0.10 E 3.00 BSC eee — — 0.10 E2 1.65 1.70 1.75 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 16 Rev. 0.5

Si4311 8. PCB Land Pattern: Si4311-B10-GM Figure8 illustrates the PCB land pattern details for the Si4311-B10-GM. Table13 lists the values for the dimensions shown in the illustration. Figure 8. PCB Land Pattern Rev. 0.5 17

Si4311 Table 13. PCB Land Pattern Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max D 2.71 REF GE 2.10 — D2 1.60 1.80 W — 0.34 e 0.50 BSC X — 0.28 E 2.71 REF Y 0.61 REF E2 1.60 1.80 ZE — 3.31 f 2.53 BSC ZD — 3.31 GD 2.10 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification. 3. This land pattern design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a fabrication allowance of 0.05mm. Solder Mask Design 5. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the solder mask and the metal pad is to be 60µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125mm (5mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 1.45x1.45mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. 18 Rev. 0.5

Si4311 DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4  Removed crystal frequency tolerance range from Revision 0.1 to Revision 0.2 Table 6 "Crystal Characteristics".  Maximum data rate changed from 10 to 4 kbps for  Corrected data rates in Section “3.1. Overview”. FSK and from 5 to 2 kbps for OOK with Manchester  Updated text in section “3.4. Bit Time BT[1:0] encoding. Selection” to show FSK receive IF bandwidth  Maximum RF input power changed from 5 to 10 equations. dBm.  Deleted voltage gain text in section “3.7. Low Noise  Changed test conditions for sensitivity Amplifier Input Circuit”. measurements and added the xtal frequency  Removed squelch circuit description in section “3.8. tolerance of 20 ppm. Crystal Oscillator”.  Updated text in section “3. Functional Description”.  Included load capacitance requirement for crystal if  Added Ideal IF Bandwidth equation and description no external capacitors are used in section “3.8. for choosing the IF bandwidth in Section “3.4. Bit Crystal Oscillator”. Time BT[1:0] Selection”.  Added reset to active time in section “3.9. Reset  Updated Table11, “Typical Sensitivity @ 433MHz, Pin”. 2-FSK,” on page11.  Changed ordering guide part number in section “5.  Changed hysteresis level from 1 dB to 6 dB in Ordering Guide”. Section “3.8. Crystal Oscillator”.  Added FSK Automatic Frequency Calibration  Added text in section “3.8. Crystal Oscillator” information regarding the crystal frequency tolerance and IF  Removed OOK feature. Bandwidth choice and sensitivity performance. Revision 0.4 to Revision 0.5 Revision 0.2 to Revision 0.3  Removed IVDD current spec when input=–30dBm  Updated features list from Table 3 "DC Characteristics"  Reduced font size in the test condition section of  Updated sensitivity specs and test conditions in Table 5 "Si4311 Receiver Characteristics" Table 5 "Si4311 Receiver Characteristics"  Added crystal tolerance equation to Table 6 "Crystal  Added AFC hold time description to section “3.6. Characteristics" Automatic Frequency Centering (AFC)”  Updated matching circuit and BOM to section “2.  Added reference clock drive capability to section Test Circuit” and section “2. Typical Application “3.8. Crystal Oscillator” Schematic”  Modified text in Section “3. Functional Description”  Changed bandwidth option in Table 11 "Bandwidth Selection Table Using BW[3:1] Pins" and test mode.  Reset section updated to reflect active blocks are powered off in reset mode. Rev. 0.5 19

Si4311 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 20 Rev. 0.5