OC-3/STS-3 Micrel, Inc. SY69952 CLOCK RECOVERING SY69952 TRANSCEIVER FEATURES DESCRIPTION (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) A complete ATM compatible single chip Transmitter Micrel's SY69952 contains fully integrated transmitter and Receiver and receiver functions designed to provide clock recovery (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Seamless operation with PMC-Sierra PM5345, VLSI and generation for either 51.84Mbit/s OC/STS-1 or VNS67200, IgT WAC-013-B/WAC-413-A and NEC 155.52Mbps OC/STS-3 SONET/SDH (SY69952) and ATM µPD98402 UNI Processors applications. On-chip clock generation is performed by a low-jitter (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Supports clock and data recovery from 51.84Mbps phase-locked loop (PLL) allowing use of 19.44MHz or 155.52Mbps NRZ or NRZI data stream reference for 155.52MHz generation or a 6.48MHz (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) 155.52MHz clock multiplication from 19.44MHz reference for 51.84MHz generation. Clock recovery is source or 51.84MHz clock multiplication from performed by synchronizing the on-chip VCO directly to 6.48MHz source the incoming data stream. (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Line Receiver Inputs: No external buffering needed The SY69952 meets the jitter compliance criteria of (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Differential output buffering Bellcore, ITU/CCITT and ANSI standards. Low jitter is ensured by Micrel's advanced PLL technology and (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Link Status Indication positive ECL (PECL) I/O. (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Loop-back testing Micre's circuit design techniques coupled with (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) 100K ECL compatible I/O ASSET™ bipolar technology result in ultra-fast (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Single +5 volt power supply performance with low noise and low power dissipation. (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Replacement for Cypress CY7B952 (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) The SY69952 complies with Bellcore, ITU/CCITT and ANSI specifications (cid:132)(cid:132)(cid:132)(cid:132)(cid:132) Available in 28-pin SOIC package FUNCTIONAL BLOCK DIAGRAM PLL2+ LOOP PLL2- MODE ROUT+ ROUT- RIN+ RCLK+ RIN- RCLK- RSER+ PLL RSER- CD LFI TOUT+ TSER+ TOUT- TSER- PLL TCLK+ x8 TCLK- REFCLK+ PLL1+ REFCLK- PLL1- ASSET is a trademark of Micrel, Inc. M9999-062805 Rev.: N Amendment: /0 1 hbwhelp@micrel.com or (408) 955-1690 Issue Date: June 2005

Micrel, Inc. SY69952 PACKAGE/ORDERING INFORMATION Ordering Information(1) ROUT+ 1 28 RCLK- ROUT- 2 27 RCLK+ Package Operating Package Lead RIN+ 3 26 RSER- RIN- 4 25 RSER+ Part Number Type Range Marking Finish MODE 5 24 LFI SY69952ZC Z28-1 Commercial SY69952ZC Sn-Pb VC 6 23 VCC CD 7 TOP VIEW 22 VEE SY69952ZH Z28-1 Commercial SY69952ZH with Pb-Free LOOP 8 SOIC 21 VCC Pb-Free bar-line indicator NiPdAu REFCLK- 9 20 TCLK- REFCLK+ 10 19 TCLK+ Notes: TOUT- 11 18 TSER+ 1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC electricals only. TOUT+ 12 17 TSER- A PLL1+ 13 16 PLL2+ PLL1- 14 15 PLL2- 28-Pin SOIC (Z28-1) M9999-062805 2 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 PIN DESCRIPTIONS INPUTS RSER± – Differential PECL Output Recovered Serial Data. These Positive ECL 100K outputs RIN± – Differential PECL Input (+5V referenced) represent the recovered data from the Receive Input. These built-in line receiver inputs are input data stream (RIN±). This recovered data is aligned connected to the differential Receive serial input data stream. with the recovered clock (RCLK±) with a sampling window An internal Receive PLL recovers the embedded clock compatible with most data processing devices. (RCLK±) and data (RSER±) information. The incoming data rate can be within one of two frequency ranges depending RCLK± – Differential PECL Output on the state of the MODE pin. Recovered Clock. These Positive ECL 100K outputs (+5V referenced) represent the recovered clock from the input CD – PECL/TTL Input data stream (RIN±). This recovered clock is used to sample Carrier Detect. This input controls the recovery function the recovered data (RSER±) and has timing compatible of the Receive PLL and can be driven by the carrier detect with most data processing devices. output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the LFI – TTL Output input data stream (RIN±) is recovered normally by the Link Fault Indicator. This input indicates the status of the Receive PLL. When this input is at an ECL LOW, the input data stream (RIN±). It is controlled by three functions; Receive PLL no longer aligns to RIN±, but instead aligns the Carrier Detect (CD) input, the internal Transition Detector, with the REFCLKx8 frequency. Also, the Link Fault Indicator and the Out of Lock (OOL) detector. The Transition Detector (LFI) will transition LOW, and the recovered data outputs determines if RIN± contains enough transitions to be (RSER) will remain LOW regardless of the signal level on accurately recovered by the Receive PLL. The Out of Lock the Receive data stream inputs (RIN). When the CD input detector determines if RIN± is within the frequency range of is at a TTL LOW (-0.8V), the internal transition detection the Receive PLL. When CD is HIGH and RIN± has sufficient circuitry is disabled. transitions and is within the frequency range of the Receive PLL, the LFI input will be high. If CD is at an ECL LOW or TSER± – Differential PECL Input RIN± does not contain sufficient transitions or RIN± is outside Transmit Serial Data. These built-in line receiver inputs the frequency range of the Receive PLL then the LFI output are connected to the differential Transmit serial input data will be LOW. If CD is at a TTL LOW then the LFI output will stream. These inputs can receive very low amplitude signals only transition LOW when the frequency of RIN± is outside and are compatible with all PECL signal levels. the range of the Receive PLL. REFCLK± – Differential PECL/TTL Input TOUT± – Differential PECL Output Reference Clock. This input is the clock frequency Transmit Output. These Positive ECL 100K outputs (+5V reference for the clock and data recovery Receive PLL. referenced) represent the buffered version of the Transmit REFCLK is multiplied internally by eight and sets the data stream (TSER±). This Transmit path is used to take approximate center frequency for the internal Receive PLL weak input signals and rebuffer them to drive low impedance to track the incoming bit stream. This input is also multiplied copper media. by eight by the frequency multiplier Transmit PLL to produce the bit rate Transmit Clock (TCLK±). REFCLK can be TCLK± – Differential PECL Output connected to either a differential PECL or single-ended TTL Transmit Clock. These Positive ECL 100K outputs (+5V frequency source. When either REFCLK+ or REFCLK- is at referenced) provide the bit rate frequency source for external a TTL LOW, the opposite REFCLK signal becomes a TTL Transmit data processing devices. This output is synthesized level input. by the Transmit PLL and is derived by multiplying the REFCLK frequency by eight. OUTPUTS LOOP – TTL Input ROUT± – Differential PECL Output Loop Back Select. This input is used to select the input Receive Output. These Positive ECL 100K outputs (+5V data stream source that the Receive PLL used for clock referenced) represent the buffered version of the input data and data recovery. When the LOOP input is HIGH, the stream (RIN±). This output pair can be used for Receiver Receive input data stream (RIN±) is used for clock and input data equalization in copper based systems, reducing data recovery. When LOOP is LOW, the Transmit input the system impact of data dependent jitter. All PECL outputs data stream (TSER±) is used by the Receive PLL for clock can be powered down by connecting both outputs to VCC and data recovery. or leaving them both unconnected. M9999-062805 3 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 PIN DESCRIPTIONS MODE – 3 Level Input PLL1±, PLL2± – Loop Filter Inputs Frequency Mode Select. This three-level input selects These pins are used to connect the external loop filters the frequency range for the clock and data recovery receive for the two on-board PLLs. See below: PLL and the frequency multiplier transmit PLL. When the input is held PECL HIGH (VCC –0.9 typ.), the two PLLs operate at the SONET (SDH) STS-3 (STM-1) line rate of 155.52MHz. When this input is held TTL LOW (connected to GND), the two PLLs operate at one SONET STS-1 line rate of 51.84MHz. The REFCLK± frequency in both operating modes is 1/8 of the operating frequency. When the MODE input is ECL LOW (VCC – 1.7 typ), the device enters into test mode, the TSER± inputs substitue for the internal PLL VCO for use in factory testing. Figure 1. Suggested Loop Filter Values DESCRIPTION General lowest operating range of the device is selected. A 6.48MHz The SY69952 Serial SONET/SDH Transceiver is used in ± 1% source must drive the REFCLK inputs and the two SONET/SDH and ATM applications to recover clock and PLLs will multiply this rate by 8 to provide output clocks that data information from a 155.52MHz or 51.84MHz NRZ (Non operate at 51.84MHz ± 1%. Return to Zero) or NRZI (Non Return to Zero Invert on ones) serial data stream. This device also provides a bit- Transmit Functions rate Transmit clock, from a byte rate source through the The transmit section of the SY69952 contains a PLL that use of a frequency multiplier PLL, and differential data takes a REFCLK input and multiplies it by 8 (REFCLKx8) to buffering for the Transmit side of the system. This device is produce a PECL (Positive ECL) differential output clock compliant with all relevant SONET/SDH specifications (TCLK±). The transmitter has two operating ranges that are including ANSI T1X1.6/91-022, ANSI T1X1.3/93-006R1 Draft selectable with the three-level MODE pin as explained and ITU/CCITT G958. above. The SY69952 Transmit frequency multiplier PLL allows low-cost byte rate clock sources to be used to time Operating Frequency the upstream serial data transmitter. The SY69952 operates at either of two frequency ranges. The REFCLK± input can be configured three ways. When The MODE input selects which of the two frequency ranges both REFCLK+ and REFCLK- are connected to a differential the Transmit frequency multiplier PLL and the Receive clock 100K-compatible PECL source, the REFCLK input will and data recovery PLL will operate. When MODE is behave as a differential PECL input. When either the connected to VCC, the highest operating range of the device REFCLK+ or the REFCLK- input is at a TTL LOW, the is selected. A 19.44MHz ± 1% source must drive the other REFCLK input becomes a TTL-level input allowing it REFCLK input and the two PLLs will multiply this rate by 8 to be connected to a low-cost TTL crystal oscillator. The to provide output clocks that operate at 155.52MHz ± 1%. REFCLK input structure, therefore, can be used as a When the MODE input is connected to ground (GND), the differential PECL input, a single TTL input, or as a dual TTL clock multiplexing input. M9999-062805 4 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 DESCRIPTION The Transmit PECL differential input pair (TSER±) is with the REFCLKx8 frequency and the recovered data buffered by the SY69952 yielding the differential data outputs outputs (RSER) will remain LOW regardless of the signal (TOUT±). These outputs can be used to directly drive level on the Receive data-stream inputs (RIN). transmission media such as Printed Circuit Board (PCB) In addition, the SY69952 has a built-in transitions detector traces, optical drivers, twisted pair, or coaxial cable. that also checks the quality of the incoming data stream. The absence of data transitions can be caused by a broken Receive Functions transmission media, a broken transmitter, or a problem with The primary function of the receiver is to recover clock the transmit or receive media coupling. The SY69952 will (RCLK±) and data (RSER±) from the incoming differential detect a quiet link by counting the number of bit times that PECL data stream (RIN±) without the need for external have passed without a data transition. A bit time is defined buffering. These built-in line receiver inputs, as well as the as the period of RCLK±. When 512 bit times have passed TSER± inputs mentioned above, have a wide common- without a data transition on RIN±, LFI will transition LOW. mode range (2.5V) and the ability to receive signals with as The receiver will assume that the serial data stream is invalid little as 50mV differential voltage. They are compatible with and, instead of allowing the RCLK± frequency to wander in all PECL signals and any copper media. the absence of data, the PLL will lock to the REFCLKx8 The clock recovery function is performed using an frequency. This will insure that RCLK± is as close to the embedded PLL. The recovered clock is not only passed to correct link operating frequency as the REFCLK accuracy. the RCLK± outputs, but also used internally to sample the LFI will be driven HIGH again and the receiver will recover input serial stream in order to recover the data pattern. The clock and data from the incoming data stream when the Receive PLL uses the REFCLK input as a byte-rate transition detection circuitry determines that adequate reference. This input is multiplied by 8 (REFCLKx8) and is transitions to ensure reliable clock and data recovery have used to improve PLL lock time and to provide a center been detected within 512 bit-times. frequency for operation in the absence of input data stream The Transition Detector can be turned off by pulling the transitions. The receiver can recover clock and data in two CD input to a TTL LOW (-0.8V). When CD is pulled to a different frequency ranges depending on the state of the TTL LOW the LFI will only be driven LOW if the recovered MODE pin as explained earlier. To insure accurate data clock is not locked to the incoming data stream. LFI LOW in and clock recovery, REFCLKx8 must be within 1000 ppm of this will only indicate that the Receiver PLL is Out of Lock the transmit bit rate. The standards, however, specify that (OOL). The CD pin should not be left unconnected. the REFCLKx8 frequency accuracy be within 20-100 ppm. The differential input serial data (RIN±) is not only used Loop Back Testing by the PLL to recover the clock and data, but it is also The TTL level LOOP pin is used to perform loop-back buffered and presented as the PECL differential output pair testing. When LOOP is asserted (held LOW) the Transmitter ROUT±. This output pair can be used as part of the serial input (TSER±) is used by the Receiver PLL for clock transmission line interface circuit for base line wander and data recovery. This allows in-system testing to be compensation, improving system performance by providing performed on the entire device except for the differential reduced input jitter and increased data eye opening. Transmit drivers (TOUT±) and the differential Receiver inputs (RIN±). For example, an ATM controller can present ATM Carrier Detect and Link Fault Indicator Functions cells to the input of the ATM cell processor and check to The Link Fault Indicator (LFI) output is a TTL-level output see that these same cells are received. When the LOOP that indicates the status of the receiver. This output can input is deasserted (held HIGH) the Receive PLL is once used by an external controller for Loss of Signal (LOS), again connected to the Receiver serial inputs (RIN±). Loss of Frame (LOF), or Out of Frame (OOF) indications. The LOOP feature can also be used in applications where LFI is controlled by the Carrier Detect input, the internal clock and data recovery are to be performed from either of Transitions Detector, and the PLL Out of Lock (OOL) two data streams. In these systems the LOOP pin is used circuitry. to select whether the TSER± or the RIN± inputs are used The CD input may be driven by external circuitry that is by the Receive PLL for clock and data recovery. In the monitoring the incoming data stream. Optical modules have Loop back testing mode, regardless of the presence of data CD outputs that indicate the presence of light on the optical at the input (RIN±), the transmit serial data stream from fiber and some copper based systems use external threshold (TSER±) will flow through the Receive PLL to the Recovered serial data output (RSER±). detection circuitry to monitor the incoming data stream. The CD input is a 100K PECL compatible signal that should be held HIGH when the incoming data stream is valid. When CD is pulled to a PECL LOW (-2.5V max.), the LFI output will transition LOW and the Receiver PLL will align itself M9999-062805 5 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Rating Unit VCC, TVCC, AVCC Power Supply (GND, TGND, AGND = 0V) 0 to +7 V VI Input Voltage (GND, TGND, AGND = 0V) 0 to VCC V IOUT Output Current Continuous 50 mA Surge 100 TA Ambient Temperature Range 0 to +85 °C Tstore Storage Temperature Range -65 to +150 °C NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. PECL DC ELECTRICAL CHARACTERISTICS VCC = TVCC = AVCC = 4.75V to 5.25V; GND, TGND, AGND = 0V, TA = 0°C to +85°C(1) TA = 0°C to 85°C Symbol Parameter Min. Typ. Max. Unit VOH Output HIGH Voltage VCC –1.075 VCC –.955 VCC –.830 V VOL Output LOW Voltage VCC –1.860 VCC –1.705 VCC –1.570 V VIH Input HIGH Voltage(2) VCC –1.165 — VCC –.880 V VIL Input LOW Voltage(2) VCC –1.810 — VCC –1.475 V IIL Input LOW Current 0.5 — — µA NOTES: 1. Equilibrium temperature 2. Forcing one input at a time. Apply VIH (max) or VIL (min) to all other inputs. TTL DC ELECTRICAL CHARACTERISTICS VCC = TVCC = AVCC = 4.75V to 5.25V; GND, TGND, AGND = 0V, TA = 0°C to +85°C Symbol Parameter Min. Max. Unit Condition VOH Output HIGH Voltage 2.4 — V IOH = –2mA VOL Output LOW Voltage — 0.45 V IOL = 4mA IOS Output Short Circuit Current –150 –60 mA VOUT = 0V VIH Input HIGH Voltage 2.0 — V — VIL Input LOW Voltage — 0.8 V — DCD ECL EELCETCRTICRAICLA CLH CAHRAARCATCETREISRTISICTSIC(1S), —(2) ,T (3T)L VCC = +5V ±5%; VEE = GND = 0V, TA = 0°C to +85°C Symbol Parameter Min. Typ. Max. Unit Condition IEE Internal Operating Current — 140 200 mA IOUT Termination Output Current — 11 — mA 50Ω to Vcc -2, 50% duty cycle NOTES: 1. To calculate total power supply current into the VCC pins: ICC = (n * IOUT); where n = number of ECL output pins used (ie, terminated). 2. To calculate total device power dissipation; PD = [IEE * (VCC - VEE)] + [n * IOUT * 1.33](3). 3. Average ECL output voltage is calculated as VOAVG = (VOH(max) + VOH(min) + VOL(max) + VOL(min)) /4 = 1.33V. M9999-062805 6 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 AC ELECTRICAL CHARACTERISTICS VCC = +5V ±5%; VEE = GND = 0V, TA = 0°C to +85°C Symbol Parameter Min. Typ. Max. Units Condition fREF Reference Frequency 6.41 6.48 6.55 MHz MODE = 0 19.24 19.44 19.64 MHZ MODE = 1 fB Bit Time(1) 19.5 19.3 19.1 ns MODE = 0 6.50 6.43 6.36 ns MODE = 1 tODC Output Duty Cycle(2) 48 — 52 % (TCLK±, RCLK±) tRF ECL Output Rise/Fall Tiime(2) 0.4 — 1.2 ns 5pf load, 50Ω to VCC –2 (20% to 80%) tLOCK PLL Lock Time(2) — — 1 µs RIN transition density 25% tRPWH REFCLK Pulse Width High 3.3 — — ns MODE = 0 10 — — ns MODE = 1 tRPWL REFCLK Pulse Width Low 3.3 — — ns MODE = 0 10 — — ns MODE = 1 tDV Data Valid 3 — — ns Prior to RCLK+ rising edge tDH Data Hold 1 — — ns After RCLK+ rising edge tPD Propagation Delay(3) — — 10 ns (RIN to ROUT, TSER to TOUT) NOTES: 1. fB is calculated as 1/(fREF * 8). 2. Tested initially and after any design or process changes that may affect these parameters. 3. The ECL switching threshold is the differential zero crossing (ie, the point where + and – signals cross). TIMING WAVEFORMS M9999-062805 7 hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. SY69952 28 LEAD SOIC .300" WIDE (Z28-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-062805 8 hbwhelp@micrel.com or (408) 955-1690

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