Cover TBD • intel ® Quartus prime ® Design software

Fastest Path to intel Quartus Your Design Prime soFtware eDitions The Intel® Quartus® Prime software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a fast path to convert your concept into reality. The Intel Quartus Prime software can easily adapt to your specific The Intel Quartus Prime software is available in three editions needs in all phases of FPGA, CPLD, and SoC design in different based on your design requirements: Pro, Standard, and Lite platforms. Edition. The Intel Quartus Prime software provides everything you need • Intel Quartus Prime Pro Editon–The Intel Quartus Prime Pro to design with Intel FPGAs. Key tools and features include: Edition software is optimized to support the advanced features • Platform Designer in Intel’s next-generation FPGAs and SoCs with the Intel • Interface Planner Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 GX device family. • Intel HLS Compiler • Intel Quartus Prime Standard Edition–The Intel Quartus Prime • Power Analyzer Standard Edition software includes extensive support for • Timing Analyzer earlier device families in addition to the Intel Cyclone 10 LP • DSP Builder for Intel FPGAs device family. • ModelSim*-Intel FPGA • Intel Quartus Prime Lite Edition–The Intel Quartus Prime Lite Edition software provides an ideal entry point to Intel’s high-volume device families and is available as a free download with no license file required. Intel Quartus Prime Software Key Benefits Industry-Leading Compile Time Improved Accelerated Design Time to Market Productivity Fewer Design Iterations 1

Features Partial Reconfiguration Incremental Optimization Reduces Full Design Iterations Partial reconfiguration of the FPGA offers several benefits and enables new applications. The Intel Quartus Prime Pro Edition software features an intuitive flow with graphical user interface The incremental capability optimizations in the Intel Quartus support for partial reconfiguration of Intel Arria 10 FPGAs and Prime Pro Edition software offers a faster methodology to SoCs. Designers can visually optimize the floorplan of the converge to design sign-off. The Intel Quartus Prime Pro Edition dynamic region that needs to be reconfigured in the chip software boosts the incremental optimization capability with an planner. Constraints can be easily assigned using the Logic Lock early placement stage. This stage, in addition to the I/O and Region feature in the Intel Quartus Prime Pro Edition software. HSSI placement, logic placement, routing, and post-route optimizations offers a more granular convergence to design The key benefits of partial reconfiguration are: closure. • Lower cost • Smaller board footprint Intel® Quartus® Prime Pro Edition Design Flow • Lower power Synthesis Runtime = Block-Based Design I/O and HSSI Placement Fraction of Early Place Full Iteration The Intel Quartus Prime Pro Edition design software offers Timing Runtime block-based design flows. They are of two types- the Analysis Early Placement Correlates Incremental Block-Based Compilation and Design Block Reuse to Final flows, which allow your geographically diverse development Timing Results Logic Placement team to collaborate on a design. Create the project Timing Analysis Routing Iterations Plan design periphery Post-Route Optimizations Define and create all partitions Timing Sign-Off Compile the design Analyze Assembler No Meets Modify Requirements Yes Preserve No Complete Yes Implement Intel Quartus Prime Brochure 2

PlatForm Designer (FormerlY QsYs) Platform Designer (Pro Edition) is the next-generation system integration tool in the Intel Quartus Prime Pro Edition software and builds on the capabilities of Platform Designer (Standard Edition), which is supported in the Intel Quartus Prime Standard Edition software. Both the Platform Designer (Standard and Pro Editions) save significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The new Platform Designer (Pro Edition) tool also supports a variety of design entry methods, such as register transfer level (RTL), block-based design entry, to schematic entry, and black boxes. Hierarchical Framework Platform Designer (formerly Qsys) Pro Edition DESIGN REUSE STANDARD INTERCONNECTS AXI*, AHB*, APB* Multiple Sources RTL IP Intel® FPGA Avalon® Interfaces “Black Box” Library OpenCLTM Kernel IP-XACT Design Descriptors DSP Builder for Intel FPGAs Subsystem 3

interFace Planner The Interface Planner explores a device’s peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legal checks in real time. This flow eliminates complex error messages and the need to wait for a full compile, thereby speeding up your I/O design by 10X. † Intel Quartus Prime Brochure 4

intel hls Power analYzer comPiler Power analysis technology features Excel-based early power estimators (EPE) and the power analyzer tool in the Intel Quartus Prime software. These power analysis tools give you the ability to estimate power consumption from early design Intel HLS Compiler is a high-level synthesis (HLS) tool that takes concept through design implementation. in untimed C++ as input and generates production-quality register transfer level (RTL) that is optimized for Intel FPGAs. Figure 1 shows the Intel HLS Compiler tool flow, which enables an accelerated time for development that rivals hand-coded Speed  Design RTL. Creating FPGA accelerators can be cumbersome if Constraints Area  Entry customers wish to stick to traditional RTL flows. Therefore, we Power  developed the Intel HLS Compiler tool. It is great for those who have already mastered the back-end flow, from high-level design to bit stream to run on the FPGA. Our high-level Synthesis synthesis compiler allows you to generate RTL codes that can be loaded onto the Platform Designer (formerly Qsys) using C++. Placement and Routing Power Analyzer Algorithms Optimize Power  HLS Functional C++ Libraries Iterations (Planned) Intel Power-Optimized Design  FPGA Architectural Intel® Iterations HLS Compiler Platform Designer Intel (formerly Qsys) FPGA IP timing analYzer Intel Quartus® Prime Software This is the second generation, easy-to-use timing analyzer that leverages industry-standard Synopsys* Design Constraints (SDC) support to achieve accurate timing, resulting in faster timing closure. 5

DsP BuilDer For moDelsim-intel intel FPgas FPga eDition soFtware The DSP Builder for Intel FPGAs software generates HDL for digital signal processing (DSP) algorithms in model-based design flow. The DSP Builder for Intel FPGAs software integrates the algorithm development, simulation, and verification capabilities of MathWorks* MATLAB* and Simulink The ModelSim-Intel FPGA Edition software is a version of the system-level design tools with the Intel Quartus Prime design ModelSim software licensed from Mentor Graphics* targeted for software. You can shorten DSP design cycles by creating the Intel devices. The software supports Intel FPGA gate-level hardware representation of a DSP design in an simulation libraries and includes behavioral simulation, HDL algorithm-friendly development environment. The DSP Builder testbenches, and Tcl scripting. The ModelSim-Intel FPGA Edition for Intel FPGAs software consists of Standard Blockset and software supports dual-language simulation. This includes Advanced Blockset. The Advanced Blockset version is designs that are written in a combination of Verilog, recommended for new designs. SystemVerilog, and VHDL languages, also known as mixed HDL. Features: Both the ModelSim-Intel FPGA Edition software and ModelSim-Intel FPGA Starter Edition software are available for • Provides superior fixed-point and IEEE 754 single-precision, all versions of the Intel Quartus Prime software. The floating-point DSP implementation with vector processing ModelSim-Intel FPGA Starter Edition software is the same as the • Offers bit-accurate and cycle-accurate simulation models ModelSim-Intel FPGA Edition software except for the following • Performs automatic generation of VHDL test benches areas: • Facilitates integration of complex DSP functions • The ModelSim-Intel FPGA Edition software is licensed • The ModelSim-Intel FPGA Starter Edition software simulation performance is lower than that of ModelSim-Intel FPGA Use Edition, and has a line limit of 10,000 executable lines MATLAB* or Simulink to Design Algorithm compared to an unlimited number of lines allowed in the ModelSim-Intel FPGA Edition software Add Functions DSP in the DSP Builder for Libraries Intel® FPGAs Perform Synthesis, Place-and-Route (Intel Quartus® Prime Software) Evaluate Hardware in a DSP Development Kit Intel Quartus Prime Brochure 6

intel Quartus Prime www.intel.com/quartus Design soFtware The Intel Quartus Prime software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest path to convert your concept into reality. The Intel Quartus Prime software also supports many third-party tools for synthesis, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. AVAILABILITY PRO EDITION STANDARD EDITION LITE EDITION INTEL QUARTUS PRIME DESIGN SOFTWARE V18.1 ($) ($) (FREE) IV, V  Stratix series 10  II 1 Arria series II, V  Device Support 10   IV, V   Cyclone series 10 LP   10 GX 2 MAX series   Partial reconfiguration  3 Rapid recompile  4 Design Flow Block-based design  Incremental optimization  Available for IP Base Suite   purchase Intel HLS Compiler    Platform Designer (Standard)   Platform Designer (Pro)  Design Partition Planner   Design Entry/Planning Chip Planner    Interface Planner  Logic Lock regions   VHDL    Verilog    SystemVerilog  5 5 VHDL-2008  ModelSim-Intel FPGA Starter Edition software    Functional Simulation ModelSim-Intel FPGA Edition software 6 6 6 Fitter (Place and Route)    Early placement  Compilation Register retiming   (Synthesis & Place and Route) Fractal synthesis  Multiprocessor support   Timing Analyzer    Timing and Power Verification Design Space Explorer II    Power Analyzer    Signal Tap Logic Analyzer    In-System Debug Transceiver toolkit   Intel Advanced Link Analyzer   Operating System (OS) Support Windows*/Linux* 64 bit support    Buy Buy Price Fixed - $3,995 Fixed - $2,995 Free Float - $4,995 Float - $3,995 Download Download Now Download Now Download Now Notes: 1. The only Arria II FPGA supported is the EP2AGX45 device. 2. The Intel Cyclone 10 GX device support is available for free in the Pro Edition software. 3. Available for Cyclone V and Stratix V devices only and requires a partial reconfiguration license. 4. Available for Stratix V, Arria V, and Cyclone V devices. 5. Limited language support. 6. Requires an additional license. 7

ADDITIONAL DEVELOPMENT TOOLS TOOLS DESCRIPTION • No additional licenses are required. • Supported with the Intel Quartus Prime Pro/Standard Edition software. Intel FPGA SDK for OpenCLTM • The software installation file includes the Intel Quartus Prime Pro/Standard Edition software and the OpenCL software. • Additional licenses are required. • DSP Builder for Intel FPGAs (Advanced Blockset only) is supported with the Intel Quartus Prime Pro Edition DSP Builder for Intel FPGAs software for Intel Stratix 10 and Intel Arria 10 devices. • DSP Builder for Intel FPGAs (Standard Blockset and Advanced Blockset) is supported with the Intel Quartus Prime Standard Edition software for Intel Arria 10, Stratix V, Arria V, and Cyclone V devices. • No additional licenses are required. Nios® II Embedded Design Suite • Supported with all editions of the Intel Quartus Prime software. • Includes Nios II software development tools and libraries. • Requires additional licenses for ARM Development Studio 5* (DS-5*) Intel SoC FPGA Edition. Intel SoC FPGA Embedded • The SoC EDS Standard Edition is supported with the Intel Quartus Prime Lite/Standard Edition software and Development Suite (SoC EDS) the SoC EDS Pro Edition is supported with the Intel Quartus Prime Pro Edition software. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. INTEL QUARTUS PRIME DESIGN SOFTWARE FEATURES SUMMARY Interface Planner Enables you to quickly create your I/O design using real time legality checks. Pin planner Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs. Automates system development by integrating IP functions and subsystems (collection of IP functions) using a Platform Designer hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture. Off-the-shelf IP cores Lets you construct your system-level design using IP cores from Intel and from Intel’s third-party IP partners. Synthesis Provides expanded language support for System Verilog and VHDL 2008. Scripting support Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design. Maximizes your productivity by reducing your compilation time (for a small design change after a full Rapid recompile compile). Improves design timing preservation. Offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer Incremental optimization stages for more control over the design flow. Creates a physical region on the FPGA that can be reconfigured to execute different functions. Synthesize, place, Partial reconfiguration route, close timing, and generate configuration bitstreams for the functions implemented in the region. Block-based design flows Provides flexibility of reusing timing-closed modules or design blocks across projects and teams. Intel Hyperflex FPGA Architecture Provides increased core performance and power efficiency for Intel Stratix 10 devices. Physical synthesis Uses post placement and routing delay knowledge of a design to improve performance. Increases performance by automatically iterating through combinations of Intel Quartus Prime software settings Design space explorer (DSE) to find optimal results. Extensive cross-probing Provides support for cross-probing between verification tools and design source files. Optimization advisors Provides design-specific advice to improve performance, resource usage, and power consumption. Reduces verification time while maintaining timing closure by enabling small, post-placement and routing Chip planner design changes to be implemented in minutes. Provides native Synopsys* Design Constraint (SDC) support and allowing you to create, manage, and analyze Timing Analyzer complex timing constraints and quickly perform advanced timing verification. Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering Signal Tap logic analyzer1 capabilities available in an embedded logic analyzer. Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to System Console quickly create a GUI to help monitor and send data into your FPGA. Power Analyzer Enables you to analyze and optimize both dynamic and static power consumption accurately. Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level EDA partners simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit www.intel.com/fpgaedapartners. Enables the Intel Quartus Prime software to efficiently pack arithmetic operations in FPGA’s logic resources Fractal synthesis resulting in significantly improved performance. Notes: 1. Available with Talkback feature enabled in the Intel Quartus Prime Lite Edition software. Getting Started Steps Step 1: Download the free Intel Quartus Prime Lite Edition software www.intel.com/quartus Step 2: Get oriented with the Intel Quartus Prime software interactive tutorial After installation, open the interactive tutorial on the welcome screen. Step 3: Sign up for training www.intel.com/fpgatraining Intel Quartus Prime Brochure 8

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. © Intel Corporation. All rights reserved. Intel, the Intel logo, the Intel Inside mark and logo, the Intel. Experience What’s Inside mark and logo, Altera, Arria, Cyclone, Enpirion, Intel Atom, Intel Core, Intel Xeon, MAX, Nios, Quartus and Stratix are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. See Trademarks on intel.com for full list of Intel trademarks. *Other marks and brands may be claimed as the property of others. GB-1001-18.1

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: I ntel: SW-MODELSIM-AE SWR-QUARTUS-SE-FIX SWR-QUARTUS-SE-FLT SWR-MODELSIM-AE SW-QUARTUS-SE- FIX SW-QUARTUS-SE-ADD SW-QUARTUS-SE-FLT SW-QII-SEPARATION SWR-QII-SEPARATION SWR-PE- QRTS-FIX SWR-PE-QRTS-FLT