STW9N150 Ω N-channel 1500 V - 1.8 - 8 A - TO-247 very high voltage PowerMESH™ Power MOSFET Features Type V R I Pw DSS DS(on) D STW9N150 1500 V < 2.5 Ω 8 A 320 W ■ 100% avalanche tested ■ Avalanche ruggedness 3 ■ Gate charge minimized 2 1 ■ Very low intrinsic capacitances TO-247 ■ High speed switching ■ Very low on-resistance Application ■ Switching applications Figure 1. Internal schematic diagram Description Using the well consolidated high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of Power MOSFETs with outstanding performances. The strengthened layout coupled with the company’s proprietary edge termination structure, gives the lowest R per area, unrivalled gate charge and DS(on) switching characteristics. Table 1. Device summary Order code Marking Package Packaging STW9N150 9N150 TO-247 Tube January 2008 Rev 2 1/12 www.st.com 12

Contents STW9N150 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12

STW9N150 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Drain-source voltage (V = 0) 1500 V DS GS V Gate- source voltage ± 30 V GS I Drain current (continuous) at T = 25 °C 8 A D C I Drain current (continuous) at T = 100 °C 5 A D C I (1) Drain current (pulsed) 32 A DM P Total dissipation at T = 25 °C 320 W TOT C Derating factor 2.56 W/°C T Operating junction temperature J -55 to 150 °C T Storage temperature stg 1. Pulse width limited by safe operating area Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 0.39 °C/W Rthj-amb Thermal resistance junction-ambient max 50 °C/W T Maximum lead temperature for soldering purpose 300 °C/W J Table 4. Avalanche characteristics Symbol Parameter Max value Unit Avalanche current, repetitive or not-repetitive I 8 A AR (pulse width limited by T max) J Single pulse avalanche energy E 720 mJ AS (starting T = 25 °C, I = I , V = 50 V) J D AR DD 3/12

Electrical characteristics STW9N150 2 Electrical characteristics (Tcase =25°C unless otherwise specified) Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source V I = 1 mA, V = 0 1500 V (BR)DSS breakdown voltage D GS Zero gate voltage V = Max rating 10 µA I DS DSS drain current (V = 0) V = Max rating, T =125 °C 500 µA GS DS C Gate-body leakage I V = ± 30 V ± 100 nA GSS current (V = 0) GS DS V Gate threshold voltage V = V , I = 250 µA 3 4 5 V GS(th) DS GS D Static drain-source on R V = 10 V, I = 4 A 1.8 2.5 Ω DS(on resistance GS D Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Forward g (1) V = 15 V, I = 4 A 7.5 S fs transconductance DS D Input capacitance C 3255 pF iss Output capacitance C V = 25 V, f = 1 MHz, V = 0 294 pF oss DS GS Reverse transfer C 22.4 pF rss capacitance Equivalent Output C V = 0, V = 0 to 1200 V 118 pF oss eq. capacitance GS DS f=1MHz Gate DC Bias=0 R Gate input resistance Test signal level=20 mV 2.4 Ω g open drain Q Total gate charge V = 1200 V, I = 8 A, 89.3 nC g DD D Q Gate-source charge V = 10 V 15.8 nC gs GS Q Gate-drain charge (see Figure 15) 50.4 nC gd 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 4/12

STW9N150 Electrical characteristics Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max Unit t Turn-on delay time 41 ns d(on) V = 750 V, I = 4 A, t Rise time DD D 14.7 ns r R = 4.7 Ω, V = 10 V t Turn-off-delay time G GS 86 ns d(off) (see Figure 14) t Fall time 52 ns f Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max Unit I Source-drain current 8 A SD I (1) Source-drain current (pulsed) 32 A SDM V (2) Forward on voltage I = 8 A, V = 0 1.6 V SD SD GS t Reverse recovery time I = 8 A, di/dt = 100 A/µs 988 ns rr SD Q Reverse recovery charge V = 60 V 9.5 µC rr DD I Reverse recovery current (see Figure 16) 19.3 A RRM t Reverse recovery time I = 8 A, di/dt = 100 A/µs 884 ns rr SD Q Reverse recovery charge V = 60 V T = 150 °C 8.2 µC rr DD J I Reverse recovery current (see Figure 16) 18.6 A RRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 5/12

Electrical characteristics STW9N150 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BV vs temperature Figure 7. Static drain-source on resistance DSS RDS(on) HV41520 (Ω) 1.9 VGS =10V 1.8 1.7 1.6 1.5 0 1 2 3 4 5 6 ID(A) 6/12

STW9N150 Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations HV41500 V(VGS) VDDID = =182A00V VGS =10V 10 8 6 4 2 0 0 20 40 60 80 100 Qg (nC) Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs vs temperature temperature Figure 12. Source-drain diode forward Figure 13. Maximum avalanche energy vs characteristics temperature HV41480 EAS (mJ) 700 ID = 8A 600 500 400 300 200 100 0 0 25 50 75 100 125 TJ (˚C) 7/12

Test circuits STW9N150 3 Test circuits Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit resistive load Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 8/12

STW9N150 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12

Package mechanical data STW9N150 TO-247 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 0.620 e 5.45 0.214 L 14.20 14.80 0.560 0.582 L1 3.70 4.30 0.14 0.17 L2 18.50 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 5.50 0.216 10/12

STW9N150 Revision history 5 Revision history T able 9. Document revision history Date Revision Changes 24-May-2007 1 First release 04-Jan-2007 2 Document status promoted from preliminary data to datasheet 11/12

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