STR73xFxx ARM7TDMI™ 32-bit MCU with Flash, 3x CAN, 4 UARTs, 20 timers, ADC, 12 comm. interfaces Features ■ Core – ARM7TDMI 32-bit RISC CPU – 32 MIPS @ 36 MHz TQFP100 14 x 14 ■ Memories TQFP144 – Up to 256 Kbytes Flash program memory 20 x 20 (10,000 cycles endurance, data retention LFBGA144 10 x 10 x 1.7 20 years @ 85° C) ■ DMA – 16 Kbytes RAM – 4 DMA controllers with 4 channels each ■ Clock, reset and supply management ■ Timers – 4.5 - 5.5 V application supply and I/Os – Embedded 1.8 V regulator for core supply – 16-bit watchdog timer (WDG) – Embedded oscillator running from external – 6/10 16-bit timers (TIM) each with: 2 input 4-8 MHz crystal or ceramic resonator captures, 2 output compares, PWM and pulse counter modes – Up to 36 MHz CPU frequency with internal PLL – 6 16-bit PWM modules (PWM) – 32 kHz or 2 MHz internal RC oscillator, – 3 16-bit timebase timers with 8-bit software configurable for fast startup and prescalers backup clock ■ 12 communications interfaces – Real-time clock for clock-calendar function – 2 I2C interfaces – Wake-up timer driven by internal RC for – 4 UART asynchronous serial interfaces wake-up from STOP mode – 3 BSPI synchronous serial interfaces – 5 power saving modes: SLOW, WFI, – Up to 3 CAN interfaces (2.0B Active) LPWFI, STOP and HALT modes ■ 10-bit A/D converter ■ Nested interrupt controller – 12/16 channels – Fast interrupt handling with multiple vectors – Conversion time: min. 3 µs, range: 0 to 5V – 64 maskable IRQs with 64 vectors and 16 priority levels ■ Development tools support – 2 maskable FIQ sources – JTAG interface – 16 external interrupts, up to 32 wake-up lines T able 1. Device summary ■ Up to 112 I/O ports Reference Part number – 72/112 multifunctional bidirectional I/Os STR730FZ1, STR730FZ2, STR731FV0, STR731FV1, STR731FV2, STR73xFxx STR735FZ1, STR735FZ2, STR736FV0, STR736FV1, STR736FV2 June 2008 Rev 7 1/52 www.st.com 52

Contents STR73xFxx Contents 1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 STR730F/STR735F (TQFP144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.2 STR730F/STR735F (LFBGA144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.3 STR731F/STR736F (TQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.2 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.4 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.6 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2/52

STR73xFxx Contents 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.1 Low power wait for interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2 PLL free running mode at high temperature . . . . . . . . . . . . . . . . . . . . . . 50 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3/52

Scope STR73xFxx 1 Scope This datasheet provides the STR73x ordering information, mechanical and electrical device characteristics. For complete information on the STR73xF microcontroller memory, registers and peripherals. please refer to the STR73x reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash programming reference manual. For information on the ARM7TDMI core please refer to the ARM7TDMI technical reference manual. 1.1 Description ARM core with embedded Flash & RAM STR73xF family combines the high performance ARM7TDMI™ CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed single voltage Flash memory and high-speed RAM. The STR73xF family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST’s ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu Figure1 shows the general block diagram of the device family. 4/52

STR73xFxx Overview 2 Overview Table 2. P roduct overview Features STR730FZx STR735FZx STR731FVx STR736FVx Flash memory - bytes 128K 256K 128K 256K 64K 128K 256K 64K 128K 256K RAM - bytes 16 K 16 K 10 TIM timers, 112 I/Os, 6 TIM timers, 72 I/Os, 18 wake-up lines, Peripheral functions 32 wake-up lines, 16 ADC 12 ADC channels CAN peripherals 3 0 3 0 Operating voltage 4.5 to 5.5 V Operating temperature -40 to +85°C/-40 to +105° C T=TQFP144 20 x 20 Packages T=TQFP100 14x14 H=LFBGA144 10 x10 Package choice: reduced pin-count TQFP100 or feature-rich 144-pin TQFP or LFBGA The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on each package. The family includes versions with and without CAN. High speed Flash memory The Flash program memory is organized in 32-bit wide memory cells which can be used for storing both code and data constants. It is accessed by CPU with zero wait states @ 36 MHz. The STR7 embedded Flash memory can be programmed using in-circuit programming or in-application programming. The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years @ 85° C. IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: ● Sector write protection ● Flash debug protection (locks JTAG access) Flexible power management To minimize power consumption, you can program the STR73xF to switch to SLOW, WFI LPWFI, STOP or HALT modes depending on the current system activity in the application. 5/52

Overview STR73xFxx Flexible clock control Two clock sources are used to drive the microcontroller, a main clock driven by an external crystal or ceramic resonator and an internal backup RC oscillator that operates at 2 MHz or 32 kHz. The embedded PLL can be configured to generate an internal system clock of up to 36 MHz. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. Voltage regulators The STR73xF requires an external 4.5 to 5.5 V power supply. There are two internal Voltage Regulators for generating the 1.8 V power supply needed by the core and peripherals. The main VR is switched off and the Low Power VR switched on when the application puts the STR73xF in Low Power Wait for Interrupt (LPWFI) mode. Low voltage detectors The voltage regulator and Flash modules each have an embedded LVD that monitors the internal 1.8 V supply. If the voltage drops below a certain threshold, the LVD will reset the STR73xF. Note: An external power-on reset must be provided ensure the microcontroller starts-up correctly. 2.1 On-chip peripherals CAN interfaces The three CAN modules are compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. These are not available in the STR735 and STR736. DMA 4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to peripheral, peripheral to memory and memory to peripheral transfers. The DMA requests are connected to TIM timers, BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be configured to be triggered by a software request, independently from any peripheral activity. 16-bit timers (TIM) Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12 in 100-pin devices) when added with the PWM modules (see next paragraph). PWM modules (PWM) The six 16-bit PWM modules have independently programmable periods and duty-cycles, with 5+3 bit prescaler factor. Timebase timers (TB) The three 16-bit timebase timers with 8-bit prescaler for general purpose time triggering operations. Real-time clock (RTC) The RTC provides a set of continuously running counters driven by separate clock signal derived from the main oscillator. The RTC can be used as a general timebase or 6/52

STR73xFxx Overview clock/calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps running, powered by the low power voltage regulator. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 625 Kbaud. Buffered serial peripheral interfaces (BSPI) Each of the three BSPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 6 Mb/s in master mode and up to 4.5 Mb/s in slave mode (@36 MHz system clock). I2C interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. A/D converter The 10-bit analog to digital converter, converts up to 16 channels in single-shot or continuous conversion modes (12 channels in 100-pin devices). The minimum conversion time is 3 µs. Watchdog The 16-bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O ports Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose input/output or alternate function. External interrupts and wake-up lines 16 external interrupts lines are available for application use. In addition, up to 32 external Wake-up lines (18 in 100-pin devices) can be used as general purpose interrupts or to wake-up the application from STOP mode. 7/52

Block diagram STR73xFxx 3 Block diagram Figure 1. STR730F/STR735F block diagram RSTIN PRCCU/PLL FLASH M0 PROGRAM MEMORY M1 64/128/256K TEST ARM7TDMI CPU JTDI RAM S JTCK U 16K B JTMS E JJTTRDSOT JTAG NATIV APB 7 BRIDGE 0 M V18 R A VDD POWERSUPPLY APB VSS VREG BRIDGE 1 VDDA VSSA AHB BRIDGE AHB BUS DMA0-3 CLOCK MGT (CMU) WATCHDOG XXTTAALL12 OSC RTC I2C0-1 4 AF INTERRUPT CTL (EIC) WAKE-UP/INT (WIU) 32 AF UART0, 1, 2, 3 8 AF 16 AF A/D CONVERTER (ADC) 12 AF TIMER (TIM) 2-4 APB BUS APB BUS TIMEB(TABS)E 0 -T2IMER WAKE-UP TIMER 12 AF BSPI 0-2 (WUT) 6 AF CAN 0-2* TIMER (TIM) 0-1 8 AF 6 AF PWM 0-5 TIMER (TIM) 5-9 20 AF 122 ports GPIO PORTS 0-6 AF:alternatefunctiononI/Oportpin *CAN peripherals not available on STR735F. 8/52

STR73xFxx Block diagram Figure 2. STR731F/STR736 block diagram RSTIN PRCCU/PLL FLASH M0 PROGRAM MEMORY M1 64/128/256K TEST ARM7TDMI CPU JTDI RAM S JTCK U 16K B JTMS E JTJTRDSOT JTAG NATIV APB M7 BRIDGE 0 V18 R A VDD POWERSUPPLY APB VSS VREG BRIDGE 1 VDDA VSSA AHB BRIDGE AHB BUS DMA0-3 CLOCK MGT (CMU) WATCHDOG XXTTAALL12 OSC RTC I2C0-1 4 AF INTERRUPT CTL (EIC) WAKE-UP/INT (WIU) 18 AF 12 AF A/D CONVERTER (ADC) UART0, 1, 2, 3 8 AF 12 AF TIMER (TIM) 2-4 APB BUS APB BUS TIMEB(TABS)E 0 -T2IMER WAKE-UP TIMER 12 AF BSPI 0-2 (WUT) 6 AF CAN 0-2* TIMER (TIM) 0-1 8 AF 6 AF PWM 0-5 TIMER (TIM) 5 4 AF 72 ports GPIO PORTS 0-6 *CAN peripherals not available on STR736F. AF:alternatefunctiononI/Oportpin 9/52

Block diagram STR73xFxx 3.1 Related documentation Available from www.arm.com: ARM7TDMI technical reference manual Available from http://www.st.com: STR73x reference manual (RM0001) STR7 Flash programming reference manual STR73x software library user manual For a list of related application notes refer to http://www.st.com. 10/52

STR73xFxx Block diagram 3.2 Pin description 3.2.1 STR730F/STR735F (TQFP144) Figure 3. STR730F/STR735F pin configuration (top view) P6.15 / WUP9P6.14 / SS0P6.13 / SCK0 / WUP11P6.12 / MOSI0P6.11 / MISO0P6.10 / WUP8P6.9 / TDO0P6.8 / RDI0 / WUP10P6.7 / WUP7P6.6 / WUP6P6.5 / WUP5 P6.4 / TDO3 / WUP4 P6.3 / WUP3P6.2 / RDI3 / WUP2P6.1 / WUP1P6.0 / WUP0 VDDVSSV18P5.15 / INT13 P5.14 / INT12 P5.13 / INT11 P5.12 / INT10 P5.11 / TDO2 / INT9 P5.10 / RDI2 / INT8 P5.9 / INT7P5.8 / INT6 P5.7 / MISO2 P5.6 / MOSI2 P5.5 / SCK2 / WUP23P5.4 / SS2 P5.3 / OCMPB9 P5.2 / OCMPA9 P5.1 / MISO1 P5.0 / MOSI1 P4.15 / SCK1 / WUP22 OCMPB2 / P0.0 1 144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108 P4.14 / SS1 OCMPA2 / P0.1 2 107 P4.13 / ICAPB9 ICAPA2 / P0.2 3 106 P4.12 / ICAPA9 / WUP21 ICAPB2 / P0.3 4 105 P4.11 / OCMPB8 VSS 5 104 P4.10 / ICAPA6 / WUP20 VDD 6 103 P4.9 / ICAPB6 OCMPA5 / P0.4 7 102 P4.8 / OCMPA8 OCMPB5 / P0.5 8 101 P4.7 / SDA1 ICAPA5 / P0.6 9 100 P4.6 / SCL1 / WUP19 ICAPB5 / P0.7 10 99 P4.5 / CAN2RX / WUP18 OCMPA6 / P0.8 11 98 P4.4 / CAN2TX OCMPB6 / P0.9 12 97 P4.3 / ICAPB8 / WUP27 OCMPA7 / P0.10 13 96 P4.2 / ICAPA8 / WUP26 OCMPB7 / P0.11 14 95 P4.1 / ICAPB7 / WUP25 VDD 15 94 P4.0 / ICAPA7 / WUP24 VSS 16 93 VDD ICAPA3 / P0.12 17 92 VSS ICAPB3 / P0.13 18 STR730F/STR735F 91 JTDO OCMPB3 / P0.14 19 90 JTCK OCMPA3 / P0.15 20 89 JTMS OCMPA4 / P1.0 21 88 JTDI OCMPB4 / P1.1 22 87 JTRST ICAPB4 / P1.2 23 86 VSS ICAPA4 / P1.3 24 85 VDD VSS 25 84 P3.15 / AIN15 / INT5 VDD 26 83 P3.14 / AIN14 / INT4 P1.4 27 82 P3.13 / AIN13 / INT3 P1.5 28 81 P3.12 / AIN12 / INT2 OCMPB1 / P1.6 29 80 P3.11 / AIN11 OCMPA1 / P1.7 30 79 P3.10 / AIN10 INT0 / OCMPA0 / P1.8 31 78 P3.9 / AIN9 INT1 / OCMPB0 / P1.9 32 77 P3.8 / AIN8 ICAPB0 / WUP28 / P1.10 33 76 VDDA ICAPA0 / WUP29 / P1.11 34 75 VSSA ICAPA1 / WUP30 / P1.12 35 74 P3.7 / AIN7 ICAPB1 / WUP31 / P1.13 36 73 P3.6 / AIN6 373839404142434445464748495051525354555657585960616263646566676869707172 WUP12 / CAN0RX / P1.14CAN0TX / P1.15PWM0 / P2.0WUP13 / CAN1RX / P2.1CAN1TX / P2.2PWM1 / P2.3PWM2 / P2.4PWM3 / P2.5PWM4 / P2.6PWM5 / P2.7M0RSTINM1VDDVSSXTAL1XTAL2VSSTDO1 / P2.8WUP14 / RDI1 / P2.9WUP16 / P2.10WUP17 / P2.11INT14 / P2.12INT15 / P2.13WUP15 / SCL0 / P2.14SDA0 / P2.15TESTVBIASVSSVDDAIN0 / P3.0AIN1 / P3.1AIN2 / P3.2AIN3 / P3.3AIN4 / P3.4AIN5 / P3.5 Note: CAN alternate functions not available on STR735F. 11/52

Block diagram STR73xFxx 3.2.2 STR730F/STR735F (LFBGA144) Table 3. STR730F/STR735F LFBGA ball connections Ball Name Ball Name Ball Name Ball Name A1 P0.0 / OCMPB2 B1 P0.4 / OCMPA5 C1 P0.5 / OCMPB5 D1 V SS A2 P6.10 / WUP8 B2 P0.1 / OCMPA2 C2 P0.2 / ICAPA2 D2 V DD A3 P6.9 / TDO0 B3 P6.15 / WUP9 C3 P0.3 / ICAPB2 D3 P0.6 / ICAPA5 A4 P6.12 / MOSI0 B4 P6.13 / SCKO / WUP11 C4 P6.14 / SSO D4 P0.7 /ICAPB5 A5 P6.6 / WUP6 B5 P6.7 / WUP7 C5 P6.8 / RDI0 / WUP10 D5 P6.11 / MISO0 A6 V B6 P6.2 / WUP2 / RDI3 C6 P6.3 / WUP3 D6 P6.4 / WUP4 /TDO3 18 A7 P5.15 / INT13 B7 P5.14 / INT12 C7 V D7 VDD SS A8 P5.8 / INT6 B8 P5.9 / INT7 C8 P5.10 / INT8 / RDI2 D8 P5.12 / INT10 A9 P5.2 / OCMPA9 B9 P5.3 / OCMPB9 C9 P5.4 / SS2 D9 P5.5 / SCK2 / WUP23 A10 P5.7 / MISO2 B10 P5.0 / MOSI1 C10 P5.1 / MISO1 D10 P4.13 / ICAPB9 A11 P5.6 / MOSI2 B11 P4.15 / SCK1 / WUP22 C11 P4.14 / SS1 D11 P4.12 / ICAPA9 / WUP21 A12 P5.11 / TDO2 / INT9 B12 P4.8 / OCMPA8 C12 P4.7 / SDA1 D12 P4.11 / OCMPB8 E1 P0.8 / OCMPA6 F1 V G1 V H1 V DD SS DD E2 P0.9 / OCMPB6 F2 P0.13 / ICAPB3 G2 P1.2 / ICAPB4 H2 P1.8 / OCMPA0 / INT0 E3 P0.10 / OCMPA7 F3 P0.14 / OCMPB3 G3 P1.3 / ICAPA4 H3 P1.9 / OCMPB0 / INT1 E4 P0.11 / OCMPB7 F4 P0.15 / OCMPA3 G4 V H4 P1.10 / ICAPB0 / WUP28 SS E5 P0.12 / ICAPA3 F5 P1.0 / OCMPA4 G5 P1.5 H5 XTAL2 E6 P6.5 / WUP5 F6 P1.1 / OCMPB4 G6 P2.11 / WUP17 H6 P2.10 / WUP16 P4.0 / ICAPA7 / E7 P6.0 / WUP0 F7 P6.1 / WUP1 G7 H7 P2.15 / SDA 0 WUP24 E8 P5.13 / INT11 F8 P4.4 / CAN2TX1) G8 VDD H8 JTMS P4.10 / ICAPA6 / P4.3 / ICAPB8 / E9 F9 G9 VSS H9 VSS WUP20 WUP27 P4.2 / ICAPA8 / E10 P4.9 / ICAPB6 F10 G10 JTDO H10 VDD WUP26 P4.1 / ICAPB7 / E11 P4.6 / SCL1 / WUP19 F11 G11 JTCK H11 P3.15 / AIN15 / INT5 WUP25 P4.5 / WUP18 / E12 F12 JTDI G12 nJTRST H12 P3.14 / AIN14 / INT4 CAN2RX1) P1.14 / CAN0RX1) / J1 P1.4 K1 P1.6 / OCMPB1 L1 P1.7 / OCMPA1 M1 WUP12 P1.11 / ICAPA0 / P1.13 / ICAPB1 / J2 K2 L2 P1.15 / CAN0TX1) M2 P2.4 / PWM2 WUP29 WUP31 P1.12 / ICAPA1 / P2.1 / CAN1RX1) / J3 K3 L3 P2.0 / PWM0 M3 P2.5 / PWM3 WUP30 WUP13 J4 P2.7 / PWM5 K4 P2.6 / PWM4 L4 P2.3 / PWM1 M4 P2.2 / CAN1TX1) J5 V K5 M1 L5 RSTIN M5 M0 DD J6 P2.9 / RDI1 / WUP14 K6 P2.8 / TDO1 L6 V M6 V SS SS J7 P2.14 / SCL 0 / WUP15 K7 P2.13 / INT15 L7 P2.12 / INT14 M7 XTAL1 J8 P3.1 / AIN1 K8 P3.0 / AIN0 L8 VBIAS M8 TST J9 P3.13 / AIN13 / INT3 K9 P3.4 / AIN4 L9 P3.3 / AIN3 M9 P3.2 / AIN2 J10 P3.12 / AIN12 / INT2 K10 V L10 P3.5 / AIN5 M10 V DDA SS J11 P3.9 / AIN9 K11 V L11 P3.7 / AIN7 M11 V SSA DD J12 P3.8 / AIN8 K12 P3.11 / AIN11 L12 P3.10 / AIN10 M12 P3.6 / AIN6 Note: CAN alternate functions not available on STR735F. 12/52

STR73xFxx Block diagram 3.2.3 STR731F/STR736F (TQFP100) Figure 4. STR731F/STR736F pin configuration (top view) 1 2 6.14 / SS06.13 / SCK0 / WUP16.12 / MOSI06.11 / MISO06.9 / TDO06.8 / RDI0 / WUP106.6 / WUP66.4 / TDO3 / WUP4 6.2 / RDI3 / WUP26.0 / WUP0 DDSS185.12 / INT10 5.11 / TDO2 / INT9 5.10 / RDI2 / INT8 5.9 / PWM5 / INT75.8 / PWM4 / INT6 5.7 / MISO2 5.6 / MOSI2 5.5 / SCK2 / WUP235.4 / SS2 /PWM35.1 / MISO1 5.0 / MOSI1 4.15 / SCK1 / WUP2 PPPPPPPPPPVVVPPPPPPPPPPPP 00987654321098765432109876 OCMPB2 / P0.0 1 1999999999988888888887777 75 P4.14 / SS1 OCMPA2 / P0.1 2 74 P4.10 / ICAPB5 / WUP20 ICAPA2 / P0.2 3 73 P4.7 / SDA1 ICAPB2 / P0.3 4 72 P4.6 / SCL1 / WUP19 OCMPA5 / P0.4 5 71 VDD OCMPB5 / P0.5 6 70 VSS ICAPA5 / P0.6 7 69 JTDO VDD 8 68 JTCK VSS 9 67 JTMS ICAPA3 / P0.12 10 66 JTDI ICAPB3 / P0.13 11 65 JTRST OCMPB3 / P0.14 12 STR731F/STR736F 64 VSS OOCCMMPPAA34 / /P P01.1.05 1134 6632 VPD3.D15 / AIN11 / INT5 OCMPB4 / P1.1 15 61 P3.14 / AIN10 / INT4 ICAPB4 / P1.2 16 60 P3.13 / AIN9 / INT3 ICAPA4 / P1.3 17 59 P3.12 / AIN8 / INT2 OCMPB1 / P1.6 18 58 P3.11 / AIN7 OCMPA1 / P1.7 19 57 P3.10 / AIN6 INT0 / OCMPA0 / P1.8 20 56 P3.9 / AIN5 INT1 / OCMPB0 / P1.9 21 55 P3.8 / AIN4 ICAPB0 / WUP28 / P1.10 22 54 VDDA ICAPA0 / WUP29 / P1.11 23 53 VSSA ICAPA1 / WUP30 / P1.12 24 52 P3.7 / AIN3 ICAPB1 / WUP31 / P1.13 25 51 P3.6 / AIN2 6789012345678901234567890 2222333333333344444444445 WUP12 / CAN0RX / P1.14CAN0TX / P1.15PWM0 / P2.0WUP13 / CAN1RX / P2.1CAN1TX / P2.2PWM1 / P2.3PWM2 / P2.4M0RSTINM1VDDVSSXTAL1XTAL2VSSCAN2RX / TDO1 / P2.814 / CAN2TX / RDI1 / P2.9WUP15 / SCL0 / P2.14SDA0 / P2.15TESTVBIASVSSVDDAIN0 / P3.4AIN1 / P3.5 P U W Note: CAN alternate functions not available on STR736F. 13/52

Block diagram STR73xFxx Legend / Abbreviations for Table4: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: T = TTL 0.8 V / 2 V with input trigger T C = CMOS 0.3V /0.7V with input trigger T DD DD Port and control configuration: Input: pu/pd = with internal 100 kΩ weak pull-up or pull down Output: OD = open drain (logic level) PP = push-pull Interrupts: INTx = external interrupt line WUPx = wake-up interrupt line The reset state (during and just after the reset) of the I/O ports is input floating (Input tristate TTL mode). To avoid excess power consumption, unused I/O ports must be tied to ground. Table 4. S TR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction 1 A1 1 P0.0/OCMPB2 I/O T 2mA X X Port 0.0 TIM2: output compare B output T 2 B2 2 P0.1/OCMPA2 I/O T 2mA X X Port 0.1 TIM2: output compare A output T 3 C2 3 P0.2/ICAPA2 I/O T 2mA X X Port 0.2 TIM2: input capture A input T 4 C3 4 P0.3/ICAPB2 I/O T 2mA X X Port 0.3 TIM2: input capture B input T 5 D1 V S Ground SS 6 D2 V S Supply voltage (5 V) DD 7 B1 5 P0.4/OCMPA5 I/O T 2mA X X Port 0.4 TIM5: output compare A output T 8 C1 6 P0.5/OCMPB5 I/O T 2mA X X Port 0.5 TIM5: output compare B output T 9 D3 7 P0.6/ICAPA5 I/O T 2mA X X Port 0.6 TIM5: input capture A input T 10 D4 P0.7/ICAPB5 I/O T 2mA X X Port 0.7 TIM5: input capture B input T 11 E1 P0.8/OCMPA6 I/O T 2mA X X Port 0.8 TIM6: output compare A output T 12 E2 P0.9/OCMPB6 I/O T 2mA X X Port 0.9 TIM6: output compare B output T 13 E3 P0.10/OCMPA7 I/O T 2mA X X Port 0.10 TIM7: output compare A output T P0.11/OCMPB 14 E4 I/O T 2mA X X Port 0.11 TIM7: output compare B output 7 T 15 F1 8 V S Supply voltage (5 V) DD 16 G1 9 V S Ground SS 17 E5 10 P0.12/ICAPA3 I/O T 2mA X X Port 0.12 TIM3: input capture A input T 18 F2 11 P0.13/ICAPB3 I/O T 2mA X X Port 0.13 TIM3: input capture B input T 14/52

STR73xFxx Block diagram Table 4. STR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction P0.14/OCMPB 19 F3 12 I/O T 2mA X X Port 0.14 TIM3: output compare B output 3 T 20 F4 13 P0.15/OCMPA3 I/O T 2mA X X Port 0.15 TIM3: output compare A output T 21 F5 14 P1.0/OCMPA4 I/O T 2mA X X Port 1.0 TIM4: output compare A output T 22 F6 15 P1.1/OCMPB4 I/O T 2mA X X Port 1.1 TIM4: output compare B output T 23 G2 16 P1.2/ICAPB4 I/O T 2mA X X Port 1.2 TIM4: input capture B input T 24 G3 17 P1.3/ICAPA4 I/O T 2mA X X Port 1.3 TIM4: input capture A input T 25 G4 V S Ground SS 26 H1 V S Supply voltage (5 V) DD 27 J1 P1.4 I/O T 2mA X X Port 1.4 T 28 G5 P1.5 I/O T 2mA X X Port 1.5 T 29 K1 18 P1.6/OCMPB1 I/O T 2mA X X Port 1.6 TIM1: output compare B output T 30 L1 19 P1.7/OCMPA1 I/O T 2mA X X Port 1.7 TIM1: output compare A output T 31 H2 20 P1.8/OCMPA0 I/O T INT0 2mA X X Port 1.8 TIM0: output compare A output T 32 H3 21 P1.9/OCMPB0 I/O T INT1 2mA X X Port 1.9 TIM0: output compare B output T 33 H4 22 P1.10/ICAPB0 I/O T WUP28 2mA X X Port 1.10 TIM0: input capture B input T 34 J2 23 P1.11/ICAPA0 I/O T WUP29 2mA X X Port 1.11 TIM0: input capture A input T 35 J3 24 P1.12/ICAPA1 I/O T WUP30 2mA X X Port 1.12 TIM1: input capture A input T 36 K2 25 P1.13/ICAPB1 I/O T WUP31 2mA X X Port 1.13 TIM1: input capture B input T 37 M1 26 P1.14/CAN0RX I/O T WUP12 2mA X X Port 1.14 CAN0: receive data input T 38 L2 27 P1.15/CAN0TX I/O T 2mA X X Port 1.15 CAN0: transmit data output T 39 L3 28 P2.0/PWM0 I/O T 2mA X X Port 2.0 PWM0: PWM output T 40 K3 29 P2.1/CAN1RX I/O T WUP13 2mA X X Port 2.1 CAN1: receive data input T 41 M4 30 P2.2/CAN1TX I/O T 2mA X X Port 2.2 CAN1: transmit data output T 42 L4 31 P2.3/PWM1 I/O T 2mA X X Port 2.3 PWM1: PWM output T 43 M2 32 P2.4/PWM2 I/O T 2mA X X Port 2.4 PWM2: PWM output T 44 M3 P2.5/PWM3 I/O T 2mA X X Port 2.5 PWM3: PWM output T 45 K4 P2.6/PWM4 I/O T 2mA X X Port 2.6 PWM4: PWM output T 46 J4 P2.7/PWM5 I/O T 2mA X X Port 2.7 PWM5: PWM output T 47 M5 33 M0 I T pd BOOT: mode selection 0 input T 48 L5 34 RSTIN I C pu Reset input T 49 K5 35 M1 I T pd BOOT: mode selection 1 input T 15/52

Block diagram STR73xFxx Table 4. STR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction 50 J5 36 V S Supply voltage (5 V) DD 51 M6 37 V S Ground SS Oscillator amplifier circuit input and 52 M7 38 XTAL1 I internal clock generator input. 53 H5 39 XTAL2 O Oscillator amplifier circuit output. 54 L6 40 V S Ground SS CAN2: receive UART1: P2.8/TDO1/CA data input 55 K6 41 I/O T 2mA X X Port 2.8 transmit data N2RX T (TQFP100 output only) CAN2: UART1: transmit data P2.9/RDI1/CAN 56 J6 42 I/O T WUP14 2mA X X Port 2.9 receive data output 2TX T input (TQFP100 only) 57 H6 P2.10 I/O T WUP16 2mA X X Port 2.10 T 58 G6 P2.11 I/O T WUP17 2mA X X Port 2.11 T 59 L7 P2.12 I/O T INT14 2mA X X Port 2.12 T 60 K7 P2.13 I/O T INT15 2mA X X Port 2.13 T 61 J7 43 P2.14/SCL0 I/O T WUP15 2mA X X Port 2.14 I2C0: serial clock T 62 H7 44 P2.15/SDA0 I/O T 2mA X X Port 2.15 I2C0: serial data T 63 M8 45 Test I pd Reserved pin. Must be tied to ground Internal RC oscillator bias. A 1.3 MΩ external resistor has to be connected to 64 L8 46 V S BIAS this pin when a 32 kHZ RC oscillator frequency is used. 65 M10 47 V S Ground SS 66 M11 48 V S Supply voltage (5 V) DD 67 K8 P3.0/AIN0 I/O T 2mA X X Port 3.0 ADC: analog input 0 T 68 J8 P3.1/AIN1 I/O T 2mA X X Port 3.1 ADC: analog input 1 T 69 M9 P3.2/AIN2 I/O T 2mA X X Port 3.2 ADC: analog input 2 T 70 L9 P3.3/AIN3 I/O T 2mA X X Port 3.3 ADC: analog input 3 T ADC: analog input 4 71 K9 49 P3.4/AIN4 I/O T 2mA X X Port 3.4 T (AIN0 in TQFP100) ADC: Analog input 5 72 L10 50 P3.5/AIN5 I/O T 2mA X X Port 3.5 T (AIN1 in TQFP100) 16/52

STR73xFxx Block diagram Table 4. STR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction ADC: analog input 6 73 M12 51 P3.6/AIN6 I/O T 2mA X X Port 3.6 T (AIN2 in TQFP100) ADC: analog input 7 74 L11 52 P3.7/AIN7 I/O T 2mA X X Port 3.7 T (AIN3 in TQFP100) 75 K11 53 V S Reference ground for A/D converter SSA 76 K10 54 V S Reference voltage for A/D converter DDA ADC: analog input 8 77 J12 55 P3.8/AIN8 I/O T 2mA X X Port 3.8 T (AIN4 in TQFP100) ADC: analog input 9 78 J11 56 P3.9/AIN9 I/O T 2mA X X Port 3.9 T (AIN5 in TQFP100) ADC: analog input 10 79 L12 57 P3.10/AIN10 I/O T 2mA X X Port 3.10 T (AIN6 in TQFP100) ADC: analog input 11 80 K12 58 P3.11/AIN11 I/O T 2mA X X Port 3.11 T (AIN7 in TQFP100) ADC: analog input 12 81 J10 59 P3.12/AIN12 I/O T INT2 2mA X X Port 3.12 T (AIN8 in TQFP100) ADC: analog input 13 82 J9 60 P3.13/AIN13 I/O T INT3 2mA X X Port 3.13 T (AIN9 in TQFP100) ADC: analog input 14 83 H12 61 P3.14/AIN14 I/O T INT4 2mA X X Port 3.14 T (AIN10 in TQFP100) ADC: analog input 15 84 H11 62 P3.15/AIN15 I/O T INT5 2mA X X Port 3.15 T (AIN11 in TQFP100) 85 H10 63 V S Supply voltage (5 V) DD 86 H9 64 V S Ground SS 87 G12 65 JTRST I T pu JTAG reset Input T 88 F12 66 JTDI I T pu JTAG data input T 89 H8 67 JTMS I T pu JTAG mode selection Input T 90 G11 68 JTCK I T pd JTAG clock Input T JTAG data output. 91 G10 69 JTDO O 4mA Note: Reset state = HiZ 92 G9 70 V S Ground SS 93 G8 71 V S Supply voltage (5 V) DD 94 G7 P4.0/ICAPA7 I/O T WUP24 2mA X X Port 4.0 TIM7: input capture A input T 95 F11 P4.1/ICAPB7 I/O T WUP25 2mA X X Port 4.1 TIM7: input capture B input T 96 F10 P4.2/ICAPA8 I/O T WUP26 2mA X X Port 4.2 TIM8: input capture A input T 17/52

Block diagram STR73xFxx Table 4. STR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction 97 F9 P4.3/ICAPB8 I/O T WUP27 2mA X X Port 4.3 TIM8: input capture B input T 98 F8 P4.4/CAN2TX I/O T 2mA X X Port 4.4 CAN2: transmit data output T 99 E12 P4.5/CAN2RX I/O T WUP18 2mA X X Port 4.5 CAN2: receive data input T 100 E11 72 P4.6/SCL1 I/O T WUP19 2mA X X Port 4.6 I2C1: serial clock T 101 C12 73 P4.7/SDA1 I/O T 2mA X X Port 4.7 I2C1: serial data T 102 B12 P4.8/OCMPA8 I/O T 2mA X X Port 4.8 TIM8: output compare A output T 103 E10 P4.9/ICAPB6 I/O T 2mA X X Port 4.9 TIM6: input capture B input T TIM5: input TIM6: input capture B P4.10/ICAPA6/I capture A input 104 E9 74 I/O T WUP20 2mA X X Port 4.10 input CAPB5 T (144-pin pkg (TQFP100 only) only) P4.11/OCMPB 105 D12 I/O T 2mA X X Port 4.11 TIM8: output compare B output 8 T 106 D11 P4.12/ICAPA9 I/O T WUP21 2mA X X Port 4.12 TIM9: input capture A input T 107 D10 P4.13/ICAPB9 I/O T 2mA X X Port 4.13 TIM9: input capture B input T 108 C11 75 P4.14/SS1 I/O T 2mA X X Port 4.14 BSPI1: slave select T 109 B11 76 P4.15/SCK1 I/O T WUP22 2mA X X Port 4.15 BSPI1: serial clock T BSPI1: master output/slave 110 B10 77 P5.0/MOSI1 I/O T 2mA X X Port 5.0 T input BSPI1: master input/Slave 111 C10 78 P5.1/MISO1 I/O T 2mA X X Port 5.1 T output 112 A9 P5.2/OCMPA9 I/O T 2mA X X Port 5.2 TIM9: output compare A output T 113 B9 P5.3/OCMPB9 I/O T 2mA X X Port 5.3 TIM9: output compare B output T PWM3: PWM P5.4/SS2/PWM BSPI2: slave output 114 C9 79 I/O T 2mA X X Port 5.4 3 T select (TQFP100 only) 115 D9 80 P5.5/SCK2 I/O T WUP23 2mA X X Port 5.5 BSPI2: serial clock T BSPI2: master output/slave 116 A11 81 P5.6/MOSI2 I/O T 2mA X X Port 5.6 T input BSPI2: master input/slave 117 A10 82 P5.7/MISO2 I/O T 2mA X X Port 5.7 T output PWM4: PWM output (TQFP100 118 A8 83 P5.8/PWM4 I/O T INT6 2mA X X Port 5.8 T only) 18/52

STR73xFxx Block diagram Table 4. STR73xF pin description Pin n° Input Output Main TQFP144 LFBGA144 TQFP100 Pin name Type Input Level pu/pd interrupt Capability OD PPfur(neascfteteitor)n Alternatefunction PWM5: PWM output (TQFP100 119 B8 84 P5.9/PWM5 I/O T INT7 2mA X X Port 5.9 T only) 120 C8 85 P5.10/RDI2 I/O T INT8 2mA X X Port 5.10 UART2: receive data input T 121 A12 86 P5.11/TDO2 I/O T INT9 2mA X X Port 5.11 UART2: transmit data output T 122 D8 87 P5.12 I/O T INT10 2mA X X Port 5.12 T 123 E8 P5.13 I/O T INT11 2mA X X Port 5.13 T 124 B7 P5.14 I/O T INT12 2mA X X Port 5.14 T 125 A7 P5.15 I/O T INT13 2mA X X Port 5.15 T 1.8 V decoupling pin: a decoupling capacitor 126 A6 88 V S (recommended value: 100 nF) 18 must be connected between this pin and nearest VSS pin. 127 C7 89 V S Ground SS 128 D7 90 V S Supply voltage (5 V) DD 129 E7 91 P6.0 I/O T WUP0 8mA X X Port 6.0 T 130 F7 P6.1 I/O T WUP1 2mA X X Port 6.1 T 131 B6 92 P6.2/RDI3 I/O T WUP2 2mA X X Port 6.2 UART3: receive data input T 132 C6 P6.3 I/O T WUP3 2mA X X Port 6.3 T 133 D6 93 P6.4/TDO3 I/O T WUP4 2mA X X Port 6.4 UART3: transmit data output T 134 E6 P6.5 I/O T WUP5 2mA X X Port 6.5 T 135 A5 94 P6.6 I/O T WUP6 2mA X X Port 6.6 T 136 B5 P6.7 I/O T WUP7 2mA X X Port 6.7 T 137 C5 95 P6.8/RDI0 I/O T WUP10 2mA X X Port 6.8 UART0: receive data input T 138 A3 96 P6.9/TDO0 I/O T 2mA X X Port 6.9 UART0: transmit data output T 139 A2 P6.10 I/O T WUP8 2mA X X Port 6.10 T BSPI0: master input/slave 140 D5 97 P6.11/MISO0 I/O T 2mA X X Port 6.11 T output BSPI0: master output/slave 141 A4 98 P6.12/MOSI0 I/O T 2mA X X Port 6.12 T input 142 B4 99 P6.13/SCK0 I/O T WUP11 2mA X X Port 6.13 BSPI0: serial clock T 143 C4 100 P6.14/SS0 I/O T 2mA X X Port 6.14 BSPI0: slave select T 144 B3 P6.15 I/O T WUP9 2mA X X Port 6.15 T 19/52

Block diagram STR73xFxx 3.3 Memory mapping Figure5 shows the various memory configurations of the STR73xF system. The system memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure, the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM addresses can be aliased to Block 0 addresses using the remapping feature Most reserved memory spaces (gray shaded areas in Figure5) are protected from access by the user code. When an access this memory space is attempted, an ABORT signal is generated. Depending on the type of access, the ARM processor will enter “prefetch abort” state (Exception vector 0x0000_000C) or “data abort” state (Exception vector 0x0000_0010). It is up to the application software to manage these abort exceptions. Figure 5. Memory map Addressable memory space APB memory space 4 Gbytes 32 Kbytes 0xFFFF FFFF 0xFFFF FFFF 0xFFFF 8000 APBB RTIOD GAERM7 32K 0xFFFF FC00 EIC 1K 0xFFFF FBFF ADC 1K 7 000xxxFFFFFFFFFFFF FFF8760F00F0 CMU 1K 0xFFFF F400 RTC 0xFFFF F3FF Flash memory space DMA 0-3 1K 0xE000 0000 0xFFFF F000 0xDFFF FFFF 64K/128/256 Kbytes 0xFFFF EFFF TIM 4 1K 0xFFFF EC00 0xFFFF EBFF 6 00xx88001100 CD0F0F0F System Memory 8K 00xxFFFFFFFF EE78F0F0 TIM 3 1K 00xx88001100 00000107 Flash registers 20B 00xxFFFFFFFF EE34F0F0 TIM 2 1K BSPI 2 1K 0xC000 0000 0xFFFF E000 0xBFFF FFFF 0xFFFF DFFF BSPI 1 1K 0xFFFF DC00 0xFFFF DBFF BSPI 0 1K 5 00xxFFFFFFFF DD78F0F0 GP I/O 0-6 1K 0xFFFF D400 0xFFFF D3FF 00xxAA000000 030F0F0F RAM 16K 0xFFFF D000 PWM 0-5 1K 0x9FFF FFFF 0xFFFF CFFF CAN 2(4) 1K 0xFFFF CC00 0xFFFF CBFF CAN 1(4) 1K 4 00xxFFFFFFFF CC78F0F0 CAN 0(4) 1K 0xFFFF C400 0xFFFF C3FF 00xx88000100 00000107 Flash 64K/128K/256K 0xFFFF C000 APB BRIDGE 1 REGS 1K 0x7FFF FFFF 0xFFFF BFFF reserved 1K 0xFFFF BC00 0xFFFF BBFF WAKEUP 1K 3 00xxFFFFFFFF BB78F0F0 reserved 1K 0xFFFF B400 0xFFFF B3FF 00xx66000000 00030F0F PRCCU 1K 0x8003 FFFF 0xFFFF B000 TIM 5-9 1K 0x5FFF FFFF 0xFFFF AFFF TIM 1 1K B0F7(2) 64K 00xxFFFFFFFF AABCF0F0 TIM 0 1K 2 00xx88000023 F0F0F0F0 000xxxFFFFFFFFFFFF AAA76800F00F WAKEUPTIM 1K 0xFFFF A400 WDG 00xx44000000 0000030F CONFIG. REGS 64B B0F6(2) 64K 000xxxFFFFFFFFFFFF AAA0320F00F0 UUAARRTT 13 1K 0x3FFF FFFF 00xxFFFFFFFF 99FEF0F0 UART 2 1K 0x8002 0000 0xFFFF 9C00 UART 0 0x8001 FFFF 0xFFFF 9BFF TB 0-2 1K 1 B0F5(3) 64K 00xxFFFFFFFF 99870F0F reserved 1K 0xFFFF 9400 0xFFFF 93FF 00xx22000000 0000000F NATIVE ARBITER 16B 00xx88000001 F0F0F0F0 0xFFFF 9000 reserved 1K 0x1FFF FFFF 0xFFFF 8FFF B0F4 32K 0xFFFF 8C00 reserved 1K 0 00000xxxxx88888000000000000000 456780F0F00F0F00F0F0 BB00FF32 88KK 000xxxFFFFFFFFFFFF 88878BF0FF0F II22CC 01 11KK 00xx00001000 00001070 Flash (1) 64K/128K/256K 0000xxxx8888000000000000 1023F00FF00FF00F BB00TFF1 88KK 000xxxFFFFFFFFFFFF 88804300F00F APB BRIDGE 0 REGS 1K (1) Flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) (2) Only available in STR73xZ2/V2 (3) Only available in STR73xZ2/V2 and STR73xZ1/V1 access to gray shaded area will return an ABORT (4) Only available in STR730/STR731 Drawing not to scale 20/52

STR73xFxx Electrical parameters 4 Electrical parameters 4.1 Parameter conditions Unless otherwise specified, all voltages are referred to V . SS 4.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T =25° C and T =T (given by the A A Amax selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 4.1.2 Typical values Unless otherwise specified, typical data are based on T =25° C and V =5 V. They are A DD given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 4.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 4.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure6. 4.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure7. F igure 6. Pin loading conditions Figure 7. Pin input voltage STR7PIN STR7PIN L=50pF VIN 21/52

Electrical parameters STR73xFxx 4.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. T able 5. Voltage characteristics Symbol Ratings Min Max Unit V - V External 5 V Supply voltage -0.3 6.0 DD SS V V Reference ground for A/D converter V V SSA SS SS V VDDA- VSSA Reference voltage for A/D converter -0.3 VDD+0.3 V VIN Input voltage on any pin -0.3 VDD+0.3 Variations between different 5 V |ΔVDDx| power pins - 0.3 mV Variations between all the different |VSSX - VSS| ground pins - 0.3 Electrostatic discharge voltage V ESD(HBM) (Human Body Model) see : Absolute maximum ratings (electrical sensitivity) on page36 Electrostatic discharge voltage V ESD(MM) (Machine Model) T a ble 6. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source) 1) 100 IVSS Total current out of VSS ground lines (sink) 1) 100 Output current sunk by any I/O and control pin 10 IIO mA Output current source by any I/O and control pin 10 IINJ(PIN) 2) & 3) Injected current on any other pin 4) &5) ±10 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 4) ±75 1. All 5 V power (V , V ) and ground (V , V ) pins must always be connected to the external 5 V DD DDA SS SSA supply 2. I must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum INJ(PIN) IN IN cannot be respected, the injection current must be limited externally to the I value. A positive INJ(PIN) injection is induced by V >V while a negative injection is induced by V <V . IN DD IN SS 3. Negative injection disturbs the analog performance of the device. See note in Section4.3.6: 10-bit ADC characteristics on page43. 4. When several inputs are submitted to a current injection, the maximum ΣI is the absolute sum of the INJ(PIN) positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI maximum current injection on four I/O port pins of the device. INJ(PIN) 5.) In 144-pin devices, only +10 mA on P0.3, P1.13, P3.6 and P4.13 pins (negative injection not allowed). 22/52

STR73xFxx Electrical parameters T able 7. Thermal characteristics Symbol Ratings Value Unit TSTG Storage temperature range -55 to +150 °C Maximum junction temperature (see Section5.2: Thermal characteristics on T J page48) 23/52

Electrical parameters STR73xFxx 4.3 Operating conditions Subject to general operating conditions for V , and T . DD A T able 8. General operating conditions Symbol Parameter Conditions Min Max Unit Accessing SRAM or Flash Internal CPU and system fMCLK clock frequency (zero wait state Flash access 0 36 MHz up to 36 MHz) Standard Operating V 4.5 5.5 V DD Voltage Operating analog reference V voltage with respect to 4.5 V +0.1 V DDA DD ground 6 partnumber suffix -40 85 TA Ambient temperature range 7 partnumber suffix -40 105 °C T able 9. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Typ Max Unit Subject to general tVDD VDD rise time rate operating conditions for - 20 - ms/V T . A 24/52

STR73xFxx Electrical parameters 4.3.1 Supply current characteristics The current consumption is measured as described in Figure6 and Figure7. Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at V or V (no load) DD SS ● All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for V , and T . DD A Table 10. Total current consumption Symbol Parameter Conditions Typ 1) Max 2) Unit Formula, fMCLK in MHz, RAM execution 7 + 1.9 fMCLK mA RUN mode3) fMCLK = 36 MHz, RAM execution 76 mA fMCLK = 36 MHz, Flash execution 86 mA f = 4 MHz, f = f /16 = 250 kHz OSC MCLK OSC Main voltage regulator ON, WFI mode 6.7 8 mA LP voltage regulator = 2 mA, RTC and WDG on, other modules off. f = high frequency (CMU_RCCTL= 0x8), RC f = f /16, LPWFI mode MCLK RC 220 350 µA LP voltage regulator = 2 mA, other modules off. I DD f = 4 MHz, RC oscillator on OSC f = high frequency (CMU_RCCTL= 0x0) RC LP voltage regulator = 6 mA, 500 700 RTC and WUT ON, other modules off. Internal wake-up possible. STOP mode f = high frequency (CMU_RCCTL= 0xF), µA RC LP voltage regulator = 2mA. 150 220 WUT ON, other modules off. Internal wake-up possible. LP voltage regulator = 2 mA, WIU on, Other 50 140 modules off, external wake-up. HALT mode LP voltage regulator = 2 mA. 50 140 µA 1. Typical data are based on T =25° C, V =5 V A DD 2. Data based on characterization results, tested in production at V max. and T = 25° C. DD A 3. I/O in static configuration (not toggling). RUN mode is almost independent of temperature. On the contrary RUN mode current is highly dependent on the application. The I value can be DDRUN significantly reduced by the application in the following ways: switch-off unused peripherals (default), reduce peripheral frequency through internal prescaler, fetch the most frequently-used functions from RAM and use low power mode when possible. 25/52

Electrical parameters STR73xFxx Figure 8. STOP I vs. VDD Figure 9. HALT I vs. V DD DD DD 300 300 250 250 200 200 OP (µA)150 TTAA==-2455°°CC LT (µA) 150 TTAA==-2455°°CC ST TA=85°C HA TA=85°C dd TA=105°C dd TA=105°C I100 I 100 50 50 0 0 3.5 4 4.5 5 5.5 6 6.5 3.5 4 4.5 5 5.5 6 6.5 Vdd (V) Vdd (V) Figure 10. WFI I vs. V Figure 11. LPWFI I vs. V DD DD DD DD 8.0 500 7.5 450 400 Wfi (mA)7.0 TTTAAA===-284555°°°CCC WFI (µA) 233505000 TTAA==-2455°°CC Idd 6.5 TA=105°C Idd LP 125000 TTAA==18055°C°C 100 6.0 50 0 5.5 3.5 4 4.5 5 5.5 6 6.5 3.5 4 4.5 5 5.5 6 6.5 Vdd (V) Vdd (V) 26/52

STR73xFxx Electrical parameters Typical application current consumption T able 11. Typical consumption in Run mode at 25°C and 85°C Conditions f (MHz) f (MHz) Typical I (mA) MCLK ADC DD 10 20 Code executing in 10 20 29 RAM V = 5.5 V, RC oscillator off, DD PLL on, RTC enabled, 1 Timer 36 9 42 (TIM) running, and ADC 10 22 running in scan mode. Code executing in 10 20 32 Flash 36 9 48 Table 12. Typical consumption in Run and low power modes at 25°C Mode Conditions f Typical I MCLK DD 36 MHz 76 mA RUN All peripherals on, RAM execution 24 MHz 56 mA Main voltage regulator on, Flash on, EIC on, WIU on, 36 MHz 33 mA WFI GPIOs on. 24 MHz 31 mA PLL off, main voltage regulator on 4 MHz 11 mA CLOCK2/16, main voltage regulator on 250 kHz 8 mA SLOW CLOCK2/16, main voltage regulator off 250 kHz 3 mA RC oscillator running in low frequency, main crystal 29 kHz 2.5 mA oscillator off, main voltage regulator off CLOCK2/16, main voltage regulator off, LP voltage LPWFI 250 kHz 528 µA regulator = 2 mA, Flash in power down mode. Main voltage regulator off, RTC on, RC oscillator off, - 378 µA LP voltage regulator = 6 mA Main voltage regulator off, RTC off, RC oscillator off, - 83 µA LP voltage regulator = 6 mA STOP Main voltage regulator off, RTC off, RC oscillator off, - 64 µA LP voltage regulator = 4 mA Main voltage regulator off, RTC off, RC oscillator off, - 44 µA LP voltage regulator = 2 mA HALT RTC off, LP voltage regulator = 2 mA - 44 µA 27/52

Electrical parameters STR73xFxx On-chip peripherals T able 13. Peripheral current consumption at T = 25°C A Symbol Parameter Conditions Typ Unit High frequency 120 µA IDD(RC) RC (backup oscillator) supply current Low frequency 60 µA IDD(TIM) TIM timer supply current 1) 350 µA IDD(BSPI) BSPI supply current 1) 1.1 mA IDD(UART) UART supply current 1) 850 µA IDD(I2C) I2C supply current 1) 430 µA IDD(ADC) ADC supply current when converting 2) 5 mA IDD(EIC) EIC supply current 2.88 mA IDD(CAN) CAN supply current 1) 2.95 mA IDD(GPIO) GPIO supply current 150 µA f =36 MHz MCLK IDD(TB) TB supply current 250 µA IDD(PWM) PWM supply current 240 µA IDD(RTC) RTC supply current 370 µA IDD(DMA) DMA supply current 2.5 mA IDD(ARB) Native arbiter supply current 180 µA IDD(AHB) AHB arbiter supply current 570 µA IDD(WUT) WUT supply current 300 µA IDD(WIU) WIU supply current 460 µA 1. Data based on a differential I measurement between the on-chip peripheral when kept under reset, not DD clocked and the on-chip peripheral when clocked and not kept under reset. This measurement does not include the pad toggling consumption. 2. Data based on a differential I measurement between reset configuration and continuous A/D DD conversions. 28/52

STR73xFxx Electrical parameters 4.3.2 Clock and timing characteristics Crystal / ceramic resonator oscillator The STR73xF can operate with a crystal oscillator or resonator clock source. Figure12 describes a simple model of the internal oscillator driver as well as example of connection for an oscillator or a resonator. Figure 12. Crystal oscillator and resonator STR73x VDD I RF 1 2 L L A A T T X X STR73x STR73x 1 2 1 2 L L L L A A A A T T T T X X X X Crystal Resonator RS CL CL Note: 1 XTAL2 must not be used to directly drive external circuits. 2 For test or boot purpose, XTAL2 can be used as an high impedance input pin to provide an external clock to the device. XTAL1 should be grounded, and XTAL2 connected to a wave signal generator providing a 0 to VDD signal. Directly driving XTAL2 may results in deteriorated jitter and duty cycle. 29/52

Electrical parameters STR73xFxx Main oscillator characteristics VDD = 5 V ± 10%, TA = -40° C to TAmax, unless otherwise specified. T able 14. Main oscillator characteristics Value Symbol Parameter Conditions Unit Min Typ Max f Oscillator frequency 4 8 MHz OSC Oscillator g 1.5 4.2 mA/V m transconductance f = 4 MHz, T = 25o C - 2.4 - V 1) Oscillation amplitude OSC A V OSC f = 8 MHz, T = 25o C 1.- OSC A Oscillator operating VAV1) point Sine wave middle, TA= 25o C - 0.77 - V External crystal, V = 5.5 V, DD - - 12 ms f = 4 MHz, T =-40o C OSC A External crystal, V = 5.0 V, DD - 5.5 - ms f = 4 MHz, T =25o C OSC A External crystal, V = 5.5 V, DD - - 8 ms f = 6 MHz, T =-40o C t 1) Oscillator start-up time OSC A STUP External crystal, V = 5.0 V, DD - 3.3 - ms f = 6 MHz, T =25o C OSC A External crystal, V = 5.5 V, DD - - 7 ms f = 8 MHz, T =-40o C OSC A External crystal, V = 5.0 V, DD - 2.7 - ms f = 8 MHz, T = 25o C OSC A 30/52

STR73xFxx Electrical parameters Table 14. Main oscillator characteristics (continued) Value Symbol Parameter Conditions Unit Min Typ Max C 3) = C 4)= 10 pF 150 555 - 1 2 fOSC = 4 MHz C1 = C2 = 20 pF 490 1035 - Cp2) = 10 pF C = C = 30 pF 490 1030 - 1 2 C = C = 40 pF 380 850 - 1 2 C = C = 10 pF 160 470 - 1 2 fOSC = 5 MHz C1 = C2 = 20 pF 415 800 - Cp = 10 pF C = C = 30 pF 340 735 - 1 2 C = C = 40 pF 260 580 - 1 2 C = C = 10 pF 160 415 - 1 2 R 1) Feedback resistor fOSC = 6 MHz C1 = C2 = 20 pF 325 640 - Ω F Cp = 10 pF C = C = 30 pF 250 550 - 1 2 C = C = 40 pF 180 420 - 1 2 C = C = 10 pF 160 375 - 1 2 fOSC = 7 MHz C1 = C2 = 20 pF 260 525 - Cp = 10 pF C = C = 30 pF 185 420 - 1 2 C = C = 40 pF 135 315 - 1 2 C = C = 10 pF 155 340 - 1 2 fOSC = 8 MHz C1 = C2 = 20 pF 210 435 - Cp = 10 pF C = C = 30 pF 145 335 - 1 2 C = C = 40 pF 100 245 - 1 2 1. Min and max values are guaranteed by characterization, not tested in production. 2. C represents the total capacitance between XTAL1 and XTAL2, including the shunt capacitance of the P external quartz crystal as well as the total board parasitic cross-capacitance between XTAL1 track and XTAL2 track. 3. C represents the total capacitance between XTAL1 and ground, including the external capacitance tied to 1 XTAL1 pin (C ) as well as the total parasitic capacitance between XTAL1 track and ground (this includes L application board track capacitance to ground and device pin capacitance). 4. C represents the total capacitance between XTAL2 and ground, including the external capacitance tied to 2 XTAL1 pin (C ) as well as the total parasitic capacitance between XTAL2 track and ground (this includes L application board track capacitance to ground and device pin capacitance). 31/52

Electrical parameters STR73xFxx RC/backup oscillator characteristics VDD = 5V ± 10%, TA = -40°C to TAmax, unless otherwise specified. T able 15. RC oscillator characteristics Value Symbol Parameter Conditions Unit Min Typ Max High frequency mode 1) 2.35 MHz f RC frequency RC Low frequency mode1) 29 kHz CMU_RCCTL = 0x0 3 MHz f RC high frequency RCHF CMU_RCCTL = 0xF 2.3 MHz CMU_RCCTL = 0x0 35 kHz f RC low frequency RCLF CMU_RCCTL = 0xF 30 kHz f 2) RC high frequency stability Fixed CMU_RCCTL 10 % RCHFS f 2) RC low frequency stability Fixed CMU_RCCTL 23 % RCLFS Stable V , tRCSTUP RC start-up time f = 2.3D5D MHz, T = 25oC 2.35 µs RC A 1) CMU_RCCTL = 0x8 2) RC frequency shift versus average value (%) 32/52

STR73xFxx Electrical parameters PLL electrical characteristics VDD = 5 V ± 10%, TA = -40° C to TAmax, unless otherwise specified T able 16. PLL characteristics Value Symbol Parameter Conditions Unit Min Typ Max FREF_RANGE = ‘0’ 1.5 3.0 f (1) PLL reference clock MHz PLLIN FREF_RANGE = ‘1’ 3.0 5.0 MX = ”00” 20 x f PLLIN MX = ”01” 12 x f f PLL output clock PLLIN MHz PLLOUT MX = ”10” 28 x f PLLIN MX = ”11” 16 x f PLLIN f System clock DX = 1..7 f /DX 36 MHz MCLK PLLOUT FREF_RANGE = ‘0’, MX0 = ’1’ 120 PLL free running FREF_RANGE = ‘0’, MX0 = ’0’ 240 f (2) kHz FREE frequency FREF_RANGE = ‘1’, MX0 = ’1’ 240 FREF_RANGE = ‘1’, MX0 = ’0’ 480 Stable oscillator t (3) PLL lock time 100 300 μs LOCK (f = 4 MHz), stable V PLLIN DD f = 4 MHz (pulse Δt PLL jitter (pk to pk) PLLIN 1.5 ns PKJIT generator) 1. f is obtained from f directly or through an optional divider by 2. PLLIN OSC 2. Typical data are based on T =25°C, V =5V A DD 3. Max value is guaranteed by characterization, not tested in production. T able 17. Low-power mode wake-up timing Symbol Parameter Conditions Typ Unit tWUHALT Wake-up from HALT mode 200 µs RC high frequency in STOP mode 180 µs tWUSTOP Wake-up from STOP mode RC low frequency in STOP mode 234 µs Main voltage regulator on RC oscillator off 27 µs f = 4 MHz, f = f /16 OSC MCLK OSC RAM or FLASH execution Main voltage regulator on t 1) Wake-up from LPWFI mode WULPWFI RC oscillator = high frequency 46 µs Flash execution Main voltage regulator on RC oscillator = low frequency 3.6 ms Flash execution 1. Flash memory programmed to enter Power Down mode during LPWFI. 33/52

Electrical parameters STR73xFxx 4.3.3 Memory characteristics Flash memory T a ble 18. Flash memory characteristics Value Symbol Parameter Test Conditions Unit Min Typ Max1) t Word program (32-bit) 35 80 μs WP t Double word program(64-bit) 64 150 μs DWP t Bank program (64 K) Double word program 0.5 1.25 s BP64 t Bank program (128 K) Double word program 1 2.5 s BP128 t Bank program (256 K) Double word program 2 4.9 s BP256 Not preprogrammed 0.6 0.9 t Sector erase (8 K) s SE8 Preprogrammed 2) 0.5 0.8 Not preprogrammed 1.1 2 tSE32 Sector erase (32 K) Preprogrammed2) 0.8 1.8 s Not preprogrammed 1.7 3.7 tSE64 Sector erase (64 K) preprogrammed 2) 1.3 3.3 s t 3) Recovery from power-down 20 μs RPD t 3) PSL Program suspend latency 10 μs t 3) Erase suspend latency 30 μs ESL Min. time from erase t 3) Erase suspend rate resume to next erase 20 20 ms ESR suspend t 3) Set protection 40 170 µs SP t 3) First word program 1 ms FPW NEND Endurance 10 kcycles tRET Data retention TA = 85° C 20 Years 1. T = -45° C after 0 cycles, Guaranteed by characterization, not tested in production. A 2. All bits programmed to 0. 3. Guaranteed by design, not tested in production. 34/52

STR73xFxx Electrical parameters 4.3.4 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. ● FTB: A burst of fast transient voltage (positive and negative) is applied to V and V DD SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). T able 19. EMS data Level/ Symbol Parameter Conditions Class VFESD Vtoo ilntadguec elim ai tfsu ntoc tbioen aapl dpilsietudr obna nacney I/O pin VcoDnDf=o5rm Vs, TtoA =IE+C25 1°0 C0,0 f-M4C-2LK=36 MHz 4A Fast transient voltage burst limits to be V =5 V, T =+25° C, f =36 MHz VEFTB applied through 100 pF on VDD and VSS DD A MCLK 4A conforms to IEC 1000-4-4 pins to induce a functional disturbance 35/52

Electrical parameters STR73xFxx Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. T able 20. EMI data Max vs. Unit Monitored [f /f ] Symbol Parameter Conditions OSC4M MCLK frequency band 6/36 MHz 8/8 MHz 0.1 MHz to 30 MHz 23 30 V =5.0V, DD 30 MHz to 130 MHz 37 34 dBµV SEMI Peak level TA=+25°C, 130 MHz to 1 GHz 20 7 All packages SAE EMI Level 4 3.5 - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and machine model. This test conforms to the JESD22-A114A/A115A standard. T a ble 21. ESD Absolute Maximum ratings Maximum Symbol Ratings Conditions Unit value 1) Electrostatic discharge voltage VESD(HBM) (human body model) 2000 Electrostatic discharge voltage VESD(MM) (machine model) TA=+25° C 200 V 750 on corner Electrostatic discharge voltage VESD(CDM) (charge device model) pins, 500 on others Notes: 1. Data based on characterization results, not tested in production. Static and dynamic latch-up ● LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each 36/52

STR73xFxx Electrical parameters sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. ● DLU: Electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. T a ble 22. Electrical sensitivities Symbol Parameter Conditions Class 1) TA=+25°C A LU Static latch-up class TA=+85°C A T =+105°C A A V = 5.5 V, f = 4 MHz, f = 32 MHz, DLU Dynamic latch-up class DD OSC4M MCLK A T = +25° C A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 37/52

Electrical parameters STR73xFxx 4.3.5 I/O port pin characteristics General characteristics Subject to general operating conditions for V and T unless otherwise specified. DD A T able 23. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage 1) 0.8 TTL ports V VIH Input high level voltage 1) 2.0 IINJ(PIN) Injected current on any I/O pin ±10 mA ΣI Total injected current (sum of all INJ(PIN) ±75 mA 2) I/O and control pins) Ilkg Input leakage current 3) VSS≤VIN≤VDD ±1 μA Floating input IS Static current consumption 4) mode 200 µA Weak pull-up equivalent RPU resistor5) VIN=VSS 55 120 220 kΩ Weak pull-down equivalent RPD resistor5) VIN=VDD 55 120 220 kΩ CIO I/O pin capacitance 5 pF 1. Data based on characterization results, not tested in production. 2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise IN refer to I specification. A positive injection is induced by V >V while a negative injection is INJ(PIN) IN 33 induced by V <V . Refer to Section4.2 on page 22 for more details. IN SS 3. Leakage could be higher than max. if negative current is injected on adjacent pins. 4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Data based on design simulation and/or technology characteristics, not tested in production. 6. The R pull-up and R pull-down equivalent resistor are based on a resistive transistor (corresponding PU PD I and I current characteristics described in Figure19). PU PD 38/52

STR73xFxx Electrical parameters Output driving current Subject to general operating conditions for V and T unless otherwise specified. DD A T able 24. Output driving current I/O Type Symbol Parameter Conditions Min Max Unit Output low level voltage for an I/O pin VOL 1) when 8 pins are sunk at same time IIO=+2 mA 0.4 Standard Output high level voltage for an I/O pin VOH 2) when 4 pins are sourced at same time IIO=-2 mA VDD-0.8 Med. VOL 1) Output low level voltage for an I/O pin IIO=+6 mA 0.4 V Current (JTDO) VOH 2) Output high level voltage for an I/O pin IIO=-6 mA VDD-0.8 High VOL 1) Output low level voltage for an I/O pin IIO=+8 mA 0.4 Current P6.0 VOH 2) Output high level voltage for an I/O pin IIO=-8 mA VDD-0.8 1. The I current sunk must always respect the absolute maximum rating specified in Table6 and the sum of IO I (I/O ports and control pins) must not exceed I . IO VSS 2. The I current sourced must always respect the absolute maximum rating specified in Table6 and the IO sum of IIO (I/O ports and control pins) must not exceed IVDD. Figure 13. V standard ports vs I @ V 5V Figure 14. V standard ports vs I @ V 5 V OH OH DD OL OL DD T -45° C A 5.10 0.25 Ta -45°C Ta 25°C 5.00 Ta 90°C 0.20 Ta 110°C V4.90 V 5 5 D= D= 0.15 D D V4.80 V at Ta -45°C at V) Ta 25°C V) 0.10 H( Ta 90°C L( VO4.70 Ta 110°C VO 0.05 4.60 4.50 0.00 0 1 2 3 4 0 1 2 3 4 Ioh (mA) Iol (mA) 39/52

Electrical parameters STR73xFxx Figure 15. V JTDO pin vs I @ V 5 V Figure 16. V JTDO pin vs I @ V 5 V OH OL DD OL OL DD 5.10 0.14 0.12 5.00 0.10 V4.90 V 5 5 D= D= 0.08 D D V4.80 V at at V) V) 0.06 H( L( O4.70 O V Ta -45°C V0.04 Ta -45°C Ta 25°C Ta 25°C 4.60 Ta 90°C Ta 90°C Ta 110°C 0.02 Ta 110°C 4.50 0.00 0 1 2 3 4 5 6 0 1.2 2.4 3.6 4.8 6 Ioh (mA) Iol (mA) Figure 17. V P6.0 pin vs I @ V 5 V Figure 18. V P6.0 pin vs I @ V 5 V OH OL DD OL OL DD 5.10 0.18 0.16 5.00 0.14 V4.90 V0.12 5 5 DD= DD= 0.10 V4.80 V V) at V) at 0.08 H( L( O4.70 O0.06 V Ta -45°C V Ta -45°C Ta 25°C 0.04 Ta 25°C 4.60 Ta 90°C Ta 90°C Ta 110°C Ta 110°C 0.02 4.50 0.00 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Ioh (mA) Iol (mA) 40/52

STR73xFxx Electrical parameters NRSTIN pin The NRSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as R (see : General characteristics on page38) PU Subject to general operating conditions for V and T unless otherwise specified. DD A T able 25. Reset pin characteristics Symbol Parameter Conditions Min Typ 1) Max Unit VIL(NRSTIN) NRSTIN Input low level voltage 1) 0.3 VDD V VIH(NRSTIN) NRSTIN Input high level voltage 1) 0.7 VDD NRSTIN Schmitt trigger voltage Vhys(NRSTIN) hysteresis 2) 800 mV VF(RSTINn) NRSTIN Input filtered pulse3) 500 ns VNF(RSTINn) NRSTIN Input not filtered pulse3) 2 µs VRP(RSTINn) NRSTIN removal after Power-up3) 100 µs 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. Data guaranteed by design, not tested in production. Figure 19. Recommended NRSTIN pin protection1) V DD R PU EXTERNAL INTERNAL RESET RESET Filter CIRCUIT 0.01μF STR7X Required 1. The R pull-up equivalent resistor is based on a resistive transistor. PU 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRSTIN pin can go below the V max. level specified in IL(NRSTIN) Table25. Otherwise the reset will not be taken into account internally. 41/52

Electrical parameters STR73xFxx Figure 20. NRSTIN R vs. V PU DD 250 200 m)150 25C h pu (kO100 -14150CC R 50 0 3 3.5 4 4.5 5 5.5 Vdd (v) 42/52

STR73xFxx Electrical parameters 4.3.6 10-bit ADC characteristics Subject to general operating conditions for V , f , and T unless otherwise specified. DDA MCLK A T able 26. ADC characteristics Symbol Parameter Conditions Min Typ 1) Max Unit f 0.4 10 MHz ADC VAIN Conversion voltage range 2) VSSA VDDA V Negative input leakage current on VIN<VSS, | IIN |< 400 Ilkg analog pins µA on adjacent 5 6 μA analog pin Internal sample and hold CADC capacitor 3.5 pF 580.2 µs tCAL2) Calibration time fADC = 10 MHz 5802 1/f ADC tS3) Sampling time fADC = 10 MHz 1 14 µs 3 µs t Total conversion time (including f = 10 MHz 30 (10 for sampling CONV sampling time) ADC +20 for successive 1/f ADC approximation) Running mode Normal mode 5 mA I ADC Power-down mode 1 μA 1. Unless otherwise specified, typical data are based on T =25°C and V -V =5.0V. They are given only A DDA SS as design guidelines and are not tested. 2. Calibration is recommended once after each power-up. 3. During the sample time the input capacitance C (6.8 max) can be charged/discharged by the external AIN source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t After the end of the sample time t , changes of the analog input voltage have no effect on S. S the conversion result. Values for the sample clock t depend on programming. S 43/52

Electrical parameters STR73xFxx T able 27. ADC accuracy with f = 20 MHz, f =10 MHz, R < 10 kΩ RAIN, MCLK ADC AIN V =5 V. This assumes that the ADC is calibrated2) DDA Symbol Parameter Conditions Typ Max Unit |ET| Total unadjusted error 1) 1.0 2.0 |EO| Offset error 1) 0.15 1.0 |EG| Gain error 1) 0.97 1.1 LSB |ED| Differential linearity error1) 0.7 1.0 |EL| Integral linearity error 1) 0.76 1.5 1. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current on robust pins is specified in Section4.3.5. Any positive injection current within the limits specified for I and ΣI in Section4.3.5 does not INJ(PIN) INJ(PIN) affect the ADC accuracy. 2. Calibration is needed once after each power-up. Figure 21. ADC accuracy characteristics EG (1) Example of an actual transfer curve 1023 (2) The ideal transfer curve 1022 VDDA–VSSA (3) End point correlation line 1LSB =----------------------------------------- 1021 IDEAL 1024 (2) ET=Total Unadjusted Error: maximum deviation 7 ET (3) bEeOt=wOefefsne tth Ee rarocrt:u dael avinadti othne b iedtewael etrna nthsefe frir csut ravcetsu.al (1) transition and the first ideal one. 6 EG=Gain Error: deviation between the last ideal 5 transition and the last actual one. 4 EO EL EbeDt=wDeieffne raecnttuiaall Lsitneepasr iatyn dE rtrhoer :i dmeaaxl imonuem. deviation 3 ED EbeLt=wIneteeng raanl yL iancetauraitl yt raEnrrsoitri:o nm aanxdim tuhme ednedv iaptoioinnt 2 correlation line. 1 1LSBIDEAL V 0 1 2 3 4 5 6 7 1021102210231024 VSSA VDDA Figure 22. Typical application with ADC VDD STR73X VT 0.6V RAIN AINx 2.3kΩ(max) 10-Bit A/D VAIN conversion CAIN V0.T6V IL CADC ±1μA 3.5pF 44/52

STR73xFxx Electrical parameters Analog power supply and reference pins The V and V pins are the analog power supply of the A/D converter cell. Theyact as DDA SSA the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see: General PCB design guidelines). General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. ● Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. ● Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines,placing 0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10 µF capacitor close to the power source (see Figure23). ● The analog and digital power supplies should be connected in a star network. Do not use a resistor, as V isused as a reference voltage by the A/D converter andany DDA resistance would cause a voltage drop and a loss of accuracy. ● Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted. Software filtering of spurious conversion results For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques. Figure 23. Power supply filtering STR73x 1 to 10 μF 0.1 μF VSS STR7 DIGITALNOISE FILTERING VDD 5V POWER SSUOPUPRLCYE 0.1 μF VDDA EXTERNAL NOISE FILTERING VSSA 45/52

Package characteristics STR73xFxx 5 Package characteristics 5.1 Package mechanical data Figure 24. 100-pin thin quad flat package mm inches(1) D A Dim. Min Typ Max Min Typ Max D1 A2 A 1.60 0.0630 A1 0.05 0.15 0.0020 0.0059 A1 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 b C 0.09 0.20 0.0035 0.0079 D 16.00 0.6299 D1 14.00 0.5512 e E 16.00 0.6299 E1 E E1 14.00 0.5512 e 0.50 0.0197 h 0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of Pins c L1 N 100 L h 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 25. 144-pin thin quad flat package mm inches(1) Dim. Min Typ Max Min Typ Max D D1 A 1.60 0.0630 A D3 A2 A1 0.05 0.15 0.0020 0.0059 A1 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 101908 7372 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 0.0.1004m inm. b c 0.09 0.20 0.0035 0.0079 b Seating Plane D 21.8022.0022.20 0.8583 0.8661 0.8740 E3 E1 E D1 19.8020.0020.20 0.7795 0.7874 0.7953 D3 17.50 0.6890 E 21.8022.0022.20 0.8583 0.8661 0.8740 144 37 E1 19.8020.0020.20 0.7795 0.7874 0.7953 1 36 E3 17.50 0.6890 c e 0.50 0.0197 e L1 L K 0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.0177 0.0236 0.0295 h L1 1.00 0.0394 Number of Pins N 144 1. Values in inches are converted from mm and rounded to 4 decimal digits. 46/52

STR73xFxx Package characteristics Figure 26. 144-ball low profile fine pitch ball grid array package mm inches1) Dim. Min Typ Max Min Typ Max A 1.21 1.70 0.0476 0.0669 AA12 0.21 1.085 0.0083 0.0427 b 0.35 0.40 0.45 0.0138 0.0157 0.0177 D 9.85 10.0010.15 0.3878 0.3937 0.3996 D1 8.80 0.3465 E 9.85 10.0010.15 0.3878 0.3937 0.3996 E1 8.80 0.3465 e 0.80 0.0315 F 0.60 0.0236 ddd 0.10 0.0039 eee 0.15 0.0059 fff 0.08 0.0031 Number of Pins N 144 1Values in inches are converted from mm and rounded to 4 decimal digits. Figure 27. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended – 4 to 6 mils screen print Dpad Dsm 47/52

Package characteristics STR73xFxx 5.2 Thermal characteristics The average chip-junction temperature, T , in degrees Celsius, may be calculated using the J following equation: T = T + (P x Θ ) (1) J A D JA Where: – T is the ambient temperature in °C, A – Θ is the package junction-to-ambient thermal resistance, in °C/W, JA – P is the sum of P and P (P = P + P ), D INT I/O D INT I/O – P is the product of I andV , expressed in Watts. This is the chip internal INT DD DD power, – P represents the power dissipation on input and output pins; user determined. I/O Most of the time for the applications P <P and may be neglected. On the other hand, I/O INT P may be significant if the device is configured to drive continuously external modules I/O and/or memories. An approximate relationship between P and T (if P is neglected) is given by: D J I/O P = K / (T + 273°C) (2) D J Therefore (solving equations 1 and 2): K = P x (T + 273°C) + Θ x P 2 (3) D A JA D Where: – K is a constant for the particular part, which may be determined from equation (3) by measuring P (at equilibrium) for a known T Using this value of K, the values D A. of P and T may be obtained by solving equations (1) and (2) iteratively for any D J value of T A T able 28. Thermal characteristics Symbol Description Package Value (typical) Unit LFBGA144 50 Θ Thermal resistance junction-ambient TQFP144 40 °C/W JA TQFP100 40 48/52

STR73xFxx Order codes 6 Order codes Table 29. O rder codes Flash RAM TIM 6x PWM CAN A/D Wake-up I/O Temp. Partnumber Package Kbytes Kbytes timers module periph chan. lines ports range STR730FZ1T6 128 TQFP144 STR730FZ2T6 256 20x20 3 STR730FZ1H6 128 LFBGA144 STR730FZ2H6 256 10x10 10 16 32 112 STR735FZ1T6 128 TQFP144 STR735FZ2T6 256 20x20 0 STR735FZ1H6 128 LFBGA144 -40 to 16 1 STR735FZ2H6 256 10x10 +85°C STR731FV0T6 64 TQFP100 STR731FV1T6 128 3 14x14 STR731FV2T6 256 6 12 18 72 STR736FV0T6 64 TQFP100 STR736FV1T6 128 0 14x14 STR736FV2T6 256 STR730FZ1T7 128 TQFP144 STR730FZ2T7 256 20x20 3 STR730FZ1H7 128 LFBGA144 STR730FZ2H7 256 10x10 10 16 32 112 STR735FZ1T7 128 TQFP144 STR735FZ2T7 256 20x20 0 STR735FZ1H7 128 LFBGA144 -40 to 16 1 STR735FZ2H7 256 10x10 +105°C STR731FV0T7 64 TQFP100 STR731FV1T7 128 3 14x14 STR731FV2T7 256 6 12 18 72 STR736FV0T7 64 TQFP100 STR736FV1T7 128 0 14x14 STR736FV2T7 256 49/52

Known limitations STR73xFxx 7 Known limitations 7.1 Low power wait for interrupt mode When the STR73x device is put in Low Power Wait For Interrupt mode (LPWFI), the Flash goes into low power mode or power down mode, depending on the setting of the PWD bit in the Flash Control Register 0 (default is ‘0’, Low Power mode). This default mode can create excessive voltage conditions on the transistor gates and may affect the long term behavior of the Low Power mode circuitry. Workaround There is no workaround. If Low Power Wait For Interrupt mode is used, it is strongly suggested to configure the Flash to enter power down mode (bit PWD = ‘1’). 7.2 PLL free running mode at high temperature When the STR73x device is operated and an ambient temperature (T ) of more than 55° C A and the main system clock (f ) is sourced by the PLL in free running mode, the device MCLK may not work properly. Workaround At high temperature (more than 55° C), it is recommended to use the internal RC oscillator as a backup clock source rather than the PLL free running mode. 50/52

STR73xFxx Revision history 8 Revision history T able 30. Document revision history Date Revision Description of changes 19-Sep-2005 1 First release Removed Table 8 power consumption in LP modes 02-Nov-2005 2 Updated PLL frequency in Section1.1 and Table12 Section3.4: Preliminary power consumption data updated 08-Mar-2006 3 Section3.5: DC electrical characteristics updated Section7: Known limitations added Section4: Electrical parameters updated Section7: Known limitations updated 04-Jun-2006 4 Added temperature range -40°C to 85°C in Section6: Order codes Changed Flash data retention to 20 years at 85°C in Table18 on 19-Jun-2006 5 page34. Changed Table24: Output driving current on page39 Added Figure14: VOL standard ports vs IOL @ VDD 5 V thru 08-Sep-2006 6 Figure18: VOL P6.0 pin vs IOL @ VDD 5 V on page40. Added Figure20: NRSTIN RPU vs. VDD Inch values rounded to 4 decimal digits in Section5.1: Package 08-Jun-2008 7 mechanical data Modified BSPI speed in Section2.1: On-chip peripherals 51/52

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