STQ2LN60K3-AP N-channel 600 V, 4 Ω typ., 0.6 A MDmesh™ K3 Power MOSFET in a TO-92 package Datasheet - production data Features Order code VDS RmDSa(oxn ) ID PTOT STQ2LN60K3-AP 600 V 4.5 Ω 0.6 A 2.5 W 3  100% avalanche tested 2  Extremely high dv/dt capability 1  Very low intrinsic capacitance TO-92 ammopack  Improved diode reverse recovery characteristics  Zener-protected Figure 1: Internal schematic diagram Applications D(2)  Switching applications Description This MDmesh™ K3 Power MOSFET is the result of improvements applied to STMicroelectronics’ G(1) MDmesh™ technology, combined with a new optimized vertical structure. This device boasts an extremely low on-resistance, superior dynamic performance and high avalanche capability, rendering it suitable for the most demanding applications. S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STQ2LN60K3-AP 2LN60K3 TO-92 Ammopack February 2017 DocID023499 Rev 3 1/13 This is information on a product in full production. www.st.com

Contents STQ2LN60K3-AP Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 TO-92 ammopack package information .......................................... 10 5 Revision history ............................................................................ 12 2/13 DocID023499 Rev 3

STQ2LN60K3-AP Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VGS Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 0.6 A ID Drain current (continuous) at TC = 100 °C 0.38 A IDM (1) Drain current (pulsed) 2.4 A PTOT Total dissipation at TC = 25 °C 2.5 W dv/dt (2) Peak diode recovery voltage slope 12 V/ns Tstg Storage temperature range -55 to 150 °C Tj Operating junction temperature range Notes: (1)Pulse width limited by safe operating area. (2)ISD ≤ 2 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 50 °C/W Rthj-amb Thermal resistance junction-ambient 120 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit Single pulse avalanche current IAS (pulse width limited by Tjmax) 2 A Single pulse avalanche energy EAS 80 mJ (starting TJ=25 °C, ID=IAR, VDD=50 V) DocID023499 Rev 3 3/13

Electrical characteristics STQ2LN60K3-AP 2 Electrical characteristics (T = 25 °C unless otherwise specified) CASE Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source V(BR)DSS ID = 1 mA, VGS = 0 V 600 V breakdown voltage VGS = 0 V, VDS = 600 V 1 Zero gate voltage drain IDSS current VGS = 0 V, VDS = 600 V, 50 µA TC= 125 °C (1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V Static drain-source on- RDS(on) resistance VGS = 10 V, ID = 1 A 4 4.5 Ω Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 235 - pF Coss Output capacitance VDS = 50 V, f = 1 MHz, - 22 - pF Reverse transfer VGS = 0 V Crss capacitance - 3.5 - pF Eq. capacitance time Co(tr)(1) related - 14 - pF VGS = 0 V, VDS = 0 to 480 V Eq. capacitance energy Co(er)(2) related - 10 pF Qg Total gate charge VDD = 480 V, ID = 1 A, - 12 - nC Qgs Gate-source charge VGS = 0 to 10 V - 1.8 - nC (see Figure 16: "Test circuit for Qgd Gate-drain charge gate charge behavior") - 7.7 - nC RG Gate input resistance f=1 MHz, ID=0 A - 7 - Ω Notes: (1)Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/13 DocID023499 Rev 3

STQ2LN60K3-AP Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 300 V, ID = 1 A, - 10 - ns tr Rise time RG = 4.7 Ω, VGS = 10 V - 8.5 - ns (see Figure 15: "Test circuit for td(off) Turn-off delay time resistive load switching times" - 23.5 - ns and Figure 20: "Switching time tf Fall time waveform") - 21 - ns Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD(1) Source-drain current - 0.6 A Source-drain current ISDM(1) (pulsed) - 2.4 A VSD(2) Forward on voltage ISD = 2 A, VGS = 0 V - 1.5 V trr Reverse recovery time ISD = 2 A, di/dt = 100 A/µs - 200 ns Qrr Reverse recovery charge VDD = 60 V - 800 nC (see Figure 17: "Test circuit for inductive load switching and IRRM Reverse recovery current - 8 A diode recovery times") trr Reverse recovery time ISD = 2 A, di/dt = 100 A/µs - 230 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 950 nC (see Figure 17: "Test circuit for inductive load switching and IRRM Reverse recovery current - 8.5 A diode recovery times") Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS= ±1 mA, ID= 0 A 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID023499 Rev 3 5/13

Electrical characteristics STQ2LN60K3-AP 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics ID AM13054v1 ID AM13055v1 (A) (A) VGS=10V VDS=15V 2.5 2.0 2.0 1.5 6V 1.5 1.0 1.0 0.5 0.5 5V 0 0 0 2 4 6 8 VDS(V) 0 2 4 6 8 VGS(V) Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance VGS AMV13D0S56v1 RDS(on) AM13057v1 (V) VDD=480V (V) (W) VGS=10V 12 ID=2A 4.2 500 VDS 10 4.0 400 8 3.8 300 6 3.6 200 4 3.4 2 100 3.2 0 0 3.0 0 5 10 Qg(nC) 0 0.2 0.4 0.6 0.8 1.0 1.2 ID(A) 6/13 DocID023499 Rev 3

STQ2LN60K3-AP Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics C AM13058v1 AM13063v1 VSD(V) (pF) TJ=-50°C 0.9 TJ=25°C Ciss 0.8 0.7 100 TJ=150°C 0.6 0.5 0.4 10 Coss 0.3 0.2 Crss 0.1 1 0 0.1 1 10 100 VDS(V) 0 1 2 3 4 5 ISD(A) Figure 10: Normalized gate threshold voltage vs Figure 11: Normalized on-resistance vs temperature temperature VGS(th) AM13060v1 RDS(on) AM13061v1 (norm) ID=50µA (norm) ID=1A 1.10 VGS=10V 2.5 1.00 2.0 1.5 0.90 1.0 0.80 0.5 0.70 0 -75 -25 25 75 125 TJ(°C) -75 -25 25 75 125 TJ(°C) Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Output capacitance stored energy V(BR)DSS AM13062v1 Eoss AM13059v1 (norm) (µJ) ID=1mA 1.10 1.5 1.05 1 1.00 0.5 0.95 0.90 0 -75 -25 25 75 125 TJ(°C) 0 100 200 300 400 500 600 VDS(V) DocID023499 Rev 3 7/13

Electrical characteristics STQ2LN60K3-AP Figure 14: Maximum avalanche energy vs temperature AM13064v1 EAS(mJ) 90 ID=2 A 80 VDD=50 V 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140TJ(°C) 8/13 DocID023499 Rev 3

STQ2LN60K3-AP Test circuits 3 Test circuits Figure 15: Test circuit for resistive load Figure 16: Test circuit for gate charge switching times behavior Figure 17: Test circuit for inductive load Figure 18: Unclamped inductive load test switching and diode recovery times circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID023499 Rev 3 9/13

Package information STQ2LN60K3-AP 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-92 ammopack package information Figure 21: TO-92 ammopack package outline T A1 T2 T1 H1 delta H H H3 H0 d L W2 l1 W W0 W1 F1 F2 F3 D0 t P2 P0 0050910_Rev_22 10/13 DocID023499 Rev 3

STQ2LN60K3-AP Package information Table 10: TO-92 ammopak mechanical data mm Dim. Min. Typ. Max. A1 4.80 T 3.80 T1 1.60 T2 2.30 d 0.45 0.47 0.48 P0 12.50 12.70 12.90 P2 5.65 6.35 7.05 F1, F2 2.40 2.50 2.94 F3 4.98 5.08 5.48 delta H -2.00 2.00 W 17.50 18.00 19.00 W0 5.50 6.00 6.50 W1 8.50 9.00 9.25 W2 0.50 H 18.50 21.00 H0 15.50 16.00 18.20 H1 25.00 27.00 H3 0.50 1.00 2.00 D0 3.80 4.00 4.20 t 0.90 L 11.00 I1 3.00 delta P -1.00 1.00 DocID023499 Rev 3 11/13

Revision history STQ2LN60K3-AP 5 Revision history Table 11: Document revision history Date Revision Changes 19-Jul-2012 1 First release. Modified title, features and description on cover page Modified Table 2: "Absolute maximum ratings", Table 5: "On/off states" and Table 9: "Gate-source Zener diode" 24-Jan-2017 2 Modified: Figure 11: "Normalized on-resistance vs temperature" Updated Section 4.1: "TO-92 ammopack package information" Minor text changes Modified Figure 2: "Safe operating area". 01-Feb-2017 3 Minor text changes. 12/13 DocID023499 Rev 3

STQ2LN60K3-AP IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID023499 Rev 3 13/13