STM8S207xx STM8S208xx Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash, integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN Datasheet - production data Features  Core – Max f : up to 24 MHz, 0 wait states @ CPU f 16 MHz CPU LQFP80 LQFP64 LQFP64 – Advanced STM8 core with Harvard 14 x 14 mm 14 x 14 mm 10 x 10 mm architecture and 3-stage pipeline – Extended instruction set – Max 20 MIPS @ 24 MHz  Memories – Program: up to 128 Kbytes Flash; data 7L Qx F7P m48m 1L0Q xF 1P04m4m 7L Qx F7P m32m retention 20 years at 55 °C after 10 kcycles – Data: up to 2 Kbytes true data EEPROM;  Communications interfaces endurance 300 kcycles – High speed 1 Mbit/s active beCAN 2.0B – RAM: up to 6 Kbytes – UART with clock output for synchronous operation - LIN master mode  Clock, reset and supply management – UART with LIN 2.1 compliant, master/slave – 2.95 to 5.5 V operating voltage modes and automatic resynchronization – Low power crystal resonator oscillator – SPI interface up to 10 Mbit/s – External clock input – I2C interface up to 400 Kbit/s – Internal, user-trimmable 16 MHz RC  10-bit ADC with up to 16 channels – Internal low power 128 kHz RC  I/Os – Clock security system with clock monitor – Up to 68 I/Os on an 80-pin package – Wait, active-halt, & halt low power modes including 18 high sink outputs – Peripheral clocks switched off individually – Highly robust I/O design, immune against – Permanently active, low consumption current injection power-on and power-down reset – Development support  Interrupt management – Single wire interface module (SWIM) and – Nested interrupt controller with 32 debug module (DM) interrupts  96-bit unique ID key for each device – Up to 37 external interrupts on 6 vectors  Timers Table 1. Device summary – 2x 16-bit general purpose timers, with 2+3 Reference Part number CAPCOM channels (IC, OC or PWM) – Advanced control timer: 16-bit, 4 CAPCOM STM8S207MB, STM8S207M8, STM8S207RB, STM8S207R8, STM8S207R6, STM8S207CB, channels, 3 complementary outputs, dead- STM8S207xx STM8S207C8, STM8S207C6, STM8S207SB, time insertion and flexible synchronization STM8S207S8, STM8S207S6, STM8S207K8, STM8S207K6 – 8-bit basic timer with 8-bit prescaler STM8S208MB, STM8S208RB, STM8S208R8, – Auto wakeup timer STM8S208R6, STM8S208CB, STM8S208C8, STM8S208xx STM8S208C6, STM8S208SB, STM8S208S8, – Window watchdog, independent watchdog STM8S208S6 February 2015 DocID14733 Rev 13 1/117 This is information on a product in full production. www.st.com

Contents STM8S207xx STM8S208xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14.5 beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Contents 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.6 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.7 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65 10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.1 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.1.1 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.1.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.1.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.1.4 LQFP44 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DocID14733 Rev 13 3/117 4

Contents STM8S207xx STM8S208xx 11.1.5 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 109 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .110 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4/117 DocID14733 Rev 13

STM8S207xx STM8S208xx List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16 Table 4. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. Flash, Data EEPROM and RAM boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 12. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 13. Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 14. Unique ID registers (96 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 19. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 20. Total current consumption with code execution in run mode at V = 5 V. . . . . . . . . . . . . 58 DD Table 21. Total current consumption with code execution in run mode at V = 3.3 V . . . . . . . . . . . 59 DD Table 22. Total current consumption in wait mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DD Table 23. Total current consumption in wait mode at V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DD Table 24. Total current consumption in active halt mode at V = 5 V, T -40 to 85° C . . . . . . . . . . 61 DD A Table 25. Total current consumption in active halt mode at V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . 61 DD Table 26. Total current consumption in halt mode at V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DD Table 27. Total current consumption in halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DD Table 28. Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 29. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 30. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 31. HSE user external clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 32. HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 34. LSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 36. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 37. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38. Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 40. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 41. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 43. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 44. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 45. ADC accuracy with R < 10 k, V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 AIN DDA Table 46. ADC accuracy with R < 10 kR , V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 AIN AIN DDA Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 48. EMI data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DocID14733 Rev 13 5/117 6

List of tables STM8S207xx STM8S208xx Table 49. ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 52. LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical . . . . . . . . . . . . . . . . 99 Table 55. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 57. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6/117 DocID14733 Rev 13

STM8S207xx STM8S208xx List of figures List of figures Figure 1. STM8S20xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4. LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 6. LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 9. Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 11. Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 12. f versus V CPUmax DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Figure 13. External capacitor C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 EXT Figure 14. Typ. I vs V , HSI RC osc,f = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DD(RUN) DD CPU Figure 15. Typ. I vs V , HSI RC osc, f = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DD(WFI) DD CPU Figure 16. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 18. Typical HSI frequency variation vs V at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 67 DD Figure 19. Typical LSI frequency variation vs V @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DD Figure 20. Typical V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 IL IH DD Figure 21. Typical pull-up resistance vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DD Figure 22. Typical pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DD Figure 23. Typ. V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 OL DD Figure 24. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 OL DD Figure 25. Typ. V @ V = 5 V (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 OL DD Figure 26. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 OL DD Figure 27. Typ. V @ V = 5 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 OL DD Figure 28. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 OL DD Figure 29. Typ. V - V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DD OH DD Figure 30. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DD OH DD Figure 31. Typ. V - V @ V = 5 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DD OH DD Figure 32. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DD OH DD Figure 33. Typical NRST V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 IL IH DD Figure 34. Typical NRST pull-up resistance vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79 DD Figure 35. Typical NRST pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DD Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 39. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 40. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 43. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 92 Figure 44. LQFP80 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 45. LQFP80 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 46. LQFP64 - 64-pin 14 mm x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 95 Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 96 Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . . 97 DocID14733 Rev 13 7/117 8

List of figures STM8S207xx STM8S208xx Figure 49. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 99 Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 100 Figure 52. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 53. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 102 Figure 54. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 104 Figure 55. LQFP44 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 105 Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 106 Figure 58. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 59. STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . 112 8/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Introduction 1 Introduction This datasheet contains the description of the STM8S20xxx features, pinout, electrical characteristics, mechanical data and ordering information.  For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).  For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).  For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).  For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). DocID14733 Rev 13 9/117 116

Description STM8S207xx STM8S208xx 2 Description The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual. All STM8S20xxx devices provide the following benefits: reduced system cost, performance robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Full documentation is offered with a wide choice of development tools. Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply. 10/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Description Table 2. STM8S20xxx performance line features y r o s m Device Pin count Max. number of GPIOs (I/O) Ext. interrupt pins Timer CAPCOM channels mer complementary output A/D converter channels High sink I/Os density Flash program me(bytes) Data EEPROM (bytes RAM (bytes) beCAN interface Ti h g Hi STM8S207MB 80 68 37 9 3 16 18 128 K 2048 6 K STM8S207M8 80 68 37 9 3 16 18 64 K 2048 6 K STM8S207RB 64 52 36 9 3 16 16 128 K 2048 6 K STM8S207R8 64 52 36 9 3 16 16 64 K 1536 6 K STM8S207R6 64 52 36 9 3 16 16 32 K 1024 6 K STM8S207CB 48 38 35 9 3 10 16 128 K 2048 6 K STM8S207C8 48 38 35 9 3 10 16 64 K 1536 6 K No STM8S207C6 48 38 35 9 3 10 16 32 K 1024 6 K STM8S207SB 44 34 31 8 3 9 15 128 K 1536 6 K STM8S207S8 44 34 31 8 3 9 15 64 K 1536 6 K STM8S207S6 44 34 31 8 3 9 15 32 K 1024 6 K STM8S207K8 32 25 23 8 3 7 12 64 K 1024 6 K STM8S207K6 32 25 23 8 3 7 12 32 K 1024 6 K STM8S208MB 80 68 37 9 3 16 18 128 K 2048 6 K STM8S208RB 64 52 37 9 3 16 16 128 K 2048 6 K STM8S208R8 64 52 37 9 3 16 16 64 K 2048 6 K STM8S208R6 64 52 37 9 3 16 16 32 K 2048 6 K STM8S208CB 48 38 35 9 3 10 16 128 K 2048 6 K Yes STM8S208C8 48 38 35 9 3 10 16 64 K 2048 6 K STM8S208C6 48 38 35 9 3 10 16 32 K 2048 6 K STM8S208SB 44 34 31 8 3 9 15 128 K 1536 6 K STM8S208S8 44 34 31 8 3 9 15 64 K 1536 6 K STM8S208S6 44 34 31 8 3 9 15 32 K 1536 6 K DocID14733 Rev 13 11/117 116

Block diagram STM8S207xx STM8S208xx 3 Block diagram Figure 1. STM8S20xxx block diagram Reset block XTAL 1-24 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR/PDR RC int. 128 kHz BOR Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire Debug/SWIM Up to 128 Kbytes debug interf. high density program Flash 400 Kbit/s I2C Up to 2 Kbytes data EEPROM s u 10 Mbit/s SPI a b Up to 6 Kbytes at RAM d d n a LIN master s Boot ROM SPI emul. UART1 es ddr Up to A 4 CAPCOM 16-bit advanced control Master/slave channels autosynchro UART3 timer (TIM1) + 3 complementary outputs 1 Mbit/s beCAN 16-bit general purpose Up to timers (TIM2, TIM3) 5 CAPCOM channels 16 channels ADC2 8-bit basic timer (TIM4) 1/2/4 kHz Beeper beep AWU timer 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area network BOR: Brownout reset I²C: Inter-integrated circuit multimaster interface Independent WDG: Independent watchdog POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module UART: Universal asynchronous receiver transmitter Window WDG: Window watchdog 12/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Product overview 4 Product overview The following section intends to give an overview of the basic features of the STM8S20xxx functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers  Harvard architecture  3-stage pipeline  32-bit wide program memory bus - single cycle fetching for most instructions  X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations  8-bit accumulator  24-bit program counter - 16-Mbyte linear memory space  16-bit stack pointer - access to a 64 K-level stack  8-bit condition code register - 7 condition flags for the result of the last instruction Addressing  20 addressing modes  Indexed indirect addressing mode for look-up tables located anywhere in the address space  Stack pointer relative addressing mode for local variables and parameter passing Instruction set  80 instructions with 2-byte average instruction size  Standard data movement and logic/arithmetic functions  8-bit by 8-bit multiplication  16-bit by 8-bit and 16-bit by 16-bit division  Bit manipulation  Data transfer between stack and accumulator (push/pop) with direct stack access  Data transfer using the X and Y registers or direct memory-to-memory transfers DocID14733 Rev 13 13/117 116

Product overview STM8S207xx STM8S208xx 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real- time by means of shadow registers.  R/W to RAM and peripheral registers in real-time  R/W access to all resources by stalling the CPU  Breakpoints on all program-memory instructions (software breakpoints)  Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller  Nested interrupts with three software priority levels  32 interrupt vectors with hardware priority  Up to 37 external interrupts on six vectors including TLI  Trap and reset interrupts 4.4 Flash program and data EEPROM memory  Up to 128 Kbytes of high density Flash program single voltage Flash memory  Up to 2K bytes true data EEPROM  Read while write: Writing in data memory possible while executing code in program memory.  User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. 14/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Product overview The size of the UBC is programmable through the UBC option byte (Table 13.), in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas:  Main program memory: Up to 128 Kbytes minus UBC  User-specific boot code (UBC): Configurable up to 128 Kbytes The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organization Data Data memory area (2 Kbytes) EEPROM memory Option bytes Programmable area from 1 Kbyte UBC area (2 first pages) up to 128 Kbytes Remains write protected during IAP (1 page steps) Up to 128Kbytes Flash program memory Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. DocID14733 Rev 13 15/117 116

Product overview STM8S207xx STM8S208xx 4.5 Clock controller The clock controller distributes the system clock (f coming from different oscillators MASTER) to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features  Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.  Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.  Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.  Master clock sources: Four different clock sources can be used to drive the master clock: – 1-24 MHz high-speed external crystal (HSE) – Up to 24 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI)  Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.  Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.  Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Peripheral Peripheral Peripheral Peripheral Bit Bit Bit Bit clock clock clock clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 beCAN PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved 16/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Product overview 4.6 Power management For efficient power management, the application can be put in one of four different low- power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.  Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.  Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.  Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.  Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. DocID14733 Rev 13 17/117 116

Product overview STM8S207xx STM8S208xx Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 Auto wakeup counter  Used for auto wakeup from active halt mode  Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock  LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver  16-bit up, down and up/down autoreload counter with 16-bit prescaler  Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output  Synchronization module to control the timer with external signals  Break input to force the timer outputs into a defined state  Three complementary outputs with adjustable dead time  Encoder mode  Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 TIM2, TIM3 - 16-bit general purpose timers  16-bit autoreload (AR) up-counter  15-bit prescaler adjustable to fixed power of 2 ratios 1…32768  Timers with 3 or 2 individually configurable capture/compare channels  PWM mode  Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 18/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Product overview 4.12 TIM4 - 8-bit basic timer  8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128  Clock source: CPU clock  Interrupt source: 1 x overflow/update Table 4. TIM timer features Timer Counter Counting CAPCOM Complem. Ext. synchr- Timer size Prescaler mode channels outputs trigger onization/ (bits) chaining TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4.13 Analog-to-digital converter (ADC2) STM8S20xxx performance line products contain a 10-bit successive approximation A/D converter (ADC2) with up to 16 multiplexed input channels and the following main features:  Input voltage range: 0 to V DDA  Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices  Conversion time: 14 clock cycles  Single and continuous modes  External trigger input  Trigger from TIM1 TRGO  End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are implemented:  UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode, IrDA mode, single wire mode.  UART3: Full feature UART, LIN2.1 master/slave capability  SPI: Full and half-duplex, 10 Mbit/s  I²C: Up to 400 Kbit/s  beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s DocID14733 Rev 13 19/117 116

Product overview STM8S207xx STM8S208xx 4.14.1 UART1 Main features  One Mbit/s full duplex SCI  SPI emulation  High precision baud rate generator  Smartcard emulation  IrDA SIR encoder decoder  LIN master mode  Single wire half duplex mode Asynchronous communication (UART mode)  Full duplex communication - NRZ standard format (mark/space)  Programmable transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of CPU following any standard baud rate regardless of the input frequency  Separate enable bits for transmitter and receiver  Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt)  Transmission error detection with interrupt generation  Parity control Synchronous communication  Full duplex synchronous transfers  SPI master operation  8-bit data communication  Maximum speed: 1 Mbit/s at 16 MHz (f /16) CPU LIN master mode  Emission: Generates 13-bit sync break frame  Reception: Detects 11-bit break frame 4.14.2 UART3 Main features  1 Mbit/s full duplex SCI  LIN master capable  High precision baud rate generator 20/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Product overview Asynchronous communication (UART mode)  Full duplex communication - NRZ standard format (mark/space)  Programmable transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of CPU following any standard baud rate regardless of the input frequency  Separate enable bits for transmitter and receiver  Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt)  Transmission error detection with interrupt generation  Parity control LIN master capability  Emission: Generates 13-bit sync break frame  Reception: Detects 11-bit break frame LIN slave mode  Autonomous header handling - one single interrupt per valid message header  Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%  Sync delimiter checking  11-bit LIN sync break detection - break detection always active  Parity check on the LIN identifier field  LIN error management  Hot plugging support 4.14.3 SPI  Maximum speed: 10 Mbit/s (f /2) both for master and slave MASTER  Full duplex synchronous transfers  Simplex synchronous transfers on two lines with a possible bidirectional data line  Master or slave operation - selectable by hardware or software  CRC calculation  1 byte Tx and Rx buffer  Slave/master selection input pin DocID14733 Rev 13 21/117 116

Product overview STM8S207xx STM8S208xx 4.14.4 I2C  I2C master features: – Clock generation – Start and stop generation  I2C slave features: – Programmable I2C address detection – Stop bit detection  Generation and detection of 7-bit/10-bit addressing and general call  Supports different communication speeds: – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz) 4.14.5 beCAN The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. For safety-critical applications the beCAN controller provides all hardware functions to support the CAN time triggered communication option (TTCAN). The maximum transmission speed is 1 Mbit. Transmission  Three transmit mailboxes  Configurable transmit priority by identifier or order request  Time stamp on SOF transmission Reception  8-, 11- and 29-bit ID  One receive FIFO (3 messages deep)  Software-efficient mailbox mapping at a unique address space  FMI (filter match index) stored with message  Configurable FIFO overrun  Time stamp on SOF reception  Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID  Filtering modes: – Mask mode permitting ID range filtering – ID list mode  Time triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Configurable timer resolution – Time stamp sent in last two data bytes 22/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description 5 Pinouts and pin description 5.1 Package pinouts Figure 3. LQFP 80-pin pinout O] C C _ K L C EEP]DC_ETR]M2_CH3] M1_BKIN] [ BATI TI PD7/TLIPD6/UART3_RXPD5/UART3_TXPD4 (HS)/TIM2_CH1 [PD3 (HS)/TIM2_CH2 [PD2 (HS)/TIM3_CH1 [PD1 (HS)/SWIMPD0 (HS)/TIM3_CH2 [PI7PI6PE0 (HS)/CLK_CCOPE1(T)/I2C_SCLPE2 (T]/I 2C_SDAPE3/TIM1_BKINPE4PG7PG6PG5PI5PI4 09876543210987654321 87777777777666666666 NRST 1 60 PI3 OSCIN/PA1 2 59 PI2 OSCOUT/PA2 3 58 PI1 VSSIO_1 4 57 PI0 VSS 5 56 PG4 VCAP 6 55 PG3 VDD 7 54 PG2 VDDIO_1 8 53 PG1/CAN_RX [TIM3_CH1] TIM2_CH3/PA3 9 52 PG0/CAN_TX UART1_RX/ (HS) PA4 10 51 PC7 (HS)/SPI_MISO UART1_TX/ (HS) PA5 11 50 PC6 (HS)/SPI_MOSI UART1_CK/ (HS) PA6 12 49 VDDIO_2 (HS) PH0 13 48 VSSIO_2 (HS) PH1 14 47 PC5 (HS)/SPI_SCK PH2 15 46 PC4 (HS)/TIM1_CH4 PH3 16 45 PC3 (HS)/TIM1_CH3 AIN15/PF7 17 44 PC2 (HS)/TIM1_CH2 AIN14/PF6 18 43 PC1 (HS)/TIM1_CH1 AIN13/PF5 19 42 PC0/ADC_ETR AIN12/PF4 20 41 PE5/SPI_NSS 12345678901234567890 22222222233333333334 AIN11/PF3VREF+VDDAVSSAVREF-AIN10/PF0AIN7/PB7AIN6/PB6SDA] AIN5/PB5SCL] AIN4/PB4ETR] AIN3/PB3H3N] AIN2/PB2H2N] AIN1/PB1H1N] AIN0/PB0TIM1_ETR/PH4M1_CH3N/PH5M1_CH2N/PH6 M1_CH1N/PH7AIN8/PE7AIN9/PE6 2C_2C_M1_1_C1_C1_C TITITI [I[ITIMMM [TITITI [[[ 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. DocID14733 Rev 13 23/117 116

Pinouts and pin description STM8S207xx STM8S208xx Figure 4. LQFP 64-pin pinout O] C C _ K L C 7/TLI6/UART3_RX5/UART3_TX4 (HS)/TIM2_CH1 [BEEP]3 (HS)/TIM2_CH2[ADC_ETR]2 (HS)/TIM3_CH1[TIM2_CH3]1 (HS)/SWIM0 (HS)/TIM3_CH2 [TIM1_BKIN] [0 (HS)/CLK_CCO1 (T)/I2C_SCL2 (T)/I2C_SDA3/TIM1_BKIN4765 DDDDDDDDEEEEEGGG PPPPPPPPPPPPPPPP 64636261605958575655545352515049 NRST 1 48 PI0 OSCIN/PA1 2 47 PG4 OSCOUT/PA2 3 46 PG3 VSSIO_1 4 45 PG2 VSS 5 44 PG1/CAN_RX VCAP 6 43 PG0/CAN_TX VDD 7 42 PC7 (HS)/SPI_MISO VDDIO_1 8 41 PC6 (HS)/SPI_MOSI [TIM3_CH1] TIM2_CH3/PA3 9 40 VDDIO_2 UART1_RX/ (HS) PA4 10 39 VSSIO_2 UART1_TX/ (HS) PA5 11 38 PC5 (HS)/SPI_SCK UART1_CK/ (HS) PA6 12 37 PC4 (HS)/TIM1_CH4 AIN15/PF7 13 36 PC3 (HS)/TIM1_CH3 AIN14/PF6 14 35 PC2 (HS)/TIM1_CH2 AIN13/PF5 15 34 PC1 (HS)/TIM1_CH1 AIN12/PF4 16 33 PE5/SPI_NSS 17181920212223242526272829303132 1/PF3VREF+ VDDAVSSAVREF- 0/PF07/PB76/PB65/PB54/PB43/PB32/PB21/PB10/PB08/PE79/PE6 1 1NNNNNNNNNN AIN AINAIAIA] AIL] AIR] AIN] AIN] AIN] AIAIAI DCT321 SSEHHH ___CCC 2C2CM11_1_1_ [I[ITIMMM [TITITI [[[ 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. 24/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description Figure 5. LQFP 48-pin pinout O] C C _ K L C EEP]DC_ETR]M2_CH3] M1_BKIN] [ BATI TI PD7/TLIPD6/UART3_RXPD5/UART3_TXPD4 (HS)/TIM2_CH1 [PD3 (HS)/TIM2_CH2 [PD2 (HS)/TIM3_CH1 [PD1 (HS)/SWIMPD0 (HS)/TIM3_CH2 [PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDAPE3/TIM1_BKIN 484746454443424140393837 NRST 1 36 PG1/CAN_RX OSCIN/PA1 2 35 PG0/CAN_TX OSCOUT/PA2 3 34 PC7 (HS)/SPI_MISO VSSIO_1 4 33 PC6 (HS)/SPI_MOSI VSS 5 32 VDDIO_2 VCAP 6 31 VSSIO_2 VDD 7 30 PC5 (HS)/SPI_SCK VDDIO_1 8 29 PC4 (HS)/TIM1_CH4 [TIM3_CH1] TIM2_CH3/PA3 9 28 PC3 (HS)/TIM1_CH3 UART1_RX/(HS) PA4 10 27 PC2 (HS)/TIM1_CH2 UART1_TX/(HS) PA5 11 26 PC1 (HS)/TIM1_CH1 UART1_CK/(HS) PA6 12 25 PE5/SPI_NSS 131415161718192021222324 AA7654321076 DSBBBBBBBBEE DSPPPPPPPPPP VV7/6/5/4/3/2/1/0/8/9/ NNNNNNNNNN AIAIAIAIAIAIAIAIAIAI A] L] R/N] N] N] [I2C_SD[I2C_SC[TIM1_ETTIM1_CH3TIM1_CH2TIM1_CH1 [[[ 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. DocID14733 Rev 13 25/117 116

Pinouts and pin description STM8S207xx STM8S208xx Figure 6. LQFP 44-pin pinout O] C C _ K L C ETR]CH3] BKIN] [ 7/TLI [TIM1_CH4]6/UART3_RX5/UART3_TX4 (HS)/TIM2_CH1[BEEP]3 (HS)/TIM2_CH2 [ADC_2 (HS)/TIM3_CH1 [TIM2_1 (HS)/SWIM0 (HS)/TIM3_CH2 [TIM1_0 (HS)/CLK_CCO1 (T)/I2C_SCL2 (T)/I2C_SDA DDDDDDDDEEE PPPPPPPPPPP 4443424140393837363534 NRST 1 33 PG1/CAN_RX OSCIN/PA1 2 32 PG0/CAN_TX OSCOUT/PA2 3 31 PC7 (HS)/SPI_MISO VSSIO_1 4 30 PC6 (HS)/SPI_MOSI VSS 5 29 VDDIO_2 VCAP 6 28 VSSIO_2 VDD 7 27 PC5 (HS)/SPI_SCK VDDIO_1 8 26 PC3 (HS)/TIM1_CH3 UART1_RX 9 25 PC2 (HS)/TIM1_CH2 UART1_TX/ 10 24 PC1 (HS)/TIM1_CH1 UART1_CK 11 23 PE5/SPI_NSS 1213141516171819202122 AA765432106 DSBBBBBBBBE DSPPPPPPPPP VV7/6/5/4/3/2/1/0/9/ NNNNNNNNN AIAIAIAIAIAIAIAIAI A] L] R] N] N] N] DCT321 SSEHHH ___CCC 2C2CM11_1_1_ [I[ITIMMM [TITITI [[( 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. 26/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description Figure 7. LQFP 32-pin pinout O] C C _ K L C TR]H3] KIN] [ EEP] DC_EM2_C M1_B 1 [B2 [A1[TI 2 [TI HHH H CCC C XX ___M_ _R_TM2M2M3WIM3 7/TLI6/UART35/UART34 (HS)/TI3 (HS)/TI2 (HS)/TI1 (HS)/S0 (HS)/TI DDDDDDDD PPPPPPPP 3231302928272625 NRST 1 24 PC7 (HS)/SPI_MISO OSCIN/PA1 2 23 PC6 (HS)/SPI_MOSI OSCOUT/PA2 3 22 PC5 (HS)/SPI_SCK VSS 4 21 PC4 (HS)/TIM1_CH4 VCAP 5 20 PC3 (HS)/TIM1_CH3 VDD 6 19 PC2 (HS)/TIM1_CH2 VDDIO 7 18 PC1 (HS)/TIM1_CH1 AIN12/PF4 8 17 PE5/SPI_NSS 910111213141516 AA543210 DSBBBBBB DSPPPPPP VV5/4/3/2/1/0/ NNNNNN AIAIAIAIAIAI A] L] R] N] N] N] DCT321 SSEHHH ___CCC 2C2CM11_1_1_ [I[ITIMMM [TITITI [[[ 1. (HS) high sink capability. 2. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14733 Rev 13 27/117 116

Pinouts and pin description STM8S207xx STM8S208xx Table 5. Legend/abbreviations for pinout table Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz)  O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset  O4 = Fast/slow programmability with fast as default state after reset Port and control Input float = floating, wpu = weak pull-up configuration Output T = True open drain, OD = Open drain, PP = Push pull Reset state Bold X (pin state after internal reset release) Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. Table 6. Pin description Pin number Input Output n LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 Pin name Type floating wpu xt. interrupt High sink Speed OD PP Main functio(after reset) afDultneecfrantiuaoltnte a[oAfftpuelttnrei ocrrentnimao btnaeit p ] E 1 1 1 1 1 NRST I/O X Reset Resonator/ 2 2 2 2 2 PA1/OSCIN I/O X X O1 X X Port A1 crystal in Resonator/ 3 3 3 3 3 PA2/OSCOUT I/O X X X O1 X X Port A2 crystal out 4 4 4 4 - V S I/O ground SSIO_1 5 5 5 5 4 V S Digital ground SS 6 6 6 6 5 VCAP S 1.8 V regulator capacitor 7 7 7 7 6 V S Digital power supply DD 8 8 8 8 7 V S I/O power supply DDIO_1 Timer 2 - TIM3_CH1 9 9 9 - - PA3/TIM2_CH3 I/O X X X O1 X X Port A3 channel3 [AFR1] PA4/UART1_RX UART1 10 10 10 9 - I/O X X X HS O3 X X Port A4 (1) receive UART1 11 11 11 10 - PA5/UART1_TX I/O X X X HS O3 X X Port A5 transmit 28/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description Table 6. Pin description (continued) Pin number Input Output n LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 Pin name Type floating wpu xt. interrupt High sink Speed OD PP Main functio(after reset) afDultneecfrantiuaoltnte a[oAfftpuelttnrei ocrrentnimao btnaeit p ] E UART1 12 12 12 11 - PA6/UART1_CK I/O X X X HS O3 X X Port A6 synchronous clock 13 - - - - PH0 I/O X X HS O3 X X Port H0 14 - - - - PH1 I/O X X HS O3 X X Port H1 15 - - - - PH2 I/O X X O1 X X Port H2 16 - - - - PH3 I/O X X O1 X X Port H3 Analog  17 13 - - - PF7/AIN15 I/O X X O1 X X Port F7 input 15 Analog  18 14 - - - PF6/AIN14 I/O X X O1 X X Port F6 input 14 Analog  19 15 - - - PF5/AIN13 I/O X X O1 X X Port F5 input 13 Analog  20 16 - - 8 PF4/AIN12 I/O X X O1 X X Port F4 input 12 Analog  21 17 - - - PF3/AIN11 I/O X X O1 X X Port F3 input 11 ADC positive reference 22 18 - - - V S REF+ voltage 23 19 13 12 9 V S Analog power supply DDA 24 20 14 13 10 V S Analog ground SSA ADC negative reference 25 21 - - - V S REF- voltage Analog  26 22 - - - PF0/AIN10 I/O X X O1 X X Port F0 input 10 Analog  27 23 15 14 - PB7/AIN7 I/O X X X O1 X X Port B7 input 7 Analog  28 24 16 15 - PB6/AIN6 I/O X X X O1 X X Port B6 input 6 Analog  I2C_SDA 29 25 17 16 11 PB5/AIN5 I/O X X X O1 X X Port B5 input 5 [AFR6] Analog  I2C_SCL 30 26 18 17 12 PB4/AIN4 I/O X X X O1 X X Port B4 input 4 [AFR6] DocID14733 Rev 13 29/117 116

Pinouts and pin description STM8S207xx STM8S208xx Table 6. Pin description (continued) Pin number Input Output n LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 Pin name Type floating wpu xt. interrupt High sink Speed OD PP Main functio(after reset) afDultneecfrantiuaoltnte a[oAfftpuelttnrei ocrrentnimao btnaeit p ] E Analog  TIM1_ETR 31 27 19 18 13 PB3/AIN3 I/O X X X O1 X X Port B3 input 3 [AFR5] TIM1_ Analog  32 28 20 19 14 PB2/AIN2 I/O X X X O1 X X Port B2 CH3N input 2 [AFR5] TIM1_ Analog  33 29 21 20 15 PB1/AIN1 I/O X X X O1 X X Port B1 CH2N input 1 [AFR5] TIM1_ Analog  34 30 22 21 16 PB0/AIN0 I/O X X X O1 X X Port B0 CH1N input 0 [AFR5] Timer 1 - 35 - - - - PH4/TIM1_ETR I/O X X O1 X X Port H4 trigger input Timer 1 - 36 - - - - PH5/ TIM1_CH3N I/O X X O1 X X Port H5 inverted channel 3 Timer 1 - 37 - - - - PH6/ TIM1_CH2N I/O X X O1 X X Port H6 inverted channel 2 Timer 1 - 38 - - - - PH7/ TIM1_CH1N I/O X X O1 X X Port H7 inverted channel 2 39 31 23 - - PE7/AIN8 I/O X X X O1 X X Port E7 Analog input 8 40 32 24 22 - PE6/AIN9 I/O X X X O1 X X Port E6 Analog input 9 SPI 41 33 25 23 17 PE5/SPI_NSS I/O X X X O1 X X Port E5 master/slave select ADC trigger 42 - - - - PC0/ADC_ETR I/O X X X O1 X X Port C0 input Timer 1 - 43 34 26 24 18 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 channel 1 Timer 1- 44 35 27 25 19 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 channel 2 Timer 1 - 45 36 28 26 20 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 channel 3 30/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description Table 6. Pin description (continued) Pin number Input Output n LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 Pin name Type floating wpu xt. interrupt High sink Speed OD PP Main functio(after reset) afDultneecfrantiuaoltnte a[oAfftpuelttnrei ocrrentnimao btnaeit p ] E Timer 1 - 46 37 29 - 21 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4 channel 4 47 38 30 27 22 PC5/SPI_SCK I/O X X X HS O3 X X Port C5 SPI clock 48 39 31 28 - V S I/O ground SSIO_2 49 40 32 29 - V S I/O power supply DDIO_2 SPI master 50 41 33 30 23 PC6/SPI_MOSI I/O X X X HS O3 X X Port C6 out/ slave in SPI master in/ 51 42 34 31 24 PC7/SPI_MISO I/O X X X HS O3 X X Port C7 slave out beCAN 52 43 35 32 - PG0/CAN_TX(2) I/O X X O1 X X Port G0 transmit beCAN 53 44 36 33 - PG1/CAN_RX(2) I/O X X O1 X X Port G1 receive 54 45 - - - PG2 I/O X X O1 X X Port G2 55 46 - - - PG3 I/O X X O1 X X Port G3 56 47 - - - PG4 I/O X X O1 X X Port G4 57 48 - - - PI0 I/O X X O1 X X Port I0 58 - - - - PI1 I/O X X O1 X X Port I1 59 - - - - PI2 I/O X X O1 X X Port I2 60 - - - - PI3 I/O X X O1 X X Port I3 61 - - - - PI4 I/O X X O1 X X Port I4 62 - - - - PI5 I/O X X O1 X X Port I5 63 49 - - - PG5 I/O X X O1 X X Port G5 64 50 - - - PG6 I/O X X O1 X X Port G6 65 51 - - - PG7 I/O X X O1 X X Port G7 66 52 - - - PE4 I/O X X X O1 X X Port E4 Timer 1 -  67 53 37 - - PE3/TIM1_BKIN I/O X X X O1 X X Port E3 break input 68 54 38 34 - PE2/I2C_SDA I/O X X O1 T(3) Port E2 I2C data DocID14733 Rev 13 31/117 116

Pinouts and pin description STM8S207xx STM8S208xx Table 6. Pin description (continued) Pin number Input Output n LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 Pin name Type floating wpu xt. interrupt High sink Speed OD PP Main functio(after reset) afDultneecfrantiuaoltnte a[oAfftpuelttnrei ocrrentnimao btnaeit p ] E 69 55 39 35 - PE1/I2C_SCL I/O X X O1 T(3) Port E1 I2C clock Configurable 70 56 40 36 - PE0/CLK_CCO I/O X X X HS O3 X X Port E0 clock output 71 - - - - PI6 I/O X X O1 X X Port I6 72 - - - - PI7 I/O X X O1 X X Port I7 TIM1_BKIN Timer 3 - [AFR3]/ 73 57 41 37 25 PD0/TIM3_CH2 I/O X X X HS O3 X X Port D0 channel 2 CLK_CCO [AFR2] SWIM data 74 58 42 38 26 PD1/SWIM(4) I/O X X X HS O4 X X Port D1 interface Timer 3 - TIM2_CH3 75 59 43 39 27 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2 channel 1 [AFR1] Timer 2 - ADC_ETR 76 60 44 40 28 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3 channel 2 [AFR0] PD4/TIM2_CH1/B Timer 2 - BEEP output 77 61 45 41 29 I/O X X X HS O3 X X Port D4 EEP channel 1 [AFR7] UART3 data 78 62 46 42 30 PD5/ UART3_TX I/O X X X O1 X X Port D5 transmit PD6/ UART3 data 79 63 47 43 31 I/O X X X O1 X X Port D6 UART3_RX(1) receive Top level TIM1_CH4 80 64 48 44 32 PD7/TLI I/O X X X O1 X X Port D7 interrupt [AFR4](5) 1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader. 2. The beCAN interface is available on STM8S208xx devices only 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V are DD not implemented). 4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release. 5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0. 5.2 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function 32/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Pinouts and pin description remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). DocID14733 Rev 13 33/117 116

Memory and register map STM8S207xx STM8S208xx 6 Memory and register map 6.1 Memory map Figure 8. Memory map 0x00 0000 RAM (up to 6 Kbytes) 0x00 17FF 1024bytesstack 0x00 1800 Reserved 0x00 3FFF 0x00 4000 Up to 2 Kbytes data EEPROM 0x00 47FF 0x00 4800 Option bytes 0x00 487F 0x00 4900 Reserved 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF (see Table 8 an d Table 9) 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 CPU/SWIM/debug/ITC 0x00 7FFF registers(see Table 10) 0x00 8000 32 interrupt vectors 0x00 807F 0x00 8080 Flash program memory (64 to 128 Kbytes) 0x02 7FFF 34/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Memory area Size (bytes) Start address End address 128 K 0x00 8000 0x02 7FFF Flash program memory 64 K 0x00 8000 0x01 7FFF 32 K 0x00 8000 0x00 FFFF 6 K 0x00 0000 0x00 17FF RAM 4 K 0x00 0000 0x00 1000 2 K 0x00 0000 0x00 07FF 2048 0x00 4000 0x00 47FF Data EEPROM 1536 0x00 4000 0x00 45FF 1024 0x00 4000 0x00 43FF 6.2 Register map Table 8. I/O port hardware register map Reset Address Block Register label Register name status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 DocID14733 Rev 13 35/117 116

Memory and register map STM8S207xx STM8S208xx Table 8. I/O port hardware register map (continued) Reset Address Block Register label Register name status 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Port E PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0x00 0x00 5020 Port G PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0x00 0x00 5025 Port H PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0x00 0x00 502A Port I PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 36/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 9. General hardware register map Reset Address Block Register label Register name status 0x00 5050 to Reserved area (10 bytes) 0x00 5059 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF Flash 0x00 505D FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF Flash in-application programming status 0x00 505F FLASH _IAPSR 0x00 register 0x00 5060 to Reserved area (2 bytes) 0x00 5061 Flash Program memory unprotection 0x00 5062 Flash FLASH _PUKR 0x00 register 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to Reserved area (59 bytes) 0x00 509F 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 ITC 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to Reserved area (17 bytes) 0x00 50B2 0x00 50B3 RST RST_SR Reset status register 0xXX(1) 0x00 50B4 to Reserved area (12 bytes) 0x00 50BF 0x00 50C0 CLK_ICKR Internal clock control register 0x01 CLK 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CB CLK_CANCCR CAN clock control register 0x00 DocID14733 Rev 13 37/117 116

Memory and register map STM8S207xx STM8S208xx Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK 0bXXXX 0x00 50CD CLK_SWIMCCR SWIM clock control register XXX0 0x00 50CE to Reserved area (3 bytes) 0x00 50D0 0x00 50D1 WWDG_CR WWDG control register 0x7F WWDG 0x00 50D2 WWDG_WR WWDR window register 0x7F 0x00 50D3 to Reserved area (13 bytes) 0x00 50DF 0x00 50E0 IWDG_KR IWDG key register 0xXX(2) 0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to Reserved area (13 bytes) 0x00 50EF 0x00 50F0 AWU_CSR1 AWU control/status register 1 0x00 0x00 50F1 AWU AWU_APR AWU asynchronous prescaler buffer register 0x3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to Reserved area (12 bytes) 0x00 50FF 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 SPI 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5208 to Reserved area (8 bytes) 0x00 520F 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 I2C 0x00 5213 I2C_OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 Reserved 38/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5216 I2C_DR I2C data register 0x00 0x00 5217 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 I2C 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E to Reserved area (18 bytes) 0x00 522F 0x00 5230 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 523B to Reserved area (5 bytes) 0x00 523F 0x00 5240 UART3_SR UART3 status register C0h 0x00 5241 UART3_DR UART3 data register 0xXX 0x00 5242 UART3_BRR1 UART3 baud rate register 1 0x00 0x00 5243 UART3_BRR2 UART3 baud rate register 2 0x00 0x00 5244 UART3_CR1 UART3 control register 1 0x00 UART3 0x00 5245 UART3_CR2 UART3 control register 2 0x00 0x00 5246 UART3_CR3 UART3 control register 3 0x00 0x00 5247 UART3_CR4 UART3 control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3_CR6 UART3 control register 6 0x00 0x00 524A to Reserved area (6 bytes) 0x00 524F DocID14733 Rev 13 39/117 116

Memory and register map STM8S207xx STM8S208xx Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 TIM1 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 0x00 5270 to Reserved area (147 bytes) 0x00 52FF 40/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 0x00 530A TIM2 TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530C0x TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 0x00 5315 to Reserved area (11 bytes) 0x00 531F 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 DocID14733 Rev 13 41/117 116

Memory and register map STM8S207xx STM8S208xx Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 TIM3 0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 5331 to Reserved area (15 bytes) 0x00 533F 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5347 to Reserved area (185 bytes) 0x00 53FF 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 ADC2 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 to Reserved area (24 bytes) 0x00 541F 0x00 5420 CAN_MCR CAN master control register 0x02 0x00 5421 CAN_MSR CAN master status register 0x02 0x00 5422 CAN_TSR CAN transmit status register 0x00 0x00 5423 CAN_TPR CAN transmit priority register 0x0C beCAN 0x00 5424 CAN_RFR CAN receive FIFO register 0x00 0x00 5425 CAN_IER CAN interrupt enable register 0x00 0x00 5426 CAN_DGR CAN diagnosis register 0x0C 0x00 5427 CAN_FPSR CAN page selection register 0x00 42/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 9. General hardware register map (continued) Reset Address Block Register label Register name status 0x00 5428 CAN_P0 CAN paged register 0 0xXX(3) 0x00 5429 CAN_P1 CAN paged register 1 0xXX(3) 0x00 542A CAN_P2 CAN paged register 2 0xXX(3) 0x00 542B CAN_P3 CAN paged register 3 0xXX(3) 0x00 542C CAN_P4 CAN paged register 4 0xXX(3) 0x00 542D CAN_P5 CAN paged register 5 0xXX(3) 0x00 542E CAN_P6 CAN paged register 6 0xXX(3) 0x00 542F CAN_P7 CAN paged register 7 0xXX(3) beCAN 0x00 5430 CAN_P8 CAN paged register 8 0xXX(3) 0x00 5431 CAN_P9 CAN paged register 9 0xXX(3) 0x00 5432 CAN_PA CAN paged register A 0xXX(3) 0x00 5433 CAN_PB CAN paged register B 0xXX(3) 0x00 5434 CAN_PC CAN paged register C 0xXX(3) 0x00 5435 CAN_PD CAN paged register D 0xXX(3) 0x00 5436 CAN_PE CAN paged register E 0xXX(3) 0x00 5437 CAN_PF CAN paged register F 0xXX(3) 0x00 5438 to Reserved area (968 bytes) 0x00 57FF 1. Depends on the previous reset source. 2. Write only register. 3. If the bootloader is enabled, it is initialized to 0x00. DocID14733 Rev 13 43/117 116

Memory and register map STM8S207xx STM8S208xx Table 10. CPU/SWIM/debug module/interrupt controller registers Reset Address Block Register Label Register Name Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU(1) XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17(2) 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 0x00 7F0B to Reserved area (85 bytes) 0x00 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF ITC 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F78 to Reserved area (2 bytes) 0x00 7F79 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 0x00 7F81 to Reserved area (15 bytes) 0x00 7F8F 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF DM 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 44/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Memory and register map Table 10. CPU/SWIM/debug module/interrupt controller registers (continued) Reset Address Block Register Label Register Name Status 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F9B to Reserved area (5 bytes) 0x00 7F9F 1. Accessible by debug module only 2. Product dependent value, see Figure 8: Memory map. DocID14733 Rev 13 45/117 116

Interrupt vector mapping STM8S207xx STM8S208xx 7 Interrupt vector mapping Table 11. Interrupt mapping IRQ Source Wakeup from Wakeup from Description Vector address no. block Halt mode Active-halt mode RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt - - 0x00 8004 0 TLI External top level interrupt - - 0x00 8008 1 AWU Auto wake up from halt - Yes 0x00 800C 2 CLK Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes(1) Yes(1) 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 beCAN beCAN RX interrupt Yes Yes 0x00 8028 9 beCAN beCAN TX/ER/SC interrupt - - 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 TIM1 update/overflow/underflow/ 11 TIM1 - - 0x00 8034 trigger/break 12 TIM1 TIM1 capture/compare - - 0x00 8038 13 TIM2 TIM2 update /overflow - - 0x00 803C 14 TIM2 TIM2 capture/compare - - 0x00 8040 15 TIM3 Update/overflow - - 0x00 8044 16 TIM3 Capture/compare - - 0x00 8048 17 UART1 Tx complete - - 0x00 804C 18 UART1 Receive register DATA FULL - - 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 20 UART3 Tx complete - - 0x00 8058 21 UART3 Receive register DATA FULL - - 0x00 805C 22 ADC2 ADC2 end of conversion - - 0x00 8060 23 TIM4 TIM4 update/overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 0x00 806C to Reserved 0x00 807C 1. Except PA1 46/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12. Option bytes Option bits Factory Option Option Addr. default name byte no. 7 6 5 4 3 2 1 0 setting Read-out 4800h protection OPT0 ROP[7:0] 00h (ROP) 4801h OPT1 UBC[7:0] 00h User boot code (UBC) 4802h NOPT1 NUBC[7:0] FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 00h function remapping 4804h NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh (AFR) LSI IWDG WWDG WWDG 4805h OPT3 Reserved 00h _EN _HW _HW _HALT Watchdog option NLSI NIWDG NWWDG NWWDG 4806h NOPT3 Reserved FFh _EN _HW _HW _HALT EXT CKAWU PRS PRS 4807h OPT4 Reserved 00h CLK SEL C1 C0 Clock option NEXT NCKAWU NPR NPR 4808h NOPT4 Reserved FFh CLK SEL SC1 SC0 4809h OPT5 HSECNT[7:0] 00h HSE clock startup 480Ah NOPT5 NHSECNT[7:0] FFh 480Bh OPT6 Reserved 00h Reserved 480Ch NOPT6 Reserved FFh 480Dh OPT7 Reserved Wait state 00h Flash wait states 480Eh NOPT7 Reserved Nwait state FFh 487Eh OPTBL BL[7:0] 00h Bootloader 487Fh NOPTBL NBL[7:0] FFh DocID14733 Rev 13 47/117 116

Option bytes STM8S207xx STM8S208xx Table 13. Option byte description Option byte no. Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol)  OPT0 Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 to 1 defined as UBC, memory write-protected 0x02: Pages 0 to 3 defined as UBC, memory write-protected 0x03: Pages 0 to 4 defined as UBC, memory write-protected OPT1 ... 0xFE: Pages 0 to 255 defined as UBC, memory write-protected 0xFF: Reserved Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details. AFR7Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CH1 1: Port D4 alternate function = BEEP AFR6 Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL AFR5 Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,  port B1 alternate function = AIN1, port B0 alternate function = AIN0 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N AFR4 Alternate function remapping option 4 0: Port D7 alternate function = TLI OPT2 1: Port D7 alternate function = TIM1_CH4 AFR3 Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = TIM1_BKIN AFR2 Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CH3, port D2 alternate function TIM3_CH1 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function TIM2_CH3 AFR0 Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CH2 1: Port D3 alternate function = ADC_ETR 48/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Option bytes Table 13. Option byte description (continued) Option byte no. Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware OPT3 WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN CKAWUSEL: Auto wakeup unit/clock 0: LSI clock source selected for AWU OPT4 1: HSE clock with prescaler selected as clock source for AWU PRSC[1:0] AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilization time. 0x00: 2048 HSE cycles OPT5 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles OPT6 Reserved WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory.  OPT7 1 wait state is required if f > 16 MHz. CPU 0: No wait state 1: 1 wait state DocID14733 Rev 13 49/117 116

Option bytes STM8S207xx STM8S208xx Table 13. Option byte description (continued) Option byte no. Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) OPTBL for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. 50/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Unique ID 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited:  For use as serial numbers  For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory.  To activate secure boot processes Table 14. Unique ID registers (96 bits) Unique ID bits Content Address description 7 6 5 4 3 2 1 0 0x48CD U_ID[7:0] X co-ordinate on the wafer 0x48CE U_ID[15:8] 0x48CF U_ID[23:16] Y co-ordinate on the wafer 0x48D0 U_ID[31:24] 0x48D1 Wafer number U_ID[39:32] 0x48D2 U_ID[47:40] 0x48D3 U_ID[55:48] 0x48D4 U_ID[63:56] 0x48D5 Lot number U_ID[71:64] 0x48D6 U_ID[79:72] 0x48D7 U_ID[87:80] 0x48D8 U_ID[95:88] DocID14733 Rev 13 51/117 116

Electrical characteristics STM8S207xx STM8S208xx 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V . SS 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T = 25 °C and T = T (given by A A Amax the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 ). 10.1.2 Typical values Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V. They are given A DD only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, V , V and V are connected DD DDIO DDA together in the configuration shown in Figure 9. Figure 9. Supply current measurement conditions 5 V or 3.3 V A VDD VDDA VDDIO VSS VSSA VSSIO 52/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.1.5 Pin loading conditions 10.1.6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions STM8 pin 50 pF 10.1.7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage STM8 pin VIN DocID14733 Rev 13 53/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Voltage characteristics Symbol Ratings Min Max Unit V - V Supply voltage (including V V )(1) -0.3 6.5 DDx SS DDA and DDIO Input voltage on true open drain pins (PE1, PE2)(2) V - 0.3 6.5 V SS V IN Input voltage on any other pin(2) V - 0.3 V + 0.3 SS DD |V - V | Variations between different power pins 50 DDx DD mV |V - V | Variations between all the different ground pins 50 SSx SS see Absolute maximum V Electrostatic discharge voltage ratings (electrical ESD sensitivity) on page 89 1. All power (V , V , V ) and ground (V , V , V ) pins must always be connected to the DD DDIO DDA SS SSIO SSA external power supply 2. I must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum INJ(PIN) IN IN cannot be respected, the injection current must be limited externally to the I value. A positive INJ(PIN) injection is induced by V >V while a negative injection is induced by V <V . For true open-drain pads, IN DD IN SS there is no positive injection current, and the corresponding V maximum must always be respected IN 54/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Table 16. Current characteristics Symbol Ratings Max.(1) Unit I Total current into V power lines (source)(2) 60 VDD DD I Total current out of V ground lines (sink)(2) 60 VSS SS Output current sunk by any I/O and control pin 20 I IO Output current source by any I/Os and control pin 20 Total output current sourced (sum of all I/O and control pins) 200 for devices with two V pins(3) DDIO Total output current sourced (sum of all I/O and control pins) 100 for devices with one V pin(3) DDIO I mA IO Total output current sunk (sum of all I/O and control pins) for 160 devices with two V pins(3) SSIO Total output current sunk (sum of all I/O and control pins) for 80 devices with one V pin(3) SSIO Injected current on NRST pin ±4 I (4)(5) Injected current on OSCIN pin ±4 INJ(PIN) Injected current on any other pin(6) ±4 I (4) Total injected current (sum of all I/O and control pins)(6) ±20 INJ(PIN) 1. Data based on characterization results, not tested in production. 2. All power (V , V , V ) and ground (V , V , V ) pins must always be connected to the DD DDIO DDA SS SSIO SSA external supply. 3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the V /V pins. DDIO SSIO 4. I must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum INJ(PIN) IN IN cannot be respected, the injection current must be limited externally to the I value. A positive INJ(PIN) injection is induced by V >V while a negative injection is induced by V <V . For true open-drain pads, IN DD IN SS there is no positive injection current, and the corresponding V maximum must always be respected IN 5. Negative injection disturbs the analog performance of the device. See note in Section 10.3.10: 10-bit ADC characteristics on page 85. 6. When several inputs are submitted to a current injection, the maximum I is the absolute sum of the INJ(PIN) positive and negative injected currents (instantaneous values). These results are based on characterization with I maximum current injection on four I/O port pins of the device. INJ(PIN) Table 17. Thermal characteristics Symbol Ratings Value Unit T Storage temperature range -65 to 150 STG °C T Maximum junction temperature 150 J DocID14733 Rev 13 55/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3 Operating conditions The device must be used in operating conditions that respect the parameters in Table 18. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 18. General operating conditions Symbol Parameter Conditions Min Max Unit TA  105 °C 0 24 MHz f Internal CPU clock frequency CPU 0 16 MHz V V Standard operating voltage 2.95 5.5 V DD/ DD_IO C : capacitance of external EXT 470 3300 nF capacitor V (1) CAP ESR of external capacitor - 0.3 Ω at 1 MHz(2) ESL of external capacitor - 15 nH 44, 48, 64, and 80-pin devices, with output on 8 standard ports, 2 high sink 443 Power dissipation at  ports and 2 open drain ports P (3) T = 85° C for suffix 6 simultaneously(4) mW D A or TA = 125° C for suffix 3 32-pin package, with output on 8 standard ports and 2 360 high sink ports simultaneously(4) Ambient temperature for 6 Maximum power dissipation -40 85 suffix version T A Ambient temperature for 3 Maximum power dissipation -40 125 suffix version °C 6 suffix version -40 105 T Junction temperature range J 3 suffix version -40 130(5) 1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. 2. This frequency of 1 MHz as a condition for V parameters is given by design of internal regulator. CAP 3. To calculate P (T ), use the formula P = (T - T )/ (see Section 11.2: Thermal Dmax A Dmax Jmax A JA characteristics on page 108) with the value for T given in Table 18 above and the value for  givenin Jmax JA Table 57: Thermal characteristics. 4. Refer to Section 11.2: Thermal characteristics on page 108 for the calculation method. 5. TJmax is given by the test limit. Above this value the product behavior is not guaranteed. 56/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 12. f versus V CPUmax DD f [MHz] CPU 24 FUNCTIONALITY GUARANTEED FUNCTIONALITY @ T -40 to 105 °C NOTGUARANTEED A 16 IN THIS AREA FUNCTIONALITY 12 GUARANTEED @ T -40 to 125 °C A 8 4 0 2.95 4.0 5.0 5.5 SUPPLYVOLTAGE [V] Table 19. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit V rise time rate 2(1)  DD t µs/V VDD V fall time rate 2(1)  DD Reset release t V rising 1.7(1) ms TEMP delay DD Power-on reset V 2.65 2.8 2.95 V IT+ threshold Brown-out reset V 2.58 2.73 2.88 V IT- threshold Brown-out reset V 70 mV HYS(BOR) hysteresis 1. Guaranteed by design, not tested in production. 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor C to the EXT V pin. C is specified in Table 18. Care should be taken to limit the series inductance CAP EXT to less than 15 nH. Figure 13. External capacitor C EXT ESR C ESL Rleak 1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance. DocID14733 Rev 13 57/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3.2 Supply current characteristics The current consumption is measured as described in Figure 9 on page 52. Total current consumption in run mode The MCU is placed under the following conditions:  All I/O pins in input mode with a static value at V or V (no load) DD SS  All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned.  When the MCU is clocked at 24 MHz, T  105 °C and the WAITSTATE option bit is set. A Subject to general operating conditions for V and T . DD A Table 20. Total current consumption with code execution in run mode at V = 5 V DD Symbol Parameter Conditions Typ Max Unit f = f = 24 MHz,  HSE crystal osc. (24 MHz) 4.4 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 3.7 7.3(1) HSE crystal osc. (16 MHz) 3.3 Supply f = f = 16 MHz HSE user ext. clock (16 MHz) 2.7 5.8 current in CPU MASTER run mode, HSI RC osc. (16 MHz) 2.5 3.4 code HSE user ext. clock (16 MHz) 1.2 4.1(1) executed f = f /128 = 125 kHz from RAM CPU MASTER HSI RC osc. (16 MHz) 1.0 1.3(1) f = f /128 = 15.625 CPU MASTER HSI RC osc. (16 MHz/8) 0.55 kHz f = f = 128 kHz LSI RC osc. (128 kHz) 0.45 CPU MASTER I mA DD(RUN) f = f = 24 MHz, HSE crystal osc. (24 MHz) 11.4 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 10.8 18(1) HSE crystal osc. (16 MHz) 9.0 Supply f = f = 16 MHz HSE user ext. clock (16 MHz) 8.2 15.2(1) current in CPU MASTER run mode, HSI RC osc.(16 MHz) 8.1 13.2(1) code f = f = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5 executed CPU MASTER from Flash f = f /128 = 125 kHz HSI RC osc. (16 MHz) 1.1 CPU MASTER f = f /128 = 15.625 CPU MASTER HSI RC osc. (16 MHz/8) 0.6 kHz f = f = 128 kHz LSI RC osc. (128 kHz) 0.55 CPU MASTER 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. 58/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Table 21. Total current consumption with code execution in run mode at V = 3.3 V DD Symbol Parameter Conditions Typ Max(1) Unit f = f = 24 MHz,  HSE crystal osc. (24 MHz) 4.0 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 3.7 7.3 HSE crystal osc. (16 MHz) 2.9 Supply f = f = 16 MHz HSE user ext. clock (16 MHz) 2.7 5.8 current in CPU MASTER run mode, HSI RC osc. (16 MHz) 2.5 3.4 code HSE user ext. clock (16 MHz) 1.2 4.1 executed f = f /128 = 125 kHz CPU MASTER from RAM HSI RC osc. (16 MHz) 1.0 1.3 f = f /128 = 15.625 CPU MASTER HSI RC osc. (16MHz/8) 0.55 kHz f = f = 128 kHz LSI RC osc. (128 kHz) 0.45 CPU MASTER I mA DD(RUN) f = f = 24 MHz, HSE crystal osc. (24 MHz) 11.0 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 10.8 18.0 HSE crystal osc. (16 MHz) 8.4 Supply f = f = 16 MHz HSE user ext. clock (16 MHz) 8.2 15.2 current in CPU MASTER run mode, HSI RC osc. (16 MHz) 8.1 13.2 code f = f = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5 executed CPU MASTER from Flash f = f /128 = 125 kHz HSI RC osc. (16 MHz) 1.1 CPU MASTER f = f /128 = 15.625 CPU MASTER HSI RC osc. (16 MHz/8) 0.6 kHz f = f = 128 kHz LSI RC osc. (128 kHz) 0.55 CPU MASTER 1. Data based on characterization results, not tested in production. 2. Default clock configuration. DocID14733 Rev 13 59/117 116

Electrical characteristics STM8S207xx STM8S208xx Total current consumption in wait mode Table 22. Total current consumption in wait mode at V = 5 V DD Symbol Parameter Conditions Typ Max(1) Unit f = f = 24 MHz,  HSE crystal osc. (24 MHz) 2.4 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 1.8 4.7 HSE crystal osc. (16 MHz) 2.0 Supply fCPU = fMASTER = 16 MHz HSE user ext. clock (16 MHz) 1.4 4.4 IDD(WFI) current in HSI RC osc. (16 MHz) 1.2 1.6 mA wait mode f = f /128 = 125 kHz HSI RC osc. (16 MHz) 1.0 CPU MASTER f = f /128 = 15.625 CPU MASTER HSI RC osc. (16 MHz/8)(2) 0.55 kHz f = f = 128 kHz LSI RC osc. (128 kHz) 0.5 CPU MASTER 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Table 23. Total current consumption in wait mode at V = 3.3 V DD Symbol Parameter Conditions Typ Max(1) Unit f = f = 24 MHz,  HSE crystal osc. (24 MHz) 2.0 CPU MASTER TA  105 °C HSE user ext. clock (24 MHz) 1.8 4.7 HSE crystal osc. (16 MHz) 1.6 f = f = 16 MHz HSE user ext. clock (16 MHz) 1.4 4.4 CPU MASTER Supply I current in HSI RC osc. (16 MHz) 1.2 1.6 mA DD(WFI) wait mode f = f /128 = 125 kHz HSI RC osc. (16 MHz) 1.0 CPU MASTER f = f /128 = 15.625 CPU MASTER HSI RC osc. (16 MHz/8)(2) 0.55 kHz f = f /128 = 15.625 CPU MASTER LSI RC osc. (128 kHz) 0.5 kHz 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. 60/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Total current consumption in active halt mode Table 2 4. Total current consumption in active halt mode at V = 5 V, T -40 to 85° C DD A Conditions Symbol Parameter Main voltage Typ Max(1) Unit regulator Flash mode(3) Clock source (MVR)(2) HSE crystal oscillator  1000 (16 MHz) Operating mode LSI RC oscillator  200 260 (128 kHz) On IDD(AH) Sacutpivpely h caultr rmenotd ien H(1S6E M cHryzs)tal oscillator  940 µA Power-down mode LSI RC oscillator  140 (128 kHz) Operating mode LSI RC oscillator  68 Off 128 kHz) Power-down mode 11 45 1. Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. Table 25. Total current consumption in active halt mode at V = 3.3 V DD Conditions Symbol Parameter Main voltage Typ(1) Unit regulator Flash mode(3) Clock source (MVR)(2) HSE crystal osc. (16 MHz) 600 Operating mode LSI RC osc. (128 kHz) 200 On HSE crystal osc. (16 MHz) 540 Supply current in I Power-down mode µA DD(AH) active halt mode LSI RC osc. (128 kHz) 140 Operating mode 66 Off LSI RC osc. (128 kHz) Power-down mode 9 1. Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. DocID14733 Rev 13 61/117 116

Electrical characteristics STM8S207xx STM8S208xx Total current consumption in halt mode Table 26. Total current consumption in halt mode at V = 5 V DD Symbol Parameter Conditions Typ Max at 85 °C Max at 125 °C Unit Flash in operating mode, HSI 63.5 Supply current in halt clock after wakeup I µA DD(H) mode Flash in power-down mode, 6.5 35 100 HSI clock after wakeup Table 27. Total current consumption in halt mode at V = 3.3 V DD Symbol Parameter Conditions Typ Unit Flash in operating mode, HSI clock after 61.5 wakeup I Supply current in halt mode µA DD(H) Flash in power-down mode, HSI clock after 4.5 wakeup Low power mode wakeup times Table 28. Wakeup times Symbol Parameter Conditions Typ Max(1) Unit See t Wakeup time from wait note(2) WU(WFI) mode to run mode(3) f = f = 16 MHz. 0.56 CPU MASTER Flash in operating 1(6) 2(6) MVR voltage mode(5) regulator on(4) Flash in power-down 3(6) Wakeup time active halt mode(5) HSI (after µs t WU(AH) mode to run mode.(3) Flash in operating wakeup) 48(6) MVR voltage mode(5) regulator off(4) Flash in power-down 50(6) mode(5) Wakeup time from halt Flash in operating mode(5) 52 t WU(H) mode to run mode(3) Flash in power-down mode(5) 54 1. Data guaranteed by design, not tested in production. 2. t = 2 x 1/f + 7 x 1/f WU(WFI) master CPU 3. Measured from interrupt event to interrupt vector fetch. 4. Configured by the REGAH bit in the CLK_ICKR register. 5. Configured by the AHALT bit in the FLASH_CR1 register. 6. Plus 1 LSI clock depending on synchronization. 62/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Total current consumption and timing in forced reset state Table 29. Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max(1) Unit V = 5 V 1.6 DD I Supply current in reset state mA DD(R) V = 3.3 V 0.8 DD Reset release to bootloader vector t 150 µs RESETBL fetch 1. Data guaranteed by design, not tested in production. Current consumption of on-chip peripherals Subject to general operating conditions for V and T . DD A HSI internal RC/f = f = 16 MHz. CPU MASTER Table 30. Peripheral current consumption Symbol Parameter Typ. Unit I TIM1 supply current (1) 220 DD(TIM1) I TIM2 supply current (1) 120 DD(TIM2) I TIM3 timer supply current (1) 100 DD(TIM3) I TIM4 timer supply current (1) 25 DD(TIM4) I UART1 supply current (2) 90 DD(UART1) µA I UART3 supply current (2) 110 DD(UART3) I SPI supply current (2) 40 DD(SPI) I 2 I2C supply current (2) 50 DD(I C) I beCAN supply current (2) 210 DD(CAN) I ADC2 supply current when converting (3) 1000 DD(ADC2) 1. Data based on a differential I measurement between reset configuration and timer counter running at  DD 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. 2. Data based on a differential I measurement between the on-chip peripheral when kept under reset and DD not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. 3. Data based on a differential I measurement between reset configuration and continuous A/D DD conversions. Not tested in production. DocID14733 Rev 13 63/117 116

Electrical characteristics STM8S207xx STM8S208xx Current consumption curves Figure 14 and Figure 15 show typical current consumption measured with code executing in RAM. Figure 14. Typ. I vs V , HSI RC osc,f = 16 MHz DD(RUN) DD CPU (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:23) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:22)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:22) (cid:36)(cid:64) (cid:80) (cid:21)(cid:17)(cid:24) (cid:62)(cid:54)(cid:3) (cid:43) (cid:21) (cid:49)(cid:12) (cid:56) (cid:53) (cid:39)(cid:11) (cid:20)(cid:17)(cid:24) (cid:39) (cid:44) (cid:20) (cid:19)(cid:17)(cid:24) (cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:20)(cid:57)(cid:20) Figure 15. Typ. I vs V , HSI RC osc, f = 16 MHz DD(WFI) DD CPU (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21)(cid:17)(cid:24) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:21) (cid:34)(cid:62) (cid:78) (cid:20)(cid:17)(cid:24) (cid:41)(cid:52)(cid:1)(cid:60) (cid:56)(cid:39)(cid:42)(cid:10) (cid:37)(cid:9) (cid:20) (cid:37) (cid:42) (cid:19)(cid:17)(cid:24) (cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:55)(cid:37)(cid:37)(cid:1)(cid:60)(cid:55)(cid:62) (cid:46)(cid:52)(cid:20)(cid:24)(cid:21)(cid:20)(cid:19)(cid:55)(cid:18) 64/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V and T . DD A Table 31. HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source f 0 24 MHz HSE_ext frequency OSCIN input pin high level V (1) 0.7 x V V + 0.3 V HSEH voltage DD DD V OSCIN input pin low level V (1) V 0.3 x V HSEL voltage SS DD OSCIN input leakage I V < V < V -1 1 µA LEAK_HSE current SS IN DD 1. Data based on characterization results, not tested in production. Figure 16. HSE external clock source VHSEH VHSEL fHSE External clock source OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). DocID14733 Rev 13 65/117 116

Electrical characteristics STM8S207xx STM8S208xx Table 32. HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit External high speed oscillator f 1 24 MHz HSE frequency R Feedback resistor 220 k F C(1) Recommended load capacitance (2) 20 pF C = 20 pF, 6 (startup) f = 24 MHz 2 (stabilized)(3) OSC I HSE oscillator power consumption mA DD(HSE) C = 10 pF, 6 (startup) f = 24 MHz 1.5 (stabilized)(3) OSC g Oscillator transconductance 5 mA/V m t (4) Startup time V is stabilized 1 ms SU(HSE) DD 1. C is approximately equivalent to 2 x crystal Cload. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value. m Refer to crystal manufacturer for more details 3. Data based on characterization results, not tested in production. 4. t is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is SU(HSE) reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 17. HSE oscillator circuit diagram Rm fHSE to core Lm CO RF CL1 Cm OSCIN gm Resonator Consumption control Resonator STM8 OSCOUT CL2 HSE oscillator critical g formula m g = 2f 2R 2Co+C2 mcrit HSE m R : Notional resistance (see crystal specification)  m L : Notional inductance (see crystal specification) m C : Notional capacitance (see crystal specification) m Co: Shunt capacitance (see crystal specification) C =C =C: Grounded external capacitance L1 L2 g >> g m mcrit 66/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for V and T . f DD A HSE High speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit f Frequency 16 MHz HSI Trimmed by the CLK_HSITRIMR register Accuracy of HSI oscillator -1.0(1) 1.0 for given V and T DD A conditions V = 5 V, T = 25 °C -1.5 1.5 DD A ACC V  5 V,  % HSI DD -2.2 2.2 25 °C T  85 °C A Accuracy of HSI oscillator (factory calibrated) 2.95 V  VDD  5.5 V, -3.0(2) 3.0(2) -40 °C T  125 °C A HSI oscillator wakeup t 1.0(1) µs su(HSI) time including calibration HSI oscillator power I 170 250(2) µA DD(HSI) consumption 1. Guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production Figure 18. Typical HSI frequency variation vs V at 4 temperatures DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:22)(cid:8) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:21)(cid:8) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:8) (cid:68)(cid:70)(cid:92) (cid:88)(cid:85) (cid:68)(cid:70)(cid:70) (cid:19)(cid:8) (cid:8)(cid:3) (cid:16)(cid:20)(cid:8) (cid:16)(cid:21)(cid:8) (cid:16)(cid:22)(cid:8) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57) (cid:3)(cid:11)(cid:57)(cid:12) (cid:39)(cid:39) (cid:68)(cid:76)(cid:20)(cid:24)(cid:19)(cid:25)(cid:26) DocID14733 Rev 13 67/117 116

Electrical characteristics STM8S207xx STM8S208xx Low speed internal RC oscillator (LSI) Subject to general operating conditions for V and T . DD A Table 34. LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit f Frequency 110 128 146 kHz LSI t LSI oscillator wakeup time 7(1) µs su(LSI) I LSI oscillator power consumption 5 µA DD(LSI) 1. Guaranteed by design, not tested in production. Figure 19. Typical LSI frequency variation vs V @ 25 °C DD (cid:22)(cid:8) (cid:21)(cid:8) (cid:20)(cid:8) (cid:68)(cid:70)(cid:92) (cid:88)(cid:85) (cid:70)(cid:70) (cid:19)(cid:8) (cid:68) (cid:8)(cid:3) (cid:16)(cid:20)(cid:8) (cid:16)(cid:21)(cid:8) (cid:16)(cid:22)(cid:8) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57) (cid:62)(cid:57)(cid:64) (cid:39)(cid:39)(cid:3) (cid:68)(cid:76)(cid:20)(cid:24)(cid:19)(cid:26)(cid:19) 68/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.3.5 Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol Parameter Conditions Min Unit V Data retention mode(1) Halt mode (or reset) V (2) V RM IT-max 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Table 19 on page 57 for the value of V . IT-max Flash program memory/data EEPROM memory General conditions: TA = -40 to 125 °C. Table 36. Flash program memory/data EEPROM memory Symbol Parameter Conditions Min(1) Typ Max Unit Operating voltage  VDD (all modes, execution/write/erase) fCPU  24 MHz 2.95 5.5 V Standard programming time (including erase) for byte/word/block  6 6.6 ms t (1 byte/4 bytes/128 bytes) prog Fast programming time for 1 block 3 3.3 ms (128 bytes) t Erase time for 1 block (128 bytes) 3 3.3 ms erase Erase/write cycles(2)  T 85 °C 10 k N (program memory) A cycles RW Erase/write cycles (data memory)(2) T 125 ° C 300 k 1M A Data retention (program memory) after 10 k erase/write cycles at  T = 55° C 20 RET T 85 °C A Data retention (data memory) after 10 t T = 55° C 20 years RET k erase/write cycles at T 85 °C RET A Data retention (data memory) after 300k erase/write cycles at  T = 85° C 1 RET T 125 °C A Supply current (Flash programming or I 2 mA DD erasing for 1 to 128 bytes) 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. DocID14733 Rev 13 69/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for V and T unless otherwise specified. All DD A unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level V -0.3 0.3 x V IL voltage DD V Input high level V = 5 V V DD 0.7 x V V + 0.3 V IH voltage DD DD V Hysteresis(1) 700 mV hys R Pull-up resistor V = 5 V, V = V 30 55 80 k pu DD IN SS Fast I/Os 20 (2) Load = 50 pF Standard and high sink I/Os 125 (2) Load = 50 pF Rise and fall time t , t ns R F (10% - 90%) Fast I/Os 35(3) Load = 20 pF Standard and high sink I/Os 125(3) Load = 20 pF Input leakage I current, V  V V ±1 µA lkg SS IN DD analog and digital Analog input I V V V ±250 (2) nA lkg ana leakage current SS IN DD Leakage current in I Injection current ±4 mA ±1(2) µA lkg(inj) adjacent I/O(2) 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data based on characterization results, not tested in production. 3. Guaranteed by design. 70/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 20. Typical V and V vs V @ 4 temperatures IL IH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:25) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:23) (cid:57)(cid:64) (cid:3)(cid:3)(cid:62)(cid:43) (cid:57)(cid:44) (cid:22) (cid:47)(cid:18) (cid:57)(cid:44) (cid:21) (cid:20) (cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:22)(cid:57)(cid:20) Figure 21. Typical pull-up resistance vs V @ 4 temperatures DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:25)(cid:19) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:24)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:58)(cid:64) (cid:159) (cid:62) (cid:24)(cid:19) (cid:72)(cid:3) (cid:70) (cid:81) (cid:68) (cid:86)(cid:87) (cid:23)(cid:24) (cid:86)(cid:76) (cid:72) (cid:83)(cid:3)(cid:85) (cid:23)(cid:19) (cid:88) (cid:88)(cid:79)(cid:79)(cid:16) (cid:51) (cid:22)(cid:24) (cid:22)(cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:23)(cid:57)(cid:20) DocID14733 Rev 13 71/117 116

Electrical characteristics STM8S207xx STM8S208xx Figure 22. Typical pull-up current vs V @ 4 temperatures DD (cid:20)(cid:23)(cid:19) (cid:20)(cid:21)(cid:19) (cid:36)(cid:64) (cid:81)(cid:87)(cid:3)(cid:62)(cid:151) (cid:20)(cid:19)(cid:19) (cid:72) (cid:88)(cid:85)(cid:85) (cid:27)(cid:19) (cid:70) (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:83)(cid:3) (cid:25)(cid:19) (cid:88) (cid:21)(cid:24)(cid:219)(cid:38) (cid:51)(cid:88)(cid:79)(cid:79)(cid:16) (cid:23)(cid:19) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:21)(cid:19) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:24)(cid:19)(cid:25)(cid:27) 1. The pull-up is a pure resistor (slope goes through 0). Table 38. Output driving current (standard ports) Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk I = 10 mA, V = 5 V 2 IO DD V V OL Output low level with 4 pins sunk I = 4 mA, V = 3.3 V 1(1) IO DD Output high level with 8 pins sourced I = 10 mA, V = 5 V 2.8 IO DD V V OH Output high level with 4 pins sourced I = 4 mA, V = 3.3 V 2.1(1) IO DD 1. Data based on characterization results, not tested in production Table 39. Output driving current (true open drain ports) Symbol Parameter Conditions Max Unit I = 10 mA, V = 5 V 1 IO DD V Output low level with 2 pins sunk I = 10 mA, V = 3.3 V 1.5(1) V OL IO DD I = 20 mA, V = 5 V 2(1) IO DD 1. Data based on characterization results, not tested in production Table 40. Output driving current (high sink ports) Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk I = 10 mA, V = 5 V 0.8 IO DD V Output low level with 4 pins sunk I = 10 mA, V = 3.3 V 1(1) OL IO DD Output low level with 4 pins sunk I = 20 mA, V = 5 V 1.5(1) IO DD V Output high level with 8 pins sourced I = 10 mA, V = 5 V 4.0 IO DD V Output high level with 4 pins sourced I = 10 mA, V = 3.3 V 2.1(1) OH IO DD Output high level with 4 pins sourced I = 20 mA, V = 5 V 3.3(1) IO DD 1. Data based on characterization results, not tested in production 72/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin. Figure 23. Typ. V @ V = 5 V (standard ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:21)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:20) (cid:57)(cid:64) (cid:3)(cid:62)(cid:47) (cid:50) (cid:19)(cid:17)(cid:26)(cid:24) (cid:57) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:24)(cid:57)(cid:20) Figure 24. Typ. V @ V = 3.3 V (standard ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:21)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:20) (cid:57)(cid:64) (cid:3)(cid:62)(cid:47) (cid:19)(cid:17)(cid:26)(cid:24) (cid:50) (cid:57) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:25)(cid:57)(cid:20) DocID14733 Rev 13 73/117 116

Electrical characteristics STM8S207xx STM8S208xx Figure 25. Typ. V @ V = 5 V (true open drain ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:20)(cid:17)(cid:21)(cid:24) (cid:3)(cid:62)(cid:47) (cid:50) (cid:57) (cid:20) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:24) (cid:20)(cid:19) (cid:20)(cid:24) (cid:21)(cid:19) (cid:21)(cid:24) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:26)(cid:57)(cid:20) Figure 26. Typ. V @ V = 3.3 V (true open drain ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:36)(cid:64) (cid:20)(cid:17)(cid:21)(cid:24) (cid:80) (cid:3)(cid:62)(cid:50)(cid:47) (cid:20) (cid:44) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:20)(cid:23) (cid:57)(cid:50)(cid:47)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:27)(cid:57)(cid:20) 74/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 27. Typ. V @ V = 5 V (high sink ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:21)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:20) (cid:57)(cid:64) (cid:3)(cid:62)(cid:47) (cid:50) (cid:19)(cid:17)(cid:26)(cid:24) (cid:57) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:24) (cid:20)(cid:19) (cid:20)(cid:24) (cid:21)(cid:19) (cid:21)(cid:24) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:28)(cid:57)(cid:20) Figure 28. Typ. V @ V = 3.3 V (high sink ports) OL DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:21)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:20) (cid:57)(cid:64) (cid:3)(cid:62)(cid:47) (cid:19)(cid:17)(cid:26)(cid:24) (cid:50) (cid:57) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:20)(cid:23) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:19)(cid:57)(cid:20) DocID14733 Rev 13 75/117 116

Electrical characteristics STM8S207xx STM8S208xx Figure 29. Typ. V V @ V = 5 V (standard ports) DD - OH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:3)(cid:62)(cid:43) (cid:20)(cid:17)(cid:21)(cid:24) (cid:50) (cid:57) (cid:3)(cid:16)(cid:3)(cid:39) (cid:20) (cid:39) (cid:57) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:20)(cid:57)(cid:20) Figure 30. Typ. V V @ V = 3.3 V (standard ports) DD - OH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:3)(cid:62)(cid:43) (cid:20)(cid:17)(cid:21)(cid:24) (cid:50) (cid:57) (cid:3)(cid:16)(cid:3)(cid:39) (cid:20) (cid:39) (cid:57) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:26) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:21)(cid:57)(cid:20) 76/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 31. Typ. V V @ V = 5 V (high sink ports) DD - OH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:20)(cid:17)(cid:21)(cid:24) (cid:3)(cid:62)(cid:43) (cid:57)(cid:50) (cid:20) (cid:3)(cid:16)(cid:3)(cid:39)(cid:39) (cid:19)(cid:17)(cid:26)(cid:24) (cid:57) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:24) (cid:20)(cid:19) (cid:20)(cid:24) (cid:21)(cid:19) (cid:21)(cid:24) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:22)(cid:57)(cid:20) Figure 32. Typ. V V @ V = 3.3 V (high sink ports) DD - OH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:21) (cid:21)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:26)(cid:24) (cid:27)(cid:24)(cid:219)(cid:38) (cid:20)(cid:17)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:3)(cid:62)(cid:43) (cid:20)(cid:17)(cid:21)(cid:24) (cid:50) (cid:57) (cid:3)(cid:16)(cid:3)(cid:39) (cid:20) (cid:39) (cid:57) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:20)(cid:23) (cid:44)(cid:50)(cid:47)(cid:3)(cid:62)(cid:80)(cid:36)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:23)(cid:57)(cid:20) DocID14733 Rev 13 77/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3.7 Reset pin characteristics Subject to general operating conditions for V and T unless otherwise specified. DD A Table 41. NRST pin characteristics Symbol Parameter Conditions Min Typ 1) Max Unit V NRST Input low level voltage (1) -0.3 V 0.3 x V IL(NRST) DD V NRST Input high level voltage (1) 0.7 x V V + 0.3 V IH(NRST) DD DD V NRST Output low level voltage (1) I = 2 mA 0.5 OL(NRST) OL R NRST Pull-up resistor (2) 30 55 80 k PU(NRST) t NRST Input filtered pulse (3) 75 ns IFP(NRST) t NRST Input not filtered pulse (3) 500 ns INFP(NRST) t NRST output pulse (1) 15 µs OP(NRST) 1. Data based on characterization results, not tested in production. 2. The R pull-up equivalent resistor is based on a resistive transistor PU 3. Data guaranteed by design, not tested in production. Figure 33. Typical NRST V and V vs V @ 4 temperatures IL IH DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:25) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:57)(cid:64) (cid:23) (cid:3)(cid:62)(cid:43) (cid:57)(cid:44) (cid:3)(cid:16)(cid:3)(cid:47) (cid:22) (cid:57)(cid:44) (cid:21) (cid:20) (cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:24)(cid:57)(cid:20) 78/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 34. Typical NRST pull-up resistance vs V @ 4 temperatures DD (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:25)(cid:19) (cid:21)(cid:24)(cid:219)(cid:38) (cid:27)(cid:24)(cid:219)(cid:38) (cid:58)(cid:64) (cid:525) (cid:24)(cid:24) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:72)(cid:3)(cid:62) (cid:70) (cid:81) (cid:24)(cid:19) (cid:68) (cid:86)(cid:87) (cid:86)(cid:76) (cid:72) (cid:83)(cid:3)(cid:85) (cid:23)(cid:24) (cid:88) (cid:83)(cid:88)(cid:79)(cid:79)(cid:16) (cid:23)(cid:19) (cid:55)(cid:3) (cid:40) (cid:54) (cid:40) (cid:22)(cid:24) (cid:53) (cid:49) (cid:22)(cid:19) (cid:21)(cid:17)(cid:24) (cid:22) (cid:22)(cid:17)(cid:24) (cid:23) (cid:23)(cid:17)(cid:24) (cid:24) (cid:24)(cid:17)(cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:62)(cid:57)(cid:64) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:23)(cid:25)(cid:57)(cid:20) Figure 35. Typical NRST pull-up current vs V @ 4 temperatures DD (cid:20)(cid:23)(cid:19) (cid:20)(cid:21)(cid:19) (cid:36)(cid:64) (cid:151) (cid:81)(cid:87)(cid:3)(cid:62) (cid:20)(cid:19)(cid:19) (cid:72) (cid:83)(cid:3)(cid:70)(cid:88)(cid:85)(cid:85) (cid:27)(cid:19) (cid:88) (cid:88)(cid:79)(cid:79)(cid:16) (cid:25)(cid:19) (cid:16)(cid:23)(cid:19)(cid:219)(cid:38) (cid:51) (cid:40)(cid:55)(cid:3) (cid:21)(cid:24)(cid:219)(cid:38) (cid:54) (cid:23)(cid:19) (cid:40) (cid:27)(cid:24)(cid:219)(cid:38) (cid:53) (cid:49) (cid:21)(cid:19) (cid:20)(cid:21)(cid:24)(cid:219)(cid:38) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:3)(cid:62)(cid:57)(cid:64) (cid:68)(cid:76)(cid:20)(cid:24)(cid:19)(cid:25)(cid:28) The reset network shown in Figure 36 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V max. level specified in IL Table 41. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRSTsignal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF. Figure 36. Recommended reset pin protection VDD STM8 R PU External NRST Internal reset reset Filter circuit 0.1µF (optional) DocID14733 Rev 13 79/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3.8 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, f frequency and V supply voltage MASTER DD conditions. t = 1/f . MASTER MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. SPI characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 10 f SCK SPI clock frequency MHz 1/tc(SCK) Slave mode 0 6 t r(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 25 t f(SCK) t (1) NSS setup time Slave mode 4 x t su(NSS) MASTER t (1) NSS hold time Slave mode 70 h(NSS) t (1) w(SCKH) SCK high and low time Master mode t /2 - 15 t /2 + 15 t (1) SCK SCK w(SCKL) t (1) Master mode 5 su(MI) Data input setup time tsu(SI)(1) Slave mode 5 t (1) Master mode 7 ns h(MI) Data input hold time th(SI)(1) Slave mode 10 t (1)(2) Data output access time Slave mode 3 x t a(SO) MASTER t (1)(3) Data output disable time Slave mode 25 dis(SO) t (1) Data output valid time Slave mode (after enable edge) 75 v(SO) t (1) Data output valid time Master mode (after enable edge) 30 v(MO) t (1) Slave mode (after enable edge) 31 h(SO) Data output hold time t (1) Master mode (after enable edge) 12 h(MO) 1. Values based on design simulation and/or characterization results, and not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 80/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 37. SPI timing diagram - slave mode and CPHA = 0 (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:83) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:38)(cid:46)(cid:3)(cid:44)(cid:81) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:12)(cid:44) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:23) Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:54)(cid:56)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:87)(cid:75)(cid:11)(cid:49)(cid:54)(cid:54)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:38)(cid:46)(cid:3)(cid:76)(cid:81)(cid:83) (cid:38)(cid:38)(cid:51)(cid:51)(cid:50)(cid:43)(cid:36)(cid:47)(cid:32)(cid:32)(cid:19)(cid:20) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:68)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:89)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:54)(cid:50)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:87)(cid:71)(cid:76)(cid:86)(cid:11)(cid:54)(cid:50)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:87)(cid:86)(cid:88)(cid:11)(cid:54)(cid:12)(cid:44) (cid:87)(cid:75)(cid:11)(cid:54)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:24) 1. Measurement points are done at CMOS levels: 0.3 V and 0.7 V DD DD. DocID14733 Rev 13 81/117 116

Electrical characteristics STM8S207xx STM8S208xx Figure 39. SPI timing diagram - master mode(1) (cid:43)(cid:76)(cid:74)(cid:75) (cid:49)(cid:54)(cid:54)(cid:3)(cid:76)(cid:81)(cid:83)(cid:88)(cid:87) (cid:87)(cid:70)(cid:11)(cid:54)(cid:38)(cid:46)(cid:12) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:81)(cid:83) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:46)(cid:3)(cid:76) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:19) (cid:38) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:88)(cid:87) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:81)(cid:83) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:19) (cid:46)(cid:3)(cid:76) (cid:38)(cid:51)(cid:43)(cid:36)(cid:32)(cid:20) (cid:38) (cid:54) (cid:38)(cid:51)(cid:50)(cid:47)(cid:32)(cid:20) (cid:87)(cid:86)(cid:88)(cid:11)(cid:48)(cid:44)(cid:12) (cid:87)(cid:87)(cid:90)(cid:90)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:43)(cid:47)(cid:12)(cid:12) (cid:87)(cid:87)(cid:85)(cid:73)(cid:11)(cid:11)(cid:54)(cid:54)(cid:38)(cid:38)(cid:46)(cid:46)(cid:12)(cid:12) (cid:48)(cid:44)(cid:54)(cid:50) (cid:48)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:37)(cid:44)(cid:55)(cid:25)(cid:3)(cid:44)(cid:49) (cid:47)(cid:54)(cid:37)(cid:3)(cid:44)(cid:49) (cid:44)(cid:49)(cid:51)(cid:56)(cid:55) (cid:87)(cid:75)(cid:11)(cid:48)(cid:44)(cid:12) (cid:48)(cid:50)(cid:54)(cid:44) (cid:50)(cid:56)(cid:55)(cid:51)(cid:56)(cid:55) (cid:48)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:37)(cid:44)(cid:55)(cid:20)(cid:3)(cid:50)(cid:56)(cid:55) (cid:47)(cid:54)(cid:37)(cid:3)(cid:50)(cid:56)(cid:55) (cid:87)(cid:89)(cid:11)(cid:48)(cid:50)(cid:12) (cid:87)(cid:75)(cid:11)(cid:48)(cid:50)(cid:12) (cid:68)(cid:76)(cid:20)(cid:23)(cid:20)(cid:22)(cid:25) 1. Measurement points are done at CMOS levels: 0.3 V and 0.7 V DD DD. 82/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.3.9 I2C interface characteristics Table 43. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Unit Min(2) Max(2) Min(2) Max(2) t SCL clock low time 4.7 1.3 w(SCLL) µs t SCL clock high time 4.0 0.6 w(SCLH) t SDA setup time 250 100 su(SDA) t SDA data hold time 0(3) 0(4) 900(3) h(SDA) tr(SDA) SDA and SCL rise time 1000 300 ns t r(SCL) t f(SDA) SDA and SCL fall time 300 300 t f(SCL) t START condition hold time 4.0 0.6 h(STA) µs t Repeated START condition setup time 4.7 0.6 su(STA) t STOP condition setup time 4.0 0.6 µs su(STO) STOP to START condition time  t 4.7 1.3 µs w(STO:STA) (bus free) C Capacitive load for each bus line 400 400 pF b 1. f , must be at least 8 MHz to achieve max fast I2C speed (400kHz) MASTER 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL DocID14733 Rev 13 83/117 116

Electrical characteristics STM8S207xx STM8S208xx Figure 40. Typical application with I2C bus and timing diagram (cid:54)(cid:36)(cid:36) (cid:54)(cid:36)(cid:36) (cid:51)(cid:52)(cid:45)(cid:24)(cid:51)(cid:18)(cid:16)(cid:88)(cid:88)(cid:88) (cid:51)(cid:36)(cid:33) (cid:41)(cid:163)(cid:35)(cid:0)(cid:66)(cid:85)(cid:83) (cid:51)(cid:35)(cid:44) (cid:51)(cid:52)(cid:33)(cid:50)(cid:52)(cid:0)(cid:50)(cid:37)(cid:48)(cid:37)(cid:33)(cid:52)(cid:37)(cid:36) (cid:51)(cid:52)(cid:33)(cid:50)(cid:52) (cid:51)(cid:52)(cid:33)(cid:50)(cid:52) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:33)(cid:9) (cid:51)(cid:36)(cid:33) (cid:84)(cid:70)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:84)(cid:82)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:51)(cid:52)(cid:47)(cid:48) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:33)(cid:26)(cid:51)(cid:52)(cid:47)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:52)(cid:33)(cid:9) (cid:84)(cid:87)(cid:8)(cid:51)(cid:35)(cid:44)(cid:44)(cid:9) (cid:84)(cid:72)(cid:8)(cid:51)(cid:36)(cid:33)(cid:9) (cid:51)(cid:35)(cid:44) (cid:84)(cid:87)(cid:8)(cid:51)(cid:35)(cid:44)(cid:40)(cid:9) (cid:84)(cid:82)(cid:8)(cid:51)(cid:35)(cid:44)(cid:9) (cid:84)(cid:70)(cid:8)(cid:51)(cid:35)(cid:44)(cid:9) (cid:84)(cid:83)(cid:85)(cid:8)(cid:51)(cid:52)(cid:47)(cid:9) (cid:65)(cid:73)(cid:17)(cid:23)(cid:20)(cid:25)(cid:16) 1. Measurement points are made at CMOS levels: 0.3 x V and 0.7 x V DD DD 84/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics 10.3.10 10-bit ADC characteristics Subject to general operating conditions for V , f , and T unless otherwise DDA MASTER A specified. Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V =3 to 5.5 V 1 4 DDA f ADC clock frequency MHz ADC V =4.5 to 5.5 V 1 6 DDA V Analog supply 3 5.5 V DDA V Positive reference voltage 2.75(1) V V REF+ DDA V Negative reference voltage V 0.5(1) V REF- SSA V V V SSA DDA VAIN Conversion voltage range(2) Devices with external V V V V /V pins REF- REF+ REF+ REF- Internal sample and hold C 3 pF ADC capacitor f = 4 MHz 0.75 t (2) Sampling time ADC µs S f = 6 MHz 0.5 ADC t Wakeup time from standby 7 µs STAB f = 4 MHz 3.5 µs ADC Total conversion time (including t f = 6 MHz 2.33 µs CONV sampling time, 10-bit resolution) ADC 14 1/f ADC 1. Data guaranteed by design, not tested in production. 2. During the sample time the input capacitance C (3 pF max) can be charged/discharged by the external AIN source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t After the end of the sample time t , changes of the analog input voltage have no effect on S. S the conversion result. Values for the sample clock t depend on programming. S DocID14733 Rev 13 85/117 116

Electrical characteristics STM8S207xx STM8S208xx Table 45. ADC accuracy with R < 10 k, V = 5 V AIN DDA Symbol Parameter Conditions Typ Max(1) Unit f = 2 MHz 1 2.5 ADC |E | Total unadjusted error (2) f = 4 MHz 1.4 3 T ADC f = 6 MHz 1.6 3.5 ADC f = 2 MHz 0.6 2 ADC |E | Offset error (2) f = 4 MHz 1.1 2.5 O ADC f = 6 MHz 1.2 2.5 ADC f = 2 MHz 0.2 2 ADC |E | Gain error (2) f = 4 MHz 0.6 2.5 LSB G ADC f = 6 MHz 0.8 2.5 ADC f = 2 MHz 0.7 1.5 ADC |E | Differential linearity error (2) f = 4 MHz 0.7 1.5 D ADC f = 6 MHz 0.8 1.5 ADC f = 2 MHz 0.6 1.5 ADC |E | Integral linearity error (2) f = 4 MHz 0.6 1.5 L ADC f = 6 MHz 0.6 1.5 ADC 1. Data based on characterization results for LQFP80 device with V /V , not tested in production. REF+ REF- 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I and INJ(PIN) I in Section 10.3.6 does not affect the ADC accuracy. INJ(PIN) Table 46. ADC accuracy with R < 10 kR , V = 3.3 V AIN AIN DDA Symbol Parameter Conditions Typ Max(1) Unit f = 2 MHz 1.1 2 |E | Total unadjusted error(2) ADC T f = 4 MHz 1.6 2.5 ADC f = 2 MHz 0.7 1.5 |E | Offset error(2) ADC O f = 4 MHz 1.3 2 ADC f = 2 MHz 0.2 1.5 |E | Gain error(2) ADC LSB G f = 4 MHz 0.5 2 ADC f = 2 MHz 0.7 1 |E | Differential linearity error(2) ADC D f = 4 MHz 0.7 1 ADC f = 2 MHz 0.6 1.5 |E | Integral linearity error(2) ADC L f = 4 MHz 0.6 1.5 ADC 86/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Figure 41. ADC accuracy characteristics EG 1023 V –V 1022 DDA SSA 1LSB =----------------------------------------- 1021 IDEAL 1024 (2) 7 ET (3) (1) 6 5 EO EL 4 3 ED 2 1 1LSBIDEAL 0 1 2 3 4 5 6 7 1021102210231024 VSSA VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. T E = Offset error: deviation between the first actual transition and the first ideal one. O E = Gain error: deviation between the last ideal transition and the last actual one. G E = Differential linearity error: maximum deviation between actual steps and the ideal one. D E = Integral linearity error: maximum deviation between any actual transition and the end point correlation L line. Figure 42. Typical application with ADC VDD STM8 VT 0.6V RAIN AINx VAIN c1o0n-bviet rAsi/oDn CAIN V0.T6V IL CADC ±1µA DocID14733 Rev 13 87/117 116

Electrical characteristics STM8S207xx STM8S208xx 10.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).  ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.  FTB: A burst of fast transient voltage (positive and negative) is applied to V and V DD SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:  Corrupted program counter  Unexpected reset  Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 47. EMS data Symbol Parameter Conditions Level/class V 5 V, T 25 °C,  Voltage limits to be applied on any I/O pin to DD A V f 16 MHz, 2B FESD induce a functional disturbance MASTER conforming to IEC 61000-4-2 Fast transient voltage burst limits to be V 5 V, T 25 °C,  DD A V applied through 100pF on V and V pins f 16 MHz,  4A EFTB DD SS MASTER to induce a functional disturbance conforming to IEC 61000-4-4 88/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and pin loading. Table 48. EMI data Conditions Max f /f (1) Symbol Parameter HSE CPU Unit Monitored General conditions frequency band 8 MHz/ 8 MHz/ 8 MHz/ 8 MHz 16 MHz 24 MHz 0.1MHz to 30 MHz 15 20 24 V 5 V  DD Peak level T 25 °C 30 MHz to 130 MHz 18 21 16 dBµV A SEMI LQFP80 package 130 MHz to 1 GHz -1 1 4 conforming to SAE IEC SAE EMI 61967-2 SAE EMI level 2 2.5 2.5 level 1. Data based on characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 49. ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class Unit value(1) Electrostatic discharge voltage T 25°C, conforming to V A A 2000 V ESD(HBM) (Human body model) JESD22-A114 Electrostatic discharge voltage T  25°C, conforming to V A IV 1000 V ESD(CDM) (Charge device model) JESD22-C101 1. Data based on characterization results, not tested in production. DocID14733 Rev 13 89/117 116

Electrical characteristics STM8S207xx STM8S208xx Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance:  A supply overvoltage (applied to each power supply pin)  A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50. Electrical sensitivities Symbol Parameter Conditions Class(1) T 25 °C A A LU Static latch-up class T 85 °C A A T 125 °C A A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 90/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics 11 Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. DocID14733 Rev 13 91/117 116

Package characteristics STM8S207xx STM8S208xx 11.1 Package information 11.1.1 LQFP80 package information Figure 43. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33) (cid:33) (cid:17) (cid:33) (cid:67) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:17) (cid:33) (cid:36) (cid:44) (cid:75) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:22)(cid:16) (cid:20)(cid:17) (cid:22)(cid:17) (cid:20)(cid:16) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:24)(cid:16) (cid:18)(cid:17) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:17) (cid:18)(cid:16) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:69) (cid:17)(cid:51)(cid:63)(cid:45)(cid:37) 1. Drawing is not to scale. Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data(1) millimeters inches Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0.0087 0.0126 0.0150 c 0.090 - 0.200 0.0035 - 0.0079 92/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data(1) (continued) millimeters inches Symbol Min Typ Max Min Typ Max D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.350 - - 0.4862 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.350 - - 0.4862 - e - 0.650 - - 0.0256 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. LQFP80 recommended footprint (cid:23)(cid:17) (cid:21)(cid:18) (cid:21) (cid:17)(cid:15) (cid:23)(cid:18) (cid:17)(cid:15)(cid:23)(cid:22) (cid:21)(cid:17) (cid:20) (cid:23)(cid:15)(cid:24) (cid:18)(cid:21)(cid:15) (cid:18) (cid:25)(cid:17) (cid:19)(cid:18) (cid:18)(cid:15)(cid:19) (cid:18) (cid:19)(cid:17) (cid:18)(cid:19)(cid:15)(cid:24)(cid:22) (cid:18)(cid:23)(cid:15)(cid:24) (cid:18)(cid:52)(cid:64)(cid:39)(cid:49) DocID14733 Rev 13 93/117 116

Package characteristics STM8S207xx STM8S208xx Device marking The following figure shows the marking for the LQFP80 package. Figure 45. LQFP80 marking example (package top view) (cid:50)(cid:83)(cid:87)(cid:76)(cid:82)(cid:81)(cid:68)(cid:79)(cid:3)(cid:74)(cid:68)(cid:87)(cid:72)(cid:3)(cid:80)(cid:68)(cid:85)(cid:78) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:11)(cid:20)(cid:12) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:51) (cid:52)(cid:53)(cid:46)(cid:25)(cid:52)(cid:19)(cid:17)(cid:24) (cid:46)(cid:25)(cid:53)(cid:23)(cid:35) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:58) (cid:56)(cid:56) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:22)(cid:19)(cid:57)(cid:20) 1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 94/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics 11.1.2 LQFP64 package information Figure 46. LQFP64 - 64-pin 14 mm x 14 mm low-profile quad flat package outline (cid:39) (cid:39)(cid:20) (cid:70)(cid:70)(cid:70) (cid:38) (cid:39)(cid:22) (cid:36) (cid:36)(cid:21) (cid:23)(cid:27) (cid:22)(cid:22) (cid:23)(cid:28) (cid:22)(cid:21) (cid:69) (cid:47)(cid:20) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:47) (cid:36)(cid:20) (cid:46) (cid:25)(cid:23) (cid:20)(cid:26) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20) (cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:20) (cid:20)(cid:25) (cid:70) (cid:72) (cid:20)(cid:53)(cid:66)(cid:48)(cid:40) Table 52. LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical data mm inches(1) Symbol Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 C 0.090 0.200 0.0035 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 12.000 0.4724 E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.800 0.0315 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 DocID14733 Rev 13 95/117 116

Package characteristics STM8S207xx STM8S208xx Table 52. LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) mm inches(1) Symbol Min Typ Max Min Typ Max k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 ° ccc 0.100 0.0039 1. Values in inches are converted from mm and rounded to four decimal places. Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:38) (cid:36) (cid:36)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80) (cid:42)(cid:36)(cid:56)(cid:42)(cid:40)(cid:3)(cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:20) (cid:70) (cid:36) (cid:70)(cid:70)(cid:70) (cid:38) (cid:20) (cid:39) (cid:36) (cid:46) (cid:39)(cid:20) (cid:47) (cid:39)(cid:22) (cid:47)(cid:20) (cid:23)(cid:27) (cid:22)(cid:22) (cid:22)(cid:21) (cid:23)(cid:28) (cid:69) (cid:40)(cid:22) (cid:40)(cid:20) (cid:40) (cid:25)(cid:23) (cid:20)(cid:26) (cid:20) (cid:20)(cid:25) (cid:51)(cid:44)(cid:49)(cid:3)(cid:20) (cid:72) (cid:44)(cid:39)(cid:40)(cid:49)(cid:55)(cid:44)(cid:41)(cid:44)(cid:38)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:24)(cid:58)(cid:66)(cid:48)(cid:40)(cid:66)(cid:57)(cid:22) Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data mm inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 96/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) mm inches(1) Symbol Min Typ Max Min Typ Max D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 -  0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal places. Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint (cid:20)(cid:24) (cid:19)(cid:19) (cid:16)(cid:14)(cid:19) (cid:20)(cid:25) (cid:16)(cid:14)(cid:21) (cid:19)(cid:18) (cid:17)(cid:18)(cid:14)(cid:23) (cid:17)(cid:16)(cid:14)(cid:19) (cid:17)(cid:16)(cid:14)(cid:19) (cid:22)(cid:20) (cid:17)(cid:23) (cid:17)(cid:14)(cid:18) (cid:17) (cid:17)(cid:22) (cid:23)(cid:14)(cid:24) (cid:17)(cid:18)(cid:14)(cid:23) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:16)(cid:25)(cid:67) DocID14733 Rev 13 97/117 116

Package characteristics STM8S207xx STM8S208xx Device marking The following figure shows the marking for the LQFP64 package. Figure 49. LQFP64 marking example (package top view) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:68)(cid:85)(cid:71)(cid:3)(cid:54)(cid:55)(cid:3)(cid:79)(cid:82)(cid:74)(cid:82) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:25)(cid:52)(cid:19)(cid:17)(cid:24)(cid:51)(cid:25)(cid:53)(cid:23)(cid:36) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:24)(cid:27)(cid:57)(cid:20) 1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 98/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics 11.1.3 LQFP48 package information Figure 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33)(cid:33) (cid:17) (cid:33) (cid:67) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:36) (cid:43) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:20)(cid:24) (cid:17)(cid:19) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:17)(cid:18) (cid:69) (cid:21)(cid:34)(cid:63)(cid:45)(cid:37)(cid:63)(cid:54)(cid:18) Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical mm inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 DocID14733 Rev 13 99/117 116

Package characteristics STM8S207xx STM8S208xx Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical (continued) mm inches(1) Symbol Min Typ Max Min Typ Max E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal places. Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint (cid:16)(cid:14)(cid:21)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:16)(cid:14)(cid:19)(cid:16) (cid:19)(cid:22) (cid:18)(cid:21) (cid:19)(cid:23) (cid:18)(cid:20) (cid:16)(cid:14)(cid:18)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:24) (cid:17)(cid:19) (cid:17) (cid:17)(cid:18) (cid:17)(cid:14)(cid:18)(cid:16) (cid:21)(cid:14)(cid:24)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:65)(cid:73)(cid:17)(cid:20)(cid:25)(cid:17)(cid:17)(cid:68) 1. Dimensions are expressed in millimeters. 100/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics Device marking The following figure shows the marking for the LQFP48 package. Figure 52. LQFP48 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:52)(cid:53)(cid:46)(cid:25)(cid:52)(cid:19)(cid:17)(cid:24) (cid:36)(cid:35)(cid:53)(cid:23) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:24)(cid:28)(cid:57)(cid:20) 1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID14733 Rev 13 101/117 116

Package characteristics STM8S207xx STM8S208xx 11.1.4 LQFP44 package information Figure 53. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:33) (cid:33)(cid:18) (cid:17) (cid:33) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:17) (cid:33) (cid:43) (cid:36) (cid:44) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:19)(cid:19) (cid:18)(cid:19) (cid:18)(cid:18) (cid:19)(cid:20) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:20)(cid:20) (cid:17)(cid:18) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:17) (cid:17)(cid:17) (cid:69) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:21)(cid:58)(cid:64)(cid:46)(cid:38) 102/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics Table 55. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical data mm inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 0.0079 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D3 - 8.000 - - 0.3150 - E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 - 8.000 - - 0.3150 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal places. DocID14733 Rev 13 103/117 116

Package characteristics STM8S207xx STM8S208xx Figure 54. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint (cid:24) (cid:23)(cid:23) (cid:22)(cid:23) (cid:19)(cid:17) (cid:19)(cid:17)(cid:27) (cid:20) (cid:22)(cid:22) (cid:26) (cid:21)(cid:17) (cid:20) (cid:22) (cid:19)(cid:17) (cid:20) (cid:20)(cid:19)(cid:17)(cid:22) (cid:20)(cid:20) (cid:21)(cid:22) (cid:20)(cid:21) (cid:21)(cid:21) (cid:20)(cid:17)(cid:21) (cid:27)(cid:17)(cid:24) (cid:20)(cid:21)(cid:17)(cid:26) (cid:23)(cid:60)(cid:66)(cid:41)(cid:51) 1. Dimensions are expressed in millimeters. Device marking The following figure shows the marking for the LQFP44 package. Figure 55. LQFP44 marking example (package top view) (cid:56)(cid:81)(cid:80)(cid:68)(cid:85)(cid:78)(cid:68)(cid:69)(cid:79)(cid:72)(cid:3)(cid:86)(cid:88)(cid:85)(cid:73)(cid:68)(cid:70)(cid:72) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:52)(cid:53)(cid:46)(cid:25)(cid:52) (cid:19)(cid:17)(cid:24)(cid:52)(cid:23)(cid:53)(cid:23)(cid:36) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:25)(cid:19)(cid:57)(cid:20) 1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 104/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics 11.1.5 LQFP32 package information Figure 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline (cid:51)(cid:37)(cid:33)(cid:52)(cid:41)(cid:46)(cid:39) (cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:35) (cid:18) (cid:33) (cid:33) (cid:17) (cid:67) (cid:33) (cid:16)(cid:14)(cid:18)(cid:21)(cid:0)(cid:77)(cid:77) (cid:39)(cid:33)(cid:53)(cid:39)(cid:37)(cid:0)(cid:48)(cid:44)(cid:33)(cid:46)(cid:37) (cid:67)(cid:67)(cid:67) (cid:35) (cid:43) (cid:36) (cid:17) (cid:44) (cid:33) (cid:36)(cid:17) (cid:44)(cid:17) (cid:36)(cid:19) (cid:18)(cid:20) (cid:17)(cid:23) (cid:18)(cid:21) (cid:17)(cid:22) (cid:66) (cid:37)(cid:19) (cid:37)(cid:17) (cid:37) (cid:19)(cid:18) (cid:25) (cid:48)(cid:41)(cid:46)(cid:0)(cid:17) (cid:41)(cid:36)(cid:37)(cid:46)(cid:52)(cid:41)(cid:38)(cid:41)(cid:35)(cid:33)(cid:52)(cid:41)(cid:47)(cid:46) (cid:17) (cid:24) (cid:69) (cid:22)(cid:55)(cid:64)(cid:46)(cid:38)(cid:64)(cid:55)(cid:19) DocID14733 Rev 13 105/117 116

Package characteristics STM8S207xx STM8S208xx Table 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data mm inches(1) Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal places. Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint (cid:16)(cid:14)(cid:24)(cid:16) (cid:17)(cid:14)(cid:18)(cid:16) (cid:19)(cid:21) (cid:18)(cid:24) (cid:19)(cid:22) (cid:18)(cid:23) (cid:16)(cid:14)(cid:21)(cid:16) (cid:19)(cid:17)(cid:22)(cid:19) (cid:23)(cid:14)(cid:19)(cid:16) (cid:22)(cid:14)(cid:17)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:23)(cid:14)(cid:19)(cid:16) (cid:20)(cid:19) (cid:26) (cid:18) (cid:25) (cid:17)(cid:14)(cid:18)(cid:16) (cid:22)(cid:14)(cid:17)(cid:16) (cid:25)(cid:14)(cid:23)(cid:16) (cid:21)(cid:54)(cid:63)(cid:38)(cid:48)(cid:63)(cid:54)(cid:18) 1. Dimensions are expressed in millimeters. 106/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics Device marking The following figure shows the marking for the LQFP32 package. Figure 58. LQFP32 marking example (package top view) (cid:51)(cid:85)(cid:82)(cid:71)(cid:88)(cid:70)(cid:87)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:11)(cid:20)(cid:12) (cid:52)(cid:53)(cid:46)(cid:25)(cid:52)(cid:19)(cid:17)(cid:24) (cid:44)(cid:23)(cid:53)(cid:23)(cid:36) (cid:39)(cid:68)(cid:87)(cid:72)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:58) (cid:56)(cid:56) (cid:53)(cid:72)(cid:89)(cid:76)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:71)(cid:72) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:71)(cid:72)(cid:81)(cid:87)(cid:76)(cid:73)(cid:76)(cid:72)(cid:85) (cid:51) (cid:48)(cid:54)(cid:22)(cid:26)(cid:23)(cid:25)(cid:20)(cid:57)(cid:20) 1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID14733 Rev 13 107/117 116

Package characteristics STM8S207xx STM8S208xx 11.2 Thermal characteristics The maximum chip junction temperature (T ) must never exceed the values given in Jmax Table 18: General operating conditions on page 56. The maximum chip-junction temperature, T , in degrees Celsius, may be calculated Jmax using the following equation: T = T + (P x  ) Jmax Amax Dmax JA Where:  T is the maximum ambient temperature in C Amax   is the package junction-to-ambient thermal resistance in C/W JA  P is the sum of P and P (P = P + P ) Dmax INTmax I/Omax Dmax INTmax I/Omax  P is the product of I andV , expressed in Watts. This is the maximum chip INTmax DD DD internal power.  P represents the maximum power dissipation on output pins, where: I/Omax P =(V *I ) + ((V -V *I ), and taking account of the actual V /I and I/Omax OL OL DD OH) OH OL OL V /I of the I/Os at low and high level in the application. OH OH Table 57. Thermal characteristics(1) Symbol Parameter Value Unit Thermal resistance junction-ambient  38 °C/W JA LQFP 80 - 14 x 14 mm Thermal resistance junction-ambient  45 °C/W JA LQFP 64 - 14 x 14 mm Thermal resistance junction-ambient  46 °C/W JA LQFP 64 - 10 x 10 mm Thermal resistance junction-ambient  57 °C/W JA LQFP 48 - 7 x 7 mm Thermal resistance junction-ambient  54 °C/W JA LQFP 44 - 10 x 10 mm Thermal resistance junction-ambient  60 °C/W JA LQFP 32 - 7 x 7 mm 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.2.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 108/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Package characteristics 11.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 59: STM8S207xx/208xx performance line ordering information scheme(1) on page 112). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions:  Maximum ambient temperature T = 82 °C (measured according to JESD51-2) Amax  I = 15 mA, V = 5.5 V DDmax DD  Maximum eight standard I/Os used at the same time in output at low level with I = 10 OL mA, V = 2 V OL  Maximum four high sink I/Os used at the same time in output at low level with I = 20 OL mA, V = 1.5 V OL  Maximum two true open drain I/Os used at the same time in output at low level with  I = 20 mA, V = 2 V OL OL P 15 mA x 5.5 V = 82.5 mW INTmax = P (10 mA x 2 V x 8) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW IOmax = This gives: P = 82.5 mW and P 360 mW: INTmax IOmax P = 82.5 mW + 360 mW Dmax Thus: P = 443 mW Dmax Using the values obtained in Table 57: Thermal characteristics on page 108 T is Jmax calculated as follows for LQFP64 10 x 10 mm = 46 °C/W: T = 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C Jmax This is within the range of the suffix 6 version parts (-40 < T < 105 °C). J In this case, parts must be ordered at least with the temperature range suffix 6. DocID14733 Rev 13 109/117 116

STM8 development tools STM8S207xx STM8S208xx 12 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet the development requirements and to adapt the emulation system to support existing and future ST microcontrollers. STice key features  Occurrence and time profiling and code coverage (new features)  Advanced breakpoints with up to 4 levels of conditions  Data breakpoints  Program and data trace recording up to 128 KB records  Read/write on the fly of memory during emulation  In-circuit debugging/programming via SWIM protocol  8-bit probe analyzer  1 input and 2 output triggers  Power supply follower managing application voltages between 1.62 to 5.5 V  Modularity that allows you to specify the components you need to meet the development requirements and adapt to future requirements  Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. 110/117 DocID14733 Rev 13

STM8S207xx STM8S208xx STM8 development tools 12.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring  Seamless integration of C and ASM toolsets  Full-featured debugger  Project management  Syntax highlighting editor  Integrated programming interface  Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of the application directly from an easy-to-use graphical interface. Available toolchains include:  Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code is available. For more information, see www.cosmic-software.com.  Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of code. For more information, see www.raisonance.com.  STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link the application source code. 12.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on the application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. DocID14733 Rev 13 111/117 116

Ordering information STM8S207xx STM8S208xx 13 Ordering information Figure 59. STM8S207xx/208xx performance line ordering information scheme(1) Example: STM8 S 208 M B T 6 B TR Product class STM8 microcontroller Family type S = Standard Sub-family type(2) 208 = Full peripheral set 207 = Intermediate peripheral set Pin count K = 32 pins S = 44 pins C = 48 pins R = 64 pins M = 80 pins Program memory size 6 = 32 Kbyte 8 = 64 Kbyte B = 128 Kbyte Package type T = LQFP Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C Package pitch No character = 0.5 mm B = 0.65 mm C = 0.8 mm Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (e.g. memory size, package) and order-able part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 2. Refer to Table 2: STM8S20xxx performance line features for detailed description. 112/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Revision history 14 Revision history Table 58. Document revision history Date Revision Changes 23-May-2008 1 Initial release. Added part numbers on page 1 and in Table 2 on page 11. 05-Jun-2008 2 Updated Section 4: Product overview. Updated Section 10: Electrical characteristics. 22-Jun-2008 3 Added part numbers on page 1 and in Table 2 on page 11. Added 32 pin device pinout and ordering information. Updated UBC option description in Table 13 on page 48. 12-Aug-2008 4 USART renamed UART1, LINUART renamed UART3. Max. ADC frequency increased to 6 MHz. Removed STM8S207K4 part number. Removed LQFP64 14 x 14 mm package. Added medium and high density Flash memory categories. Added Section 6: Memory and register map on page 34. 20-Oct-2008 5 Replaced beCAN3 by beCAN in Section 4.14.5: beCAN. Updated Section 10: Electrical characteristics on page 52. Updated LQFP44 (Figure 53 and Table 55), and LQFP32 outline and mechanical data (Figure 56, and Table 56). Changed V minimum value from 3.0 to 2.95 V. DD Updated number of High Sink I/Os in pinout. 08-Dec-2008 6 Removed FLASH _NFPR and FLASH _FPR registers in Table 9: General hardware register map. Removed preliminary status. Removed VQFN32 package. 30-Jan-2009 7 Added STM8S207C6, STM8S207S6. Updated external interrupts in Table 2 on page 11. Updated Section 10: Electrical characteristics. Document status changed from “preliminary data” to “datasheet”. Added LQFP64 14 x 14 mm package. Added STM8S207M8, STM8S207SB, STM8S208R8, STM8S208R6, STM8S208C8, and STM8S208C6, STM8S208SB, STM8S208S8, and STM8S208S6. Replaced “CAN” with “beCAN”. 10-Jul-2009 8 Added Table 3 to Section 4.5: Clock controller. Updated Section 4.8: Auto wakeup counter. Added beCAN peripheral (impacting Table 1 and Figure 6). Added footnote about CAN_RX/TX to pinout figures 5, 4, and 6. Table 6: Removed ‘X’ from wpu column of I2C pins (no wpu available). Added Table 11: Interrupt mapping. DocID14733 Rev 13 113/117 116

Revision history STM8S207xx STM8S208xx Table 58. Document revision history (continued) Date Revision Changes Section 10: Electrical characteristics: Added data for TBD values; updated Table 15: Voltage characteristics and Table 18: General operating conditions; updated VCAP specifications in Table 18 and in Section 10.3.1: VCAP external capacitor; updated Figure 18; 8 replaced Figure 19; updated Table 35: RAM and hardware registers; 10-Jul-2009 cont’d updated Figure 22 and Figure 35; added Figure 40: Typical application with I2C bus and timing diagram. Removed Table 56: Junction temperature range. Added link between ordering information Figure 59 and STM8S20xx features Table 2. Document status changed from “preliminary data” to “datasheet”. Table 2: STM8S20xxx performance line features: high sink I/O for STM8S207C8 is 16 (not 13). Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers: updated bit positions for TIM2 and TIM3. Figure 5: LQFP 48-pin pinout: added CAN_TX and CAN_RX to pins 35 and 36; noted that these pins are available only in STM8S208xx devices. Figure 7: LQFP 32-pin pinout: replaced uart2 with uart3. Table 6: Pin description: added footnotes concerning beCAN availability and UART1_RX and UART3_RX pins. Table 13: Option byte description: added description of STM8L bootloader option bytes to the option byte description table. Added Section 9: Unique ID (and listed this attribute in Features). 13-Apr-2010 9 Section 10.3: Operating conditions: added introductory text. Table 18: General operating conditions: replaced “C ” with “VCAP” EXT and added data for ESR and ESL; removed “low power dissipation” condition for T . A Table 26: Total current consumption in halt mode at VDD = 5 V: replaced max value of I at 85 °C from 30 µA to 35 µA for the DD(H) condition “Flash in power-down mode, HSI clock after wakeup”. Table 33: HSI oscillator characteristics: updated the ACC factory HSI calibrated values. Functional EMS (electromagnetic susceptibility) and Table 47: replaced “IEC 1000” with “IEC 61000”. Electromagnetic interference (EMI) and Table 48: replaced “SAE J1752/3” with “IEC 61967-2”. Table 57: Thermal characteristics: changed the thermal resistance junction-ambient value of LQFP32 (7x7 mm) from 59 °C/W to 60 °C/W. 114/117 DocID14733 Rev 13

STM8S207xx STM8S208xx Revision history Table 58. Document revision history (continued) Date Revision Changes Added part number STM8S208M8 to Table 1: Device summary. Updated “reset state” of Table 5: Legend/abbreviations for pinout table. Added footnote 4 to Table 6: Pin description. Table 9: General hardware register map: standardized all reset state values; updated the reset state values of RST_SR, CLK_SWCR, 14-Sep-2010 10 CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, and ADC_DRx registers; added the reset values of the CAN paged registers. Figure 36: Recommended reset pin protection: replaced 0.01 µF with 0.1 µF. Figure 40: Typical application with I2C bus and timing diagram: t , t , t , and t replaced by t , t , w(SCKH) w(SCKL) r(SCK) f(SCK) w(SCLH) w(SCLL) t , and t respectively. r(SCL) f(SCL) Table 1: Device summary: added STM8S207K8. Table 2: STM8S20xxx performance line features: added STM8S207K8 device and changed the RAM value of all other devices to 6 Kbytes. Figure 5, Figure 4, Figure 5, and Figure 7: removed TIM1_CH4 from 22-Mar-2011 11 pins 80, 64, 48, and 32 respectively. Table 6: Pin description: updated note 3 and added note 5. Table 9: General hardware register map: removed I2C_PECR register. Section 10.3.7: Reset pin characteristics: added text regarding the rest network. Figure 1: STM8S20xxx block diagram: updated POR/PDR and BOR; updated LINUART input; added legend. Table 18: General operating conditions: updated V . CAP Table 26: Total current consumption in halt mode at VDD = 5 V: updated title, modified existing max column, and added new max column (at 125 °C) with data. 10-Feb-2012 12 Table 37: I/O static characteristics: added new condition and new max values for rise and fall time; added footnote 3; updated Typ and max pull-up resistor values. Section 10.3.7: Reset pin characteristics: updated cross reference in text below Figure 35 Table 41: NRST pin characteristics: updated Typ and max values of the NRST pull-up resistor. DocID14733 Rev 13 115/117 116

Revision history STM8S207xx STM8S208xx Table 58. Document revision history (continued) Date Revision Changes Updated: – Figure 43: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline – Table 51: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data – Figure 51: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data – Figure 47: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline – Table 53: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data – Figure 50: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline – Table 54: LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical – Figure 56: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline 18-Feb-2015 13 – Table 56: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data Added: – Figure 44: LQFP80 recommended footprint – Figure 45: LQFP80 marking example (package top view) – Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint – Figure 49: LQFP64 marking example (package top view) – Figure 51: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint – Figure 52: LQFP48 marking example (package top view) – Figure 54: LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint – Figure 55: LQFP44 marking example (package top view) – Figure 57: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint – Figure 58: LQFP32 marking example (package top view) 116/117 DocID14733 Rev 13

STM8S207xx STM8S208xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID14733 Rev 13 117/117 117

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